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Gen4_R-Car_Trace32/2_Trunk/pernm1120.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: NM1120 On-Chip Peripherals
; @Props: Released
; @Author: KRZ
; @Changelog: 2023-08-23 KRZ
; 2023-11-09 KRZ
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
; @Doc: Generated (TRACE32, build: 164352.), based on:
; NM1120AE_v1.svd (Ver. 1.0)
; @Core: Cortex-M0
; @Chip: NM1120EC1AE, NM1120FC1AE, NM1120XC1AE
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pernm1120.per 16971 2023-11-09 16:09:22Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ACMP (Analog Comparator)"
base ad:0x400D0000
group.long 0x0++0x13
line.long 0x0 "ACMP_CTL0,Analog Comparator0 Control Register"
bitfld.long 0x0 31. "PRESET,Comparator Result Preset Value\n" "0: 0 for preset value,1: 1 for preset value"
bitfld.long 0x0 28.--30. "CPPSEL,Comparator Positive Input Select\n" "0: ACMP0_P0 (PB.0),1: ACMP0_P1 (PB.1),?,?,?,?,?,?"
newline
bitfld.long 0x0 24.--25. "CPNSEL,Comparator Negative Input Select\n" "0: ACMP0_N (PB.4),1: Band_Gap,?,?"
bitfld.long 0x0 23. "NFDIS,Disable Comparator Noise Filter\n" "0: Noise filter Enabled,1: Noise filter Disabled"
newline
bitfld.long 0x0 20.--21. "NFCLKS,Noise Filter Clock Pre-divided Selection\nTo determine the sampling frequency of the Noise Filter clock\n" "0: PCLK,1: PCLK / 2,?,?"
bitfld.long 0x0 19. "POLARITY,Analog Comparator Polarity Control\n" "0: Analog Comparator normal output,1: Analog Comparator invert output"
newline
bitfld.long 0x0 13. "DLYTRGIE,Analog Comparator Delay Trigger Mode Interrupt Enable Control\n" "0: Analog Comparator Delay Trigger Mode Interrupt..,1: Analog Comparator Delay Trigger Mode Interrupt.."
bitfld.long 0x0 12. "DLYTRGEN,Analog Comparator Delay Trigger Mode Enable Control\n" "0: Analog Comparator Delay Trigger Mode Disabled,1: Analog Comparator Delay Trigger Mode Enabled"
newline
bitfld.long 0x0 10.--11. "DLYTRGSOR,Analog Comparator Delay Trigger Mode Trigger Source Selection\n" "0: PWM0,1: PWM2,?,?"
bitfld.long 0x0 8.--9. "DLYTRGSEL,Analog Comparator Delay Trigger Mode Trigger Level Selection\n" "0: Analog Comparator Delay Trigger Mode Trigger..,1: Rising,?,?"
newline
bitfld.long 0x0 6. "PBRKSEL,ACMP to EPWM Brake Selection\n" "0: ACMP Result direct output,1: ACMP Delay Trigger Result output"
bitfld.long 0x0 4.--5. "EDGESEL,Interrupt Flag Trigger Edge Detection\n" "0: Interrupt Flag Trigger Edge Disabled,1: Rising,?,?"
newline
bitfld.long 0x0 2.--3. "ACMPHYSEN,Comparator0 Hysteresis Enable Control (Only 20mV)\n" "0: ACMP0 Hysteresis function Disabled (Default),1: ACMP0 Hysteresis function at comparator 0..,?,?"
bitfld.long 0x0 1. "ACMPIE,Comparator Interrupt Enable Control\nNote1: Interrupt is generated if ACMPIE bit is set to '1' after ACMP conversion is finished.\nNote2: ACMP interrupt will wake CPU up in Power-down mode." "0: ACMP interrupt function Disabled,1: Interrupt is generated if ACMPIE bit is set to.."
newline
bitfld.long 0x0 0. "ACMPEN,Comparator Enable Control\nNote: Comparator output needs to wait 2 us stable time after ACMPEN is set." "0: Comparator Disabled,1: Comparator Enabled"
line.long 0x4 "ACMP_CTL1,Analog Comparator1 Control Register"
bitfld.long 0x4 31. "PRESET,Comparator Result Preset Value\n" "0: 0 for preset value,1: 1 for preset value"
bitfld.long 0x4 28.--30. "CPPSEL,Comparator Positive Input Selection\n" "0: ACMP1_P0 (PC.0),1: ACMP1_P1 (PC.1),?,?,?,?,?,?"
newline
bitfld.long 0x4 24.--25. "CPNSEL,Comparator Negative Input Selection\n" "0: ACMP1_N (PB.3),1: Band_Gap,?,?"
bitfld.long 0x4 23. "NFDIS,Disable Comparator Noise Filter\n" "0: Noise filter Enable,1: Noise filter Disable"
newline
bitfld.long 0x4 20.--21. "NFCLKS,Noise Filter Clock Pre-divided Selection\nTo determine the sampling frequency of the Noise Filter clock\n" "0: PCLK,1: PCLK / 2,?,?"
bitfld.long 0x4 19. "POLARITY,Analog Comparator Polarity Control\n" "0: Analog Comparator normal output,1: Analog Comparator invert output"
newline
bitfld.long 0x4 13. "DLYTRGIE,Analog Comparator Delay Trigger Mode Interrupt Enable\n" "0: Analog Comparator Delay Trigger Mode Interrupt..,1: Analog Comparator Delay Trigger Mode Interrupt.."
bitfld.long 0x4 12. "DLYTRGEN,Analog Comparator Delay Trigger Mode Enable\n" "0: Analog Comparator Delay Trigger Mode Disabled,1: Analog Comparator Delay Trigger Mode Enabled"
newline
bitfld.long 0x4 10.--11. "DLYTRGSOR,Analog Comparator Delay Trigger Mode Trigger Source Selection\n" "0: PWM0,1: PWM2,?,?"
bitfld.long 0x4 8.--9. "DLYTRGSEL,Analog Comparator Delay Trigger Mode Trigger Level Selection\n" "0: Analog Comparator Delay Trigger Mode Trigger..,1: Rising,?,?"
newline
bitfld.long 0x4 6. "PBRKSEL,ACMP to EPWM Brake Selection\n" "0: ACMP Result direct output,1: ACMP Delay Trigger Result output"
bitfld.long 0x4 4.--5. "EDGESEL,Interrupt Flag Trigger Edge Detection\n" "0: Interrupt Flag Trigger Edge Detection Disable,1: Rising,?,?"
newline
bitfld.long 0x4 2.--3. "ACMPHYSEN,Comparator1 Hysteresis Enable Control (Only 20mV)\n" "0: ACMP0 Hysteresis function Disabled (Default),1: ACMP0 Hysteresis function at comparator 0..,?,?"
bitfld.long 0x4 1. "ACMPIE,Comparator Interrupt Enable Control\nNote1: Interrupt is generated if ACMPIE bit is set to '1' after ACMP conversion is finished.\nNote2: ACMP interrupt will wake CPU up in Power-down mode." "0: ACMP interrupt function Disabled,1: Interrupt is generated if ACMPIE bit is set to.."
newline
bitfld.long 0x4 0. "ACMPEN,Comparator Enable Control\nNote: Comparator output needs to wait 2 us stable time after ACMPEN is set." "0: Comparator Disabled,1: Comparator Enabled"
line.long 0x8 "ACMP_STATUS,Analog Comparator Status Register"
bitfld.long 0x8 7. "DLYTRGO1,Analog Comparator1 Delay Trigger Mode Comparator Output\n" "0,1"
bitfld.long 0x8 6. "DLYTRGO0,Analog Comparator0 Delay Trigger Mode Comparator Output\n" "0,1"
newline
bitfld.long 0x8 5. "DLYTRGF1,Comparator1 Flag\nThis bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if DLYTRGIEN set.\nWrite '1' to clear this bit to 0." "0,1"
bitfld.long 0x8 4. "DLYTRGF0,Comparator0 Flag\nThis bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if DLYTRGIEN set.\nWrite '1' to clear this bit to 0." "0,1"
newline
bitfld.long 0x8 3. "ACMPO1,Comparator1 Output\n" "0,1"
bitfld.long 0x8 2. "ACMPO0,Comparator0 Output\n" "0,1"
newline
bitfld.long 0x8 1. "ACMPF1,Comparator1 Flag\nThis bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if ACMPIE set.\nWrite '1' to clear this bit to 0." "0,1"
bitfld.long 0x8 0. "ACMPF0,Comparator0 Flag\nThis bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if ACMPIE set.\nWrite '1' to clear this bit to 0." "0,1"
line.long 0xC "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
hexmask.long.byte 0xC 0.--3. 1. "CRVCTL,Comparator Reference Voltage Setting\n"
line.long 0x10 "ACMP_TRGDLY,Analog Comparator Delay Trigger Mode Dleay Register"
hexmask.long.word 0x10 0.--8. 1. "DELAY,Analog Comparator Delay Trigger Mode Dleay cycle"
tree.end
tree "ADC (Analog-to-Digital Converter)"
base ad:0x400E0000
rgroup.long 0x0++0x7
line.long 0x0 "ADC_DAT0,ADC data register 0"
bitfld.long 0x0 31. "ADC1VALID,ADC1 Valid Flag\nNote: This bit is set to '1' when A/D conversion is completed and cleared by hardware after the ADC_DAT0 register is read." "0: Data in ADC1DAT0[27:16] bits not valid,1: Data in ADC1DAT0[27:16] bits valid"
bitfld.long 0x0 30. "ADC1OV,ADC1 over Run Flag\nNote1: If converted data in ADC1DAT0[27:16] has not been read before the new conversion result is loaded to this register OV is set to '1'. \nNote2:It is cleared by hardware after the ADC_DAT0 register is read." "0: Data in ADC1DAT0[27:16] is recent conversion..,1: If converted data in ADC1DAT0[27:16] has not.."
newline
hexmask.long.word 0x0 16.--27. 1. "ADC1DAT0,ADC1 Conversion Result\nThis field contains conversion result of ADC."
bitfld.long 0x0 15. "ADC0VALID,ADC0 Valid Flag\nNote: This bit is set to '1' when A/D conversion is completed and cleared by hardware after the ADC_DAT0 register is read." "0: Data in ADC0DAT0[11:0] bits not valid,1: Data in ADC0DAT0[11:0] bits valid"
newline
bitfld.long 0x0 14. "ADC0OV,ADC0 over Run Flag\nNote1: If converted data in ADC0DAT0[11:0] has not been read before\n the new conversion result is loaded to this register OV is set to '1'. \nNote2: It is cleared by hardware after the ADC_DAT0 register is read." "0: Data in ADC0DAT0[11:0] is recent conversion result,1: If converted data in ADC0DAT0[11:0] has not been.."
hexmask.long.word 0x0 0.--11. 1. "ADC0DAT0,ADC0 Conversion Result\nThis field contains conversion result of ADC."
line.long 0x4 "ADC_DAT1,ADC Data Register 1"
bitfld.long 0x4 31. "ADC1VALID,ADC1 Valid Flag\nNote: This bit is set to '1' when A/D conversion is completed and cleared by hardware after the ADC_DAT1 register is read." "0: Data in ADC1DAT1[27:16] bits not valid,1: Data in ADC1DAT1[27:16] bits valid"
bitfld.long 0x4 30. "ADC1OV,ADC1 over Run Flag\nNote1: If converted data in ADC1DAT1[27:16] has not been read before the new conversion result is loaded to this register OV is set to '1'. \nNote2: It is cleared by hardware after the ADC_DAT1 register is read." "0: Data in ADC1DAT1[27:16] is recent conversion..,1: If converted data in ADC1DAT1[27:16] has not.."
newline
hexmask.long.word 0x4 16.--27. 1. "ADC1DAT1,ADC1 Conversion Result for FIFO1\nThis field contains conversion result of ADC."
bitfld.long 0x4 15. "ADC0VALID,ADC0 Valid Flag\nNote: This bit is set to '1' when A/D conversion is completed and cleared by hardware after the ADC_DAT1 register is read." "0: Data in ADC0DAT1[11:0] bits not valid,1: Data in ADC0DAT1[11:0] bits valid"
newline
bitfld.long 0x4 14. "ADC0OV,ADC0Over Run Flag\nNote1: If converted data in ADC0DAT1[11:0] has not been read before the new conversion result is loaded to this register OV is set to '1'. \nNote2: It is cleared by hardware after the ADC_DAT1 register is read." "0: Data in ADC0DAT1[11:0] is recent conversion result,1: If converted data in ADC0DAT1[11:0] has not been.."
hexmask.long.word 0x4 0.--11. 1. "ADC0DAT1,ADC0 Conversion Result for FIFO1\nThis field contains conversion result of ADC."
group.long 0x20++0x1B
line.long 0x0 "ADC_CTL,ADC Control Register"
bitfld.long 0x0 28.--30. "ADC1SEQSEL,ADC1 Sequential Input Pin Selection (Second Input)\n" "0: ADC1_CH0,1: ADC1_CH1,?,?,?,?,?,?"
bitfld.long 0x0 24.--26. "ADC1CHSEL,ADC1 Channel Select\n" "0: ADC1_CH0,1: ADC1_CH1,?,?,?,?,?,?"
newline
bitfld.long 0x0 20.--22. "ADC0SEQSEL,ADC0 Sequential Input Pin Selection\n" "0: ADC0_CH0,1: ADC0_CH1,?,?,?,?,?,?"
bitfld.long 0x0 16.--18. "ADC0CHSEL,ADC1 Channel Select\n" "0: ADC0_CH0,1: ADC0_CH1,?,?,?,?,?,?"
newline
bitfld.long 0x0 11. "ADC1SWTRG,ADC1 Conversion Start\nNote: ADC1SWTRG can be set to '1' from two sources: software and external pin STADC. This bit will be cleared to '0' by hardware automatically." "0: Conversion stopped and A/D converter entered..,1: Conversion start"
bitfld.long 0x0 10. "ADC1HWTRGEN,Hardware Trigger ADC Convertion Enable Control\nEnable or disable triggering of A/D conversion by Hardware (PWM Timer ADC self)\n" "0: Hardware Trigger ADC Convertion Disabled,1: Hardware Trigger ADC Convertion Enabled"
newline
bitfld.long 0x0 9. "ADC1IEN,ADC1 Interrupt Enable Control\nNote: A/D conversion end interrupt request is generated if ADC1IEN bit is set to '1'." "0: ADC1 interrupt function Disabled,1: ADC1 interrupt function Enabled"
bitfld.long 0x0 6.--7. "ADCMODE,A/D Conversion Mode\n" "0: Independent simple; independent function and..,1: Independent 2SH; independent trigger function..,?,?"
newline
bitfld.long 0x0 5. "ADCSS3R," "0: convert sequential is ADC0 - ADC1 - ADC0 - ADC1..,1: convert sequential is ADC0 - ADC1 - ADC0 three.."
bitfld.long 0x0 3. "ADC0SWTRG,ADC0 Conversion Start\nNote: ADC0SWTRG can be set to '1' from two sources: software and external pin STADC. This bit will be cleared to '0' by hardware automatically." "0: Conversion stopped and A/D converter entered..,1: Conversion start"
newline
bitfld.long 0x0 2. "ADC0HWTRGEN,Hardware Trigger ADC Convertion Enable\nEnable or disable triggering of A/D conversion by Hardware (PWM Timer ADC self)\n" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "ADC0IEN,ADC0 Interrupt Enable\nNote: A/D conversion end interrupt request is generated if ADC0IEN bit is set to '1'." "0: ADC0 interrupt function Disabled,1: ADC0 interrupt function Enabled"
newline
bitfld.long 0x0 0. "ADCEN,ADC Converter Enable\nNote: Before starting the A/D conversion function this bit should be set to '1'. Clear it to '0' to disable A/D converter analog circuit power consumption." "0: ADC Converter Disabled,1: ADC Converter Enabled"
line.long 0x4 "ADC_TRGSOR,ADC Hardware Trigger Source Control Register"
bitfld.long 0x4 22.--23. "ADC1STADCSEL,ADC1 External Trigger Pin (STADC) Trigger Selection\n" "0: Rising,1: Falling,?,?"
bitfld.long 0x4 20.--21. "ADC1PWMTRGSEL,PWM Trigger Selection for ADC1\n" "0: EPWM Signal Falling,1: EPWM Counter Central,?,?"
newline
hexmask.long.byte 0x4 16.--19. 1. "ADC1TRGSOR,ADC1 Trigger Source \n"
bitfld.long 0x4 6.--7. "ADC0STADCSEL,ADC0 External Trigger Pin (STADC) Trigger Selection\n" "0: Rising,1: Falling,?,?"
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bitfld.long 0x4 4.--5. "ADC0PWMTRGSEL,PWM Trigger Selection for ADC0\n" "0: EPWM Signal Falling,1: EPWM Counter Central,?,?"
hexmask.long.byte 0x4 0.--3. 1. "ADC0TRGSOR,ADC0 Trigger Source \n"
line.long 0x8 "ADC_TRGDLY,ADC Trigger Delay Control Register"
hexmask.long.byte 0x8 16.--23. 1. "ADC1DELAY,ADC1 Trigger Delay Timer\nSetting this field will delay ADC start conversion time after ADCxTRGCTL trigger is coming. (x:0/1)\nDelay time is (4 * ADC1DELAY) * system clock"
hexmask.long.byte 0x8 0.--7. 1. "ADC0DELAY,ADC0 Trigger Delay Timer\nSetting this field will delay ADC start conversion time after ADCxTRGCTL trigger is coming. (x:0/1)\nDelay time is (4 * ADC0DELAY) * system clock"
line.long 0xC "ADC_SMPCNT,ADC Sampling Time Counter Register"
hexmask.long.byte 0xC 0.--3. 1. "ADCSMPCNT,ADC Sampling Counter\nADC sampling counters are 6 ADC clock is suggestion\n"
line.long 0x10 "ADC_STATUS,ADC Status Register"
bitfld.long 0x10 19. "HIGHFG,Window Comparator High Bound Flag\nWhen A/D conversion result higher than the setting condition in High Bound (WCMPHIGHDAT) this bit is set to '1'.\nThen it is cleared by writing '1' to ifself.\n" "0: Conversion result in ADC_DAT1 does not meet the..,1: Conversion result in ADC_DAT1 meets the.."
bitfld.long 0x10 18. "MIDFG,Window Comparator Middle Bound Flag\nWhen A/D conversion result is between High Bound (WCMPHIGHDAT) and Low Bound (WCMPLOWDAT) this bit is set to '1'.\nThen it is cleared by writing '1' to ifself.\n" "0: Conversion result in ADC_DAT1 isn't between High..,1: Conversion result in ADC_DAT1 is between High.."
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bitfld.long 0x10 17. "LOWFG,Window Comparator Low Bound Flag\nWhen A/D conversion result lower than the setting condition in Low Bound (WCMPLOWDAT) this bit is set to '1'.\nThen it is cleared by writing '1' to ifself.\n" "0: Conversion result in ADC_DAT1 does not meet the..,1: Conversion result in ADC_DAT1 meets the.."
bitfld.long 0x10 16. "WCMPIF,Window Comparator Interrupt Flag\nWhen Windows Comparator has generat a result output this bit is set to '1'.\nThen it is cleared by writing '1' to ifself.\n" "0: Conversion result in ADC_DAT1 does not meets the..,1: Conversion result in ADC_DAT1 meets the.."
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hexmask.long.byte 0x10 12.--15. 1. "ADC1CH,Current Conversion Channel\nIt is read only."
bitfld.long 0x10 11. "ADC1BUSY,BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR." "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
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bitfld.long 0x10 9. "ADC1OV,Over Run Flag\nIt is a mirror to OV bit in ADDR." "0,1"
bitfld.long 0x10 8. "ADC1IF,ADC1 Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to '1' When A/D conversion ends.\nThis flag can be cleared by writing '1' to itself." "0,1"
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hexmask.long.byte 0x10 4.--7. 1. "ADC0CH,Current Conversion Channel\nIt is read only."
bitfld.long 0x10 3. "ADC0BUSY,BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR." "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
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bitfld.long 0x10 1. "ADC0OV,Over Run Flag\nIt is a mirror to OV bit in ADDR." "0,1"
bitfld.long 0x10 0. "ADC0IF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to '1' When A/D conversion ends.\nThis flag can be cleared by writing '1' to itself." "0,1"
line.long 0x14 "ADC_WCMPCTL,ADC Window Comparator Control Register"
hexmask.long.byte 0x14 8.--11. 1. "WCMPMCNT,Window Compare Match Count\nWhen the A/D conversion result matches the compare condition\n defined by CMP Flag setting (CMPUPEN CMPEQUEN CMPLOWEN and WCFLAGCTL) the internal match counter will increase 1. \nWhen the internal counter reaches.."
bitfld.long 0x14 7. "WFLAGCTL,Window Comparator Flag Control\nWhen the A/D conversion result matches the compare condition\n" "0: Auto-update,1: none"
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bitfld.long 0x14 6. "WCMPHIGHEN,Window Comparator High Flag Enable Control\nset A/D conversion result higher than compare condition High bound range\n" "0: Window Comparator High Flag Disabled,1: Window Comparator High Flag Enabled"
bitfld.long 0x14 5. "WCMPMIDEN,Window Comparator Middle Flag Enable Control\nset A/D conversion result equal to compare condition at Low and High bound range\n" "0: Window Comparator Middle Flag Disabled,1: Window Comparator Middle Flag Enabled"
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bitfld.long 0x14 4. "WCMPLOWEN,Window Comparator Low Flag Enable Control\nset A/D conversion result lower than compare condition Low bound range\n" "0: Window Comparator Low Flag Disabled,1: Window Comparator Low Flag Enabled"
bitfld.long 0x14 1. "WCMPIEN,Window Comparator Interrupt Enable Control\n" "0: Window Comparator Interrupt Disabled,1: Window Comparator Interrupt Enabled"
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bitfld.long 0x14 0. "WCMPEN,Window Comparator Enable Control\n" "0: Window Comparator Disabled,1: Window Comparator Enabled"
line.long 0x18 "ADC_WCMPDAT,ADC Window Comparator Data Register"
hexmask.long.word 0x18 16.--27. 1. "WCMPHIGHDAT,Window Comparator High Bound Data"
hexmask.long.word 0x18 0.--11. 1. "WCMPLOWDAT,Window Comparator Low Bound Data"
tree.end
tree "BPWM (Basic PWM Generator)"
base ad:0x40140000
group.long 0x0++0x13
line.long 0x0 "BPWM_CLKPSC,Basic PWM Pre-scalar Register"
hexmask.long.byte 0x0 16.--23. 1. "DTI01,Dead-zone Interval for Pair of Channel 0 and Channel 1\nThese 8-bit determine the Dead-zone length.\n"
hexmask.long.byte 0x0 0.--7. 1. "CLKPSC01,Clock Prescaler\nClock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM-timer\n"
line.long 0x4 "BPWM_CLKDIV,Basic PWM Clock Source Divider Select Register"
bitfld.long 0x4 4.--6. "CLKDIV1,PWM Timer 1 Clock Source Divider Selection\nSelect clock source divider for PWM timer 1.\n" "0: 1/2,1: 1/4,?,?,?,?,?,?"
bitfld.long 0x4 0.--2. "CLKDIV0,PWM Timer 0 Clock Source Divider Selection\nSelect clock source divider for PWM timer 0.\n(Table is the same as CLKDIV1)" "0,1,2,3,4,5,6,7"
line.long 0x8 "BPWM_CTL,Basic PWM Control Register"
bitfld.long 0x8 30. "CNTTYPE01,PWM01 Aligned Type Selection\n" "0: Edge-aligned type,1: Center-aligned type"
bitfld.long 0x8 11. "CNTMODE1,PWM-timer 1 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit it will cause BPWM_PERIOD1 and BPWM_CMPDAT1 be cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 10. "CMPINV1,PWM-timer 1 Output Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled"
bitfld.long 0x8 9. "PINV1,PWM-timer 1 Output Polar Inverse Enable Control\n" "0: PWM1 output polar inverse Disabled,1: PWM1 output polar inverse Enabled"
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bitfld.long 0x8 8. "CNTEN1,PWM-timer 1 Enable Control\n" "0: Corresponding PWM-Timer Stopped,1: Corresponding PWM-Timer Start Running"
bitfld.long 0x8 4. "DTCNT01,Dead-zone 0 Generator Enable Control\nNote: When Dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair." "0: Dead-zone 0 Generator Disabled,1: Dead-zone 0 Generator Enabled"
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bitfld.long 0x8 3. "CNTMODE0,PWM-timer 0 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit it will cause BPWM_PERIOD0 and BPWM_CMPDAT0 be cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 2. "CMPINV0,PWM-timer 0 Output Inverter Enable Control\n" "0: Inverter Disabled,1: Inverter Enabled"
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bitfld.long 0x8 1. "PINV0,PWM-timer 0 Output Polar Inverse Enable Control\n" "0: PWM0 output polar inverse Disabled,1: PWM0 output polar inverse Enabled"
bitfld.long 0x8 0. "CNTEN0,PWM-timer 0 Enable Control\n" "0: The corresponding PWM-Timer stops running,1: The corresponding PWM-Timer starts running"
line.long 0xC "BPWM_PERIOD0,Basic PWM Period Counter Register 0"
hexmask.long.word 0xC 0.--15. 1. "PERIOD,Basic PWM Period Counter Register\nPERIOD data determines the PWM period.\nFor Edge-aligned type:\nNote: Any write to PERIOD will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type PERIOD value should be set between.."
line.long 0x10 "BPWM_CMPDAT0,Basic PWM Comparator Register 0"
hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM duty.\nNote: Any write to PERIOD will take effect in next PWM cycle."
rgroup.long 0x14++0x3
line.long 0x0 "BPWM_CNT0,Basic PWM Data Register 0"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register\nUser can monitor CNT to know the current value in 16-bit counter."
group.long 0x18++0x7
line.long 0x0 "BPWM_PERIOD1,Basic PWM Period Counter Register 1"
hexmask.long.word 0x0 0.--15. 1. "PERIOD,Basic PWM Period Counter Register\nPERIOD data determines the PWM period.\nFor Edge-aligned type:\nNote: Any write to PERIOD will take effect in next PWM cycle.\nNote: When PWM operating at Center-aligned type PERIOD value should be set between.."
line.long 0x4 "BPWM_CMPDAT1,Basic PWM Comparator Register 1"
hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM duty.\nNote: Any write to PERIOD will take effect in next PWM cycle."
rgroup.long 0x20++0x3
line.long 0x0 "BPWM_CNT1,Basic PWM Data Register 1"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register\nUser can monitor CNT to know the current value in 16-bit counter."
group.long 0x40++0x7
line.long 0x0 "BPWM_INTEN,Basic PWM Interrupt Enable Register"
bitfld.long 0x0 16. "PINTTYPE,BPWM Interrupt Period Type Selection\nNote: This bit is effective when BPWM in Center-aligned type only." "0: PIFn will be set if BPWM counter underflow,1: PIFn will be set if BPWM counter matches PERIODn.."
bitfld.long 0x0 9. "DIEN1,BPWM Channel 1 Duty Interrupt Enable Control\n" "0: BPWM Channel 1 Duty Interrupt Disabled,1: BPWM Channel 1 Duty Interrupt Enabled"
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bitfld.long 0x0 8. "DIEN0,BPWM Channel 0 Duty Interrupt Enable Control\n" "0: BPWM Channel 0 Duty Interrupt Disabled,1: BPWM Channel 0 Duty Interrupt Enabled"
bitfld.long 0x0 1. "PIEN1,BPWM Channel 1 Period Interrupt Enable Control\n" "0: BPWM Channel 1 Period Interrupt Disabled,1: BPWM Channel 1 Period Interrupt Enabled"
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bitfld.long 0x0 0. "PIEN0,BPWM Channel 0 Period Interrupt Enable Control\n" "0: BPWM Channel 0 Period Interrupt Disabled,1: BPWM Channel 0 Period Interrupt Enabled"
line.long 0x4 "BPWM_INTSTS,Basic PWM Interrupt Indication Register"
bitfld.long 0x4 9. "DIF1,BPWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when channel 1 BPWM counter down count and reaches BPWM_CMPDAT 1 software can clear this bit by writing a one to it.\nNote: If CMP equal to PERIOD this flag is not working in Edge-aligned.." "0,1"
bitfld.long 0x4 8. "DIF0,BPWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when channel 0 BPWM counter down count and reaches BPWM_CMPDAT 0 software can clear this bit by writing a one to it.\nNote: If CMP equal to PERIOD this flag is not working in Edge-aligned.." "0,1"
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bitfld.long 0x4 1. "PIF1,BPWM Channel 1 Period Interrupt Status\nThis bit is set by hardware when BPWM1 counter reaches the requirement of interrupt (depend on PINTTYPE bit of PWM_INTEN register) software can write 1 to clear this bit to 0." "0,1"
bitfld.long 0x4 0. "PIF0,BPWM Channel 0 Period Interrupt Status\nThis bit is set by hardware when BPWM0 counter reaches the requirement of interrupt (depend on PINTTYPE bit of PWM_INTEN register) software can write 1 to clear this bit to 0." "0,1"
group.long 0x7C++0x3
line.long 0x0 "BPWM_POEN,Basic PWM Output Enable"
bitfld.long 0x0 1. "POEN1,Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to BPWM function" "0: BPWM channel 1 output to pin Disabled,1: BPWM channel 1 output to pin Enabled"
bitfld.long 0x0 0. "POEN0,Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to BPWM function" "0: BPWM channel 0 output to pin Disabled,1: BPWM channel 0 output to pin Enabled"
tree.end
tree "CLK (Clock Controller)"
base ad:0x50000200
group.long 0x0++0xB
line.long 0x0 "CLK_PWRCTL,System Power-down Control Register"
bitfld.long 0x0 10.--11. "HXTGAIN,HXT Gain Control (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled crystal will.." "0: HXT frequency is lower than from 8 MHz,1: HXT frequency is from 8 MHz to 12 MHz,?,?"
bitfld.long 0x0 9. "PDLXT,LXT Alive in Power-down\n" "0: LXT will be turned off automatically when chip..,1: If XTLEN[1:0] are 0x2 LXT keeps active in.."
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bitfld.long 0x0 7. "PDEN,System Power-down Enable Control (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled.\nWhen chip wakes up from Power-down mode this bit is auto cleared. Users need to set this bit again for next Power-down.\nIn Power-down mode .." "0: Chip operating normally or chip in idle mode..,1: Chip enters Power-down mode when CPU sleep.."
bitfld.long 0x0 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' it indicates that resume from 'Power-down mode' \nThe flag is set if the GPIO USCI01 WDT ACMP01 BOD TMR01 wake-up occurred.\nNote1: Write 1 to clear the bit to.." "?,1: Write 1 to clear the bit to 0"
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bitfld.long 0x0 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Control (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up interrupt Disabled,1: The interrupt will occur when both PDWKIF and.."
bitfld.long 0x0 4. "PDWKDLY,Wake-up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
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bitfld.long 0x0 3. "LIRCEN,LIRC Enable Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
bitfld.long 0x0 2. "HIRCEN,HIRC Enable Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 48 MHz internal high speed RC oscillator (HIRC)..,1: 48 MHz internal high speed RC oscillator (HIRC).."
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bitfld.long 0x0 0.--1. "XTLEN,XTL Enable Control (Write Protect)\nThese two bits are default set to '00' and the XT_IN and XT_OUT pins are GPIO.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: XT_IN and XT_OUT are GPIO disable both LXT HXT..,1: HXT Enabled,?,?"
line.long 0x4 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
bitfld.long 0x4 4. "HDIVCKEN,Hardware Divider Controller Clock Enable Control \n" "0: HDIV peripheral clock Disabled,1: HDIV peripheral clock Enabled"
bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Control\n" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
line.long 0x8 "CLK_APBCLK,APB Devices Clock Enable Control Register"
bitfld.long 0x8 30. "ACMPCKEN,Analog Comparator Clock Enable Control\n" "0: Analog comparator clock Disabled,1: Analog comparator clock Enabled"
bitfld.long 0x8 28. "ADCCKEN,Analog-digital-converter (ADC) Clock Enable Control\n" "0: ADC clock Disabled,1: ADC clock Enabled"
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bitfld.long 0x8 25. "USCI1CKEN,USCI1 Clock Enable Control\n" "0: USCI1 clock Disabled,1: USCI1 clock Enabled"
bitfld.long 0x8 24. "USCI0CKEN,USCI0 Clock Enable Control\n" "0: USCI0 clock Disabled,1: USCI0 clock Enabled"
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bitfld.long 0x8 23. "BPWMCKEN,Basic PWM Channel 0/1 Clock Enable Control\n" "0: BBPWM channel 0/1 clock Disabled,1: BPWM channel 0/1 clock Enabled"
bitfld.long 0x8 20. "EPWMCKEN,Enhanced PWM Clock Enable Control\n" "0: EPWM channel 0/1 clock Disabled,1: EPWM channel 0/1 clock Enabled"
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bitfld.long 0x8 12. "PGACKEN,PGA Clock Enable Control\n" "0: PGA clock Disabled,1: PGA clock Enabled"
bitfld.long 0x8 8. "ECAPCKEN,Input Capture Clock Enable Control\n" "0: CAP clock Disabled,1: CAP clock Enabled"
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bitfld.long 0x8 6. "CLKOCKEN,CLKO Clock Enable Control\n" "0: CLKO clock Disabled,1: CLKO clock Enabled"
bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Control\n" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
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bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Control\n" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
bitfld.long 0x8 0. "WDTCKEN,Watchdog Timer Clock Enable Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Watchdog timer clock Disabled,1: Watchdog timer clock Enabled"
group.long 0x10++0x7
line.long 0x0 "CLK_CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x0 3.--4. "STCLKSEL,Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HXT/LXT,1: Clock source from (HXT or LXT)/2,?,?"
bitfld.long 0x0 0.--1. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HXT/LXT,1: Clock source from LIRC,?,?"
line.long 0x4 "CLK_CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x4 30.--31. "CLKOSEL,Clock Divider Clock Source Selection\n" "0: Clock source from external crystal oscillator..,1: Reserved,?,?"
bitfld.long 0x4 12.--14. "TMR1SEL,TIMER1 Clock Source Selection\n" "0: Clock source from external crystal oscillator..,1: Clock source from 10 kHz internal low speed RC..,?,?,?,?,?,?"
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bitfld.long 0x4 8.--10. "TMR0SEL,TIMER0 Clock Source Selection\n" "0: Clock source from external crystal oscillator..,1: Clock source from 10 kHz internal low speed RC..,?,?,?,?,?,?"
bitfld.long 0x4 4.--5. "ADCSEL,ADC Peripheral Clock Source Selection\n" "0: Clock source from external crystal oscillator..,1: Reserved,?,?"
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bitfld.long 0x4 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock source from external crystal oscillator..,1: Reserved,?,?"
group.long 0x20++0x3
line.long 0x0 "CLK_CLKDIV,Clock Divider Number Register"
hexmask.long.byte 0x0 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source\n"
hexmask.long.byte 0x0 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source\n"
rgroup.long 0x50++0x3
line.long 0x0 "CLK_STATUS,Clock Status Monitor Register"
bitfld.long 0x0 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1.\nNote: Write 1.." "0: Clock switching success,1: Clock switching failure"
bitfld.long 0x0 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)\n" "0: 48 MHz internal high speed RC oscillator (HIRC)..,1: 48 MHz internal high speed RC oscillator (HIRC).."
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bitfld.long 0x0 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)\n" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
bitfld.long 0x0 0. "XTLSTB,XTL Clock Source Stable Flag (Read Only)\n" "0: External crystal oscillator (HXT or LXT) clock..,1: External crystal oscillator (HXT or LXT) clock.."
group.long 0x60++0x3
line.long 0x0 "CLK_CLKOCTL,Clock Output Control Register"
bitfld.long 0x0 5. "DIV1EN,Clock Output Divide One Enable Control\n" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
bitfld.long 0x0 4. "CLKOEN,Clock Output Enable Control\n" "0: Clock Output function Disabled,1: Clock Output function Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]."
tree.end
tree "ECAP (Enhanced Input Capture Timer)"
base ad:0x401B0000
group.long 0x0++0x1F
line.long 0x0 "ECAP_CNT,Input Capture Counter"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Input Capture Timer/Counter (24-bit Up Counter)\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the CAP_CLK is divided by 1 4 16 32 64 96 112 or 128."
line.long 0x4 "ECAP_HLD0,Input Capture Counter Hold Register 0"
hexmask.long.tbyte 0x4 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HLDx.."
line.long 0x8 "ECAP_HLD1,Input Capture Counter Hold Register 1"
hexmask.long.tbyte 0x8 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HLDx.."
line.long 0xC "ECAP_HLD2,Input Capture Counter Hold Register 2"
hexmask.long.tbyte 0xC 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HLDx.."
line.long 0x10 "ECAP_CNTCMP,Input Capture Counter Compare Register"
hexmask.long.tbyte 0x10 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register\n"
line.long 0x14 "ECAP_CTL0,Input Capture Control Register 0"
bitfld.long 0x14 30. "CAPPHGEN,Input Capture Flag Trigger PWM Phase Change Function Enable Control\n" "0: CAPTF2 or CAPTF1 or CAPTF0 trigger PWM phase..,1: CAPTF2 or CAPTF1 or CAPTF0 trigger PWM phase.."
bitfld.long 0x14 29. "CAPEN,Input Capture Timer/Counter Enable Control\n" "0: Input Capture function Disabled,1: Input Capture function Enabled"
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bitfld.long 0x14 28. "CMPEN,The Compare Function Enable Control\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CAPCMPF will be set.\n" "0: Compare function Disabled,1: Compare function Enabled"
bitfld.long 0x14 27. "RLDEN,The Reload Function Enable Control\nSetting this bit to enable reload function. If the reload control is enabled an overflow event (CAPOVF) or capture events (CAPTFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.\n" "0: Reload function Disabled,1: Reload function Enabled"
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bitfld.long 0x14 26. "CPTCLR,Input Capture Counter Clear by Capture Events Control\nIf this bit is set to 1 the capture counter (ECAP_CNT) will be cleared to 0 when any one of capture events (CAPTF0~3) occurs.\n" "0: Capture events (CAPTF0~3) can clear capture..,1: Capture events (CAPTF0~3) can clear capture.."
bitfld.long 0x14 25. "CMPCLR,Input Capture Counter Clear by Compare-match Control\n" "0: Compare-match event (CAMCMPF) can clear capture..,1: Compare-match event (CAMCMPF) can clear capture.."
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bitfld.long 0x14 24. "CPTST,Input Capture Counter Start Bit\nSetting this bit to 1 the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK). \n" "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
bitfld.long 0x14 21. "CAPCMPIEN,Enable CAPCMPF Trigger Input Capture Interrupt\n" "0: Disabling flag CAPCMPF can trigger Input Capture..,1: Enabling flag CAPCMPF can trigger Input Capture.."
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bitfld.long 0x14 20. "CAPOVIEN,Enable CAPOVF Trigger Input Capture Interrupt\n" "0: Disabling flag CAPOVF can trigger Input Capture..,1: Enabling flag CAPOVF can trigger Input Capture.."
bitfld.long 0x14 18. "CAPTF2IEN,Enable Input Capture Channel 2 Interrupt\n" "0: Disabling flag CAPTF2 can trigger Input Capture..,1: Enabling flag CAPTF2 can trigger Input Capture.."
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bitfld.long 0x14 17. "CAPTF1IEN,Enable Input Capture Channel 1 Interrupt\n" "0: Disabling flag CAPTF1 can trigger Input Capture..,1: Enabling flag CAPTF1 can trigger Input Capture.."
bitfld.long 0x14 16. "CAPTF0IEN,Enable Input Capture Channel 0 Interrupt\n" "0: Disabling flag CAPTF0 can trigger Input Capture..,1: Enabling flag CAPTF0 can trigger Input Capture.."
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bitfld.long 0x14 12.--13. "CAP2SEL,CAP2 Input Source Selection\n" "0: CAP2 input is from port pin ECAP_P2,1: CAP2 input is from signal ACMP0_O (Analog..,?,?"
bitfld.long 0x14 10.--11. "CAP1SEL,CAP1 Input Source Selection\n" "0: CAP1 input is from port pin ECAP_P1,1: CAP1 input is from signal ACMP0_O (Analog..,?,?"
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bitfld.long 0x14 8.--9. "CAP0SEL,CAP0 Input Source Selection\n" "0: CAP0 input is from port pin ECAP_P0,1: CAP0 input is from signal ACMP0_O (Analog..,?,?"
bitfld.long 0x14 6. "IC2EN,Enable Port Pin IC2 Input to Input Capture Unit\n" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
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bitfld.long 0x14 5. "IC1EN,Enable Port Pin IC1 Input to Input Capture Unit\n" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
bitfld.long 0x14 4. "IC0EN,Enable Port Pin IC0 Input to Input Capture Unit\n" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
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bitfld.long 0x14 3. "CAPNFDIS,Disable Input Capture Noise Filter\n" "0: Noise filter of Input Capture Enabled,1: The noise filter of Input Capture Disabled"
bitfld.long 0x14 0.--1. "NFCLKS,Noise Filter Clock Pre-divided Selection\nTo determine the sampling frequency of the Noise Filter clock \n" "0: CAPCLK,1: CAPCLK / 2,?,?"
line.long 0x18 "ECAP_CTL1,Input Capture Control Register 1"
bitfld.long 0x18 16.--17. "CNTSRC,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source\n" "0: CAPCLK (Default),1: CAP0,?,?"
bitfld.long 0x18 12.--14. "CAPDIV,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with four divided options controlled by CAPDIV[2:0].\n" "0: CAPCLK / 1,1: CAPCLK / 4,?,?,?,?,?,?"
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bitfld.long 0x18 8.--10. "CPRLDS,ECAP_CNT Reload Trigger Source Selection\n" "0: CAPTF0,1: CAPTF1,?,?,?,?,?,?"
bitfld.long 0x18 4.--5. "CAPEDG2,Channel 2 Captured Edge Selection\nInput capture can detect falling edge change only rising edge change only or one of both edge change \n" "0: Detect rising edge,1: Detect falling edge,?,?"
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bitfld.long 0x18 2.--3. "CAPEDG1,Channel 1 Captured Edge Selection\nInput capture can detect falling edge change only rising edge change only or one of both edge change \n" "0: Detect rising edge,1: Detect falling edge,?,?"
bitfld.long 0x18 0.--1. "CAPEDG0,Channel 0 Captured Edge Selection\nInput capture can detect falling edge change only rising edge change only or one of both edge change \n" "0: Detect rising edge,1: Detect falling edge,?,?"
line.long 0x1C "ECAP_STS,Input Capture Status Register"
bitfld.long 0x1C 10. "ECAP2,Input Capture Pin 2 Status\nInput capture pin 2 (ECAP_P2) status. It is read only." "0,1"
bitfld.long 0x1C 9. "ECAP1,Input Capture Pin 1 Status\nInput capture pin 1 (ECAP_P1) status. It is read only." "0,1"
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bitfld.long 0x1C 8. "ECAP0,Input Capture Pin 0 Status\nInput capture pin 0 (ECAP_P0) status. It is read only." "0,1"
bitfld.long 0x1C 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (CNT) overflows from 0x00FF_FFFF to 0.\nNote: This bit is only cleared by writing 1 to itself through software." "0: No overflow occurs in CNT,1: CNT overflows"
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bitfld.long 0x1C 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled the flag is set by hardware while capture counter (CNT) up counts and reach to the CNTCMP value.\nNote: This bit is only cleared by writing 1 to itself through.." "0: CNT does not match with CNTCMP value,1: CNT counts to the same as CNTCMP value"
bitfld.long 0x1C 2. "CAPTF2,Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to itself through software." "0: No valid edge change is detected at CAP2 input,1: A valid edge change is detected at CAP2 input"
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bitfld.long 0x1C 1. "CAPTF1,Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to itself through software." "0: No valid edge change is detected at CAP1 input,1: A valid edge change is detected at CAP1 input"
bitfld.long 0x1C 0. "CAPTF0,Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to itself through software." "0: No valid edge change is detected at CAP0 input,1: A valid edge change is detected at CAP0 input"
tree.end
tree "EPWM (Enhanced PWM Generator)"
base ad:0x40040000
group.long 0x0++0xF
line.long 0x0 "EPWM_NPCTL,EPWM Negative Polarity Control Register"
bitfld.long 0x0 5. "NEGPOLAR5,PWM5 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n" "0: PWM output is active high,1: PWM output is active low"
bitfld.long 0x0 4. "NEGPOLAR4,PWM4 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n" "0: PWM output is active high,1: PWM output is active low"
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bitfld.long 0x0 3. "NEGPOLAR3,PWM3 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n" "0: PWM output is active high,1: PWM output is active low"
bitfld.long 0x0 2. "NEGPOLAR2,PWM2 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n" "0: PWM output is active high,1: PWM output is active low"
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bitfld.long 0x0 1. "NEGPOLAR1,PWM1 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n" "0: PWM output is active high,1: PWM output is active low"
bitfld.long 0x0 0. "NEGPOLAR0,PWM0 Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n" "0: PWM output is active high,1: PWM output is active low"
line.long 0x4 "EPWM_CLKDIV,EPWM Clock Select Register"
hexmask.long.byte 0x4 0.--3. 1. "CLKDIV,EPWM Clock Divider (9 Step Divider)\nSelect clock input for PWM timer\n"
line.long 0x8 "EPWM_CTL,EPWM Control Register"
bitfld.long 0x8 31. "CNTTYPE,PWM Aligned Type Selection\n" "0: Edge-aligned type,1: Center-aligned type"
bitfld.long 0x8 30. "GROUPEN,Group Bit\n" "0: The signals timing of PWM0 PWM2 and PWM4 are..,1: Unify the signals timing of PWM0 PWM2 and PWM4.."
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bitfld.long 0x8 28.--29. "MODE,PWM Operating Mode Selection\n" "0: Independent mode,1: Complementary mode,?,?"
bitfld.long 0x8 27. "CNTCLR,Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware." "0: Do not clear PWM counter,1: 16-bit PWM counter cleared to 0x000"
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bitfld.long 0x8 26. "DTCNT45,Dead-zone 4 Generator Enable/Disable (PWM4 and PWM5 Pair for PWM Group)\nNote: When the dead-zone generator is enabled the pair of PWM4 and PWM5 becomes a complementary pair for PWM group." "0: Dead-zone 4 Generator Disabled,1: Dead-zone 4 Generator Enabled"
bitfld.long 0x8 25. "DTCNT23,Dead-zone 2 Generator Enable/Disable (PWM2 and PWM3 Pair for PWM Group)\nNote: When the dead-zone generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair for PWM group." "0: Dead-zone 2 Generator Disabled,1: Dead-zone 2 Generator Enabled"
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bitfld.long 0x8 24. "DTCNT01,Dead-zone 0 Generator Enable/Disable (PWM0 and PWM1 Pair for PWM Group)\nNote: When the dead-zone generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair for PWM group." "0: Dead-zone 0 Generator Disabled,1: Dead-zone 0 Generator Enabled"
bitfld.long 0x8 23. "DBGTRIOFF,PWM Debug Mode Configuration Bit (Available in DEBUG Mode Only)\n" "0: Safe mode: The timer is frozen and PWM outputs..,1: Normal mode: The timer continues to operate.."
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bitfld.long 0x8 20. "ASYMEN,Asymmetric Mode in Center-aligned Type \n" "0: Symmetric mode in center-aligned type,1: Asymmetric mode in center-aligned type"
bitfld.long 0x8 16.--17. "HCUPDT,Half Cycle Update Enable for Center-aligned Type\n" "0: Update PERIOD CMP at pwm_counter = PERIOD (Period),1: Update PERIOD CMP at pwm_counter = 0,?,?"
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bitfld.long 0x8 8. "CNTMODE,PWM-timer Auto-reload/One-shot Mode\n" "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 5. "CNTEN5,PWM-timer 5 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
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bitfld.long 0x8 4. "CNTEN4,PWM-timer 4 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
bitfld.long 0x8 3. "CNTEN3,PWM-timer 3 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
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bitfld.long 0x8 2. "CNTEN2,PWM-timer 2 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
bitfld.long 0x8 1. "CNTEN1,PWM-timer 1 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
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bitfld.long 0x8 0. "CNTEN0,PWM-timer 0 Enable/Disable Start Run\n" "0: Corresponding PWM-timer running Stopped,1: Corresponding PWM-timer start run Enabled"
line.long 0xC "EPWM_PERIOD,EPWM Period Counter Register"
hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Counter/Timer Loaded Value\nPERIODn determines the PWM Period.\nEdge-aligned mode: where xy could be 01 23 45 depending on the selected PWM channel.\nNote: Any write to PERIODn will take effect in next PWM cycle."
group.long 0x24++0x17
line.long 0x0 "EPWM_CMPDAT0,EPWM Comparator Register 0"
hexmask.long.word 0x0 16.--31. 1. "CMPU,PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode\nCMPU PERIOD: @ up counter PWM output is keep to Max. duty.\n"
hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM Duty.\nEdge-aligned mode: where xy could be 01 23 45 depending on the selected PWM channel.\nNote: Any write to CMPn will take effect in next PWM cycle."
line.long 0x4 "EPWM_CMPDAT1,EPWM Comparator Register 1"
hexmask.long.word 0x4 16.--31. 1. "CMPU,PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode\nCMPU PERIOD: @ up counter PWM output is keep to Max. duty.\n"
hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM Duty.\nEdge-aligned mode: where xy could be 01 23 45 depending on the selected PWM channel.\nNote: Any write to CMPn will take effect in next PWM cycle."
line.long 0x8 "EPWM_CMPDAT2,EPWM Comparator Register 2"
hexmask.long.word 0x8 16.--31. 1. "CMPU,PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode\nCMPU PERIOD: @ up counter PWM output is keep to Max. duty.\n"
hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM Duty.\nEdge-aligned mode: where xy could be 01 23 45 depending on the selected PWM channel.\nNote: Any write to CMPn will take effect in next PWM cycle."
line.long 0xC "EPWM_CMPDAT3,EPWM Comparator Register 3"
hexmask.long.word 0xC 16.--31. 1. "CMPU,PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode\nCMPU PERIOD: @ up counter PWM output is keep to Max. duty.\n"
hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM Duty.\nEdge-aligned mode: where xy could be 01 23 45 depending on the selected PWM channel.\nNote: Any write to CMPn will take effect in next PWM cycle."
line.long 0x10 "EPWM_CMPDAT4,EPWM Comparator Register 4"
hexmask.long.word 0x10 16.--31. 1. "CMPU,PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode\nCMPU PERIOD: @ up counter PWM output is keep to Max. duty.\n"
hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM Duty.\nEdge-aligned mode: where xy could be 01 23 45 depending on the selected PWM channel.\nNote: Any write to CMPn will take effect in next PWM cycle."
line.long 0x14 "EPWM_CMPDAT5,EPWM Comparator Register 5"
hexmask.long.word 0x14 16.--31. 1. "CMPU,PWM Comparator Register for UP Counter in Center-aligned Asymmetric Mode\nCMPU PERIOD: @ up counter PWM output is keep to Max. duty.\n"
hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register\nCMP determines the PWM Duty.\nEdge-aligned mode: where xy could be 01 23 45 depending on the selected PWM channel.\nNote: Any write to CMPn will take effect in next PWM cycle."
rgroup.long 0x3C++0x3
line.long 0x0 "EPWM_CNT,EPWM Data Register"
bitfld.long 0x0 31. "CNTDIR,PWM Counter (Up/Down) Direction\n" "0: PWM counter is down counting,1: PWM counter is up counting"
hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register\nUser can monitor CNT to know the current value in 16-bit down counter."
group.long 0x54++0x13
line.long 0x0 "EPWM_INTEN,EPWM Interrupt Enable Register"
bitfld.long 0x0 29. "CMPDIEN5,PWM Channel 5 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n" "0: Interrupt compare Disabled,1: Interrupt when EPWM_CH5 PWM DOWN counter reaches.."
bitfld.long 0x0 28. "CMPDIEN4,PWM Channel 4 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n" "0: Interrupt compare Disabled,1: interrupt when EPWM_CH4 PWM DOWN counter reaches.."
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bitfld.long 0x0 27. "CMPDIEN3,PWM Channel 3 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n" "0: Interrupt compare Disabled,1: interrupt when EPWM_CH3 PWM DOWN counter reaches.."
bitfld.long 0x0 26. "CMPDIEN2,PWM Channel 2 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n" "0: Interrupt compare Disabled,1: interrupt when EPWM_CH2 PWM DOWN counter reaches.."
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bitfld.long 0x0 25. "CMPDIEN1,PWM Channel 1 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n" "0: Interrupt compare Disabled,1: interrupt when EPWM_CH1 PWM DOWN counter reaches.."
bitfld.long 0x0 24. "CMPDIEN0,PWM Channel 0 DOWN Interrupt Enable Control\nDOWN for Edge-aligned and Center-aligned\n" "0: Interrupt compare Disabled,1: interrupt when EPWM_CH0 PWM DOWN counter reaches.."
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bitfld.long 0x0 18. "CIEN,PWM Central Interrupt Enable Control\nfor Center-aligned only \n" "0: Interrupt when EPWM Central Enabled,1: Interrupt when EPWM Central Enabled"
bitfld.long 0x0 17. "BRK1IEN,Fault Brake1 Interrupt Enable Control\n" "0: BRK1IF trigger PWM interrupt Disabed,1: BRK1IF trigger PWM interrupt Enabled"
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bitfld.long 0x0 16. "BRK0IEN,Fault Brake0 Interrupt Enable Control\n" "0: BRK0IF trigger PWM interrupt Disabled,1: BRK0IF trigger PWM interrupt Enabled"
bitfld.long 0x0 13. "CMPUIEN5,PWM Channel 5 UP Interrupt Enable Control\nUP for Center-aligned only\n" "0: PWM Channel 5 UP Interrupt Disabled,1: Interrupt when EPWM_CH5 PWM UP counter reaches.."
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bitfld.long 0x0 12. "CMPUIEN4,PWM Channel 4 UP Interrupt Enable Control\nUP for Center-aligned only\n" "0: EPWM_CH4 PWM UP counter reaches EPWM_CMPDAT4..,1: EPWM_CH4 PWM UP counter reaches EPWM_CMPDAT4.."
bitfld.long 0x0 11. "CMPUIEN3,PWM Channel 3 UP Interrupt Enable Control\nUP for Center-aligned only\n" "0: EPWM_CH3 PWM UP counter reaches EPWM_CMPDAT3..,1: EPWM_CH3 PWM UP counter reaches EPWM_CMPDAT3.."
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bitfld.long 0x0 10. "CMPUIEN2,PWM Channel 2 UP Interrupt Enable Control\nUP for Center-aligned only\n" "0: EPWM_CH2 PWM UP counter reaches EPWM_CMPDAT2..,1: EPWM_CH2 PWM UP counter reaches EPWM_CMPDAT2.."
bitfld.long 0x0 9. "CMPUIEN1,PWM Channel 1 UP Interrupt Enable Control\nUP for Center-aligned only\n" "0: EPWM_CH1 PWM UP counter reaches EPWM_CMPDAT1..,1: EPWM_CH1 PWM UP counter reaches EPWM_CMPDAT1.."
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bitfld.long 0x0 8. "CMPUIEN0,PWM Channel 0 UP Interrupt Enable Control\nUP for Center-aligned only\n" "0: EPWM_CH0 PWM UP counter reaches EPWM_CMPDAT0..,1: EPWM_CH0 PWM UP counter reaches EPWM_CMPDAT0.."
bitfld.long 0x0 0. "PIEN,PWM Channel 0 Period Interrupt Enable Control\nfor Edge-aligned and Center-aligned \n" "0: EPWM Period interrupt Disabled,1: EPWM Period interrupt Enabled"
line.long 0x4 "EPWM_INTSTS,EPWM Interrupt Status Register"
bitfld.long 0x4 29. "CMPDIF5,PWM Channel 5 DOWN Interrupt Flag\nFlag is set by hardware when a channel 5 PWM DOWN counter reaches EPWM_CMPDAT5. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 28. "CMPDIF4,PWM Channel 4 DOWN Interrupt Flag\nFlag is set by hardware when a channel 4 PWM DOWN counter reaches EPWM_CMPDAT4. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 27. "CMPDIF3,PWM Channel 3 DOWN Interrupt Flag\nFlag is set by hardware when a channel 3 PWM DOWN counter reaches EPWM_CMPDAT3. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 26. "CMPDIF2,PWM Channel 2 DOWN Interrupt Flag\nFlag is set by hardware when a channel 2 PWM DOWN counter reaches EPWM_CMPDAT2. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 25. "CMPDIF1,PWM Channel 1 DOWN Interrupt Flag\nFlag is set by hardware when a channel 1 PWM DOWN counter reaches EPWM_CMPDAT1. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 24. "CMPDIF0,PWM Channel 0 DOWN Interrupt Flag\nFlag is set by hardware when a channel 0 PWM DOWN counter reaches EPWM_CMPDAT0. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 18. "CIF,PWM Channel 0 Central Interrupt Flag\nFlag is set by hardware when PWM down counter reaches zero point. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 17. "BRK1IF,PWM Brake1 Flag\nNote: Software can write 1 to clear this bit." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.."
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bitfld.long 0x4 16. "BRK0IF,PWM Brake0 Flag\nNote: Software can write 1 to clear this bit." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.."
bitfld.long 0x4 13. "CMPUIF5,PWM Channel 5 UP Interrupt Flag\nFlag is set by hardware when a channel 5 PWM UP counter reaches PWM_CMPDAT5. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 12. "CMPUIF4,PWM Channel 4 UP Interrupt Flag\nFlag is set by hardware when a channel 4 PWM UP counter reaches PWM_CMPDAT4. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 11. "CMPUIF3,PWM Channel 3 UP Interrupt Flag\nFlag is set by hardware when a channel 3 PWMUP counter reaches PWM_CMPDAT3. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 10. "CMPUIF2,PWM Channel 2 UP Interrupt Flag\nFlag is set by hardware when a channel 2 PWM UP counter reaches PWM_CMPDAT2. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 9. "CMPUIF1,PWM Channel 1 UP Interrupt Flag\nFlag is set by hardware when a channel 1 PWM UP counter reaches PWM_CMPDAT1. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x4 8. "CMPUIF0,PWM Channel 0 UP Interrupt Flag\nFlag is set by hardware when a channel 0 PWM UP counter reaches PWM_CMPDAT0. Software can write 1 to clear this bit." "0,1"
bitfld.long 0x4 0. "PIF,PWM Channel 0 Period Interrupt Flag\nEdge-aligned mode:\nFlag is set by hardware when PWM down counter reaches zero point. \nCenter-aligned mode:\nFlag is set by hardware when PWM down counter reaches zero point and then up counter reaches.." "0,1"
line.long 0x8 "EPWM_RESDLY,EPWM BRK Low Voltage Detect Resume Delay"
hexmask.long.word 0x8 0.--11. 1. "DELAY,PWM BRK Low Voltage Detect Resume Delay\n12 bits Down-Counter"
line.long 0xC "EPWM_BRKCTL,EPWM Fault Brake Control Register"
bitfld.long 0xC 31. "NFPEN,Noise Filter for External Brake Input Pin (BRAKE) Enable Control\n" "0: Noise Filter for External Brake Input Pin..,1: Noise Filter for External Brake Input Pin.."
bitfld.long 0xC 29. "BKOD5,PWM Channel 5 Brake Output Selection\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
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bitfld.long 0xC 28. "BKOD4,PWM Channel 4 Brake Output Selection\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 27. "BKOD3,PWM Channel 3 Brake Output Selection\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
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bitfld.long 0xC 26. "BKOD2,PWM Channel 2 Brake Output Selection\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 25. "BKOD1,PWM Channel 1 Brake Output Selection\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
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bitfld.long 0xC 24. "BKOD0,PWM Channel 0 Brake Output Selection\n" "0: PWM output low when fault brake conditions..,1: PWM output high when fault brake conditions.."
bitfld.long 0xC 15. "LVDTYPE,Low-level Detection Resume Type\n" "0: Brake resume at BRK resume delay counter..,1: Brake resume at period edge"
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bitfld.long 0xC 14. "LVDBKEN,Low-level Detection Trigger PWM Brake Function 1 Enable Control\n" "0: Brake Function 1 triggered by Low-level..,1: Brake Function 1 triggered by Low-level.."
bitfld.long 0xC 13. "BRK1PEN,BRK1 Source From External Pin Enable Control\n" "0: BRK1 Source From External Pin Disabled,1: BRK1 Source From External Pin Enabled"
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bitfld.long 0xC 12. "BK1ADCEN,BRK1 Source From ADC Enable Control\n" "0: BRK1 Source From ADC Disabled,1: BRK1 Source From ADC Enabled"
bitfld.long 0xC 11. "BRK1A1EN,BRK1 Source From ACMP1 Enable Control\n" "0: BRK1 Source From ACMP1 Disabled,1: BRK1 Source From ACMP1 Enabled"
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bitfld.long 0xC 10. "BRK1A0EN,BRK1 Source From ACMP0 Enable Control\n" "0: BRK1 Source From ACMP0 Disabled,1: BRK1 Source From ACMP0 Enabled"
bitfld.long 0xC 9. "SWBRK,Software Break\n" "0: Software break and back to normal PWM function..,1: Issue Software break Enabled"
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bitfld.long 0xC 5. "BRK0PEN,BRK0 Source From External Pin Enable Control\n" "0: BRK0 Source From External Pin Disabled,1: BRK0 Source From External Pin Enabled"
bitfld.long 0xC 4. "BK0ADCEN,BRK0 Source From ADC Enable Control\n" "0: BRK0 Source From ADC Disabled,1: BRK0 Source From ADC Enabled"
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bitfld.long 0xC 3. "BRK0A1EN,BRK0 Source From ACMP1 Enable Control\n" "0: BRK0 Source From ACMP1 Disabled,1: BRK0 Source From ACMP1 Enabled"
bitfld.long 0xC 2. "BRK0A0EN,BRK0 Source From ACMP0 Enable Control\n" "0: BRK0 Source From ACMP0 Disabled,1: BRK0 Source From ACMP0 Enabled"
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bitfld.long 0xC 1. "BRK1EN,Brake1 Function Enable Control\n" "0: Brake1 detect function Disabled,1: Brake1 detect function Enabled"
bitfld.long 0xC 0. "BRK0EN,Brake0 Function Enable Control\n" "0: Brake0 detect function Disabled,1: Brake0 detect function Enabled"
line.long 0x10 "EPWM_DTCTL,EPWM Dead-zone Interval Register"
hexmask.long.byte 0x10 16.--23. 1. "DTCNT45,Dead-zone Interval Register for Pair of Channel4 and Channel5 (PWM4 and PWM5 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits."
hexmask.long.byte 0x10 8.--15. 1. "DTCNT23,Dead-zone Interval Register for Pair of Channel2 and Channel3 (PWM2 and PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits."
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hexmask.long.byte 0x10 0.--7. 1. "DTCNT01,Dead-zone Interval Register for Pair of Channel0 and Channel1 (PWM0 and PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding EPWM_CLKDIV bits."
group.long 0x78++0xF
line.long 0x0 "EPWM_PHCHG,EPWM Phase Changed Register"
bitfld.long 0x0 29. "ACMP1TEN,ACMP1 Trigger Function Enable Control\n" "0: ACMP1 trigger PWM function Disabled,1: ACMP1 trigger PWM function Enabled"
bitfld.long 0x0 28. "ACMP0TEN,ACMP0 Trigger Function Enable Control\n" "0: ACMP0 trigger PWM function Disabled,1: ACMP0 trigger PWM function Enabled"
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bitfld.long 0x0 26.--27. "A1POSSEL,Alternative Comparator 1 Positive Input Selection\nSelect the positive input source of ACMP1.\n" "0: Select ACMP1_P0 (PC.0) as the input of ACMP1,1: Select ACMP1_P1 (PC.1) as the input of ACMP1,?,?"
bitfld.long 0x0 24.--25. "A0POSSEL,Alternative Comparator 0 Positive Input Selection\nSelect the positive input source of ACMP0.\n" "0: Select ACMP0_P0 (PB.0) as the input of ACMP0,1: Select ACMP0_P1 (PB.1) as the input of ACMP0,?,?"
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bitfld.long 0x0 20.--22. "TRGSEL,Phase Change Trigger Selection\nSelect the trigger condition to load PHCHG from PHCHG_NXT.\nWhen the trigger condition occurs it will load PHCHG_NOW with PHCHG_NXT.\nPhase Change: PWM outputs are masked according with the definition of MSKENn and.." "0: Triggered by Timer0 event,1: Triggered by Timer1 event,?,?,?,?,?,?"
bitfld.long 0x0 13. "MSKEN5,Enable PWM5 Mask Function\n" "0: PWM5 Mask Function Disabled,1: PWM5 Mask Function Enabled"
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bitfld.long 0x0 12. "MSKEN4,Enable PWM4 Mask Function\n" "0: PWM4 Mask Function Disabled,1: PWM4 Mask Function Enabled"
bitfld.long 0x0 11. "MSKEN3,Enable PWM3 Mask Function\n" "0: PWM3 Mask Function Disabled,1: PWM3 Mask Function Enabled"
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bitfld.long 0x0 10. "MSKEN2,Enable PWM2 Mask Function\n" "0: PWM2 Mask Function Disabled,1: PWM2 Mask Function Enabled"
bitfld.long 0x0 9. "MSKEN1,Enable PWM1 Mask Function\n" "0: PWM1 Mask Function Disabled,1: PWM1 Mask Function Enabled"
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bitfld.long 0x0 8. "MSKEN0,Enable PWM0 Mask Function\n" "0: PWM0 Mask Function Disabled,1: PWM0 Mask Function Enabled"
bitfld.long 0x0 5. "MSKDAT5,Enable PWM5 Mask Data\n" "0: PWM5 state is masked with zero,1: PWM5 state is masked with one"
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bitfld.long 0x0 4. "MSKDAT4,Enable PWM4 Mask Data\n" "0: PWM4 state is masked with zero,1: PWM4 state is masked with one"
bitfld.long 0x0 3. "MSKDAT3,Enable PWM3 Mask Data\n" "0: PWM3 state is masked with zero,1: PWM3 state is masked with one"
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bitfld.long 0x0 2. "MSKDAT2,Enable PWM2 Mask Data\n" "0: PWM2 state is masked with zero,1: PWM2 state is masked with one"
bitfld.long 0x0 1. "MSKDAT1,Enable PWM1 Mask Data\n" "0: PWM1 state is masked with zero,1: PWM1 state is masked with one"
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bitfld.long 0x0 0. "MSKDAT0,Enable PWM0 Mask Data\n" "0: PWM0 state is masked with zero,1: PWM0 state is masked with one"
line.long 0x4 "EPWM_PHCHGNXT,EPWM Next Phase Change Register"
bitfld.long 0x4 29. "ACMP1TEN,ACMP1 Trigger Function Control Preset Bit\nThis bit will be load to bit ACMP1TEN in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
bitfld.long 0x4 28. "ACMP0TEN,ACMP0 Trigger Function Control Preset Bit\nThis bit will be load to bit ACMP0TEN in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
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bitfld.long 0x4 26.--27. "A1POSSEL,Alternative Comparator 1 Positive Input Selection Preset Bits\nThis bit field will be load to bit field A1POSSEL in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1,2,3"
bitfld.long 0x4 24.--25. "A0POSSEL,Alternative Comparator 0 Positive Input Selection Preset Bits\nThis bit field will be load to bit field A0POSSEL in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1,2,3"
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bitfld.long 0x4 20.--22. "TRGSEL,Phase Change Trigger Selection Preset Bits\nThis bit field will be load to bit field TRGSEL in PHCHG_NOW when load trigger condition occurs.\nRefer to register EPWM_PHCHG for detailed definition." "0: Triggered by Timer0 event,1: Triggered by Timer1 event,?,?,?,?,?,?"
bitfld.long 0x4 16.--18. "HALLSTS,Predicted Next HALL State\nThis bit field indicates the predicted hall state at next commutation. \nthe hardware will compare bits (CAP2 CAP1 CAP0) in timer 2 with HALLSTS [2:0] when any hall state change occurs.\nIf the comparison is matched.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 13. "MSKEN5,Enable PWM5 Mask Function Preset Bit\nThis bit will be load to bit MSKEN5 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
bitfld.long 0x4 12. "MSKEN4,Enable PWM4 Mask Function Preset Bit\nThis bit will be load to bit MSKEN4 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
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bitfld.long 0x4 11. "MSKEN3,Enable PWM3 Mask Function Preset Bit\nThis bit will be load to bit MSKEN3 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
bitfld.long 0x4 10. "MSKEN2,Enable PWM2 Mask Function Preset Bit\nThis bit will be load to bit MSKEN2 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
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bitfld.long 0x4 9. "MSKEN1,Enable PWM1 Mask Function Preset Bit\nThis bit will be load to bit MSKEN1 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
bitfld.long 0x4 8. "MSKEN0,Enable PWM0 Mask Function Preset Bit\nThis bit will be load to bit MSKEN0 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
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bitfld.long 0x4 5. "MSKDAT5,Enable PWM5 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT5 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
bitfld.long 0x4 4. "MSKDAT4,Enable PWM4 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT4 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
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bitfld.long 0x4 3. "MSKDAT3,Enable PWM3 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT3 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
bitfld.long 0x4 2. "MSKDAT2,Enable PWM2 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT2 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
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bitfld.long 0x4 1. "MSKDAT1,Enable PWM1 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT1 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
bitfld.long 0x4 0. "MSKDAT0,Enable PWM0 Mask Data Preset Bit\nThis bit will be load to bit MSKDAT0 in PHCHG_NOW when load trigger condition occurs. \nRefer to register PHCHG_NOW for detailed definition." "0,1"
line.long 0x8 "EPWM_PHCHGALT,EPWM Phase Change Alternative Control Register"
bitfld.long 0x8 1. "POSCTL1,Positive Input Control for ACMP1\nNote: Register ACMP_CTL1 is describe in Comparator Controller chapter" "0: The input of ACMP1 is controlled by ACMP_CTL1,1: The input of ACMP1 is controlled by A1POSSEL in.."
bitfld.long 0x8 0. "POSCTL0,Positive Input Control for ACMP0\nNote: Register ACMP_CTL0 is describe in Comparator Controller chapter" "0: The input of ACMP0 is controlled by ACMP_CTL0,1: The input of ACMP0 is controlled by A0POSSEL in.."
line.long 0xC "EPWM_IFA,EPWM Period Interrupt Accumulation Control Register"
hexmask.long.byte 0xC 12.--15. 1. "IFDAT,Period Interrupt Down-counter Data Register (Read Only)\nWhen IFAEN is set IFDAT will decrease when every PWM Interrupt flag is set \n and when IFDAT reaches 0 the PWM interrupt will occurred and IFCNT will reload to IFDAT."
hexmask.long.byte 0xC 4.--7. 1. "IFCNT,Period Interrupt Accumulation Counter Value Setting Register (Write Only)\n16 step Down-Counter value setting register.\nWhen IFAEN is set IFCNT value will load into IFDAT and decrase gradually."
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bitfld.long 0xC 0. "IFAEN,Enable Period Interrupt Accumulation Function\n" "0: Period Interrupt Accumulation Disabled,1: Period Interrupt Accumulation Enabled"
tree.end
tree "FMC (Flash Memory Controller)"
base ad:0x5000C000
group.long 0x0++0x13
line.long 0x0 "FMC_ISPCTL,ISP Control Register"
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) SPROM writes to itself.." "0,1"
bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Control (Write Protect)\n" "0: LDROM cannot be updated,1: LDROM can be updated when the MCU runs in APROM"
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bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Control (Write Protect)\nWriting this bit to 1 enables software to update CONFIG value by ISP register control procedure regardless of program code is running in APROM or LDROM.\n" "0: ISP update User Configuration Disabled,1: ISP update User Configuration Enabled"
bitfld.long 0x0 3. "APUEN,APROM Update Enable Control (Write Protect)\n" "0: APROM cannot be updated when chip runs in APROM,1: APROM can be updated when chip runs in APROM"
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bitfld.long 0x0 2. "SPUEN,SPROM Update Enable Control (Write Protect)\n" "0: SPROM cannot be updated,1: SPROM can be updated when the MCU runs in APROM"
bitfld.long 0x0 1. "BS,Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Boot from APROM,1: Boot from LDROM"
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bitfld.long 0x0 0. "ISPEN,ISP Enable Control (Write Protect)\nSet this bit to enable ISP function.\n" "0: ISP function Disabled,1: ISP function Enabled"
line.long 0x4 "FMC_ISPADDR,ISP Address Register"
hexmask.long 0x4 0.--31. 1. "ISPADR,ISP Address\nThe NM1120 series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation."
line.long 0x8 "FMC_ISPDAT,ISP Data Register"
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation."
line.long 0xC "FMC_ISPCMD,ISP Command Register"
hexmask.long.byte 0xC 0.--5. 1. "CMD,ISP Command \nISP commands are shown below:\n"
line.long 0x10 "FMC_ISPTRG,ISP Trigger Register"
bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n" "0: ISP operation is finished,1: ISP operation is progressed"
rgroup.long 0x14++0x3
line.long 0x0 "FMC_DFBA,Data Flash Start Address"
hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash start address is defined by user. Since on chip flash erase unit is 512 bytes it is mandatory to keep bit 8-0 as 0."
group.long 0x40++0x3
line.long 0x0 "FMC_ISPSTS,ISP Status Register"
bitfld.long 0x0 29.--31. "SCODE,Security Code Active Flag\nThis bit field set by hardware when detecting SPROM secured code is active at flash initiation or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation.\n" "0: SPROM0/1/2 secured code are inactive,1: SPROM0 secured code is active,?,?,?,?,?,?"
hexmask.long.word 0x0 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}."
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) SPROM writes to itself.." "0,1"
rbitfld.long 0x0 1.--2. "CBS,Config Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0." "0,1,2,3"
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rbitfld.long 0x0 0. "ISPBUSY,ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with FMC_ISPTRG bit 0." "0: ISP operation is finished,1: ISP operation is progressed"
group.long 0x50++0x3
line.long 0x0 "FMC_CRCSEED,ISP CRC Seed Register"
hexmask.long 0x0 0.--31. 1. "CRCSEED,CRC Seed Data\nThis register was provided to be the initial value for CRC operation.\nWrite data to this register before ISP CRC operation.\nRead data from this register after ISP CRC read operation."
rgroup.long 0x54++0x3
line.long 0x0 "FMC_CRCCV,ISP CRC Current Value Register"
hexmask.long 0x0 0.--31. 1. "CRCCV,CRC Current Value\nThis register provided current value of CRC durning calculation."
tree.end
tree "GPIO (General-Purpose Input/Output)"
base ad:0x50004000
group.long 0x0++0xF
line.long 0x0 "PA_MODE,PA I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PA_DINOFF,PA Digital Input Path Disable Control"
bitfld.long 0x4 23. "DINOFF7,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PA_DOUT,PA Data Output Value"
bitfld.long 0x8 7. "DOUT7,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PA_DATMSK,PA Data Output Write Mask"
bitfld.long 0xC 7. "DATMSK7,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "PA_PIN,PA Pin Value"
bitfld.long 0x0 7. "PIN7,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
group.long 0x14++0x1F
line.long 0x0 "PA_DBEN,PA De-Bounce Enable Control Register"
bitfld.long 0x0 7. "DBEN7,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PA_INTTYPE,PA Interrupt Trigger Type Control"
bitfld.long 0x4 7. "TYPE7,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PA_INTEN,PA Interrupt Enable Control Register"
bitfld.long 0x8 23. "RHIEN7,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PA_INTSRC,PA Interrupt Source Flag"
bitfld.long 0xC 7. "INTSRC7,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PA_SMTEN,PA Input Schmitt Trigger Enable Register"
bitfld.long 0x10 7. "SMTEN7,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PA_SLEWCTL,PA High Slew Rate Control Register"
bitfld.long 0x14 7. "HSREN7,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 6. "HSREN6,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 4. "HSREN4,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 2. "HSREN2,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 1. "HSREN1,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 0. "HSREN0,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
line.long 0x18 "PA_PLEN,PA Pull-Low Control Register"
bitfld.long 0x18 7. "PLEN7,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 6. "PLEN6,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 5. "PLEN5,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 4. "PLEN4,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 3. "PLEN3,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 2. "PLEN2,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 1. "PLEN1,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 0. "PLEN0,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
line.long 0x1C "PA_PHEN,PA Pull-High Control Register"
bitfld.long 0x1C 7. "PHEN7,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 6. "PHEN6,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 5. "PHEN5,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 4. "PHEN4,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 3. "PHEN3,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 2. "PHEN2,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 1. "PHEN1,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 0. "PHEN0,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
group.long 0x40++0xF
line.long 0x0 "PB_MODE,PB I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PB_DINOFF,PB Digital Input Path Disable Control"
bitfld.long 0x4 23. "DINOFF7,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PB_DOUT,PB Data Output Value"
bitfld.long 0x8 7. "DOUT7,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PB_DATMSK,PB Data Output Write Mask"
bitfld.long 0xC 7. "DATMSK7,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x50++0x3
line.long 0x0 "PB_PIN,PB Pin Value"
bitfld.long 0x0 7. "PIN7,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
group.long 0x54++0x1F
line.long 0x0 "PB_DBEN,PB De-bounce Enable Control Register"
bitfld.long 0x0 7. "DBEN7,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PB_INTTYPE,PB Interrupt Trigger Type Control"
bitfld.long 0x4 7. "TYPE7,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PB_INTEN,PB Interrupt Enable Control Register"
bitfld.long 0x8 23. "RHIEN7,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PB_INTSRC,PB Interrupt Source Flag"
bitfld.long 0xC 7. "INTSRC7,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PB_SMTEN,PB Input Schmitt Trigger Enable Register"
bitfld.long 0x10 7. "SMTEN7,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PB_SLEWCTL,PB High Slew Rate Control Register"
bitfld.long 0x14 7. "HSREN7,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 6. "HSREN6,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 4. "HSREN4,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 2. "HSREN2,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 1. "HSREN1,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 0. "HSREN0,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
line.long 0x18 "PB_PLEN,PB Pull-low Control Register"
bitfld.long 0x18 7. "PLEN7,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 6. "PLEN6,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 5. "PLEN5,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 4. "PLEN4,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 3. "PLEN3,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 2. "PLEN2,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 1. "PLEN1,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 0. "PLEN0,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
line.long 0x1C "PB_PHEN,PB Pull-high Control Register"
bitfld.long 0x1C 7. "PHEN7,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 6. "PHEN6,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 5. "PHEN5,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 4. "PHEN4,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 3. "PHEN3,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 2. "PHEN2,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 1. "PHEN1,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 0. "PHEN0,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
group.long 0x80++0xF
line.long 0x0 "PC_MODE,PC I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PC_DINOFF,PC Digital Input Path Disable Control"
bitfld.long 0x4 23. "DINOFF7,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PC_DOUT,PC Data Output Value"
bitfld.long 0x8 7. "DOUT7,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PC_DATMSK,PC Data Output Write Mask"
bitfld.long 0xC 7. "DATMSK7,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x90++0x3
line.long 0x0 "PC_PIN,PC Pin Value"
bitfld.long 0x0 7. "PIN7,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
group.long 0x94++0x1F
line.long 0x0 "PC_DBEN,PC De-bounce Enable Control Register"
bitfld.long 0x0 7. "DBEN7,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PC_INTTYPE,PC Interrupt Trigger Type Control"
bitfld.long 0x4 7. "TYPE7,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PC_INTEN,PC Interrupt Enable Control Register"
bitfld.long 0x8 23. "RHIEN7,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PC_INTSRC,PC Interrupt Source Flag"
bitfld.long 0xC 7. "INTSRC7,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PC_SMTEN,PC Input Schmitt Trigger Enable Register"
bitfld.long 0x10 7. "SMTEN7,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PC_SLEWCTL,PC High Slew Rate Control Register"
bitfld.long 0x14 7. "HSREN7,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 6. "HSREN6,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 4. "HSREN4,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 2. "HSREN2,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 1. "HSREN1,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 0. "HSREN0,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
line.long 0x18 "PC_PLEN,PC Pull-low Control Register"
bitfld.long 0x18 7. "PLEN7,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 6. "PLEN6,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 5. "PLEN5,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 4. "PLEN4,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 3. "PLEN3,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 2. "PLEN2,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 1. "PLEN1,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 0. "PLEN0,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
line.long 0x1C "PC_PHEN,PC Pull-high Control Register"
bitfld.long 0x1C 7. "PHEN7,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 6. "PHEN6,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 5. "PHEN5,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 4. "PHEN4,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 3. "PHEN3,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 2. "PHEN2,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 1. "PHEN1,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 0. "PHEN0,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
group.long 0xC0++0xF
line.long 0x0 "PD_MODE,PD I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "PD_DINOFF,PD Digital Input Path Disable Control"
bitfld.long 0x4 23. "DINOFF7,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port A-D Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "PD_DOUT,PD Data Output Value"
bitfld.long 0x8 7. "DOUT7,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "PD_DATMSK,PD Data Output Write Mask"
bitfld.long 0xC 7. "DATMSK7,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0xD0++0x3
line.long 0x0 "PD_PIN,PD Pin Value"
bitfld.long 0x0 7. "PIN7,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 6. "PIN6,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 4. "PIN4,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 2. "PIN2,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 0. "PIN0,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
group.long 0xD4++0x1F
line.long 0x0 "PD_DBEN,PD De-bounce Enable Control Register"
bitfld.long 0x0 7. "DBEN7,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port A-D Pin[n] Input Signal De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "PD_INTTYPE,PD Interrupt Trigger Type Control"
bitfld.long 0x4 7. "TYPE7,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "PD_INTEN,PD Interrupt Enable Control Register"
bitfld.long 0x8 23. "RHIEN7,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Control\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Control\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "PD_INTSRC,PD Interrupt Source Flag"
bitfld.long 0xC 7. "INTSRC7,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation :\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
line.long 0x10 "PD_SMTEN,PD Input Schmitt Trigger Enable Register"
bitfld.long 0x10 7. "SMTEN7,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 6. "SMTEN6,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 4. "SMTEN4,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 2. "SMTEN2,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
bitfld.long 0x10 0. "SMTEN0,Port A-D Pin[n] Input Schmitt Trigger Enable Control\n" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
line.long 0x14 "PD_SLEWCTL,PD High Slew Rate Control Register"
bitfld.long 0x14 7. "HSREN7,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 6. "HSREN6,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 4. "HSREN4,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 2. "HSREN2,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 1. "HSREN1,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
bitfld.long 0x14 0. "HSREN0,Port A-D Pin[n] High Slew Rate Control\n" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
line.long 0x18 "PD_PLEN,PD Pull-low Control Register"
bitfld.long 0x18 7. "PLEN7,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 6. "PLEN6,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 5. "PLEN5,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 4. "PLEN4,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 3. "PLEN3,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 2. "PLEN2,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
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bitfld.long 0x18 1. "PLEN1,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
bitfld.long 0x18 0. "PLEN0,Port A-D Pull-low Resistor Control\n" "0: Pull-Low Resistor Disabled,1: Pull-Low Resistor Enabled"
line.long 0x1C "PD_PHEN,PD Pull-high Control Register"
bitfld.long 0x1C 7. "PHEN7,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 6. "PHEN6,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 5. "PHEN5,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 4. "PHEN4,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 3. "PHEN3,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 2. "PHEN2,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
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bitfld.long 0x1C 1. "PHEN1,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
bitfld.long 0x1C 0. "PHEN0,Port A-D Pull-high Resistor Control\n" "0: Pull-High Resistor Enabled,1: Pull-High Resistor Disabled"
group.long 0x440++0x3
line.long 0x0 "GPIO_DBCTL,Interrupt De-bounce Control Register"
bitfld.long 0x0 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern." "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
bitfld.long 0x0 4. "DBCLKSRC,De-bounce Counter Clock Source Selection\n" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection\n"
group.long 0x800++0x17
line.long 0x0 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x840++0x13
line.long 0x0 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x880++0x13
line.long 0x0 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x8C0++0x1B
line.long 0x0 "PD0_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "PD1_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "PD2_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "PD3_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "PD4_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "PD5_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x14 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "PD6_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x18 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "HDIV (Hardware Divider)"
base ad:0x50014000
group.long 0x0++0xF
line.long 0x0 "HDIV_DIVIDEND,Dividend Source Register"
hexmask.long 0x0 0.--31. 1. "DIVIDEND,Dividend Source\nThis register is given the dividend of divider before calculation is started."
line.long 0x4 "HDIV_DIVISOR,Divisor Source Resister"
hexmask.long.word 0x4 0.--15. 1. "DIVISOR,Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written hardware divider will start calculation."
line.long 0x8 "HDIV_QUOTIENT,Quotient Result Resister"
hexmask.long 0x8 0.--31. 1. "QUOTIENT,Quotient Result\nThis register holds the quotient result of divider after calculation is completed."
line.long 0xC "HDIV_REM,Remainder Result Register"
hexmask.long 0xC 0.--31. 1. "REM,Remainder Result\nThe remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension (REM[31:16]) to 32-bit integer."
rgroup.long 0x10++0x3
line.long 0x0 "HDIV_STATUS,Divider Status Register"
bitfld.long 0x0 1. "DIVBYZERO,Divisor Zero Warning (Read Only)\nNote: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever HDIV_DIVISOR is written. This bit is read only." "0: The divisor is not 0,1: The divisor is 0"
tree.end
tree "INT (Interrupt Source Control Registers)"
base ad:0x50000300
group.long 0x80++0x7
line.long 0x0 "INT_NMICTL,NMI Source Interrupt Select Control Register"
bitfld.long 0x0 8. "NMISELEN,NMI Interrupt Enable Control (Write Protected)\nNote: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address.." "0: NMI interrupt Disabled,1: NMI interrupt Enabled"
hexmask.long.byte 0x0 0.--4. 1. "NMISEL,NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMTSEL."
line.long 0x4 "INT_IRQSTS,MCU IRQ Number Identity Register"
hexmask.long 0x4 0.--31. 1. "IRQ,MCU IRQ Source Register\nThe IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There is one mode to generate interrupt to Cortex-M0 - the normal mode.\nThe IRQ collects all interrupts from.."
tree.end
tree "PGA (Programmable Gain Amplifier)"
base ad:0x400F0000
group.long 0x0++0x3
line.long 0x0 "PGA_CTL,Programmable Gain Amplifier Control Register"
bitfld.long 0x0 4.--6. "GAIN,PGA Gain Selection\n" "0: 2,1: 3,?,?,?,?,?,?"
bitfld.long 0x0 0. "PGAEN,Programmable Gain Amplifier Enable Control\nNote: The PGA output needs to wait stable 20 s after PGAEN is first set." "0: Programmable Gain Amplifier Disabled,1: Programmable Gain Amplifier Enabled"
tree.end
tree "SCS (System Control)"
base ad:0xE000E000
group.long 0x10++0xB
line.long 0x0 "SYST_CTL,SysTick Control and Status"
bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag\nReturn 1 If Timer Counted to 0 Since Last Time this Register Was Read\n" "0: COUNTFLAG is cleared on read or by a write to..,1: COUNTFLAG is set by a count transition from 1 to 0"
bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Select Bit\n" "0: Clock source is optional refer to STCLKSEL,1: Core clock used for SysTick timer"
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bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enable Control\n" "0: Counting down to 0 will not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
bitfld.long 0x0 0. "ENABLE,System Tick Counter Enable Control\n" "0: System Tick counter Disabled,1: System Tick counter will operate in a multi-shot.."
line.long 0x4 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0."
line.long 0x8 "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the.."
group.long 0x100++0x3
line.long 0x0 "NVIC_ISER,IRQ0 ~ IRQ31 Set-Enable Control Register"
hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Enable Register \nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite operation:\nRead value indicates the current enable status."
group.long 0x180++0x3
line.long 0x0 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-Enable Control Register"
hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt Disable Register\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite operation:\nNote: Read value indicates the current enable status."
group.long 0x200++0x3
line.long 0x0 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-Pending Control Register"
hexmask.long 0x0 0.--31. 1. "SETPEND,Set Interrupt Pending Register\nWrite operation:\nNote: Read value indicates the current pending status."
group.long 0x280++0x3
line.long 0x0 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-Pending Control Register"
hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear Interrupt Pending Register\nWrite operation:\nNote: Read value indicates the current pending status."
group.long 0x400++0x1F
line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ3 Interrupt Priority Control Register"
bitfld.long 0x0 30.--31. "PRI_3,Priority of IRQ3\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_2,Priority of IRQ2\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x0 14.--15. "PRI_1,Priority of IRQ1\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x0 6.--7. "PRI_0,Priority of IRQ0\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x4 "NVIC_IPR1,IRQ4 ~ IRQ7 Interrupt Priority Control Register"
bitfld.long 0x4 30.--31. "PRI_7,Priority of IRQ7\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x4 22.--23. "PRI_6,Priority of IRQ6\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x4 14.--15. "PRI_5,Priority of IRQ5\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x4 6.--7. "PRI_4,Priority of IRQ4\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x8 "NVIC_IPR2,IRQ8 ~ IRQ11 Interrupt Priority Control Register"
bitfld.long 0x8 30.--31. "PRI_11,Priority of IRQ11\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x8 22.--23. "PRI_10,Priority of IRQ10\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x8 14.--15. "PRI_9,Priority of IRQ9\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x8 6.--7. "PRI_8,Priority of IRQ8\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0xC "NVIC_IPR3,IRQ12 ~ IRQ15 Interrupt Priority Control Register"
bitfld.long 0xC 30.--31. "PRI_15,Priority of IRQ15\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0xC 22.--23. "PRI_14,Priority of IRQ14\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0xC 14.--15. "PRI_13,Priority of IRQ13\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0xC 6.--7. "PRI_12,Priority of IRQ12\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x10 "NVIC_IPR4,IRQ16 ~ IRQ19 Interrupt Priority Control Register"
bitfld.long 0x10 30.--31. "PRI_19,Priority of IRQ19\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x10 22.--23. "PRI_18,Priority of IRQ18\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x10 14.--15. "PRI_17,Priority of IRQ17\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x10 6.--7. "PRI_16,Priority of IRQ16\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x14 "NVIC_IPR5,IRQ20 ~ IRQ23 Interrupt Priority Control Register"
bitfld.long 0x14 30.--31. "PRI_23,Priority of IRQ23\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x14 22.--23. "PRI_22,Priority of IRQ22\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x14 14.--15. "PRI_21,Priority of IRQ21\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x14 6.--7. "PRI_20,Priority of IRQ20\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x18 "NVIC_IPR6,IRQ24 ~ IRQ27 Interrupt Priority Control Register"
bitfld.long 0x18 30.--31. "PRI_27,Priority of IRQ27\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x18 22.--23. "PRI_26,Priority of IRQ26\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x18 14.--15. "PRI_25,Priority of IRQ25\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x18 6.--7. "PRI_24,Priority of IRQ24\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x1C "NVIC_IPR7,IRQ28 ~ IRQ31 Interrupt Priority Control Register"
bitfld.long 0x1C 30.--31. "PRI_31,Priority of IRQ31\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x1C 22.--23. "PRI_30,Priority of IRQ30\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x1C 14.--15. "PRI_29,Priority of IRQ29\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x1C 6.--7. "PRI_28,Priority of IRQ28\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
rgroup.long 0xD00++0x3
line.long 0x0 "SCS_CPUID,CPUID Base Register"
hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer Code \n"
hexmask.long.byte 0x0 16.--19. 1. "PART,Architecture of the Processor \nReads as 0xC for ARMv6-M parts"
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hexmask.long.word 0x0 4.--15. 1. "PARTNO,Part Number of the Processor \nReads as 0xC20."
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Revision Number \nReads as 0x0"
group.long 0xD04++0x3
line.long 0x0 "SCS_ICSR,Interrupt Control State Register"
bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception normally the processor entersthe NMI exception handler as soon as it detects a write of 1 to this bit. Entering thehandler then clears this bit to 0." "0: No effect.\nNMI exception not pending,1: Changes NMI exception state to pending.\nNMI.."
bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
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bitfld.long 0x0 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nThis bit is write-only. To clear the PENDSV bit you must 'write 0 to PENDSVSET andwrite 1 to PENDSVCLR' at the same time." "0: No effect,1: Removes the pending state from the PendSV.."
bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation:\n" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
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bitfld.long 0x0 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This bit is write-only. When you want to clear PENDST bit you must 'write 0 toPENDSTSET and write 1 to PENDSTCLR' at the same time." "0: No effect,1: Removes the pending state from the SysTick.."
rbitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preempt Bit(Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state" "0,1"
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rbitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)\n" "0: Interrupt not pending,1: Interrupt pending"
hexmask.long.word 0x0 12.--20. 1. "VECTPENDING,Exception Number of the Highest Priority Pending Enabled Exception\n"
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hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Contains the Active Exception Number\n"
group.long 0xD10++0x3
line.long 0x0 "SCS_SCR,System Control Register"
bitfld.long 0x0 4. "SEVONPEND,Send Event on Pending Bit\nWhen an event or interrupt enters pending state the event signal wakes up the processorfrom WFE. If the processor is not waiting for an event the event is registered and affectsthe next WFE.\nThe processor also.." "0: Only enabled interrupts or events can wake-up..,1: Enabled events and all interrupts including.."
bitfld.long 0x0 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n" "0: Sleep mode,1: Deep Sleep mode"
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bitfld.long 0x0 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\n" "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep when returning from.."
group.long 0xD1C++0x7
line.long 0x0 "SCS_SHPR2,System Handler Priority Register 2"
bitfld.long 0x0 30.--31. "PRI_11,Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
line.long 0x4 "SCS_SHPR3,System Handler Priority Register 3"
bitfld.long 0x4 30.--31. "PRI_15,Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
bitfld.long 0x4 22.--23. "PRI_14,Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
tree.end
tree "SYS (System Manager)"
base ad:0x50000000
rgroup.long 0x0++0x3
line.long 0x0 "SYS_PDID,Part Device Identification Number Register"
hexmask.long 0x0 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used."
group.long 0x4++0xF
line.long 0x0 "SYS_RSTSTS,System Reset Status Register"
bitfld.long 0x0 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0." "0: No reset from CPU,1: The Cortex-M0 Core and FMC are reset by software.."
bitfld.long 0x0 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.."
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bitfld.long 0x0 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.."
bitfld.long 0x0 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x0 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote1: Write 1 to clear this bit to 0.\nNote2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is.." "0: No reset from watchdog timer or window watchdog..,1: Write 1 to clear this bit to 0"
bitfld.long 0x0 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.."
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bitfld.long 0x0 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0." "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued the.."
line.long 0x4 "SYS_IPRST0,Peripheral Reset Control Register 0"
bitfld.long 0x4 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to.." "0: Processor core normal operation,1: Processor core one-shot reset"
bitfld.long 0x4 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the.." "0: Chip normal operation,1: Chip one-shot reset"
line.long 0x8 "SYS_IPRST1,Peripheral Reset Control Register 1"
bitfld.long 0x8 30. "ACMPRST,ACMP Controller Reset \n" "0: ACMP controller normal operation,1: ACMP controller reset"
bitfld.long 0x8 28. "ADCRST,ADC Controller Reset\n" "0: ADC controller normal operation,1: ADC controller reset"
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bitfld.long 0x8 25. "USCI1RST,USCI1 Controller Reset\n" "0: USCI1 controller normal operation,1: USCI1 controller reset"
bitfld.long 0x8 24. "USCI0RST,USCI0 Controller Reset\n" "0: USCI0 controller normal operation,1: USCI0 controller reset"
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bitfld.long 0x8 20. "EPWMRST,Enhanced PWM Controller Reset\n" "0: EPWM controller normal operation,1: EPWM controller reset"
bitfld.long 0x8 16. "BPWMRST,Basic PWM Controller Reset\n" "0: BPWM controller normal operation,1: BPWM controller reset"
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bitfld.long 0x8 12. "PGARST,PGA Controller Reset\n" "0: PGA controller normal operation,1: PGA controller reset"
bitfld.long 0x8 8. "CAPRST,CAP Controller Reset\n" "0: CAP controller normal operation,1: CAP controller reset"
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bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset\n" "0: Timer1 controller normal operation,1: Timer1 controller reset"
bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset\n" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset\n" "0: GPIO controller normal operation,1: GPIO controller reset"
line.long 0xC "SYS_WAIT,HCLK Wait State Cycle Control Register"
bitfld.long 0xC 0. "HCLKWS,HCLK Wait State Cycle Control Bit\nThis bit is used to enable/disable HCLK wait state when access Flash.\nNote: When HCLK frequency is faster than 48MHz insert one wait state is necessary." "0: No wait state,1: One wait state inserted when CPU access Flash"
group.long 0x18++0x7
line.long 0x0 "SYS_BODCTL,Brown-Out Detector Control Register"
bitfld.long 0x0 15. "LVREN,Low Voltage Reset Enable Control (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote: This bit is write protected. Refer to the SYS_REGLCTL.." "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled"
bitfld.long 0x0 7. "BODOUT,Brown-out Detector Output Status\n" "0: Brown-out Detector output status is 0. It means..,1: Brown-out Detector output status is 1. It means.."
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bitfld.long 0x0 6. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL.." "0: BOD operate in normal mode (default),1: The BOD consumes about 100uA in normal mode"
bitfld.long 0x0 5. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.."
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bitfld.long 0x0 4. "BODRSTEN,Brown-out Reset Enable Control (Write Protect)\nThe default value is set by flash controller user configuration register CBORST(CONFIG0[19]) bit .\nNote1: \nWhile the Brown-out Detector function is enabled (BODEN high) and BOD reset function is.." "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled"
bitfld.long 0x0 1.--3. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0 [22:20]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Brown-Out Detector threshold voltage is 2.0V,1: Brown-Out Detector threshold voltage is 2.2V,?,?,?,?,?,?"
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bitfld.long 0x0 0. "BODEN,Brown-out Detector Enable Control (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 [18]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
line.long 0x4 "SYS_IVSCTL,Internal Voltage Source Control Register"
bitfld.long 0x4 0. "VTEMPEN,Temperature Sensor Enable Control\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1 the value of temperature sensor output can be obtained from A/D conversion result. Please refer to ADC function.." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
group.long 0x24++0x3
line.long 0x0 "SYS_PORCTL,Power-On-Reset Controller Register"
hexmask.long.word 0x0 0.--15. 1. "POROFF,Power-on Reset Enable Control (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.."
group.long 0x30++0xF
line.long 0x0 "SYS_GPA_MFP,GPIOA Multiple Function Control Register"
hexmask.long.byte 0x0 20.--23. 1. "PA5MFP,PA.5 Multi-function Pin Selection"
hexmask.long.byte 0x0 16.--19. 1. "PA4MFP,PA.4 Multi-function Pin Selection"
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hexmask.long.byte 0x0 12.--15. 1. "PA3MFP,PA.3 Multi-function Pin Selection"
hexmask.long.byte 0x0 8.--11. 1. "PA2MFP,PA.2 Multi-function Pin Selection"
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hexmask.long.byte 0x0 4.--7. 1. "PA1MFP,PA.1 Multi-function Pin Selection"
hexmask.long.byte 0x0 0.--3. 1. "PA0MFP,PA.0 Multi-function Pin Selection"
line.long 0x4 "SYS_GPB_MFP,GPIOB Multiple Function Control Register"
hexmask.long.byte 0x4 16.--19. 1. "PB4MFP,PB.4 Multi-function Pin Selection"
hexmask.long.byte 0x4 12.--15. 1. "PB3MFP,PB.3 Multi-function Pin Selection"
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hexmask.long.byte 0x4 8.--11. 1. "PB2MFP,PB.2 Multi-function Pin Selection"
hexmask.long.byte 0x4 4.--7. 1. "PB1MFP,PB.1 Multi-function Pin Selection"
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hexmask.long.byte 0x4 0.--3. 1. "PB0MFP,PB.0 Multi-function Pin Selection"
line.long 0x8 "SYS_GPC_MFP,GPIOC Multiple Function Control Register"
hexmask.long.byte 0x8 16.--19. 1. "PC4MFP,PC.4 Multi-function Pin Selection"
hexmask.long.byte 0x8 12.--15. 1. "PC3MFP,PC.3 Multi-function Pin Selection"
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hexmask.long.byte 0x8 8.--11. 1. "PC2MFP,PC.2 Multi-function Pin Selection"
hexmask.long.byte 0x8 4.--7. 1. "PC1MFP,PC.1 Multi-function Pin Selection"
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hexmask.long.byte 0x8 0.--3. 1. "PC0MFP,PC.0 Multi-function Pin Selection"
line.long 0xC "SYS_GPD_MFP,GPIOD Multiple Function Control Register"
hexmask.long.byte 0xC 24.--27. 1. "PD6MFP,PD.6 Multi-function Pin Selection"
hexmask.long.byte 0xC 20.--23. 1. "PD5MFP,PD.5 Multi-function Pin Selection"
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hexmask.long.byte 0xC 16.--19. 1. "PD4MFP,PD.4 Multi-function Pin Selection"
hexmask.long.byte 0xC 12.--15. 1. "PD3MFP,PD.3 Multi-function Pin Selection"
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hexmask.long.byte 0xC 8.--11. 1. "PD2MFP,PD.2 Multi-function Pin Selection"
hexmask.long.byte 0xC 4.--7. 1. "PD1MFP,PD.1 Multi-function Pin Selection"
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hexmask.long.byte 0xC 0.--3. 1. "PD0MFP,PD.0 Multi-function Pin Selection"
group.long 0x80++0xB
line.long 0x0 "SYS_IRCTCTL,HIRC Trim Control Register"
bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?"
bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
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bitfld.long 0x0 0. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\n" "0: HIRC auto trim function Disabled,1: HIRC auto trim function and trim HIRC to 48 MHz.."
line.long 0x4 "SYS_IRCTIEN,HIRC Trim Interrupt Enable Register"
bitfld.long 0x4 2. "CLKEIEN,Clock Error Interrupt Enable Control\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation an interrupt will.." "0: CLKERRIF(SYS_IRCTSTS[2]) status to trigger an..,1: CLKERRIF(SYS_IRCTSTS[2]) status to trigger an.."
bitfld.long 0x4 1. "TFAILIEN,Trim Failure Interrupt Enable Control\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).\nIf this.." "0: TFAILIF(SYS_IRCTSTS[1]) status to trigger an..,1: TFAILIF(SYS_IRCTSTS[1]) status to trigger an.."
line.long 0x8 "SYS_IRCTISTS,HIRC Trim Interrupt Status Register"
bitfld.long 0x8 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will.." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.."
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bitfld.long 0x8 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\n" "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
group.long 0x100++0x3
line.long 0x0 "SYS_REGLCTL,Register Write-Protection Control Register"
hexmask.long.byte 0x0 1.--7. 1. "REGPROTDIS,Register Write-protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59 0x16 0x88 to this field. After this sequence is.."
rbitfld.long 0x0 0. "REGLCTL,Register Lock Control Disable Index (Read Only)\n\nThe Protected registers are:\nSYS_IPRST0\nSYS_IPRST0 \nSYS_BODCTL \nLDOCR \nSYS_PORCTL \nCLK_PWRCTL \nCLK_APBCLK bit[0]\nCLK_CLKSEL0 \nCLK_CLKSEL1.." "0: Write-protection Enabled for writing protected..,1: Write-protection Disabled for writing protected.."
rgroup.long 0x114++0x3
line.long 0x0 "SYS_TSOFFSET,Temperature sensor offset Register"
hexmask.long.word 0x0 16.--27. 1. "VTEMP1,Temperature Sensor Offset Value\nThis field reflects temperature sensor output voltage offset at 125oC."
hexmask.long.word 0x0 0.--11. 1. "VTEMP0,Temperature Sensor Offset Value\nThis field reflects temperature sensor output voltage offset at 25oC."
tree.end
tree "TMR (Timer Controller)"
base ad:0x40010000
group.long 0x0++0xB
line.long 0x0 "TIMER0_CTL,Timer0 Control and Status Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CNTEN,Timer Enable Control \n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Interrupt Enable Control\nNote: If this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode\n" "0: The timer is operating in One-shot mode. The..,1: The timer is operating in Periodic mode. The..,?,?"
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bitfld.long 0x0 26. "RSTCNT,Timer Reset\n" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter value.."
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 'Event Counting Mode' for.." "0: External event counter mode Disabled,1: External event counter mode Enabled"
bitfld.long 0x0 23. "WKEN,Wake-up Enable Control\nWhen WKEN is set and the TIF or CAPIF is set the timer controller will generator a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
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bitfld.long 0x0 17. "CMPCTL,TIMERx_CMP Mode Control\n" "0: In One-shot or Periodic mode when write new..,1: In One-shot or Periodic mode when write new.."
bitfld.long 0x0 16. "CNTDATEN,Data Load Enable Control\nWhen CNTDATEN is set CNT (TIMERx_CNT[23:0]) (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.."
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\n"
line.long 0x4 "TIMER0_CMP,Timer0 Compare Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field or the core will run into unknown.."
line.long 0x8 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER0_CNT,Timer0 Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register\nIf CNTDATEN is set to 1 CNT register value will be updated continuously to monitor 24-bit up counter value."
line.long 0x4 "TIMER0_CAP,Timer0 Capture Data Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on ACMPOx matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer.."
group.long 0x14++0x7
line.long 0x0 "TIMER0_EXTCTL,Timer0 Extended Event Control Register"
bitfld.long 0x0 8. "CAPMODE,Capture Mode Select Bit\n" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function"
bitfld.long 0x0 7. "ECNTDBEN,Timer Counter Input Pin De-bounce Enable Control\n" "0: TMx (x = 0~1) pin de-bounce Disabled,1: TMx (x = 0~1) pin de-bounce Enabled"
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bitfld.long 0x0 5. "CAPIEN,Timer Capture Interrupt Enable Control\n" "0: Timer Capture Interrupt Disabled,1: Timer Capture Interrupt Enabled"
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Select Bit\nNote1: When CAPFUNCS is 0 transition on ACMPOx is using to save the 24-bit timer counter value to CAPDAT register.\nNote2: When CAPFUNCS is 1 transition on ACMPOx is using to reset the 24-bit timer counter value." "0: Capture Mode Enabled,1: When CAPFUNCS is 0"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Function Enable Control\nThis bit enables the Timer Capture Function\n" "0: Timer Capture Function Disabled,1: Timer Capture Function Enabled"
bitfld.long 0x0 1.--2. "CAPEDGE,Timer Capture Pin Edge Detection\n" "0: A falling edge on ACMPOx will be detected,1: A rising edge on ACMPO1 will be detected,?,?"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Pin Phase Detect Selection\n" "0: A falling edge of TMx (x = 0~1) pin will be..,1: A rising edge of TMx (x = 0~1) pin will be counted"
line.long 0x4 "TIMER0_EINTSTS,Timer0 Extended Event Interrupt Status Register"
bitfld.long 0x4 0. "CAPIF,Timer Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote1: This bit is cleared by writing 1 to it.\nNote2: When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a.." "0: Timer Cpautre interrupt did not occur,1: This bit is cleared by writing 1 to it"
group.long 0x20++0xB
line.long 0x0 "TIMER1_CTL,Timer1 Control and Status Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CNTEN,Timer Enable Control \n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Interrupt Enable Control\nNote: If this bit is enabled when the timer interrupt flag (TIF) is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt function Disabled,1: Timer Interrupt function Enabled"
bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode\n" "0: The timer is operating in One-shot mode. The..,1: The timer is operating in Periodic mode. The..,?,?"
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bitfld.long 0x0 26. "RSTCNT,Timer Reset\n" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter value.."
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 'Event Counting Mode' for.." "0: External event counter mode Disabled,1: External event counter mode Enabled"
bitfld.long 0x0 23. "WKEN,Wake-up Enable Control\nWhen WKEN is set and the TIF or CAPIF is set the timer controller will generator a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled,1: Wake-up trigger event Enabled"
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bitfld.long 0x0 17. "CMPCTL,TIMERx_CMP Mode Control\n" "0: In One-shot or Periodic mode when write new..,1: In One-shot or Periodic mode when write new.."
bitfld.long 0x0 16. "CNTDATEN,Data Load Enable Control\nWhen CNTDATEN is set CNT (TIMERx_CNT[23:0]) (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while Timer.."
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\n"
line.long 0x4 "TIMER1_CMP,Timer1 Compare Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field or the core will run into unknown.."
line.long 0x8 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of Timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
rgroup.long 0x2C++0x7
line.long 0x0 "TIMER1_CNT,Timer1 Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register\nIf CNTDATEN is set to 1 CNT register value will be updated continuously to monitor 24-bit up counter value."
line.long 0x4 "TIMER1_CAP,Timer1 Capture Data Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on ACMPOx matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer.."
group.long 0x34++0x7
line.long 0x0 "TIMER1_EXTCTL,Timer1 Extended Event Control Register"
bitfld.long 0x0 8. "CAPMODE,Capture Mode Select Bit\n" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function"
bitfld.long 0x0 7. "ECNTDBEN,Timer Counter Input Pin De-bounce Enable Control\n" "0: TMx (x = 0~1) pin de-bounce Disabled,1: TMx (x = 0~1) pin de-bounce Enabled"
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bitfld.long 0x0 5. "CAPIEN,Timer Capture Interrupt Enable Control\n" "0: Timer Capture Interrupt Disabled,1: Timer Capture Interrupt Enabled"
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Select Bit\nNote1: When CAPFUNCS is 0 transition on ACMPOx is using to save the 24-bit timer counter value to CAPDAT register.\nNote2: When CAPFUNCS is 1 transition on ACMPOx is using to reset the 24-bit timer counter value." "0: Capture Mode Enabled,1: When CAPFUNCS is 0"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Function Enable Control\nThis bit enables the Timer Capture Function\n" "0: Timer Capture Function Disabled,1: Timer Capture Function Enabled"
bitfld.long 0x0 1.--2. "CAPEDGE,Timer Capture Pin Edge Detection\n" "0: A falling edge on ACMPOx will be detected,1: A rising edge on ACMPO1 will be detected,?,?"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Pin Phase Detect Selection\n" "0: A falling edge of TMx (x = 0~1) pin will be..,1: A rising edge of TMx (x = 0~1) pin will be counted"
line.long 0x4 "TIMER1_EINTSTS,Timer1 Extended Event Interrupt Status Register"
bitfld.long 0x4 0. "CAPIF,Timer Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote1: This bit is cleared by writing 1 to it.\nNote2: When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a.." "0: Timer Cpautre interrupt did not occur,1: This bit is cleared by writing 1 to it"
group.long 0x40++0x3
line.long 0x0 "TIMER_CCAPCTL,Timer Continuous Capture Control Register"
bitfld.long 0x0 16.--17. "CCAPIEN,Capture Interrupt Enable Control\n" "0: Interrupt Disabled,1: Capture Rising Edge 1 and Falling Edge 1..,?,?"
bitfld.long 0x0 11. "CAPF2F,Capture Falling Edge 2 Flag\nSecond falling edge already captured this bit will be set to 1\nNote: This bit is cleared by hardware automatically when writing 1 to this bit." "0: None,1: CAPDAT(TIMER_CCAP3[23:0]) data is ready for read"
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bitfld.long 0x0 10. "CAPR2F,Capture Rising Edge 2 Flag\nSecond rising edge already captured this bit will be set to 1.\nNote: This bit is cleared by hardware automatically when writing 1 to this bit." "0: None,1: CAPDAT(TIMER_CCAP2[23:0]) data is ready for read"
bitfld.long 0x0 9. "CAPF1F,Capture Falling Edge 1 Flag\nFirst falling edge already captured this bit will be set to 1.\nNote: This bit is cleared by hardware automatically when writing 1 to this bit." "0: None,1: CAPDAT(TIMER_CCAP1[23:0]) data is ready for read"
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bitfld.long 0x0 8. "CAPR1F,Capture Rising Edge 1 Flag\nFirst rising edge already captured this bit will be set to 1.\nNote: This bit is cleared by hardware automatically when writing 1 to this bit." "0: None,1: CAPDAT(TIMER_CCAP0[23:0]) data is ready for read"
bitfld.long 0x0 4. "CAPCHSEL,Capture Timer Channel Selection\nSelect the channel to be the continuous capture event.\n" "0: PD.2,1: PC.2"
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bitfld.long 0x0 2.--3. "CNTSEL,Capture Timer Selection\nSelect the timer to continuous capture the input signal.\n" "0: TIMER0,1: TIMER1,?,?"
bitfld.long 0x0 1. "INV,Input Signal Inverse\nInvert the input signal which be captured.\n" "0: None,1: Inverse"
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bitfld.long 0x0 0. "CCAPEN,Continuous Capture Enable Control\nThis bit is to be enabled the continuous capture function.\nNote: This bit is cleared by hardware automatically when capture operation finish or writing 0 to it" "0: Continuous capture function Disabled,1: Continuous capture function Enabled"
rgroup.long 0x44++0xF
line.long 0x0 "TIMER_CCAP0,Timer Continuous Capture Data Register 0"
hexmask.long.tbyte 0x0 0.--23. 1. "CAPDAT,Timer Continuous Capture Data Register\nTIMER_CCAP0 store the timer count value of first rising edge\nTIMER_CCAP1 store the timer count value of first falling edge\nTIMER_CCAP2 store the timer count value of second rising edge\nTIMER_CCAP3 store.."
line.long 0x4 "TIMER_CCAP1,Timer Continuous Capture Data Register 1"
hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Continuous Capture Data Register\nTIMER_CCAP0 store the timer count value of first rising edge\nTIMER_CCAP1 store the timer count value of first falling edge\nTIMER_CCAP2 store the timer count value of second rising edge\nTIMER_CCAP3 store.."
line.long 0x8 "TIMER_CCAP2,Timer Continuous Capture Data Register 2"
hexmask.long.tbyte 0x8 0.--23. 1. "CAPDAT,Timer Continuous Capture Data Register\nTIMER_CCAP0 store the timer count value of first rising edge\nTIMER_CCAP1 store the timer count value of first falling edge\nTIMER_CCAP2 store the timer count value of second rising edge\nTIMER_CCAP3 store.."
line.long 0xC "TIMER_CCAP3,Timer Continuous Capture Data Register 3"
hexmask.long.tbyte 0xC 0.--23. 1. "CAPDAT,Timer Continuous Capture Data Register\nTIMER_CCAP0 store the timer count value of first rising edge\nTIMER_CCAP1 store the timer count value of first falling edge\nTIMER_CCAP2 store the timer count value of second rising edge\nTIMER_CCAP3 store.."
tree.end
tree "UI2C (Inter-Integrated Circuit)"
base ad:0x0
tree "UI2C0"
base ad:0x40070000
group.long 0x0++0x3
line.long 0x0 "UI2C_CTL,USCI Control Register"
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
group.long 0x8++0x3
line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.."
hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter\n" "0,1,2,3"
bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection\n" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.\n" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?"
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bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). \n" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). \n" "0: Peripheral device clock fPCLK,1: External input clock"
group.long 0x2C++0x3
line.long 0x0 "UI2C_LINECTL,USCI Line Control Register"
hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
bitfld.long 0x0 0. "LSB,LSB First Transmission Selection\n" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x3
line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register"
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
rgroup.long 0x34++0x3
line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote 1: In I2C protocol only use RXDAT[7:0]."
group.long 0x44++0x3
line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0"
hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX the AA bits are compared to the bits DEVADDR[9:8] to check for address match where the X is R/W bit. Then.."
group.long 0x4C++0x3
line.long 0x0 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
hexmask.long.word 0x0 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set to 0 .."
group.long 0x54++0x13
line.long 0x0 "UI2C_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x0 1. "WKADDREN,Wake-up Address Match Enable Bit\n" "0: The chip is woken up according to data toggle,1: The chip is woken up according to address match"
bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit\n" "0: Wake-up function Disabled,1: Wake-up function Enabled"
line.long 0x4 "UI2C_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
line.long 0x8 "UI2C_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x8 31. "PROTEN,I2C Protocol Enable Bit\n" "0: I2C Protocol disable,1: I2C Protocol enable"
hexmask.long.word 0x8 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.."
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bitfld.long 0x8 5. "PTRG,I2C Protocol Trigger\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1.." "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
bitfld.long 0x8 4. "ADDR10EN,Address 10-bit Function Enable Bit\n" "0: Address match 10 bit function is disabled,1: Address match 10 bit function is enabled"
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bitfld.long 0x8 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
bitfld.long 0x8 2. "STO,I2C STOP Control\n" "0,1"
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bitfld.long 0x8 1. "AA,Assert Acknowledge Control\n" "0,1"
bitfld.long 0x8 0. "GCFUNC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0xC 6. "ACKIEN,Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.\n" "0: The acknowledge interrupt is disabled,1: The acknowledge interrupt is enabled"
bitfld.long 0xC 5. "ERRIEN,Error Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).\n" "0: The error interrupt is disabled,1: The error interrupt is enabled"
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bitfld.long 0xC 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.\n" "0: The arbitration lost interrupt is disabled,1: The arbitration lost interrupt is enabled"
bitfld.long 0xC 3. "NACKIEN,Non - Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.\n" "0: The non - acknowledge interrupt is disabled,1: The non - acknowledge interrupt is enabled"
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bitfld.long 0xC 2. "STORIEN,Stop Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a stop condition is detected.\n" "0: The stop condition interrupt is disabled,1: The stop condition interrupt is enabled"
bitfld.long 0xC 1. "STARIEN,Start Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a start condition is detected.\n" "0: The start condition interrupt is disabled,1: The start condition interrupt is enabled"
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bitfld.long 0xC 0. "TOIEN,Time-out Interrupt Enable Control\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event.\n" "0: The time-out interrupt is disabled,1: The time-out interrupt is enabled"
line.long 0x10 "UI2C_PROTSTS,USCI Protocol Status Register"
bitfld.long 0x10 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL.." "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
bitfld.long 0x10 17. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\n" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x10 16. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
bitfld.long 0x10 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: A slave read request has not been detected,1: A slave read request has been detected"
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bitfld.long 0x10 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave"
bitfld.long 0x10 13. "ACKIF,Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
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bitfld.long 0x10 12. "ERRIF,Error Interrupt Flag\nIt is cleared by software writing one into this bit\nNote: This bit is set when slave mode user must write one into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: An I2C error has been detected"
bitfld.long 0x10 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nIt is cleared by software writing one into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost"
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bitfld.long 0x10 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
bitfld.long 0x10 9. "STORIF,Stop Condition Received Interrupt Flag\nIt is cleared by software writing one into this bit" "0: A stop condition has not yet been detected,1: A stop condition has been detected"
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bitfld.long 0x10 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However this bit also indicates that a repeated start condition has been detected on slave mode.\nIt.." "0: A start condition has not yet been detected,1: A start condition has been detected"
bitfld.long 0x10 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected\n" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x10 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing one into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
group.long 0x8C++0x3
line.long 0x0 "UI2C_TMCTL,I2C Timing Configure Control Register"
hexmask.long.byte 0x0 6.--11. 1. "HTCTL,Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.\n"
hexmask.long.byte 0x0 0.--5. 1. "STCTL,Setup Time Configure Control Register\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.\n"
tree.end
tree "UI2C1"
base ad:0x40170000
group.long 0x0++0x3
line.long 0x0 "UI2C_CTL,USCI Control Register"
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
group.long 0x8++0x3
line.long 0x0 "UI2C_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x0 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.."
hexmask.long.byte 0x0 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x0 8.--9. "PDSCNT,Pre-divider for Sample Counter\n" "0,1,2,3"
bitfld.long 0x0 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection\n" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x0 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
bitfld.long 0x0 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.\n" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?"
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bitfld.long 0x0 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). \n" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x0 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). \n" "0: Peripheral device clock fPCLK,1: External input clock"
group.long 0x2C++0x3
line.long 0x0 "UI2C_LINECTL,USCI Line Control Register"
hexmask.long.byte 0x0 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
bitfld.long 0x0 0. "LSB,LSB First Transmission Selection\n" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x3
line.long 0x0 "UI2C_TXDAT,USCI Transmit Data Register"
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
rgroup.long 0x34++0x3
line.long 0x0 "UI2C_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote 1: In I2C protocol only use RXDAT[7:0]."
group.long 0x44++0x3
line.long 0x0 "UI2C_DEVADDR0,USCI Device Address Register 0"
hexmask.long.word 0x0 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX the AA bits are compared to the bits DEVADDR[9:8] to check for address match where the X is R/W bit. Then.."
group.long 0x4C++0x3
line.long 0x0 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
hexmask.long.word 0x0 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set to 0 .."
group.long 0x54++0x13
line.long 0x0 "UI2C_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x0 1. "WKADDREN,Wake-up Address Match Enable Bit\n" "0: The chip is woken up according to data toggle,1: The chip is woken up according to address match"
bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit\n" "0: Wake-up function Disabled,1: Wake-up function Enabled"
line.long 0x4 "UI2C_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
line.long 0x8 "UI2C_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x8 31. "PROTEN,I2C Protocol Enable Bit\n" "0: I2C Protocol disable,1: I2C Protocol enable"
hexmask.long.word 0x8 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero.."
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bitfld.long 0x8 5. "PTRG,I2C Protocol Trigger\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1.." "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
bitfld.long 0x8 4. "ADDR10EN,Address 10-bit Function Enable Bit\n" "0: Address match 10 bit function is disabled,1: Address match 10 bit function is enabled"
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bitfld.long 0x8 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
bitfld.long 0x8 2. "STO,I2C STOP Control\n" "0,1"
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bitfld.long 0x8 1. "AA,Assert Acknowledge Control\n" "0,1"
bitfld.long 0x8 0. "GCFUNC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0xC 6. "ACKIEN,Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.\n" "0: The acknowledge interrupt is disabled,1: The acknowledge interrupt is enabled"
bitfld.long 0xC 5. "ERRIEN,Error Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).\n" "0: The error interrupt is disabled,1: The error interrupt is enabled"
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bitfld.long 0xC 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.\n" "0: The arbitration lost interrupt is disabled,1: The arbitration lost interrupt is enabled"
bitfld.long 0xC 3. "NACKIEN,Non - Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.\n" "0: The non - acknowledge interrupt is disabled,1: The non - acknowledge interrupt is enabled"
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bitfld.long 0xC 2. "STORIEN,Stop Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a stop condition is detected.\n" "0: The stop condition interrupt is disabled,1: The stop condition interrupt is enabled"
bitfld.long 0xC 1. "STARIEN,Start Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a start condition is detected.\n" "0: The start condition interrupt is disabled,1: The start condition interrupt is enabled"
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bitfld.long 0xC 0. "TOIEN,Time-out Interrupt Enable Control\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event.\n" "0: The time-out interrupt is disabled,1: The time-out interrupt is enabled"
line.long 0x10 "UI2C_PROTSTS,USCI Protocol Status Register"
bitfld.long 0x10 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL.." "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
bitfld.long 0x10 17. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\n" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x10 16. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
bitfld.long 0x10 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: A slave read request has not been detected,1: A slave read request has been detected"
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bitfld.long 0x10 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware." "0: The device is not selected as slave,1: The device is selected as slave"
bitfld.long 0x10 13. "ACKIF,Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
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bitfld.long 0x10 12. "ERRIF,Error Interrupt Flag\nIt is cleared by software writing one into this bit\nNote: This bit is set when slave mode user must write one into STO register to the defined 'not addressed' slave mode." "0: An I2C error has not been detected,1: An I2C error has been detected"
bitfld.long 0x10 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nIt is cleared by software writing one into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost"
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bitfld.long 0x10 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
bitfld.long 0x10 9. "STORIF,Stop Condition Received Interrupt Flag\nIt is cleared by software writing one into this bit" "0: A stop condition has not yet been detected,1: A stop condition has been detected"
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bitfld.long 0x10 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However this bit also indicates that a repeated start condition has been detected on slave mode.\nIt.." "0: A start condition has not yet been detected,1: A start condition has been detected"
bitfld.long 0x10 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected\n" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x10 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing one into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
group.long 0x8C++0x3
line.long 0x0 "UI2C_TMCTL,I2C Timing Configure Control Register"
hexmask.long.byte 0x0 6.--11. 1. "HTCTL,Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.\n"
hexmask.long.byte 0x0 0.--5. 1. "STCTL,Setup Time Configure Control Register\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.\n"
tree.end
tree.end
tree "USPI (Serial Peripheral Interface)"
base ad:0x0
tree "USPI0"
base ad:0x40070000
group.long 0x0++0xB
line.long 0x0 "USPI_CTL,USCI Control Register"
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register"
bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\n" "0: The receive end interrupt is disabled,1: The receive end interrupt is enabled"
bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\n" "0: The receive start interrupt is disabled,1: The receive start interrupt is enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\n" "0: The transmit finish interrupt is disabled,1: The transmit finish interrupt is enabled"
bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\n" "0: The transmit start interrupt is disabled,1: The transmit start interrupt is enabled"
line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider\nNote: For I2C function the minimum value of CLKDIV is 8."
bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection\n" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.\n" "0: fDIV_CLK,1: fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK). \n" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK). \n" "0: Peripheral device clock fPCLK,1: External input clock"
group.long 0x10++0x3
line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested that the bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x20++0x3
line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\n" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x28++0x7
line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested that the bit.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
line.long 0x4 "USPI_LINECTL,USCI Line Control Register"
hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol the control.." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.\n" "0: Data output level is not inverted,1: Data output level is inverted"
bitfld.long 0x4 0. "LSB,LSB First Transmission Selection\n" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x3
line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register"
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.To avoid overwriting the transmit data user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field."
rgroup.long 0x34++0x3
line.long 0x0 "USPI_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer."
group.long 0x38++0x3
line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
bitfld.long 0x0 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.."
bitfld.long 0x0 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.."
bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Control\n" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.."
bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit\n" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
rgroup.long 0x3C++0x3
line.long 0x0 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
bitfld.long 0x0 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]) the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.."
bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator\n" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator\n" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.."
bitfld.long 0x0 3. "RXOVIF,Receive Buffer Overrun Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected"
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bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator\n" "0: Receive buffer is not full,1: Receive buffer is full"
bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator \n" "0: Receive buffer is not empty,1: Receive buffer is empty"
group.long 0x54++0x13
line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option\n" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit\n" "0: Wake-up function Disabled,1: Wake-up function Enabled"
line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit\n" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring. \n" "0: The output data level is 0 if TX under-run event..,1: The output data level is 1 if TX under-run event.."
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hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only)\nIn Slave mode this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC USPI_BRGEN[5]) between the two edges of input SCLK will assert the.."
bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge.\n" "0,1,2,3"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)\n" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
bitfld.long 0x8 2. "SS,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the.." "0,1"
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bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.\n" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
bitfld.long 0x8 0. "SLAVE,Slave Mode Selection\n" "0: Master mode,1: Slave mode"
line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Control\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Control\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event.\n" "0: Slave time-out interrupt Disabled,1: Slave time-out interrupt Enabled"
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bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Control\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active.\n" "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled"
bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Control\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.\n" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled"
line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register"
rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)\n" "0: SPI is in idle state,1: SPI is in busy state"
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rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.\n" "0: The slave select line status is 0,1: The slave select line status is 1"
bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active"
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bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software writes 1 to this bit." "0: Slave bit count error event does not occur,1: Slave bit count error event occurs"
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bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software writes 1 to this bit" "0: Slave time-out event does not occur,1: Slave time-out event occurs"
bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Receive end event does not occur,1: Receive end event occurs"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Receive start event does not occur,1: Receive start event occurs"
bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Transmit end event does not occur,1: Transmit end event occurs"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Transmit start event does not occur,1: Transmit start event occurs"
tree.end
tree "USPI1"
base ad:0x40170000
group.long 0x0++0xB
line.long 0x0 "USPI_CTL,USCI Control Register"
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
line.long 0x4 "USPI_INTEN,USCI Interrupt Enable Register"
bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\n" "0: The receive end interrupt is disabled,1: The receive end interrupt is enabled"
bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\n" "0: The receive start interrupt is disabled,1: The receive start interrupt is enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\n" "0: The transmit finish interrupt is disabled,1: The transmit finish interrupt is enabled"
bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\n" "0: The transmit start interrupt is disabled,1: The transmit start interrupt is enabled"
line.long 0x8 "USPI_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider\nNote: For I2C function the minimum value of CLKDIV is 8."
bitfld.long 0x8 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection\n" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.\n" "0: fDIV_CLK,1: fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK). \n" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK). \n" "0: Peripheral device clock fPCLK,1: External input clock"
group.long 0x10++0x3
line.long 0x0 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested that the bit should be set as 0." "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x20++0x3
line.long 0x0 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\n" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x28++0x7
line.long 0x0 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested that the bit.." "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
line.long 0x4 "USPI_LINECTL,USCI Line Control Register"
hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol the control.." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.\n" "0: Data output level is not inverted,1: Data output level is inverted"
bitfld.long 0x4 0. "LSB,LSB First Transmission Selection\n" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x3
line.long 0x0 "USPI_TXDAT,USCI Transmit Data Register"
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.To avoid overwriting the transmit data user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field."
rgroup.long 0x34++0x3
line.long 0x0 "USPI_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer."
group.long 0x38++0x3
line.long 0x0 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
bitfld.long 0x0 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the receive-related counters state machine.."
bitfld.long 0x0 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared. Should only be.."
bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Control\n" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared. Should only be.."
bitfld.long 0x0 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit\n" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
rgroup.long 0x3C++0x3
line.long 0x0 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
bitfld.long 0x0 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]) the corresponding interrupt request is activated. It is cleared by software writes 1.." "0: A transmit buffer under-run event has not been..,1: A transmit buffer under-run event has been.."
bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator\n" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator\n" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for the.."
bitfld.long 0x0 3. "RXOVIF,Receive Buffer Overrun Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software writes 1 to.." "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been detected"
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bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator\n" "0: Receive buffer is not full,1: Receive buffer is full"
bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator \n" "0: Receive buffer is not empty,1: Receive buffer is empty"
group.long 0x54++0x13
line.long 0x0 "USPI_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option\n" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit\n" "0: Wake-up function Disabled,1: Wake-up function Enabled"
line.long 0x4 "USPI_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
line.long 0x8 "USPI_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x8 31. "PROTEN,SPI Protocol Enable Bit\n" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
bitfld.long 0x8 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring. \n" "0: The output data level is 0 if TX under-run event..,1: The output data level is 1 if TX under-run event.."
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hexmask.long.word 0x8 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only)\nIn Slave mode this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC USPI_BRGEN[5]) between the two edges of input SCLK will assert the.."
bitfld.long 0x8 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 8.--11. 1. "SUSPITV,Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
bitfld.long 0x8 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge.\n" "0,1,2,3"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)\n" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
bitfld.long 0x8 2. "SS,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the.." "0,1"
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bitfld.long 0x8 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.\n" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
bitfld.long 0x8 0. "SLAVE,Slave Mode Selection\n" "0: Master mode,1: Slave mode"
line.long 0xC "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0xC 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Control\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
bitfld.long 0xC 2. "SLVTOIEN,Slave Time-out Interrupt Enable Control\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event.\n" "0: Slave time-out interrupt Disabled,1: Slave time-out interrupt Enabled"
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bitfld.long 0xC 1. "SSACTIEN,Slave Select Active Interrupt Enable Control\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active.\n" "0: Slave select active interrupt generation Disabled,1: Slave select active interrupt generation Enabled"
bitfld.long 0xC 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Control\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.\n" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation Enabled"
line.long 0x10 "USPI_PROTSTS,USCI Protocol Status Register"
rbitfld.long 0x10 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1. This bit indicates whether the.." "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
rbitfld.long 0x10 17. "BUSY,Busy Status (Read Only)\n" "0: SPI is in idle state,1: SPI is in busy state"
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rbitfld.long 0x10 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.\n" "0: The slave select line status is 0,1: The slave select line status is 1"
bitfld.long 0x10 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to active,1: The slave select signal has changed to active"
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bitfld.long 0x10 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high." "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
bitfld.long 0x10 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software writes 1 to this bit." "0: Slave bit count error event does not occur,1: Slave bit count error event occurs"
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bitfld.long 0x10 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software writes 1 to this bit" "0: Slave time-out event does not occur,1: Slave time-out event occurs"
bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Receive end event does not occur,1: Receive end event occurs"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Receive start event does not occur,1: Receive start event occurs"
bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Transmit end event does not occur,1: Transmit end event occurs"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Transmit start event does not occur,1: Transmit start event occurs"
tree.end
tree.end
tree "UUART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "UUART0"
base ad:0x40070000
group.long 0x0++0xB
line.long 0x0 "UUART_CTL,USCI Control Register"
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register"
bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\n" "0: The receive end interrupt is disabled,1: The receive end interrupt is enabled"
bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\n" "0: The receive start interrupt is disabled,1: The receive start interrupt is enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\n" "0: The transmit finish interrupt is disabled,1: The transmit finish interrupt is enabled"
bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\n" "0: The transmit start interrupt is disabled,1: The transmit start interrupt is enabled"
line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.."
hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter\n" "0,1,2,3"
bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection\n" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n" "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.\n" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). \n" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). \n" "0: Peripheral device clock fPCLK,1: External input clock"
group.long 0x10++0x3
line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 10." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\n" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\n" "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x20++0x3
line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\n" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\n" "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x28++0x7
line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\n" "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
line.long 0x4 "UUART_LINECTL,USCI Line Control Register"
hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.\n" "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.."
bitfld.long 0x4 0. "LSB,LSB First Transmission Selection\n" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x3
line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register"
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
rgroup.long 0x34++0x3
line.long 0x0 "UUART_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])."
group.long 0x38++0x3
line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
bitfld.long 0x0 17. "RXRST,Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: It is cleared automatically after one PCLK cycle"
bitfld.long 0x0 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.."
bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Control\n" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.."
rgroup.long 0x3C++0x3
line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator\n" "0: Transmit buffer is not full,1: Transmit buffer is full"
bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator\n" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator\n" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator \n" "0: Receive buffer is not empty,1: Receive buffer is empty"
group.long 0x54++0x13
line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option\n" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit\n" "0: Wake-up function Disabled,1: Wake-up function Enabled"
line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit\n" "0: UART Protocol Disabled,1: UART Protocol Enabled"
bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit\nNote:" "0: Stick parity Disabled,1: Stick parity Enabled"
hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.."
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hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode."
bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit\n" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x8 8. "LINRXEN,LIN RX Duplex Mode Enable Control\nNote: This bit is used to check the break duration for incoming data when the LIN operation is active." "0: LIN RX Duplex mode Disabled,1: LIN RX Duplex mode Enabled. The LIN can be play.."
bitfld.long 0x8 7. "LINBRKEN,LIN TX Break Mode Enable Control\nNote: \n1. When TX break field transfer operation is finished this bit will be cleared automatically. 2. 13-bit level 0 and 1-bit level 1 were sent out before the 1st data be transmitted." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame.\n" "0: The parity bit Disabled,1: The parity bit Enabled"
bitfld.long 0x8 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame.\n" "0: The number of stop bits is 1,1: The number of stop bits is 2"
line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit\n" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0xC 0. "BRKIEN,LIN Break Detected Interrupt Enable Control\n" "0: The LIN break detected interrupt generation is..,1: The LIN break detected interrupt generation is.."
line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register"
bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: This bit is set at the same time of ABRDETIF"
rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver.\n" "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
rbitfld.long 0x10 8. "BRKDETIF,LIN Break Detected Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than 12-bit transmission time in LIN mode function.\nNote: This bit is read only .." "0: LIN Break is no detected,1: LIN Break is detected"
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bitfld.long 0x10 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
bitfld.long 0x10 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by write '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x10 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by write '1' among the BREAK FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing one into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing one into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred"
bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing one into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: It is cleared by software writing one into this.."
tree.end
tree "UUART1"
base ad:0x40170000
group.long 0x0++0xB
line.long 0x0 "UUART_CTL,USCI Control Register"
bitfld.long 0x0 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols the USCI has to be disabled before.." "0: The USCI is disabled. All protocol related state..,1: The SPI protocol is selected,?,?,?,?,?,?"
line.long 0x4 "UUART_INTEN,USCI Interrupt Enable Register"
bitfld.long 0x4 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\n" "0: The receive end interrupt is disabled,1: The receive end interrupt is enabled"
bitfld.long 0x4 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\n" "0: The receive start interrupt is disabled,1: The receive start interrupt is enabled"
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bitfld.long 0x4 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\n" "0: The transmit finish interrupt is disabled,1: The transmit finish interrupt is enabled"
bitfld.long 0x4 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\n" "0: The transmit start interrupt is disabled,1: The transmit start interrupt is enabled"
line.long 0x8 "UUART_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x8 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and.."
hexmask.long.byte 0x8 10.--14. 1. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value."
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bitfld.long 0x8 8.--9. "PDSCNT,Pre-divider for Sample Counter\n" "0,1,2,3"
bitfld.long 0x8 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection\n" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x8 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.\n" "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
bitfld.long 0x8 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.\n" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,?,?"
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bitfld.long 0x8 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK). \n" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x8 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK). \n" "0: Peripheral device clock fPCLK,1: External input clock"
group.long 0x10++0x3
line.long 0x0 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
bitfld.long 0x0 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 10." "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,?,?"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\n" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
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bitfld.long 0x0 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\n" "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x20++0x3
line.long 0x0 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
bitfld.long 0x0 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\n" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be inverted"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\n" "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
group.long 0x28++0x7
line.long 0x0 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
bitfld.long 0x0 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\n" "0: The un-synchronized signal can be taken as input..,1: The synchronized signal can be taken as input.."
line.long 0x4 "UUART_LINECTL,USCI Line Control Register"
hexmask.long.byte 0x4 8.--11. 1. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word.."
bitfld.long 0x4 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal." "0: No effect,1: The control signal will be inverted before its.."
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bitfld.long 0x4 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.\n" "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of data.."
bitfld.long 0x4 0. "LSB,LSB First Transmission Selection\n" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x3
line.long 0x0 "UUART_TXDAT,USCI Transmit Data Register"
hexmask.long.word 0x0 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission."
rgroup.long 0x34++0x3
line.long 0x0 "UUART_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x0 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])."
group.long 0x38++0x3
line.long 0x0 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
bitfld.long 0x0 17. "RXRST,Receive Reset\nNote 1: It is cleared automatically after one PCLK cycle.\nNote 2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1." "0: No effect,1: It is cleared automatically after one PCLK cycle"
bitfld.long 0x0 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x0 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The receive buffer is cleared (filling level is.."
bitfld.long 0x0 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Control\n" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x0 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle." "0: No effect,1: The transmit buffer is cleared (filling level is.."
rgroup.long 0x3C++0x3
line.long 0x0 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
bitfld.long 0x0 9. "TXFULL,Transmit Buffer Full Indicator\n" "0: Transmit buffer is not full,1: Transmit buffer is full"
bitfld.long 0x0 8. "TXEMPTY,Transmit Buffer Empty Indicator\n" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x0 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled the corresponding interrupt request is activated. It is cleared by software.." "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
bitfld.long 0x0 1. "RXFULL,Receive Buffer Full Indicator\n" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x0 0. "RXEMPTY,Receive Buffer Empty Indicator \n" "0: Receive buffer is not empty,1: Receive buffer is empty"
group.long 0x54++0x13
line.long 0x0 "UUART_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x0 2. "PDBOPT,Power Down Blocking Option\n" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit\n" "0: Wake-up function Disabled,1: Wake-up function Enabled"
line.long 0x4 "UUART_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x4 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1. Software can write 1 to clear this bit." "0,1"
line.long 0x8 "UUART_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x8 31. "PROTEN,UART Protocol Enable Bit\n" "0: UART Protocol Disabled,1: UART Protocol Enabled"
bitfld.long 0x8 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x8 26. "STICKEN,Stick Parity Enable Bit\nNote:" "0: Stick parity Disabled,1: Stick parity Enabled"
hexmask.long.word 0x8 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data.."
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hexmask.long.byte 0x8 11.--14. 1. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode."
bitfld.long 0x8 9. "DATWKEN,Data Wake-up Mode Enable Bit\n" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x8 8. "LINRXEN,LIN RX Duplex Mode Enable Control\nNote: This bit is used to check the break duration for incoming data when the LIN operation is active." "0: LIN RX Duplex mode Disabled,1: LIN RX Duplex mode Enabled. The LIN can be play.."
bitfld.long 0x8 7. "LINBRKEN,LIN TX Break Mode Enable Control\nNote: \n1. When TX break field transfer operation is finished this bit will be cleared automatically. 2. 13-bit level 0 and 1-bit level 1 were sent out before the 1st data be transmitted." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x8 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit. The associated interrupt ABRDETIF (USCI_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled)." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
bitfld.long 0x8 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x8 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame.\n" "0: The parity bit Disabled,1: The parity bit Enabled"
bitfld.long 0x8 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame.\n" "0: The number of stop bits is 1,1: The number of stop bits is 2"
line.long 0xC "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0xC 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt." "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
bitfld.long 0xC 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit\n" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0xC 0. "BRKIEN,LIN Break Detected Interrupt Enable Control\n" "0: The LIN break detected interrupt generation is..,1: The LIN break detected interrupt generation is.."
line.long 0x10 "UUART_PROTSTS,USCI Protocol Status Register"
bitfld.long 0x10 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the.." "0: Auto-baud rate detect counter is not overrun,1: This bit is set at the same time of ABRDETIF"
rbitfld.long 0x10 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver.\n" "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x10 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set the auto-baud rate interrupt will be generated. This bit can be set 4 times.." "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
rbitfld.long 0x10 8. "BRKDETIF,LIN Break Detected Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than 12-bit transmission time in LIN mode function.\nNote: This bit is read only .." "0: LIN Break is no detected,1: LIN Break is detected"
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bitfld.long 0x10 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
bitfld.long 0x10 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by write '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x10 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by write '1' among the BREAK FRMERR and PARITYERR bits." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x10 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing one into this bit." "0: A receive finish interrupt status has not occurred,1: A receive finish interrupt status has occurred"
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bitfld.long 0x10 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing one into this bit." "0: A receive start interrupt status has not occurred,1: A receive start interrupt status has occurred"
bitfld.long 0x10 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing one into this bit." "0: A transmit end interrupt status has not occurred,1: A transmit end interrupt status has occurred"
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bitfld.long 0x10 1. "TXSTIF,Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer." "0: A transmit start interrupt status has not occurred,1: It is cleared by software writing one into this.."
tree.end
tree.end
tree "WDT (Watchdog Timer)"
base ad:0x40004000
group.long 0x0++0x3
line.long 0x0 "WDT_CTL,Watchdog Timer Control Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control (Write Protect)\nWDT up counter will keep going no matter CPU is hanging by ICE or not." "0: ICE debug mode acknowledgement effects WDT..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 8.--10. "TOUTSEL,Watchdog Timer Interval Selection\nThese three bits select the time-out interval for the Watchdog Timer.\n" "0: 24 * TWDT,1: 26 * TWDT,?,?,?,?,?,?"
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bitfld.long 0x0 7. "WDTEN,Watchdog Timer Enable Control (Write Protect)\n" "0: WDT Disabled. (This action will reset the..,1: WDT Enabled"
bitfld.long 0x0 6. "INTEN,Watchdog Timer Time-out Interrupt Enable Control (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU.\n" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x0 5. "WKF,Watchdog Timer Time-out Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if WDT.."
bitfld.long 0x0 4. "WKEN,Watchdog Timer Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while IF is generated to 1 and INTEN enabled the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by.." "0: Wake-up trigger event Disabled if WDT time-out..,1: Wake-up trigger event Enabled if WDT time-out.."
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bitfld.long 0x0 3. "IF,Watchdog Timer Time-out Interrupt Flag\nThis bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
bitfld.long 0x0 2. "RSTF,Watchdog Timer Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
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bitfld.long 0x0 1. "RSTEN,Watchdog Timer Time-out Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period (1024 * TWDT) expires.\n" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
bitfld.long 0x0 0. "RSTCNT,Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware." "0: No effect,1: Reset the internal 18-bit WDT up counter value"
tree.end
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