1271 lines
129 KiB
Plaintext
1271 lines
129 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: N571 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2023-04-07 NEJ
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; 2023-11-08 NEJ
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: Generated (TRACE32, build: 164352.), based on:
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; N571P032_v3_fixed.svd (Ver. 1.0)
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; @Core: Cortex-M0
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; @Chip: N571P032
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pern571.per 16971 2023-11-09 16:09:22Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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tree.end
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width 6.
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tree "Interrupt Priority Registers"
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group.long 0x400++0x1F
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line.long 0x00 "INT0,Interrupt Priority Register"
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bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
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bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
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bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
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bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
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line.long 0x04 "INT1,Interrupt Priority Register"
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bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
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bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
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bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
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bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
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line.long 0x08 "INT2,Interrupt Priority Register"
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bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
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bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
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bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
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bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
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line.long 0x0C "INT3,Interrupt Priority Register"
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bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
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bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
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bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
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bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
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line.long 0x10 "INT4,Interrupt Priority Register"
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bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
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bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
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bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
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bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
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line.long 0x14 "INT5,Interrupt Priority Register"
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bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
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bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
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bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
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bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog to Digital Converter)"
|
|
base ad:0x400E0000
|
|
rgroup.long 0x0++0x1F
|
|
line.long 0x0 "ADC_DAT0,A/D Data Register for the channel defined in CHSEQ0"
|
|
bitfld.long 0x0 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid"
|
|
bitfld.long 0x0 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]."
|
|
hexmask.long.word 0x0 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit."
|
|
line.long 0x4 "ADC_DAT1,A/D Data Register for the channel defined in CHSEQ0"
|
|
bitfld.long 0x4 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid"
|
|
bitfld.long 0x4 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]."
|
|
hexmask.long.word 0x4 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit."
|
|
line.long 0x8 "ADC_DAT2,A/D Data Register for the channel defined in CHSEQ0"
|
|
bitfld.long 0x8 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid"
|
|
bitfld.long 0x8 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]."
|
|
hexmask.long.word 0x8 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit."
|
|
line.long 0xC "ADC_DAT3,A/D Data Register for the channel defined in CHSEQ0"
|
|
bitfld.long 0xC 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid"
|
|
bitfld.long 0xC 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten"
|
|
newline
|
|
hexmask.long.byte 0xC 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]."
|
|
hexmask.long.word 0xC 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit."
|
|
line.long 0x10 "ADC_DAT4,A/D Data Register for the channel defined in CHSEQ0"
|
|
bitfld.long 0x10 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid"
|
|
bitfld.long 0x10 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten"
|
|
newline
|
|
hexmask.long.byte 0x10 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]."
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hexmask.long.word 0x10 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit."
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line.long 0x14 "ADC_DAT5,A/D Data Register for the channel defined in CHSEQ0"
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bitfld.long 0x14 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid"
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bitfld.long 0x14 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten"
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hexmask.long.byte 0x14 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]."
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hexmask.long.word 0x14 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit."
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line.long 0x18 "ADC_DAT6,A/D Data Register for the channel defined in CHSEQ0"
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bitfld.long 0x18 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid"
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bitfld.long 0x18 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten"
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hexmask.long.byte 0x18 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]."
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hexmask.long.word 0x18 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit."
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line.long 0x1C "ADC_DAT7,A/D Data Register for the channel defined in CHSEQ0"
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bitfld.long 0x1C 17. "VALID,Valid Flag. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are not valid,1: Data in RESULT are valid"
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bitfld.long 0x1C 16. "OV,Over Run Flag. If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after ADC_DAT register is read." "0: Data in RESULT are recent conversion result,1: Data in RESULT are overwritten"
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hexmask.long.byte 0x1C 12.--15. 1. "EXTS,Extension Bits Of RESULT for Different Data Format. If ADCFM is '0' EXTS all are read as '0'.. If ADCFM is '1' EXTS all are read as bit RESULT[11]."
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hexmask.long.word 0x1C 0.--11. 1. "RESULT,A/D Conversion Result. This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit."
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group.long 0x20++0x13
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line.long 0x0 "ADC_CTL,A/D Control Register"
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bitfld.long 0x0 23. "HP_EN,High-pass Filter Enable." "0: High-pass filter is disabled,1: High-pass filter is enabled (must in continuous.."
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bitfld.long 0x0 20.--22. "HP_FSEL,High-pass Filter Frequency Selection:." "0: Do not remove DC part,1: DC part is suppressed by -40dB -3dB at 0.005 x..,?,?,?,?,?,?"
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bitfld.long 0x0 19. "DS_EN,Down Sample Function Enable ." "0: Down sample function is disabled,1: Down sample function is enabled. When this field.."
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bitfld.long 0x0 18. "DS_1CH,This bit will be effective only when field DS_EN effective. ." "0: ADC down sample is applied to 2 ADC channels..,1: ADC down sample function is applied to one ADC.."
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bitfld.long 0x0 16.--17. "DS_RATE,Down Sample Rate." "0: Down sample X2,1: Down sample X4,?,?"
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bitfld.long 0x0 12. "ADCFM,Data Format Of ADC Conversion Result." "0: Unsigned,1: 2'Complemet"
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bitfld.long 0x0 11. "SWTRG,A/D Conversion Start. Note: SWTRG bit can be reset to 0 by software or can be cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In continuous scan mode A/D conversion is continuously.." "0: Conversion is stopped and A/D converter enters..,1: Start conversion"
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bitfld.long 0x0 2.--3. "OPMODE,A/D Converter Operation Mode. . Note 1: This field will be effective only when DS_EN field in this register is set as '0'.. When DS_EN is set as '1' ADC conversion will be forced to 'continuous scan mode'. Note 2: When changing the operation.." "0: Single conversion,1: This field will be effective only when DS_EN..,2: When changing the operation mode,?"
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bitfld.long 0x0 1. "ADCIE,A/D Interrupt Enable. A/D conversion end interrupt request is generated if ADCIE bit is set to 1." "0: Disable A/D interrupt function,1: Enable A/D interrupt function"
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bitfld.long 0x0 0. "ADCEN,A/D Converter Enable. Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption." "0: Disable,1: Enable"
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line.long 0x4 "ADC_CHSEQ,A/D Channel Sequence Register"
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hexmask.long.byte 0x4 28.--31. 1. "CHSEQ7,Select Channel N As The 8th Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0."
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hexmask.long.byte 0x4 24.--27. 1. "CHSEQ6,Select Channel N As The 7th Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0."
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hexmask.long.byte 0x4 20.--23. 1. "CHSEQ5,Select Channel N As The 6th Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0."
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hexmask.long.byte 0x4 16.--19. 1. "CHSEQ4,Select Channel N As The 5th Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0."
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hexmask.long.byte 0x4 12.--15. 1. "CHSEQ3,Select Channel N As The 4th Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0."
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hexmask.long.byte 0x4 8.--11. 1. "CHSEQ2,Select Channel N As The 3rd Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0."
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hexmask.long.byte 0x4 4.--7. 1. "CHSEQ1,Select Channel N As The 2nd Conversion In Scan Sequence. The definition of channel selection is the same as CHSEQ0."
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hexmask.long.byte 0x4 0.--3. 1. "CHSEQ0,Select Channel N As The 1st Conversion In Scan Sequence."
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line.long 0x8 "ADC_CMP0,A/D Compare Register 0"
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hexmask.long.byte 0x8 23.--27. 1. "CMPDAT,Compare Data. This field possessing the 5 MSB of 12-bit compare data and 7 LSB are treated as '0' is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in.."
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hexmask.long.byte 0x8 8.--11. 1. "CMPMCNT,Compare Match Count. When the specified A/D channel analog conversion result matches the comparing condition the internal match counter will increase 1. When the internal counter achieves the setting (CMPMCNT+1) hardware will set the ADCMPF bit."
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bitfld.long 0x8 3.--5. "CMPCH,Compare Channel Selection." "0: Reserved,1: Reserved,?,?,?,?,?,?"
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bitfld.long 0x8 2. "CMPCOND,Compare Condition." "0: ADCMPFx bit is set if conversion result is less..,1: ADCMPFx bit is set if conversion result is.."
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bitfld.long 0x8 1. "ADCMPIE,Compare Interrupt Enable. When converted data in RESULT is less (or greater) than the compare data CMPDAT ADCMPF bit is asserted. If ADCMPIE is set to 1 a compare interrupt request is generated." "0: Disable,1: Enable"
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bitfld.long 0x8 0. "ADCMPEN,Compare Enable. Set this bit to 1 to enable the comparison CMPDAT with specified channel conversion result when converted data is loaded into ADC_DAT register." "0: Disable compare,1: Enable compare"
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line.long 0xC "ADC_CMP1,A/D Compare Register 0"
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hexmask.long.byte 0xC 23.--27. 1. "CMPDAT,Compare Data. This field possessing the 5 MSB of 12-bit compare data and 7 LSB are treated as '0' is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in.."
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hexmask.long.byte 0xC 8.--11. 1. "CMPMCNT,Compare Match Count. When the specified A/D channel analog conversion result matches the comparing condition the internal match counter will increase 1. When the internal counter achieves the setting (CMPMCNT+1) hardware will set the ADCMPF bit."
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bitfld.long 0xC 3.--5. "CMPCH,Compare Channel Selection." "0: Reserved,1: Reserved,?,?,?,?,?,?"
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bitfld.long 0xC 2. "CMPCOND,Compare Condition." "0: ADCMPFx bit is set if conversion result is less..,1: ADCMPFx bit is set if conversion result is.."
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bitfld.long 0xC 1. "ADCMPIE,Compare Interrupt Enable. When converted data in RESULT is less (or greater) than the compare data CMPDAT ADCMPF bit is asserted. If ADCMPIE is set to 1 a compare interrupt request is generated." "0: Disable,1: Enable"
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bitfld.long 0xC 0. "ADCMPEN,Compare Enable. Set this bit to 1 to enable the comparison CMPDAT with specified channel conversion result when converted data is loaded into ADC_DAT register." "0: Disable compare,1: Enable compare"
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line.long 0x10 "ADC_STATUS,A/D Status Register"
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hexmask.long.byte 0x10 16.--23. 1. "OV,Over Run Flag. It is a mirror to OV bit in ADC_DATn."
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hexmask.long.byte 0x10 8.--15. 1. "VALID,Data Valid Flag. It is a mirror of VALID bit in ADC_DATn."
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bitfld.long 0x10 4.--6. "CHANNEL,Current Conversion Channel. It is read only." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 3. "BUSY,BUSY/IDLE. This bit is mirror of SWTRG bit in ADC_CTL.. It is read only." "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
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bitfld.long 0x10 2. "ADCMPF1,Compare Flag. When the selected channel A/D conversion result meets setting conditions in ADC_CMP1 then this bit is set to 1. And it is cleared by write 1.." "0: Converted result RESULT in ADC_DAT does not meet..,1: Converted result RESULT in ADC_DAT meets.."
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bitfld.long 0x10 1. "ADCMPF0,Compare Flag. When the selected channel A/D conversion result meets setting conditions in ADC_CMP0 then this bit is set to 1. And it is cleared by write 1.." "0: Converted result RESULT in ADC_DAT does not meet..,1: Converted result RESULT in ADC_DAT meets.."
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bitfld.long 0x10 0. "ADIF,A/D Conversion End Flag. A status flag that indicates the end of A/D conversion.. ADIF is set to 1 under the following two conditions:. When A/D conversion ends in single mode . When A/D conversion ends on all channels specified by channel sequence.." "0,1"
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group.long 0x3C++0x3
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line.long 0x0 "ADC_PGCTL,ADC Pre-amplifier Gain Control Register"
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hexmask.long.byte 0x0 24.--28. 1. "POST_GAIN,Gain setting bits for the second stage of pre-amp. Gain start from 14dB till 34dB for 0.65dB per step.."
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hexmask.long.byte 0x0 8.--13. 1. "OS,Configuration for Pre-Amp OP Offset Bias Compensation Voltage. There are 64 levels and 0.25mV per level @ 5V condition."
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bitfld.long 0x0 3. "GAIN_CHG,Change Gain method of PGC." "0: Load Boost & Post gain to PGC directly,1: Load Boost & Post gain to PGC when zero cross.."
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bitfld.long 0x0 1.--2. "BOOST_GAIN,Gain Setting Bits For The First Stage Of Pre-Amp." "0: 0 dB,1: 10 dB,?,?"
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bitfld.long 0x0 0. "OPMUTE,Mute Control of First Stage Pre-Amp for Offset Bias Calibration. When this bit set is as '1' two input end of first stage pre-amp will be shorted and feedback resistor of this stage will be shorted.." "0: Open,1: Short"
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group.long 0x44++0x3
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line.long 0x0 "ADC_HWPARA,ADC H/W Parameter Control Register"
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hexmask.long.byte 0x0 8.--14. 1. "CONV_N,Specify ADC conversion clock number. CONV_N has to be equal to or great than 11.. To update this field programmer can only revise bit [14:8] and keep other bits the same as before.. Note: CONV_N valid range is from 11~127"
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hexmask.long.byte 0x0 0.--5. 1. "SHCLK_N,Specify the high level of ADC start signal.. Note: Suggested and default value is 0."
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tree.end
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tree "APU (Audio Processing Unit)"
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base ad:0x50008000
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group.long 0x0++0x7
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line.long 0x0 "APU_CTL,APU Control Register"
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bitfld.long 0x0 10. "DAC_ZERO_CROSS,DAC Output Data Cross Zero Point Flag. Note: This bit is set by hardware when DAC output data cross zero point software can clear this bit by write 1." "0: DAC output data doesn't cross zero point,1: DAC output data cross zero point"
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bitfld.long 0x0 9. "BPPAM,Bypass Power Amplifier DAC Output To Pin." "0: SPK+/DAC pin is one of power amplifier output,1: SPK+/DAC pin is current DAC output no output on.."
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bitfld.long 0x0 8. "DACE,DAC Enable." "0: Disable DAC function,1: Enable DAC function"
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bitfld.long 0x0 7. "PAMPE,Power Amplifier Enable." "0: Disable PA function,1: Enable PA function"
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bitfld.long 0x0 6. "APUIE,APU Interrupt Enable." "0: Disable the APU threshold interrupt,1: Enable the APU threshold interrupt"
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bitfld.long 0x0 5. "APUIS,APU Interrupt Status. This flag is set by hardware when APU threshold is met. Software can clear this bit by writing a zero to it." "0: APU threshold interrupt does not occur,1: APU threshold interrupt occur"
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bitfld.long 0x0 4. "FIXI,DAC mode select." "0: DAC current varies by voltage (structure is same..,1: DAC current fix (structure is same as N572F064)"
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bitfld.long 0x0 3. "UP4EN,Up sample X4 Enable. Note: Once UP4_EN set as 1 TM0CP field in TM0CPR suggest to be set as multiple times of 4 to avoid playback rate shift. Worst case of the playback rate deviation is 3/TM0CPR * 100% when least significant 2 bits of is TM0CPR.." "0: Disable the APU up sample X4,1: Enable the APU up sample X4 and filtering"
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bitfld.long 0x0 0.--2. "TSHD,APU Interrupt Threshold." "0: Buffer 0 is read out by APU,1: Buffer 1 is read out by APU,?,?,?,?,?,?"
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line.long 0x4 "APU_VM,APU Volume Control Register"
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bitfld.long 0x4 0.--2. "VOLUM,APU Volume Adjustment." "0: 0 dB,1: -3 dB,?,?,?,?,?,?"
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group.long 0xC++0x23
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line.long 0x0 "APU_CH1DAT0,APU Channel 1 Data Buffer Register"
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hexmask.long.word 0x0 0.--15. 1. "PCM1,PCM Data Of Channel 1 . This field contains 16-bit PCM data that is one of the Mixer input.. User needs to take care of the effective bit of PCM because the H/W mixer output is clipped to 13 bits automatically.. The data format of PCM is 2'complement."
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line.long 0x4 "APU_CH0DAT0,APU Channel 0 Data Buffer Register 0"
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hexmask.long.word 0x4 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to mixer H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is 2'complement."
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line.long 0x8 "APU_CH0DAT1,APU Channel 0 Data Buffer Register 0"
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hexmask.long.word 0x8 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to mixer H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is 2'complement."
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line.long 0xC "APU_CH0DAT2,APU Channel 0 Data Buffer Register 0"
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hexmask.long.word 0xC 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to mixer H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is 2'complement."
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line.long 0x10 "APU_CH0DAT3,APU Channel 0 Data Buffer Register 0"
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hexmask.long.word 0x10 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to mixer H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is 2'complement."
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line.long 0x14 "APU_CH0DAT4,APU Channel 0 Data Buffer Register 0"
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hexmask.long.word 0x14 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to mixer H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is 2'complement."
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line.long 0x18 "APU_CH0DAT5,APU Channel 0 Data Buffer Register 0"
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hexmask.long.word 0x18 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to mixer H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is 2'complement."
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line.long 0x1C "APU_CH0DAT6,APU Channel 0 Data Buffer Register 0"
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hexmask.long.word 0x1C 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to mixer H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is 2'complement."
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line.long 0x20 "APU_CH0DAT7,APU Channel 0 Data Buffer Register 0"
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hexmask.long.word 0x20 0.--15. 1. "PCM,PCM Data Of Channel 0 . This field contains 16-bit PCM data that will be sent to mixer H/W.. User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.. The data format of PCM is 2'complement."
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tree.end
|
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tree "CLK (Clock Controller)"
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base ad:0x50000200
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group.long 0x0++0xB
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line.long 0x0 "CLK_PWRCTL,System Power Control Register"
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bitfld.long 0x0 8. "PD_WAIT_CPU,This Bit Controls the Power Down Entry Condition. Please refer to PWR_DOWN bit for the usage of PD_WAIT_CPU bit.. The following is a brief description of PD_WAIT_CPU bit.." "0: Chip is at normal mode. Note that PWR_DOWN..,1: Chip waits to enter power-down mode"
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bitfld.long 0x0 7. "PWR_DOWN,System Power Down Active Or Enable Bit." "0: Chip operates at normal mode,1: Chip is standing by power-down entry condition"
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newline
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bitfld.long 0x0 6. "WINT_STS,Chip Power Down Wake Up Status Flag. Set by 'power down wake up' it indicates that resume from power down mode. . The flag is set if the GPIO WDT or RTC wakeup.. Note: Write 1 to clear the bit." "0,1"
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bitfld.long 0x0 5. "WINT_EN,Enable Interrupt When Wake Up From Power Down Mode." "0: Disable,1: Enable. The interrupt will occur when MCU wakes.."
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bitfld.long 0x0 4. "WU_DLY,Enable the Wake Up Delay Time Selection. When the chip wakes up from power down the clock control will delay some times as selection to wait LDO33 stable. . 1: Delay 200us for LDO33 stable. . 0: Delay 60us for LDO33 stable." "0: Delay 60us for LDO33 stable,1: Delay 200us for LDO33 stable"
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bitfld.long 0x0 3. "XTL32K_FILTER,Filter the XTL32K output clock . Note: High level of XTL32K must keep 112 HCLK for recognition valid when this bit is enabled." "0: Disable XTL32K output clock without filter,1: Enable XTL32K output clock will be filtered to.."
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bitfld.long 0x0 2. "OSC46M_EN,Internal 46MHz RC Oscillator Control. After reset this bit is '1'. ." "0: 46MHz oscillation is disabled,1: 46MHz oscillation is enabled"
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bitfld.long 0x0 1. "XTL32K_EN,External 32.768KHz Crystal Control. After reset this bit is '0'.." "0: 32.768KHz Crystal is disabled,1: 32.768KHz Crystal is enabled"
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bitfld.long 0x0 0. "XTL32K_WEAK,XTL32K weak mode." "0: Normal mode,1: Weak mode"
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line.long 0x4 "CLK_AHBCLK,AHB Device Clock Enable Control Register"
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bitfld.long 0x4 3. "APUCKEN,APU Clock Enable Control." "0: To disable the APU engine clock,1: To enable the APU engine clock"
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bitfld.long 0x4 2. "ISPCKEN,OTP ISP Controller Clock Enable Control.. The OTP ISP engine clock always is from 46MHz RC oscillator.." "0: Disable the OTP ISP engine clock,1: Enable the OTP ISP engine clock"
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line.long 0x8 "CLK_APBCLK,APB Device Clock Enable Control Register"
|
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bitfld.long 0x8 28. "ADC_EN,Audio Analog-Digital-Converter (ADC) Clock Enable Control." "0: Disable,1: Enable"
|
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bitfld.long 0x8 20. "PWM_EN,PWM Block Clock Enable Control." "0: Disable,1: Enable"
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newline
|
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bitfld.long 0x8 12. "SPI0_EN,SPI0 Clock Enable Control." "0: Disable,1: Enable"
|
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bitfld.long 0x8 5. "TMRF_EN,TimerF Clock Enable Control." "0: Disable,1: Enable"
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newline
|
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bitfld.long 0x8 4. "TMR2_EN,Timer2 Clock Enable Control." "0: Disable,1: Enable"
|
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bitfld.long 0x8 3. "TMR1_EN,Timer1 Clock Enable Control." "0: Disable,1: Enable"
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newline
|
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bitfld.long 0x8 2. "TMR0_EN,Timer0 Clock Enable Control." "0: Disable,1: Enable"
|
|
bitfld.long 0x8 1. "RTC_EN,Real-Time-Clock APB Interface Clock Control. This bit is used to control the RTC APB clock only. The RTC engine clock source is from the 32.768KHz crystal.." "0: Disable,1: Enable"
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newline
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bitfld.long 0x8 0. "WDT_EN,Watchdog Clock Enable Control. This bit is the protected bit. To program this bit needs an open lock sequence write '59h' '16h' '88h' to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.. The.." "0: Disable,1: Enable"
|
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group.long 0x10++0xB
|
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line.long 0x0 "CLK_CLKSEL0,Clock Source Select Control Register 0"
|
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bitfld.long 0x0 0.--2. "HCLKSEL,HCLK Clock Source Select. . Note:. 1. When power on 23MHz RC is selected as HCLK clock source.. 2. Before clock switch the related clock sources (pre-select and new-select) must be turned on." "0: clock source from XTL_32K,?,?,?,?,?,?,?"
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line.long 0x4 "CLK_CLKSEL1,Clock Source Select Control Register 1"
|
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bitfld.long 0x4 28.--29. "PWMSEL,PWM Timer Clock Source Select ." "0: Clock source from HCLK,1: Clock source from XTL_32K,?,?"
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bitfld.long 0x4 20.--22. "TMRFSEL,TimerF Clock Source Select." "0: Clock source from external XTL_32K/32,1: Clock source from external XTL_32K/(4x32),?,?,?,?,?,?"
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newline
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bitfld.long 0x4 16.--18. "TMR2SEL,Timer2 Clock Source Select." "0: Clock source from HCLK,1: Clock source from XTL_32K.. Clock source from..,?,?,?,?,?,?"
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bitfld.long 0x4 12.--14. "TMR1SEL,Timer1 Clock Source Select." "0: Clock source from HCLK,1: Clock source from XTL_32K.. Clock source from..,?,?,?,?,?,?"
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newline
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bitfld.long 0x4 8.--10. "TMR0SEL,Timer0 Clock Source Select." "0: Clock source from HCLK,1: Clock source from XTL_32K.. Clock source from..,?,?,?,?,?,?"
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bitfld.long 0x4 4.--5. "SPI0SEL,SPI0 Clock Source Select." "0: Clock source from HCLK,1: Clock source from PLL_FOUT.. Clock source from..,?,?"
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newline
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bitfld.long 0x4 2.--3. "ADCSEL,ADC Clock Source Select." "0: Clock source from PLL_FOUT,1: Clock source from HCLK .. Clock source from RC_46M,?,?"
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bitfld.long 0x4 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect) . These bits are protected bits. To program these bits needs an open lock sequence write '59h' '16h' '88h' to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address.." "0: Clock source from HCLK/2048,1: Clock source from XTL_32K,?,?"
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line.long 0x8 "CLK_CLKDIV,Clock Divider Number Register"
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hexmask.long.byte 0x8 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source. The ADC engine clock must meet the constraint: ADCLK ( HCKL/2."
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hexmask.long.byte 0x8 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source."
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group.long 0x20++0x3
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line.long 0x0 "CLK_PLLCON,PLL Control Register"
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tree.end
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tree "GPIO (General Purpose I/Os)"
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base ad:0x50004000
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group.long 0x0++0x3
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line.long 0x0 "PA_MODE,GPIO PA Pin I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 26.--27. "MODE13,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 22.--23. "MODE11,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 18.--19. "MODE9,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 14.--15. "MODE7,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 10.--11. "MODE5,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 6.--7. "MODE3,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 2.--3. "MODE1,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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group.long 0x8++0x3
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line.long 0x0 "PA_DOUT,GPIO PA Data Output Value"
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hexmask.long.word 0x0 0.--15. 1. "DOUT,Port [A/B] Pin[N] Output Value. Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output open-drain or quasi-bidirectional mode.. Note: PB_DOUT[3:0] are reserved to 0."
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rgroup.long 0x10++0x3
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line.long 0x0 "PA_PIN,GPIO PA Pin Value"
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hexmask.long.word 0x0 0.--15. 1. "PIN,Port [A/B] Pin[N] Pin Values. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low. . Note: PB_PIN[3:0] are reserved to 0."
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group.long 0x18++0xB
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line.long 0x0 "PA_INTTYPE,GPIO PA Interrupt Trigger Type"
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hexmask.long.word 0x0 0.--15. 1. "TYPE,Port [A/B] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control. TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered the input source is sampled by one HCLK.."
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line.long 0x4 "PA_INTEN,GPIO PA Interrupt Enable"
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bitfld.long 0x4 31. "RHIEN15,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 30. "RHIEN14,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 29. "RHIEN13,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 28. "RHIEN12,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 27. "RHIEN11,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 26. "RHIEN10,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 25. "RHIEN9,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 24. "RHIEN8,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 23. "RHIEN7,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 22. "RHIEN6,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 21. "RHIEN5,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 20. "RHIEN4,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 19. "RHIEN3,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 18. "RHIEN2,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 17. "RHIEN1,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 16. "RHIEN0,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 15. "FLIEN15,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 14. "FLIEN14,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 13. "FLIEN13,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 12. "FLIEN12,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 11. "FLIEN11,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 10. "FLIEN10,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 9. "FLIEN9,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 8. "FLIEN8,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 7. "FLIEN7,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 6. "FLIEN6,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 5. "FLIEN5,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 4. "FLIEN4,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 3. "FLIEN3,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 2. "FLIEN2,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 1. "FLIEN1,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 0. "FLIEN0,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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line.long 0x8 "PA_INTSRC,GPIO PA Interrupt Source Flag"
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hexmask.long.word 0x8 0.--15. 1. "INTSRC,Port [A/B] Interrupt Source Flag. Read operation:."
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group.long 0x40++0x3
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line.long 0x0 "PB_MODE,GPIO PA Pin I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 28.--29. "MODE14,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 26.--27. "MODE13,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 24.--25. "MODE12,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 22.--23. "MODE11,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 20.--21. "MODE10,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 18.--19. "MODE9,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 16.--17. "MODE8,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 14.--15. "MODE7,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 12.--13. "MODE6,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 10.--11. "MODE5,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 8.--9. "MODE4,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 6.--7. "MODE3,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 4.--5. "MODE2,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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newline
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bitfld.long 0x0 2.--3. "MODE1,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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bitfld.long 0x0 0.--1. "MODE0,Port [A/B] Pin[N] I/O Mode Control . Each GPIO Px pin has four modes:. Note: PB_MODE[7:0] are reserved to 0." "0: GPIO Px[n] pin is in INPUT mode,1: GPIO Px[n] pin is in OUTPUT mode,?,?"
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group.long 0x48++0x3
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line.long 0x0 "PB_DOUT,GPIO PA Data Output Value"
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hexmask.long.word 0x0 0.--15. 1. "DOUT,Port [A/B] Pin[N] Output Value. Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output open-drain or quasi-bidirectional mode.. Note: PB_DOUT[3:0] are reserved to 0."
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rgroup.long 0x50++0x3
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line.long 0x0 "PB_PIN,GPIO PA Pin Value"
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hexmask.long.word 0x0 0.--15. 1. "PIN,Port [A/B] Pin[N] Pin Values. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low. . Note: PB_PIN[3:0] are reserved to 0."
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group.long 0x58++0xB
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line.long 0x0 "PB_INTTYPE,GPIO PA Interrupt Trigger Type"
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hexmask.long.word 0x0 0.--15. 1. "TYPE,Port [A/B] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control. TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered the input source is sampled by one HCLK.."
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line.long 0x4 "PB_INTEN,GPIO PA Interrupt Enable"
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bitfld.long 0x4 31. "RHIEN15,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 30. "RHIEN14,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 29. "RHIEN13,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 28. "RHIEN12,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 27. "RHIEN11,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 26. "RHIEN10,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 25. "RHIEN9,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 24. "RHIEN8,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 23. "RHIEN7,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 22. "RHIEN6,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 21. "RHIEN5,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 20. "RHIEN4,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 19. "RHIEN3,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 18. "RHIEN2,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 17. "RHIEN1,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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bitfld.long 0x4 16. "RHIEN0,Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High. RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-to-high or level-high..,1: Enable Px.n for low-to-high or level-high.."
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newline
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bitfld.long 0x4 15. "FLIEN15,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 14. "FLIEN14,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 13. "FLIEN13,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 12. "FLIEN12,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 11. "FLIEN11,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 10. "FLIEN10,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 9. "FLIEN9,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 8. "FLIEN8,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 7. "FLIEN7,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 6. "FLIEN6,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 5. "FLIEN5,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 4. "FLIEN4,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 3. "FLIEN3,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 2. "FLIEN2,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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newline
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bitfld.long 0x4 1. "FLIEN1,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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bitfld.long 0x4 0. "FLIEN0,Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low. FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set '1' also enables the pin wake-up function.. When setting the.." "0: Disable Px.n for low-level or high-to-low..,1: Enable Px.n for low-level or high-to-low interrupt"
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line.long 0x8 "PB_INTSRC,GPIO PA Interrupt Source Flag"
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hexmask.long.word 0x8 0.--15. 1. "INTSRC,Port [A/B] Interrupt Source Flag. Read operation:."
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tree.end
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tree "INT (Interrupt Multiplexer)"
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base ad:0x50000300
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rgroup.long 0x0++0xB
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line.long 0x0 "IRQ0_SRC,IRQ0 (WDT) Interrupt Source Identity Register"
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bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: WDT_INT" "0: WDT_INT,?,?,?,?,?,?,?"
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line.long 0x4 "IRQ1_SRC,IRQ1 (APU) Interrupt Source Identity Register"
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bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: APU_INT" "0: APU_INT,?,?,?,?,?,?,?"
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line.long 0x8 "IRQ2_SRC,IRQ2 (ADC) Interrupt Source Identity Register"
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bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: ADC_INT" "0: ADC_INT,?,?,?,?,?,?,?"
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rgroup.long 0x14++0x17
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line.long 0x0 "IRQ5_SRC,IRQ5 (Timer0) Interrupt Source Identity Register"
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bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: Timer0_INT" "0: Timer0_INT,?,?,?,?,?,?,?"
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line.long 0x4 "IRQ6_SRC,IRQ6 (Timer1) Interrupt Source Identity Register"
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bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: Timer1_INT" "0: Timer1_INT,?,?,?,?,?,?,?"
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line.long 0x8 "IRQ7_SRC,IRQ7 (Timer2) Interrupt Source Identity Register"
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bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: Timer2_INT" "0: Timer2_INT,?,?,?,?,?,?,?"
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line.long 0xC "IRQ8_SRC,IRQ8 (GPA/B) Interrupt Source Identity Register"
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bitfld.long 0xC 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: GPB_INT. Bit0: GPA_INT" "0: GPA_INT,1: GPB_INT,?,?,?,?,?,?"
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line.long 0x10 "IRQ9_SRC,IRQ9 (SPI0) Interrupt Source Identity Register"
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bitfld.long 0x10 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: SPI0_INT" "0: SPI0_INT,?,?,?,?,?,?,?"
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line.long 0x14 "IRQ10_SRC,IRQ10 (PWM) Interrupt Source Identity Register"
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bitfld.long 0x14 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: PWM_INT" "0: PWM_INT,?,?,?,?,?,?,?"
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rgroup.long 0x30++0xB
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line.long 0x0 "IRQ12_SRC,IRQ12 (TimerF) Interrupt Source Identity Register"
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bitfld.long 0x0 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: TimerF_INT" "0: TimerF_INT,?,?,?,?,?,?,?"
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line.long 0x4 "IRQ13_SRC,IRQ13 (RTC) Interrupt Source Identity Register"
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bitfld.long 0x4 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: RTC_INT" "0: RTC_INT,?,?,?,?,?,?,?"
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line.long 0x8 "IRQ14_SRC,IRQ14 (PWRWU) Interrupt Source Identity Register"
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bitfld.long 0x8 0.--2. "INT_SRC,Interrupt Source Identity. Bit2: 0. Bit1: 0. Bit0: PWRWU_INT" "0: PWRWU_INT,?,?,?,?,?,?,?"
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group.long 0x80++0x7
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line.long 0x0 "NMI_SEL,NMI Source Interrupt Select Control Register"
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bitfld.long 0x0 7. "IRQ_TM,IRQ Test Mode. This bit is the protected bit. To program this bit needs an open lock sequence write '59h' '16h' '88h' to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.." "0: The interrupt register MCU_IRQ operates in..,1: All the interrupts from peripheral to MCU are.."
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hexmask.long.byte 0x0 0.--3. 1. "NMI_SEL,NMI Source Interrupt Select. The NMI interrupt to Cortex-M0 can be selected from one of the interrupt[15:0].. The NMI_SEL bit is used to select the NMI interrupt source.. Note: IRQ4 and IRQ15 are reserved in N571P032."
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line.long 0x4 "MCU_IRQ,MCU IRQ Number Identify Register"
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hexmask.long.word 0x4 0.--15. 1. "MCU_IRQ,MCU IRQ Source Test Mode. The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to MCU Cortex-M0 the normal mode and test mode.. When.."
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tree.end
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tree "PWM (PWM Generator and Capture Timer)"
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|
base ad:0x40040000
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group.long 0x0++0x13
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line.long 0x0 "PWM_CLKPSC,PWM Prescaler Register"
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hexmask.long.byte 0x0 24.--31. 1. "DZI1,Dead Zone Interval Register 1. These 8 bits determine dead zone length.. The unit time of dead zone length is that from clock selector."
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hexmask.long.byte 0x0 16.--23. 1. "DZI0,Dead Zone Interval Register 0. These 8 bits determine dead zone length.. The unit time of dead zone length is that from clock selector."
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newline
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hexmask.long.byte 0x0 0.--7. 1. "CLKPSC,Clock Prescaler For PWM Timer. Clock input is divided by (CLKPSC + 1) ."
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line.long 0x4 "PWM_CLKDIV,PWM Clock Select Register"
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bitfld.long 0x4 0.--2. "CLKDIV,PWM Timer Clock Source Selection. Value : Input clock divided by. 000 : 2. 001 : 4. 010 : 8. 011 : 16. 1xx : 1" "0,1,2,3,4,5,6,7"
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line.long 0x8 "PWM_CTL,PWM Control Register"
|
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bitfld.long 0x8 5. "DTEN1,Dead-Zone 1 Generator Enable/Disable." "0: Disable,1: Enable"
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bitfld.long 0x8 4. "DTEN0,Dead-Zone 0 Generator Enable/Disable." "0: Disable,1: Enable"
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newline
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bitfld.long 0x8 3. "CNTMODE,PWM-Timer Auto-Reload/One-Shot Mode." "0: One-Shot Mode,1: Auto-reload Mode"
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bitfld.long 0x8 2. "PINV,PWM-Timer Output Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON"
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newline
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bitfld.long 0x8 0. "CNTEN,PWM-Timer Enable." "0: Stop PWM-Timer Running,1: Enable PWM-Timer"
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line.long 0xC "PWM_PERIOD,PWM Period Register"
|
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hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Counter/Timer Reload Value. PERIOD determines the PWM period.."
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line.long 0x10 "PWM_CMPDAT0,PWM Comparator Register 0"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty ratio.. Assumption: PWM output initial is high. Note2: Any write to CMP will take effect in next PWM cycle."
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rgroup.long 0x14++0x3
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line.long 0x0 "PWM_CNT,PWM Counter Register"
|
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Counter Register. Reports the current value of the 16-bit down counter."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "PWM_CMPDAT1,PWM Comparator Register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty ratio.. Assumption: PWM output initial is high. Note2: Any write to CMP will take effect in next PWM cycle."
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|
group.long 0x28++0x3
|
|
line.long 0x0 "PWM_CMPDAT2,PWM Comparator Register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty ratio.. Assumption: PWM output initial is high. Note2: Any write to CMP will take effect in next PWM cycle."
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|
group.long 0x34++0x3
|
|
line.long 0x0 "PWM_CMPDAT3,PWM Comparator Register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register. CMP determines the PWM duty ratio.. Assumption: PWM output initial is high. Note2: Any write to CMP will take effect in next PWM cycle."
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|
group.long 0x40++0x7
|
|
line.long 0x0 "PWM_INTEN,PWM Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "PIEN,PWM Timer Interrupt Enable." "0: Disable,1: Enable"
|
|
line.long 0x4 "PWM_INTSTS,PWM Interrupt Flag Register"
|
|
bitfld.long 0x4 0. "PIF,PWM Timer Interrupt Flag. Flag is set by hardware when PWM down counter reaches zero software can clear this bit by writing '1' to it." "0,1"
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|
group.long 0x50++0x3
|
|
line.long 0x0 "PWM_CAPCTL,Capture Control Register"
|
|
bitfld.long 0x0 7. "CFLIF,PWM_FCAPDAT Latched Indicator Bit. When input channel has a falling transition PWM_FCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1"
|
|
bitfld.long 0x0 6. "CRLIF,PWM_RCAPDAT Latched Indicator Bit. When input channel has a rising transition PWM_RCAPDAT was latched with the value of PWM down-counter and this bit is set by hardware software can clear this bit by writing a zero to it." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CAPIF,Capture Interrupt Indication Flag. Note:If this bit is '1' PWM counter will not be reloaded when next capture interrupt occurs." "0,1"
|
|
bitfld.long 0x0 3. "CAPEN,Capture Channel Input Transition Enable/Disable. When enabled Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition.. When disabled Capture function is inactive as is.." "0: Disable capture function,1: Enable capture function"
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|
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|
|
bitfld.long 0x0 2. "CFLIEN,Falling Latch Interrupt Enable ON/OFF. When enabled capture block generates an interrupt on falling edge of input." "0: Disable falling latch interrupt,1: Enable falling latch interrupt"
|
|
bitfld.long 0x0 1. "CRLIEN,Rising Latch Interrupt Enable ON/OFF. When enabled capture block generates an interrupt on rising edge of input." "0: Disable rising latch interrupt,1: Enable rising latch interrupt"
|
|
newline
|
|
bitfld.long 0x0 0. "CAPINV,Inverter ON/OFF." "0: Inverter OFF,1: Inverter ON. Reverse the input signal from GPIO.."
|
|
rgroup.long 0x58++0x7
|
|
line.long 0x0 "PWM_RCAPDAT,Capture Rising Latch Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RCAPDAT,Capture Rising Latch Register. In Capture mode this register is latched with the value of the PWM counter on a rising edge of the input signal."
|
|
line.long 0x4 "PWM_FCAPDAT,Capture Falling Latch Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "FCAPDAT,Capture Falling Latch Register. In Capture mode this register is latched with the value of the PWM counter on a falling edge of the input signal."
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "PWM_PCEN,PWM Output and Capture Input Enable Register"
|
|
bitfld.long 0x0 8. "CAPINEN,Capture Input Enable Register." "0: OFF (PB.12 pin input disconnected from Capture..,1: ON (PB.12 pin if in PWM alternative function.."
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|
bitfld.long 0x0 3. "POEN3,PWM3 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPB_MFP Table 58)" "0: Disable PWM3 output to pin,1: Enable PWM3 output to pin"
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|
newline
|
|
bitfld.long 0x0 2. "POEN2,PWM2 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 58)" "0: Disable PWM2 output to pin,1: Enable PWM2 output to pin"
|
|
bitfld.long 0x0 1. "POEN1,PWM1 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 58)" "0: Disable PWM1 output to pin,1: Enable PWM1 output to pin"
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|
newline
|
|
bitfld.long 0x0 0. "POEN0,PWM0 Output Enable Register. Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 58)" "0: Disable PWM0 output to pin,1: Enable PWM0 output to pin"
|
|
tree.end
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "RTC_CTL,RTC Control Register"
|
|
bitfld.long 0x0 3.--4. "RTIS,RTC Timer Interval Select. These two bits select the timeout interval for the RTC. ." "0: Time-out frequency is 0.25Hz,1: Time-out frequency is 2Hz,?,?"
|
|
bitfld.long 0x0 2. "RTCE,RTC Enable." "0: Disable RTC function,1: Enable RTC function"
|
|
bitfld.long 0x0 1. "RTIE,RTC Interrupt Enable." "0: Disable the RTC interrupt,1: Enable the RTC interrupt"
|
|
bitfld.long 0x0 0. "RTIF,RTC Interrupt Flag. If the RTC interrupt is enabled then the hardware will set this bit to indicate that the RTC interrupt has occurred. If the RTC interrupt is not enabled then this bit indicates that a timeout period has elapsed.. Note: This bit.." "0: RTC interrupt does not occur,1: RTC interrupt occurs"
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|
tree.end
|
|
tree "SCS (System Controllable Space)"
|
|
base ad:0xE000E000
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "NVIC_ISER,IRQ0 ~ IRQ15 Set-Enable Control Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SETENA,Interrupt Set-Enable Bit. The NVIC_ISER register enables interrupts and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).. . Write Operation: ."
|
|
group.long 0x180++0x3
|
|
line.long 0x0 "NVIC_ICER,IRQ0 ~ IRQ15 Clear-Enable Control Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CLRENA,Interrupt Clear-Enable Bit. The NVIC_ICER register disables interrupts and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).. . Write Operation: ."
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|
group.long 0x200++0x3
|
|
line.long 0x0 "NVIC_ISPR,IRQ0 ~ IRQ15 Set-Pending Control Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SETPEND,Interrupt Set-Pending Bit. The NVIC_ISPR register forces interrupts into the pending state and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).. . Write Operation: ."
|
|
group.long 0x280++0x3
|
|
line.long 0x0 "NVIC_ICPR,IRQ0 ~ IRQ15 Clear-Pending Control Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CLRPEND,Interrupt Clear-Pending Bit. The NVIC_ICPR register removes the pending state of associated interrupts and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ15 (Vector number from 16 ~ 31).. Write.."
|
|
group.long 0x400++0xF
|
|
line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ3 Priority Control Register"
|
|
bitfld.long 0x0 30.--31. "PRI_3,Priority Of IRQ3. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "PRI_2,Priority Of IRQ2. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "PRI_1,Priority Of IRQ1. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "PRI_0,Priority Of IRQ0. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0x4 "NVIC_IPR1,IRQ4 ~ IRQ7 Priority Control Register"
|
|
bitfld.long 0x4 30.--31. "PRI_7,Priority Of IRQ7. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 22.--23. "PRI_6,Priority Of IRQ6. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "PRI_5,Priority Of IRQ5. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x4 6.--7. "PRI_4,Priority Of IRQ4. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0x8 "NVIC_IPR2,IRQ8 ~ IRQ11 Priority Control Register"
|
|
bitfld.long 0x8 30.--31. "PRI_11,Priority Of IRQ11. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "PRI_10,Priority Of IRQ10. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "PRI_9,Priority Of IRQ9. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "PRI_8,Priority Of IRQ8. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
line.long 0xC "NVIC_IPR3,IRQ12 ~ IRQ15 Priority Control Register"
|
|
bitfld.long 0xC 30.--31. "PRI_15,Priority Of IRQ15. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PRI_14,Priority Of IRQ14. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PRI_13,Priority Of IRQ13. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PRI_12,Priority Of IRQ12. '0' denotes the highest priority and '3' denotes lowest priority" "0,1,2,3"
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40030000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "SPI0_CTL,Control and Status Register"
|
|
bitfld.long 0x0 20. "REORDER,BYTE ENDIAN." "0: Disable the BYTE ENDIAN,1: Enable the BYTE ENDIAN. Only the 16 24 and 32.."
|
|
bitfld.long 0x0 18. "SLAVE,Master/Slave Mode Select." "0: Master mode,1: Slave mode"
|
|
newline
|
|
bitfld.long 0x0 17. "UNIT_INTEN,Unit Transfer Interrupt Enable." "0: Disable SPI Unit Transfer Interrupt,1: Enable SPI Unit Transfer Interrupt to CPU"
|
|
bitfld.long 0x0 16. "UNIT_INTSTS,Unit Transfer Interrupt Status. Note: This bit is read only but can be cleared by writing 1 to this bit." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SUSPITV,Suspend Interval (Master Mode Only). (SUSPITV+2)* SPI0_CLK clock cycles . Note: SUSPITV cannot be '0'."
|
|
bitfld.long 0x0 11. "CLKP,Clock Polarity." "0: SPI_SCLK0 idle low,1: SPI_SCLK0 idle high"
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|
newline
|
|
bitfld.long 0x0 10. "LSB,Send LSB First." "0: The MSB is transmitted/received first (which bit..,1: The LSB (SPI0_TXn[0]) is sent first to.."
|
|
bitfld.long 0x0 8.--9. "TX_NUM,Transmit/Receive Numbers. This field specifies how many transmit/receive numbers should be executed in one transfer.." "0: Only one transmit/receive will be executed in..,1: Two successive transmit/receive will be executed..,?,?"
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|
newline
|
|
hexmask.long.byte 0x0 3.--7. 1. "DWIDTH,Transmit Bit Length. This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.."
|
|
bitfld.long 0x0 2. "TX_NEG,Transmit On Negative Edge." "0: The output on SPI_MOSI0 is changed on the rising..,1: The output on SPI_MOSI0 is changed on the.."
|
|
newline
|
|
bitfld.long 0x0 1. "RX_NEG,Receive On Negative Edge." "0: The input on SPI_MISO0 is latched on the rising..,1: The input on SPI_MISO0 is latched on the falling.."
|
|
bitfld.long 0x0 0. "GO_BUSY,Go And Busy Status. NOTE: All registers should be set readily before writing 1 to the GO_BUSY bit. When a transfer is in progress writing to any register of the SPI core has no effect." "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit starts the transfer. This.."
|
|
line.long 0x4 "SPI0_CLKDIV,Clock Divider Register (Master Only)"
|
|
hexmask.long.word 0x4 0.--15. 1. "DIVIDER,Clock Divider Register (Master Mode Only). SPI0 clock pin SPI_SCLK0 output clock frequency is SPI0_CIN/(DIVIDER+1).DIVIDER can be from 0 to 65535. But due to I/O transaction speed limitation the maximum clock of SPI_SCLK0 is 23 MHz. So the.."
|
|
line.long 0x8 "SPI0_SSCTL,Slave Select Register"
|
|
bitfld.long 0x8 5. "LTRIG_FLAG,Level Trigger Flag (Slave Mode Only). When the SS_LTRIG bit is set in slave mode this bit can be read to indicate the received bit number meets the requirement or not.. . Note 1: This bit is READ only." "0: One of the received number and the received bit..,1: This bit is READ only"
|
|
bitfld.long 0x8 4. "SS_LTRIG,Slave Select Level Trigger (Slave Mode Only)." "0: The input slave select signal is edge-trigger.,1: The slave select signal will be level-trigger."
|
|
newline
|
|
bitfld.long 0x8 3. "AUTOSS,Automatic Slave Select (Master Mode Only)." "0: Slave select signal (SPI_SSB00/SPI_SSB01) is..,1: Slave select signal (SPI_SSB00/SPI_SSB01) is.."
|
|
bitfld.long 0x8 2. "SS_LVL,Slave Select Active Level. It defines the active level of device/slave select signal.." "0: The SPI_SSB00/SPI_SSB01 slave select signal is..,1: The SPI_SSB00/SPI_SSB01 slave select signal is.."
|
|
newline
|
|
bitfld.long 0x8 0.--1. "SS,Slave Select Pin Control. If AUTOSS bit is 0 . SPI0_SSB00 and SPI0_SSB01 output are determined by SS[0] and SS[1] respectively. . Note 1: This interface can only drive one device/slave at a given time. Therefore the slaves select of the selected.." "0: Any bit location of this field forces the pin to..,1: This interface can only drive one device/slave..,2: SPIn_SSB10 is also defined as device/slave..,?"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "SPI0_RX0,Data Receive Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register. Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops."
|
|
line.long 0x4 "SPI0_RX1,Data Receive Register 0"
|
|
hexmask.long 0x4 0.--31. 1. "RX,Data Receive Register. Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops."
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "SPI0_TX0,Data Transmit Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register. Note: The SPI0_RXn and SPI0_TXn registers share the same flip-flops which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI0_TXn register between the two.."
|
|
line.long 0x4 "SPI0_TX1,Data Transmit Register 0"
|
|
hexmask.long 0x4 0.--31. 1. "TX,Data Transmit Register. Note: The SPI0_RXn and SPI0_TXn registers share the same flip-flops which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI0_TXn register between the two.."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "SPI0_RCLK,SPI0 Receive Timing Control Register"
|
|
bitfld.long 0x0 2.--3. "SPI0_CTIM,Coarse Timing Control For SPI0 Data Receiving. Setting these bits can adjust receiving clock for latching serial-in data correctly in high speed transmission mode. ." "0: Receiving data clock of SPI0 is same as the..,1: Receiving data clock of SPI0 is delayed 2 half..,?,?"
|
|
bitfld.long 0x0 0.--1. "SPI0_FTIM,Fine Timing Control For SPI0 Data Receiving. The delay timing selected by SPI0_CTIM can be further tuned finely by SPI0_FTIM. ." "0: Receiving data clock of SPI0 has extra 7.5nS delay,1: Receiving data clock of SPI0 has extra 5.0nS..,?,?"
|
|
tree.end
|
|
tree "SYS (System Control Registers)"
|
|
base ad:0x50000000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SYS_PDID,Product Identifier Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "IMG2,Product Identifier. Data in MAP2 of information block are copied to this register after power on. MAP2 is used to store part number defined by Nuvoton."
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "SYS_RSTSTS,System Reset Source Register"
|
|
bitfld.long 0x0 6. "PMURSTF,Reset Source From PMU. The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source.. Note: Write 1 to clear this bit to 0." "0: No reset from PMU,1: The PMU has issued the reset signal to reset the.."
|
|
bitfld.long 0x0 3. "LVRF,LVR Reset Flag . The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source. . Note: Write 1 to clear this bit to 0." "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
|
|
newline
|
|
bitfld.long 0x0 2. "WDTRF,Reset Source From WDG. The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.. Note: Write 1 to clear this bit to 0." "0: No reset from Watch-Dog,1: The Watch-Dog module issued the reset signal to.."
|
|
bitfld.long 0x0 1. "PINRF,nRESET Pin Reset Flag . The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source. . Note: Write 1 to clear this bit to 0." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.."
|
|
newline
|
|
bitfld.long 0x0 0. "PORF,POR Reset Flag . The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller to indicate the previous reset source. . Note: Write 1 to clear this bit to 0." "0: No reset from POR,1: Power-on Reset (POR) Controller had issued the.."
|
|
line.long 0x4 "SYS_IPRST0,IP Reset Control Resister0"
|
|
bitfld.long 0x4 2. "CPUWS,CPU Wait-State Control For OTP Memory Access. Note: there must be 1 HCLK wait state if HCLK equal 23MHz." "0: 1 HCLK clock wait-state,1: zero wait-state"
|
|
bitfld.long 0x4 1. "CPURST,CPU Kernel One Shot Reset. Setting this bit will reset the CPU kernel and OTP Memory Controller(OMC) this bit will automatically return to '0' after the 2 clock cycles." "0: Normal,1: Reset CPU"
|
|
newline
|
|
bitfld.long 0x4 0. "CHIPRST,CHIP One Shot Reset. Set this bit will reset the whole chip this bit will automatically return to '0' after 2 clock cycles.. CHIPRST is same as POR reset all the chip modules are reset and the chip configuration settings from OTP are reloaded.." "0: Normal,1: Reset CHIP"
|
|
line.long 0x8 "SYS_IPRST1,IP Reset Control Resister1"
|
|
bitfld.long 0x8 28. "ADCRST,ADC Controller Reset ." "0: Normal Operation,1: Reset"
|
|
bitfld.long 0x8 20. "PWMRST,PWM Controller Reset." "0: Normal Operation,1: Reset"
|
|
newline
|
|
bitfld.long 0x8 12. "SPI0RST,SPI0 Controller Reset." "0: Normal Operation,1: Reset"
|
|
bitfld.long 0x8 6. "TMRFRST,TimerF Controller Reset." "0: Normal operation,1: Reset"
|
|
newline
|
|
bitfld.long 0x8 5. "APURST,APU Controller Reset." "0: Normal operation,1: Reset"
|
|
bitfld.long 0x8 4. "TMR2RST,Timer2 Controller Reset." "0: Normal operation,1: Reset"
|
|
newline
|
|
bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset." "0: Normal Operation,1: Reset"
|
|
bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset." "0: Normal Operation,1: Reset"
|
|
newline
|
|
bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset." "0: Normal operation,1: Reset"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "SYS_BODCTL,Brown-Out Detector Control Register"
|
|
bitfld.long 0x0 8.--9. "LVR_FILTER," "0: LVR outputs without to be filtered,1: LVR output will be filtered by 2 HCLK,?,?"
|
|
bitfld.long 0x0 7. "LVR_EN,Low Voltage Reset (LVR) Enable (Protected Bit). The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default.." "0: Disable LVR function,1: Enable LVR function - After enable the bit the.."
|
|
newline
|
|
bitfld.long 0x0 6. "BOD_OUT,The Status for Brown-Out Detector Output It's a read only bit.." "0: The detected voltage is lower than BOD_VL..,1: The detected voltage is higher than BOD_VL setting"
|
|
bitfld.long 0x0 2. "BOD_POL,Brown-Out Detector Output Polarity Select." "0: PB.15 will output the BOD out directly when..,1: PB.15 will output the inverse of BOD out when.."
|
|
newline
|
|
bitfld.long 0x0 1. "BOD_VL,Brown-Out Detector Threshold Voltage Selection (Initiated & Protected Bit)." "0: Threshold voltage is 2.7V,1: Threshold voltage is 3.0V"
|
|
bitfld.long 0x0 0. "BOD_EN,Brown-Out Detector Enable (Initiated & Protected Bit)." "0: Brown-Out Detector function is disabled,1: Brown-Out Detector function is enabled"
|
|
line.long 0x4 "SYS_PORCTL,Power-On-Reset Controller Register"
|
|
bitfld.long 0x4 16. "POROFFSTS,This bit is status bit of POR it is read only.." "0: POR is active now,1: POR is non-active now while POROFF equals 0x5aa5"
|
|
hexmask.long.word 0x4 0.--15. 1. "POROFF,Power-On Reset Enable Code (Write Protect) . When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.."
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "SYS_GPA_MFP,GPIO PA Multiple Alternate Functions and Input Type Control Register"
|
|
bitfld.long 0x0 15. "PA15MFP," "0: The GPIOA-15 is selected to the pin PA.15,1: PGC Reference Voltage pin"
|
|
bitfld.long 0x0 14. "PA14MFP," "0: The GPIOA-14 is selected to the pin PA.14,1: MIC Bias pin"
|
|
newline
|
|
bitfld.long 0x0 13. "PA13MFP," "0: The GPIOA-13 is selected to the pin PA.13,1: Mic. IN- pin to Pre-Amp"
|
|
bitfld.long 0x0 12. "PA12MFP," "0: The GPIOA-12 is selected to the pin PA.12,1: Mic. IN+ pin to Pre-Amp"
|
|
newline
|
|
bitfld.long 0x0 11. "PA11MFP," "0: The GPIOA-11 is selected to the pin PA.11,1: ADC input channel 3"
|
|
bitfld.long 0x0 10. "PA10MFP," "0: The GPIOA-10 is selected to the pin PA.10,1: ADC input channel 2"
|
|
newline
|
|
bitfld.long 0x0 5. "PA5MFP," "0: The GPIOA-5 is selected to the pin PA.5,1: Timer0 counter external input"
|
|
bitfld.long 0x0 4. "PA4MFP," "0: The GPIOA-4 is selected to the pin PA.4,1: SPI0 data output"
|
|
newline
|
|
bitfld.long 0x0 3. "PA3MFP," "0: The GPIOA-3 is selected to the pin PA.3,1: SPI0 data input"
|
|
bitfld.long 0x0 2. "PA2MFP," "0: The GPIOA-2 is selected to the pin PA.2,1: SPI0 clock output"
|
|
newline
|
|
bitfld.long 0x0 1. "PA1MFP," "0: The GPIOA-1 is selected to the pin PA.1,1: SPI0 1st chip select output"
|
|
bitfld.long 0x0 0. "PA0MFP," "0: The GPIOA-0 is selected to the pin PA.0,1: SPI0 2nd chip select output"
|
|
line.long 0x4 "SYS_GPB_MFP,GPIO PB Multiple Alternate Functions and Input Type Control Register"
|
|
bitfld.long 0x4 15. "PB15MFP," "0: The GPIOB-15 is selected to the pin PB.15,1: BOD active signal output"
|
|
bitfld.long 0x4 14. "PB14MFP," "0: The GPIOB-14 is selected to the pin PB.14,1: Timer1 counter external input"
|
|
newline
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bitfld.long 0x4 13. "PB13MFP," "0: The GPIOB-13 is selected to the pin PB.13,1: IR carrier output"
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bitfld.long 0x4 12. "PB12MFP," "0: The GPIOB-12 is selected to the pin PB.12,1: PWM timer capture input"
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newline
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bitfld.long 0x4 11. "PB11MFP," "0: The GPIOB-11 is selected to the pin PB.11,1: PWM output pin 3"
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bitfld.long 0x4 10. "PB10MFP," "0: The GPIOB-10 is selected to the pin PB.10,1: PWM output pin 2"
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newline
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bitfld.long 0x4 9. "PB9MFP," "0: The GPIOB-9 is selected to the pin PB.9,1: PWM output pin 1"
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bitfld.long 0x4 8. "PB8MFP," "0: The GPIOB-8 is selected to the pin PB.8,1: PWM output pin 0"
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line.long 0x8 "SYS_GPA_HS,PA.4 ~ PA.0 High Speed Transition Control Register"
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hexmask.long.byte 0x8 0.--4. 1. "GPA_HS,"
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group.long 0x40++0x3
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line.long 0x0 "SYS_ICE_MFP,ICE Multi-Function-Pin Controller Register"
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bitfld.long 0x0 0. "ICE_EN,This bit will set ICE_CLK & ICE_DAT pins to be serial debug wires or PB.4/5." "0: ICE_CLK and ICE_DAT will be assigned as PB.4 and..,1: ICE_CLK and ICE_DAT will be set as ICE CLCOK/.."
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rgroup.long 0xF4++0x3
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line.long 0x0 "SYS_DEVICEID,Device ID Register"
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hexmask.long.word 0x0 0.--15. 1. "DEVICEID,Device ID Data . This register provides specific read-only information for the Device ID"
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rgroup.long 0xFC++0x3
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line.long 0x0 "SYS_IMGMAP1,MAP1 Data Image Register"
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hexmask.long 0x0 0.--31. 1. "IMG1,Data Image of MAP1. Data in MAP1 of information block are copied to this register after power on."
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group.long 0x100++0x3
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line.long 0x0 "SYS_REGLCTL,Register Lock Control Register"
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rbitfld.long 0x0 0. "REGLCTL,Protected Register Lock/Unlock Index (Read Only). SPI0_RCLK - address 0x4003_0030. WDT_CTL -- address 0x4000_4000" "0: Protected registers are locked. Any write to the..,1: Protected registers are unlocked"
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hexmask.long.byte 0x0 0.--7. 1. "SYS_REGLCTL,Register Lock Control Code (Write Only) . Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is.."
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group.long 0x120++0x3
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line.long 0x0 "SYS_PA_ADJ,PA Offset Voltage Adjustment Register"
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hexmask.long.byte 0x0 0.--5. 1. "PADCADJ,Turning the Offset voltage between SPKP/SPKN. PADCADJ[5] is selection bit PADCADJ[4:0] are offset trim bits.."
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tree.end
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tree "TMR (Timer Controller)"
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base ad:0x40010000
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group.long 0x0++0x7
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line.long 0x0 "TIMER0_CTL,Timer0 Control and Status Register"
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bitfld.long 0x0 31. "Reserved,Reserved." "0,1"
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bitfld.long 0x0 30. "CNTEN,Counter Enable Bit." "0: Stop/Suspend counting,1: Start counting"
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newline
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bitfld.long 0x0 29. "INTEN,Interrupt Enable Bit. If timer interrupt is enabled the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP." "0: Disable TIMER Interrupt,1: Enable TIMER Interrupt"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode." "0: The Timer is operating in the one-shot mode. The..,1: The Timer is operating in the periodic mode. The..,?,?"
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newline
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bitfld.long 0x0 26. "RSTCNT,Counter Reset Bit. Set this bit will reset the Timer counter pre-scale and also force CNTEN to 0.." "0: No effect,1: Reset Timer's pre-scale counter internal 16-bit.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the counter status of Timer.." "0: Timer is not active,1: Timer is active"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Timer Clock Prescaler."
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line.long 0x4 "TIMER0_CMP,Timer0 Compare Register"
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hexmask.long.word 0x4 0.--15. 1. "CMPDAT,Timer Comparison Value. Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.. Note 2: No matter CNTEN is 0 or 1 whenever software writes a new value into this register TIMER will restart counting by using this new value.."
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rgroup.long 0x8++0x7
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line.long 0x0 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
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bitfld.long 0x0 0. "TIF,Timer Interrupt Flag (Read Only). This bit indicates the interrupt status of Timer.. TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself." "0: No effect,1: CNT (TIMERx_CNT[15:0]) value matches the CMPDAT.."
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line.long 0x4 "TIMER0_CNT,Timer0 Data Register"
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hexmask.long.word 0x4 0.--15. 1. "CNT,Timer Data Register. User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1 "
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group.long 0x20++0x7
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line.long 0x0 "TIMER1_CTL,Timer0 Control and Status Register"
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bitfld.long 0x0 31. "Reserved,Reserved." "0,1"
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bitfld.long 0x0 30. "CNTEN,Counter Enable Bit." "0: Stop/Suspend counting,1: Start counting"
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newline
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bitfld.long 0x0 29. "INTEN,Interrupt Enable Bit. If timer interrupt is enabled the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP." "0: Disable TIMER Interrupt,1: Enable TIMER Interrupt"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode." "0: The Timer is operating in the one-shot mode. The..,1: The Timer is operating in the periodic mode. The..,?,?"
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newline
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bitfld.long 0x0 26. "RSTCNT,Counter Reset Bit. Set this bit will reset the Timer counter pre-scale and also force CNTEN to 0.." "0: No effect,1: Reset Timer's pre-scale counter internal 16-bit.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the counter status of Timer.." "0: Timer is not active,1: Timer is active"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Timer Clock Prescaler."
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line.long 0x4 "TIMER1_CMP,Timer0 Compare Register"
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hexmask.long.word 0x4 0.--15. 1. "CMPDAT,Timer Comparison Value. Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.. Note 2: No matter CNTEN is 0 or 1 whenever software writes a new value into this register TIMER will restart counting by using this new value.."
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rgroup.long 0x28++0x7
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line.long 0x0 "TIMER1_INTSTS,Timer0 Interrupt Status Register"
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bitfld.long 0x0 0. "TIF,Timer Interrupt Flag (Read Only). This bit indicates the interrupt status of Timer.. TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself." "0: No effect,1: CNT (TIMERx_CNT[15:0]) value matches the CMPDAT.."
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line.long 0x4 "TIMER1_CNT,Timer0 Data Register"
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hexmask.long.word 0x4 0.--15. 1. "CNT,Timer Data Register. User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1 "
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group.long 0x30++0x7
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line.long 0x0 "TIMERF_INTSTS,TimerF Interrupt Status Register"
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bitfld.long 0x0 1. "TFIE,TimerF Interrupt Enable." "0: Disable TimerF Interrupt,1: Enable TimerF Interrupt"
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bitfld.long 0x0 0. "TFIF,TimerF Interrupt Flag. This bit indicates the interrupt status of TimerF.. TFIF bit is set by hardware when TimerF time out. It is cleared by writing 1 to this bit.." "0: It indicates that TimerF does not time out yet,1: It indicates that TimerF time out. The interrupt.."
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line.long 0x4 "IR_CTL,IR Carrier Output Control Register"
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group.long 0x40++0x7
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line.long 0x0 "TIMER2_CTL,Timer0 Control and Status Register"
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bitfld.long 0x0 31. "Reserved,Reserved." "0,1"
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bitfld.long 0x0 30. "CNTEN,Counter Enable Bit." "0: Stop/Suspend counting,1: Start counting"
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newline
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bitfld.long 0x0 29. "INTEN,Interrupt Enable Bit. If timer interrupt is enabled the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP." "0: Disable TIMER Interrupt,1: Enable TIMER Interrupt"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Operating Mode." "0: The Timer is operating in the one-shot mode. The..,1: The Timer is operating in the periodic mode. The..,?,?"
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newline
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bitfld.long 0x0 26. "RSTCNT,Counter Reset Bit. Set this bit will reset the Timer counter pre-scale and also force CNTEN to 0.." "0: No effect,1: Reset Timer's pre-scale counter internal 16-bit.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the counter status of Timer.." "0: Timer is not active,1: Timer is active"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Timer Clock Prescaler."
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|
line.long 0x4 "TIMER2_CMP,Timer0 Compare Register"
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hexmask.long.word 0x4 0.--15. 1. "CMPDAT,Timer Comparison Value. Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly.. Note 2: No matter CNTEN is 0 or 1 whenever software writes a new value into this register TIMER will restart counting by using this new value.."
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rgroup.long 0x48++0x7
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line.long 0x0 "TIMER2_INTSTS,Timer0 Interrupt Status Register"
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bitfld.long 0x0 0. "TIF,Timer Interrupt Flag (Read Only). This bit indicates the interrupt status of Timer.. TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself." "0: No effect,1: CNT (TIMERx_CNT[15:0]) value matches the CMPDAT.."
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line.long 0x4 "TIMER2_CNT,Timer0 Data Register"
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hexmask.long.word 0x4 0.--15. 1. "CNT,Timer Data Register. User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1 "
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tree.end
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tree "WDT (Watchdog Timer)"
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|
base ad:0x40004000
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group.long 0x0++0x3
|
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line.long 0x0 "WDT_CTL,Watchdog Timer Control Register"
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bitfld.long 0x0 8.--10. "TOUTSEL,Watchdog Timer Interval Select. These three bits select the timeout interval for the Watchdog timer a watchdog reset will occur 1024 clock cycles later if Watchdog timer is not reset. . The WDT interrupt timeout is given by:. Where WDT_CLK is.." "0: 24 * WDT_CLK,1: 26 * WDT_CLK,?,?,?,?,?,?"
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bitfld.long 0x0 7. "WDTEN,Watchdog Timer Enable." "0: Disable the WDT(Watchdog timer) (This action..,1: Enable the WDT(Watchdog timer)"
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newline
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bitfld.long 0x0 6. "INTEN,Watchdog Time-Out Interrupt Enable." "0: Disable the WDT time-out interrupt,1: Enable the WDT time-out interrupt"
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bitfld.long 0x0 5. "WKF,WDT Time-Out Wake-Up Flag. If WDT causes CPU wake up from sleep or power-down mode this bit will be set to high.. Note: This bit is cleared by writing 1 to it." "0: WDT does not cause CPU wake-up,1: CPU wakes up from sleep or power-down mode by.."
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newline
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bitfld.long 0x0 4. "WKEN,WDT Time-Out Wake-Up Function Control. If this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will generate a wake-up.." "0: Enable the Wakeup function that WDT timeout can..,1: Disable WDT Wakeup CPU function"
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bitfld.long 0x0 3. "IF,Watchdog Timer Interrupt Flag. If the Watchdog timer interrupt is enabled then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled then this bit indicates that a.." "0: Watchdog timer interrupt has not occurred,1: Watchdog timer interrupt has occurred"
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newline
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bitfld.long 0x0 2. "RSTF,Watchdog Timer Reset Flag. When the Watchdog timer initiates a reset the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is.." "0: Watchdog timer reset has not occurred,1: Watchdog timer reset has occurred"
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bitfld.long 0x0 1. "RSTEN,Watchdog Timer Reset Enable. Setting this bit will enable the Watchdog timer reset function.. Note: This function cannot work with XTL32-based clock source." "0: Disable Watchdog timer reset function,1: Enable Watchdog timer reset function"
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newline
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bitfld.long 0x0 0. "RSTCNT,Clear Watchdog Timer . Set this bit will clear the Watchdog timer. . Note: This bit will auto clear after few clock cycles" "0: Writing 0 to this bit has no effect,1: Reset the contents of the Watchdog timer"
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tree.end
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AUTOINDENT.OFF
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