31767 lines
2.2 MiB
31767 lines
2.2 MiB
; --------------------------------------------------------------------------------
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|
; @Title: MSPM0 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2022-06-27 NEJ
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; 2023-03-31 NEJ
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; 2024-01-23 NEJ
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; 2024-02-20 NEJ
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; @Manufacturer: TI - Texas Instruments
|
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; @Doc: Generated (TRACE32, build: 166909.), based on:
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; MSPM0C110X_fixed.svd (Preliminary), MSPM0G110X.svd (Preliminary),
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; MSPM0G150X.svd (Preliminary), MSPM0G310X.svd (Preliminary),
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; MSPM0G350x.svd (Preliminary), MSPM0L110X.svd (Preliminary),
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; MSPM0L122X.svd (Preliminary), MSPM0L134X_fixed.svd (Preliminary),
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; MSPM0L130x.svd (Preliminary), MSPM0L222X.svd (Preliminary)
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; @Core: Cortex-M0+
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; @Chip: MSPM0C1103, MSPM0C1104, MSPM0G1105, MSPM0G1106,
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; MSPM0G1107, MSPM0G1505, MSPM0G1506, MSPM0G1507,
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; MSPM0G3105, MSPM0G3105Q1, MSPM0G3106, MSPM0G3106Q1,
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; MSPM0G3107, MSPM0G3107Q1, MSPM0G3505, MSPM0G3505Q1,
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; MSPM0G3506, MSPM0G3506Q1, MSPM0G3507, MSPM0G3507Q1,
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; MSPM0L1105, MSPM0L1106, MSPM0L1227, MSPM0L1228,
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; MSPM0L1303, MSPM0L1304, MSPM0L1304Q1, MSPM0L1305,
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; MSPM0L1305Q1, MSPM0L1306, MSPM0L1306Q1, MSPM0L1343,
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; MSPM0L1344, MSPM0L1345, MSPM0L1346, MSPM0L2227,
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; MSPM0L2228, MSPS003F3, MSPS003F4
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
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;
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; Redistribution and use in source and binary forms, with or without
|
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; modification, are permitted provided that the following conditions
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; are met:
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;
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; Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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;
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; Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
|
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; documentation and/or other materials provided with the
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; distribution.
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;
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; Neither the name of Texas Instruments Incorporated nor the names of
|
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; its contributors may be used to endorse or promote products derived
|
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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; --------------------------------------------------------------------------------
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; $Id: permspm0.per 17517 2024-02-21 10:31:51Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
|
|
ENUMDELIMITER ","
|
|
base ad:0x0
|
|
tree.close "Core Registers (Cortex-M0+)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0x8
|
|
if (CORENAME()=="CORTEXM1")
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
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|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
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|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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|
else
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
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|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
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|
rgroup.long 0x1c++0x03
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|
line.long 0x00 "STCR,SysTick Calibration Value Register"
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|
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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|
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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|
else
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|
rgroup.long 0x1c++0x03
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|
line.long 0x00 "STCR,SysTick Calibration Value Register"
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|
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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|
textline " "
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|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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|
rgroup.long 0xd00++0x03
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|
line.long 0x00 "CPUID,CPU ID Base Register"
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|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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|
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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|
textline " "
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|
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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|
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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|
group.long 0xd04++0x03
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|
line.long 0x00 "ICSR,Interrupt Control State Register"
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|
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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|
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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|
textline " "
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|
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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|
textline " "
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|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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|
if (CORENAME()=="CORTEXM0+")
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|
group.long 0xd08++0x03
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|
line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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|
else
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|
textline " "
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|
endif
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|
group.long 0xd0c++0x03
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|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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|
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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|
group.long 0xd1c++0x0b
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|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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|
line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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|
else
|
|
textline " "
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
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|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x0
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
tree "ADC0"
|
|
base ad:0x40004000
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "FSUB_0,Subscriber Configuration Register."
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher Configuration Register."
|
|
bitfld.long 0x0 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,ADC clock configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,Unlock key"
|
|
bitfld.long 0x0 5. "CLKCFG_CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "CLKCFG_CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CLKCFG_SAMPCLK,ADC sample clock source selection." "0: ULPCLK,1: SYSOSC,2: HFCLK,?"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_DMADONE,Raw interrupt flag for DMADONE." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_DMADONE,Raw interrupt flag for DMADONE." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 8. "INT_EVENT1_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_IMASK_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 8. "INT_EVENT1_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_RIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 8. "INT_EVENT1_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_MIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ISET_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ICLR_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask extension"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT2_IMASK_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_IMASK_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT2_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status extension"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT2_RIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_RIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT2_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status extension"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT2_MIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_MIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT2_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set extension"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT2_ISET_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_ISET_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT2_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear extension"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT2_ICLR_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT2_ICLR_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT2_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CTL0,Control Register 0"
|
|
bitfld.long 0x0 24.--26. "CTL0_SCLKDIV,Sample clock divider" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_4,3: DIV_BY_8,4: DIV_BY_16,5: DIV_BY_24,6: DIV_BY_32,7: DIV_BY_48"
|
|
bitfld.long 0x0 16. "CTL0_PWRDN,Power down policy" "0: AUTO,1: MANUAL"
|
|
bitfld.long 0x0 0. "CTL0_ENC,Enable conversion" "0: OFF,1: ON"
|
|
line.long 0x4 "CTL1,Control Register 1"
|
|
bitfld.long 0x4 28.--30. "CTL1_AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated." "0: SHIFT0,1: SHIFT1,2: SHIFT2,3: SHIFT3,4: SHIFT4,5: SHIFT5,6: SHIFT6,7: SHIFT7"
|
|
bitfld.long 0x4 24.--26. "CTL1_AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: DISABLE,1: AVG_2,2: AVG_4,3: AVG_8,4: AVG_16,5: AVG_32,6: AVG_64,7: AVG_128"
|
|
bitfld.long 0x4 20. "CTL1_SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: AUTO,1: MANUAL"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CTL1_CONSEQ,Conversion sequence mode" "0: SINGLE,1: SEQUENCE,2: REPEATSINGLE,3: REPEATSEQUENCE"
|
|
bitfld.long 0x4 8. "CTL1_SC,Start of conversion" "0: STOP,1: START"
|
|
bitfld.long 0x4 0. "CTL1_TRIGSRC,Sample trigger source" "0: SOFTWARE,1: EVENT"
|
|
line.long 0x8 "CTL2,Control Register 2"
|
|
hexmask.long.byte 0x8 24.--28. 1. "CTL2_ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode."
|
|
hexmask.long.byte 0x8 16.--20. 1. "CTL2_STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode."
|
|
hexmask.long.byte 0x8 11.--15. 1. "CTL2_SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger"
|
|
newline
|
|
bitfld.long 0x8 10. "CTL2_FIFOEN,Enable FIFO based operation" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "CTL2_DMAEN,Enable DMA trigger for data transfer." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 1.--2. "CTL2_RES,Resolution. These bits define the resolution of ADC conversion result." "0: BIT_12,1: BIT_10,2: BIT_8,?"
|
|
newline
|
|
bitfld.long 0x8 0. "CTL2_DF,Data read-back format. Data is always stored in binary unsigned format." "0: UNSIGNED,1: SIGNED"
|
|
group.long 0x1110++0xB
|
|
line.long 0x0 "CLKFREQ,Sample Clock Frequency Range Register"
|
|
bitfld.long 0x0 0.--2. "CLKFREQ_FRANGE,Frequency Range." "0: RANGE1TO4,1: RANGE4TO8,2: RANGE8TO16,3: RANGE16TO20,4: RANGE20TO24,5: RANGE24TO32,6: RANGE32TO40,7: RANGE40TO48"
|
|
line.long 0x4 "SCOMP0,Sample Time Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "SCOMP0_VAL,Specifies the number of sample clocks."
|
|
line.long 0x8 "SCOMP1,Sample Time Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "SCOMP1_VAL,Specifies the number of sample clocks."
|
|
group.long 0x1148++0x3
|
|
line.long 0x0 "WCLOW,Window Comparator Low Threshold Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WCLOW_DATA,If DF = 0 unsigned binary format has to be used."
|
|
group.long 0x1150++0x3
|
|
line.long 0x0 "WCHIGH,Window Comparator High Threshold Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WCHIGH_DATA,If DF = 0 unsigned binary format has to be used."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1180)++0x3
|
|
line.long 0x0 "MEMCTL[$1],Conversion Memory Control Register"
|
|
bitfld.long 0x0 28. "MEMCTL_WINCOMP,Enable window comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 24. "MEMCTL_TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: AUTO_NEXT,1: TRIGGER_NEXT"
|
|
bitfld.long 0x0 20. "MEMCTL_BCSEN,Enable burn out current source." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 16. "MEMCTL_AVGEN,Enable hardware averaging." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12. "MEMCTL_STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: SEL_SCOMP0,1: SEL_SCOMP1"
|
|
bitfld.long 0x0 8.--9. "MEMCTL_VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA,1: EXTREF,2: INTREF,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "MEMCTL_CHANSEL,Input channel select."
|
|
repeat.end
|
|
rgroup.long 0x1340++0x3
|
|
line.long 0x0 "STATUS,Status Register"
|
|
bitfld.long 0x0 1. "STATUS_REFBUFRDY,Indicates reference buffer is powered up and ready." "0: NOTREADY,1: READY"
|
|
rbitfld.long 0x0 0. "STATUS_BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: IDLE,1: ACTIVE"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0L110*")||cpuis("MSPM0L122*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*")||cpuis("MSPM0L222*"))
|
|
tree "ADC0_SVT"
|
|
base ad:0x4055A000
|
|
rgroup.long 0x160++0x3
|
|
line.long 0x0 "FIFODATA,FIFO Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "FIFODATA_DATA,Read from this data field returns the ADC sample from FIFO."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x280)++0x3
|
|
line.long 0x0 "MEMRES[$1],Memory Result Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "MEMRES_DATA,MEMRES result register."
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "ADC0"
|
|
base ad:0x40000000
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "FSUB_0,Subscriber Configuration Register."
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher Configuration Register."
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,ADC clock configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,Unlock key"
|
|
bitfld.long 0x0 5. "CLKCFG_CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "CLKCFG_CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CLKCFG_SAMPCLK,ADC sample clock source selection." "0: SYSOSC,1: ULPCLK,2: HFCLK,?"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 19. "INT_EVENT0_MIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_MIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 19. "INT_EVENT0_ISET_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ISET_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_DMADONE,Raw interrupt flag for DMADONE." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 19. "INT_EVENT0_ICLR_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ICLR_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_DMADONE,Raw interrupt flag for DMADONE." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 8. "INT_EVENT1_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_IMASK_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 8. "INT_EVENT1_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_RIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 8. "INT_EVENT1_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_MIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ISET_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ICLR_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_IMASK_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_IMASK_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_IMASK_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_IMASK_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_IMASK_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_IMASK_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_IMASK_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_IMASK_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_IMASK_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_IMASK_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_RIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_RIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_RIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 16. "INT_EVENT2_RIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_RIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_RIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 13. "INT_EVENT2_RIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_RIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 10. "INT_EVENT2_RIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_RIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_MIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_MIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_MIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_MIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_MIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_MIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_MIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_MIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_MIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_MIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_ISET_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ISET_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ISET_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ISET_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_ISET_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_ISET_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_ISET_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_ISET_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_ISET_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_ISET_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_ICLR_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ICLR_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ICLR_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ICLR_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "INT_EVENT2_ICLR_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT2_ICLR_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_ICLR_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT2_ICLR_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_ICLR_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT2_ICLR_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT2_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CTL0,Control Register 0"
|
|
bitfld.long 0x0 24.--26. "CTL0_SCLKDIV,Sample clock divider" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_4,3: DIV_BY_8,4: DIV_BY_16,5: DIV_BY_24,6: DIV_BY_32,7: DIV_BY_48"
|
|
bitfld.long 0x0 16. "CTL0_PWRDN,Power down policy" "0: AUTO,1: MANUAL"
|
|
bitfld.long 0x0 0. "CTL0_ENC,Enable conversion" "0: OFF,1: ON"
|
|
line.long 0x4 "CTL1,Control Register 1"
|
|
bitfld.long 0x4 28.--30. "CTL1_AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: SHIFT0,1: SHIFT1,2: SHIFT2,3: SHIFT3,4: SHIFT4,5: SHIFT5,6: SHIFT6,7: SHIFT7"
|
|
bitfld.long 0x4 24.--26. "CTL1_AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: DISABLE,1: AVG_2,2: AVG_4,3: AVG_8,4: AVG_16,5: AVG_32,6: AVG_64,7: AVG_128"
|
|
bitfld.long 0x4 20. "CTL1_SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: AUTO,1: MANUAL"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CTL1_CONSEQ,Conversion sequence mode" "0: SINGLE,1: SEQUENCE,2: REPEATSINGLE,3: REPEATSEQUENCE"
|
|
bitfld.long 0x4 8. "CTL1_SC,Start of conversion" "0: STOP,1: START"
|
|
bitfld.long 0x4 0. "CTL1_TRIGSRC,Sample trigger source" "0: SOFTWARE,1: EVENT"
|
|
line.long 0x8 "CTL2,Control Register 2"
|
|
hexmask.long.byte 0x8 24.--28. 1. "CTL2_ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode."
|
|
hexmask.long.byte 0x8 16.--20. 1. "CTL2_STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode."
|
|
hexmask.long.byte 0x8 11.--15. 1. "CTL2_SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger"
|
|
newline
|
|
bitfld.long 0x8 10. "CTL2_FIFOEN,Enable FIFO based operation" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "CTL2_DMAEN,Enable DMA trigger for data transfer." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 1.--2. "CTL2_RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: BIT_12,1: BIT_10,2: BIT_8,?"
|
|
newline
|
|
bitfld.long 0x8 0. "CTL2_DF,Data read-back format. Data is always stored in binary unsigned format." "0: UNSIGNED,1: SIGNED"
|
|
group.long 0x1110++0xB
|
|
line.long 0x0 "CLKFREQ,Sample Clock Frequency Range Register"
|
|
bitfld.long 0x0 0.--2. "CLKFREQ_FRANGE,Frequency Range." "0: RANGE1TO4,1: RANGE4TO8,2: RANGE8TO16,3: RANGE16TO20,4: RANGE20TO24,5: RANGE24TO32,6: RANGE32TO40,7: RANGE40TO48"
|
|
line.long 0x4 "SCOMP0,Sample Time Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "SCOMP0_VAL,Specifies the number of sample clocks."
|
|
line.long 0x8 "SCOMP1,Sample Time Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "SCOMP1_VAL,Specifies the number of sample clocks."
|
|
group.long 0x1148++0x3
|
|
line.long 0x0 "WCLOW,Window Comparator Low Threshold Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WCLOW_DATA,If DF = 0 unsigned binary format has to be used."
|
|
group.long 0x1150++0x3
|
|
line.long 0x0 "WCHIGH,Window Comparator High Threshold Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WCHIGH_DATA,If DF = 0 unsigned binary format has to be used."
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1180)++0x3
|
|
line.long 0x0 "MEMCTL[$1],Conversion Memory Control Register"
|
|
bitfld.long 0x0 28. "MEMCTL_WINCOMP,Enable window comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 24. "MEMCTL_TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: AUTO_NEXT,1: TRIGGER_NEXT"
|
|
bitfld.long 0x0 20. "MEMCTL_BCSEN,Enable burn out current source." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 16. "MEMCTL_AVGEN,Enable hardware averaging." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12. "MEMCTL_STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: SEL_SCOMP0,1: SEL_SCOMP1"
|
|
bitfld.long 0x0 8.--9. "MEMCTL_VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA,1: EXTREF,2: INTREF,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "MEMCTL_CHANSEL,Input channel select."
|
|
repeat.end
|
|
rgroup.long 0x1340++0x3
|
|
line.long 0x0 "STATUS,Status Register"
|
|
bitfld.long 0x0 1. "STATUS_REFBUFRDY,Indicates reference buffer is powered up and ready." "0: NOTREADY,1: READY"
|
|
rbitfld.long 0x0 0. "STATUS_BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: IDLE,1: ACTIVE"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "ADC0_SVT"
|
|
base ad:0x40556000
|
|
rgroup.long 0x160++0x3
|
|
line.long 0x0 "FIFODATA,FIFO Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "FIFODATA_DATA,Read from this data field returns the ADC sample from FIFO."
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x280)++0x3
|
|
line.long 0x0 "MEMRES[$1],Memory Result Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "MEMRES_DATA,MEMRES result register."
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "ADC1"
|
|
base ad:0x40002000
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "FSUB_0,Subscriber Configuration Register."
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher Configuration Register."
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,ADC clock configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,Unlock key"
|
|
bitfld.long 0x0 5. "CLKCFG_CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "CLKCFG_CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CLKCFG_SAMPCLK,ADC sample clock source selection." "0: SYSOSC,1: ULPCLK,2: HFCLK,?"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 19. "INT_EVENT0_MIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_MIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 19. "INT_EVENT0_ISET_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ISET_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_DMADONE,Raw interrupt flag for DMADONE." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 19. "INT_EVENT0_ICLR_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ICLR_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_DMADONE,Raw interrupt flag for DMADONE." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 8. "INT_EVENT1_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_IMASK_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 8. "INT_EVENT1_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_RIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 8. "INT_EVENT1_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_MIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ISET_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ICLR_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_IMASK_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_IMASK_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_IMASK_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_IMASK_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_IMASK_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_IMASK_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_IMASK_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_IMASK_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_IMASK_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_IMASK_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_RIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_RIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_RIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_RIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_RIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_RIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_RIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_RIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_RIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_RIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_MIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_MIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_MIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_MIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_MIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_MIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_MIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_MIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_MIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_MIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_ISET_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ISET_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ISET_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ISET_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_ISET_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_ISET_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_ISET_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_ISET_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_ISET_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_ISET_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_ICLR_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ICLR_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ICLR_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ICLR_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "INT_EVENT2_ICLR_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT2_ICLR_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_ICLR_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT2_ICLR_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_ICLR_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT2_ICLR_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT2_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CTL0,Control Register 0"
|
|
bitfld.long 0x0 24.--26. "CTL0_SCLKDIV,Sample clock divider" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_4,3: DIV_BY_8,4: DIV_BY_16,5: DIV_BY_24,6: DIV_BY_32,7: DIV_BY_48"
|
|
bitfld.long 0x0 16. "CTL0_PWRDN,Power down policy" "0: AUTO,1: MANUAL"
|
|
bitfld.long 0x0 0. "CTL0_ENC,Enable conversion" "0: OFF,1: ON"
|
|
line.long 0x4 "CTL1,Control Register 1"
|
|
bitfld.long 0x4 28.--30. "CTL1_AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: SHIFT0,1: SHIFT1,2: SHIFT2,3: SHIFT3,4: SHIFT4,5: SHIFT5,6: SHIFT6,7: SHIFT7"
|
|
bitfld.long 0x4 24.--26. "CTL1_AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: DISABLE,1: AVG_2,2: AVG_4,3: AVG_8,4: AVG_16,5: AVG_32,6: AVG_64,7: AVG_128"
|
|
bitfld.long 0x4 20. "CTL1_SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: AUTO,1: MANUAL"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CTL1_CONSEQ,Conversion sequence mode" "0: SINGLE,1: SEQUENCE,2: REPEATSINGLE,3: REPEATSEQUENCE"
|
|
bitfld.long 0x4 8. "CTL1_SC,Start of conversion" "0: STOP,1: START"
|
|
bitfld.long 0x4 0. "CTL1_TRIGSRC,Sample trigger source" "0: SOFTWARE,1: EVENT"
|
|
line.long 0x8 "CTL2,Control Register 2"
|
|
hexmask.long.byte 0x8 24.--28. 1. "CTL2_ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode."
|
|
hexmask.long.byte 0x8 16.--20. 1. "CTL2_STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode."
|
|
hexmask.long.byte 0x8 11.--15. 1. "CTL2_SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger"
|
|
newline
|
|
bitfld.long 0x8 10. "CTL2_FIFOEN,Enable FIFO based operation" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "CTL2_DMAEN,Enable DMA trigger for data transfer." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 1.--2. "CTL2_RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: BIT_12,1: BIT_10,2: BIT_8,?"
|
|
newline
|
|
bitfld.long 0x8 0. "CTL2_DF,Data read-back format. Data is always stored in binary unsigned format." "0: UNSIGNED,1: SIGNED"
|
|
group.long 0x1110++0xB
|
|
line.long 0x0 "CLKFREQ,Sample Clock Frequency Range Register"
|
|
bitfld.long 0x0 0.--2. "CLKFREQ_FRANGE,Frequency Range." "0: RANGE1TO4,1: RANGE4TO8,2: RANGE8TO16,3: RANGE16TO20,4: RANGE20TO24,5: RANGE24TO32,6: RANGE32TO40,7: RANGE40TO48"
|
|
line.long 0x4 "SCOMP0,Sample Time Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "SCOMP0_VAL,Specifies the number of sample clocks."
|
|
line.long 0x8 "SCOMP1,Sample Time Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "SCOMP1_VAL,Specifies the number of sample clocks."
|
|
group.long 0x1148++0x3
|
|
line.long 0x0 "WCLOW,Window Comparator Low Threshold Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WCLOW_DATA,If DF = 0 unsigned binary format has to be used."
|
|
group.long 0x1150++0x3
|
|
line.long 0x0 "WCHIGH,Window Comparator High Threshold Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WCHIGH_DATA,If DF = 0 unsigned binary format has to be used."
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1180)++0x3
|
|
line.long 0x0 "MEMCTL[$1],Conversion Memory Control Register"
|
|
bitfld.long 0x0 28. "MEMCTL_WINCOMP,Enable window comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 24. "MEMCTL_TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: AUTO_NEXT,1: TRIGGER_NEXT"
|
|
bitfld.long 0x0 20. "MEMCTL_BCSEN,Enable burn out current source." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 16. "MEMCTL_AVGEN,Enable hardware averaging." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12. "MEMCTL_STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: SEL_SCOMP0,1: SEL_SCOMP1"
|
|
bitfld.long 0x0 8.--9. "MEMCTL_VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA,1: EXTREF,2: INTREF,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "MEMCTL_CHANSEL,Input channel select."
|
|
repeat.end
|
|
rgroup.long 0x1340++0x3
|
|
line.long 0x0 "STATUS,Status Register"
|
|
bitfld.long 0x0 1. "STATUS_REFBUFRDY,Indicates reference buffer is powered up and ready." "0: NOTREADY,1: READY"
|
|
rbitfld.long 0x0 0. "STATUS_BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: IDLE,1: ACTIVE"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "ADC1_SVT"
|
|
base ad:0x40558000
|
|
rgroup.long 0x160++0x3
|
|
line.long 0x0 "FIFODATA,FIFO Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "FIFODATA_DATA,Read from this data field returns the ADC sample from FIFO."
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x280)++0x3
|
|
line.long 0x0 "MEMRES[$1],Memory Result Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "MEMRES_DATA,MEMRES result register."
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "ADC0"
|
|
base ad:0x40004000
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "FSUB_0,Subscriber Configuration Register."
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher Configuration Register."
|
|
bitfld.long 0x0 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,ADC clock configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,Unlock key"
|
|
bitfld.long 0x0 5. "CLKCFG_CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "CLKCFG_CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CLKCFG_SAMPCLK,ADC sample clock source selection." "0: SYSOSC,1: ULPCLK,2: HFCLK,?"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_DMADONE,Raw interrupt flag for DMADONE." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_DMADONE,Raw interrupt flag for DMADONE." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 8. "INT_EVENT1_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_IMASK_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 8. "INT_EVENT1_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_RIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 8. "INT_EVENT1_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_MIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ISET_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ICLR_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask extension"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT2_IMASK_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_IMASK_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT2_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status extension"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT2_RIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_RIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT2_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status extension"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT2_MIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_MIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT2_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set extension"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT2_ISET_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_ISET_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT2_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear extension"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT2_ICLR_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT2_ICLR_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT2_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CTL0,Control Register 0"
|
|
bitfld.long 0x0 24.--26. "CTL0_SCLKDIV,Sample clock divider" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_4,3: DIV_BY_8,4: DIV_BY_16,5: DIV_BY_24,6: DIV_BY_32,7: DIV_BY_48"
|
|
bitfld.long 0x0 16. "CTL0_PWRDN,Power down policy" "0: AUTO,1: MANUAL"
|
|
bitfld.long 0x0 0. "CTL0_ENC,Enable conversion" "0: OFF,1: ON"
|
|
line.long 0x4 "CTL1,Control Register 1"
|
|
bitfld.long 0x4 28.--30. "CTL1_AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated." "0: SHIFT0,1: SHIFT1,2: SHIFT2,3: SHIFT3,4: SHIFT4,5: SHIFT5,6: SHIFT6,7: SHIFT7"
|
|
bitfld.long 0x4 24.--26. "CTL1_AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: DISABLE,1: AVG_2,2: AVG_4,3: AVG_8,4: AVG_16,5: AVG_32,6: AVG_64,7: AVG_128"
|
|
bitfld.long 0x4 20. "CTL1_SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: AUTO,1: MANUAL"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CTL1_CONSEQ,Conversion sequence mode" "0: SINGLE,1: SEQUENCE,2: REPEATSINGLE,3: REPEATSEQUENCE"
|
|
bitfld.long 0x4 8. "CTL1_SC,Start of conversion" "0: STOP,1: START"
|
|
bitfld.long 0x4 0. "CTL1_TRIGSRC,Sample trigger source" "0: SOFTWARE,1: EVENT"
|
|
line.long 0x8 "CTL2,Control Register 2"
|
|
hexmask.long.byte 0x8 24.--28. 1. "CTL2_ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode."
|
|
hexmask.long.byte 0x8 16.--20. 1. "CTL2_STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode."
|
|
hexmask.long.byte 0x8 11.--15. 1. "CTL2_SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger"
|
|
newline
|
|
bitfld.long 0x8 10. "CTL2_FIFOEN,Enable FIFO based operation" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "CTL2_DMAEN,Enable DMA trigger for data transfer." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 1.--2. "CTL2_RES,Resolution. These bits define the resolutoin of ADC conversion result." "0: BIT_12,1: BIT_10,2: BIT_8,?"
|
|
newline
|
|
bitfld.long 0x8 0. "CTL2_DF,Data read-back format. Data is always stored in binary unsigned format." "0: UNSIGNED,1: SIGNED"
|
|
group.long 0x1110++0xB
|
|
line.long 0x0 "CLKFREQ,Sample Clock Frequency Range Register"
|
|
bitfld.long 0x0 0.--2. "CLKFREQ_FRANGE,Frequency Range." "0: RANGE1TO4,1: RANGE4TO8,2: RANGE8TO16,3: RANGE16TO20,4: RANGE20TO24,5: RANGE24TO32,6: RANGE32TO40,7: RANGE40TO48"
|
|
line.long 0x4 "SCOMP0,Sample Time Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "SCOMP0_VAL,Specifies the number of sample clocks."
|
|
line.long 0x8 "SCOMP1,Sample Time Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "SCOMP1_VAL,Specifies the number of sample clocks."
|
|
group.long 0x1148++0x3
|
|
line.long 0x0 "WCLOW,Window Comparator Low Threshold Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WCLOW_DATA,If DF = 0 unsigned binary format has to be used."
|
|
group.long 0x1150++0x3
|
|
line.long 0x0 "WCHIGH,Window Comparator High Threshold Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WCHIGH_DATA,If DF = 0 unsigned binary format has to be used."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1180)++0x3
|
|
line.long 0x0 "MEMCTL[$1],Conversion Memory Control Register"
|
|
bitfld.long 0x0 28. "MEMCTL_WINCOMP,Enable window comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 24. "MEMCTL_TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: AUTO_NEXT,1: TRIGGER_NEXT"
|
|
bitfld.long 0x0 20. "MEMCTL_BCSEN,Enable burn out current source." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 16. "MEMCTL_AVGEN,Enable hardware averaging." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12. "MEMCTL_STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: SEL_SCOMP0,1: SEL_SCOMP1"
|
|
bitfld.long 0x0 8.--9. "MEMCTL_VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA,1: EXTREF,2: INTREF,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "MEMCTL_CHANSEL,Input channel select."
|
|
repeat.end
|
|
rgroup.long 0x1340++0x3
|
|
line.long 0x0 "STATUS,Status Register"
|
|
bitfld.long 0x0 1. "STATUS_REFBUFRDY,Indicates reference buffer is powered up and ready." "0: NOTREADY,1: READY"
|
|
rbitfld.long 0x0 0. "STATUS_BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: IDLE,1: ACTIVE"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "ADC0"
|
|
base ad:0x40004000
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "FSUB_0,Subscriber Configuration Register."
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher Configuration Register."
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,ADC clock configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,Unlock key"
|
|
bitfld.long 0x0 5. "CLKCFG_CCONSTOP,CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "CLKCFG_CCONRUN,CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CLKCFG_SAMPCLK,ADC sample clock source selection." "0: ULPCLK,1: SYSOSC,2: HFCLK,?"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_TOVIFG,Raw interrupt flag for sequence conversion trigger overflow." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 19. "INT_EVENT0_MIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_MIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_DMADONE,Raw interrupt flag for DMADONE." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 19. "INT_EVENT0_ISET_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ISET_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_DMADONE,Raw interrupt flag for DMADONE." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 19. "INT_EVENT0_ICLR_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ICLR_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_UVIFG,Raw interrupt flag for MEMRESx underflow." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_DMADONE,Raw interrupt flag for DMADONE." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_TOVIFG,Raw interrupt flag for sequence conversion timeout overflow." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_OVIFG,Raw interrupt flag for MEMRESx overflow." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 8. "INT_EVENT1_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_IMASK_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 8. "INT_EVENT1_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_RIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 8. "INT_EVENT1_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_MIS_INIFG,Mask INIFG in MIS_EX register." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ISET_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ICLR_INIFG,Mask INIFG in MIS_EX register." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_LOWIFG,Raw interrupt flag for the MEMRESx result register being below" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_HIGHIFG,Raw interrupt flag for the MEMRESx result register being higher" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.word 0x0 0.--9. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_IMASK_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_IMASK_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_IMASK_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_IMASK_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_IMASK_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_IMASK_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_IMASK_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_IMASK_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_IMASK_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_IMASK_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_IMASK_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_RIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_RIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_RIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_RIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_RIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_RIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_RIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_RIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_RIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_RIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_RIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_MIS_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_MIS_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_MIS_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_MIS_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_MIS_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_MIS_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_MIS_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_MIS_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_MIS_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_MIS_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_MIS_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_ISET_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ISET_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ISET_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ISET_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT2_ISET_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT2_ISET_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_ISET_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT2_ISET_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_ISET_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT2_ISET_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT2_ISET_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear extension"
|
|
bitfld.long 0x0 19. "INT_EVENT2_ICLR_MEMRESIFG11,Raw interrupt status for MEMRES11." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ICLR_MEMRESIFG10,Raw interrupt status for MEMRES10." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ICLR_MEMRESIFG9,Raw interrupt status for MEMRES9." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ICLR_MEMRESIFG8,Raw interrupt status for MEMRES8." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "INT_EVENT2_ICLR_MEMRESIFG7,Raw interrupt status for MEMRES7." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT2_ICLR_MEMRESIFG6,Raw interrupt status for MEMRES6." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT2_ICLR_MEMRESIFG5,Raw interrupt status for MEMRES5." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT2_ICLR_MEMRESIFG4,Raw interrupt status for MEMRES4." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_MEMRESIFG3,Raw interrupt status for MEMRES3." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT2_ICLR_MEMRESIFG2,Raw interrupt status for MEMRES2." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT2_ICLR_MEMRESIFG1,Raw interrupt status for MEMRES1." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT2_ICLR_MEMRESIFG0,Raw interrupt status for MEMRES0." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CTL0,Control Register 0"
|
|
bitfld.long 0x0 24.--26. "CTL0_SCLKDIV,Sample clock divider" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_4,3: DIV_BY_8,4: DIV_BY_16,5: DIV_BY_24,6: DIV_BY_32,7: DIV_BY_48"
|
|
bitfld.long 0x0 16. "CTL0_PWRDN,Power down policy" "0: AUTO,1: MANUAL"
|
|
bitfld.long 0x0 0. "CTL0_ENC,Enable conversion" "0: OFF,1: ON"
|
|
line.long 0x4 "CTL1,Control Register 1"
|
|
bitfld.long 0x4 28.--30. "CTL1_AVGD,Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropriately result will be truncated." "0: SHIFT0,1: SHIFT1,2: SHIFT2,3: SHIFT3,4: SHIFT4,5: SHIFT5,6: SHIFT6,7: SHIFT7"
|
|
bitfld.long 0x4 24.--26. "CTL1_AVGN,Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx." "0: DISABLE,1: AVG_2,2: AVG_4,3: AVG_8,4: AVG_16,5: AVG_32,6: AVG_64,7: AVG_128"
|
|
bitfld.long 0x4 20. "CTL1_SAMPMODE,Sample mode. This bit selects the source of the sampling signal." "0: AUTO,1: MANUAL"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CTL1_CONSEQ,Conversion sequence mode" "0: SINGLE,1: SEQUENCE,2: REPEATSINGLE,3: REPEATSEQUENCE"
|
|
bitfld.long 0x4 8. "CTL1_SC,Start of conversion" "0: STOP,1: START"
|
|
bitfld.long 0x4 0. "CTL1_TRIGSRC,Sample trigger source" "0: SOFTWARE,1: EVENT"
|
|
line.long 0x8 "CTL2,Control Register 2"
|
|
hexmask.long.byte 0x8 24.--28. 1. "CTL2_ENDADD,Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode."
|
|
hexmask.long.byte 0x8 16.--20. 1. "CTL2_STARTADD,Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode."
|
|
hexmask.long.byte 0x8 11.--15. 1. "CTL2_SAMPCNT,Number of ADC converted samples to be transferred on a DMA trigger"
|
|
newline
|
|
bitfld.long 0x8 10. "CTL2_FIFOEN,Enable FIFO based operation" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "CTL2_DMAEN,Enable DMA trigger for data transfer." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 1.--2. "CTL2_RES,Resolution. These bits define the resolution of ADC conversion result." "0: BIT_12,1: BIT_10,2: BIT_8,?"
|
|
newline
|
|
bitfld.long 0x8 0. "CTL2_DF,Data read-back format. Data is always stored in binary unsigned format." "0: UNSIGNED,1: SIGNED"
|
|
group.long 0x1110++0xB
|
|
line.long 0x0 "CLKFREQ,Sample Clock Frequency Range Register"
|
|
bitfld.long 0x0 0.--2. "CLKFREQ_FRANGE,Frequency Range." "0: RANGE1TO4,1: RANGE4TO8,2: RANGE8TO16,3: RANGE16TO20,4: RANGE20TO24,5: RANGE24TO32,6: RANGE32TO40,7: RANGE40TO48"
|
|
line.long 0x4 "SCOMP0,Sample Time Compare 0 Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "SCOMP0_VAL,Specifies the number of sample clocks."
|
|
line.long 0x8 "SCOMP1,Sample Time Compare 1 Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "SCOMP1_VAL,Specifies the number of sample clocks."
|
|
group.long 0x1148++0x3
|
|
line.long 0x0 "WCLOW,Window Comparator Low Threshold Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WCLOW_DATA,If DF = 0 unsigned binary format has to be used."
|
|
group.long 0x1150++0x3
|
|
line.long 0x0 "WCHIGH,Window Comparator High Threshold Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "WCHIGH_DATA,If DF = 0 unsigned binary format has to be used."
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1180)++0x3
|
|
line.long 0x0 "MEMCTL[$1],Conversion Memory Control Register"
|
|
bitfld.long 0x0 28. "MEMCTL_WINCOMP,Enable window comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 24. "MEMCTL_TRIG,Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions." "0: AUTO_NEXT,1: TRIGGER_NEXT"
|
|
bitfld.long 0x0 20. "MEMCTL_BCSEN,Enable burn out current source." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 16. "MEMCTL_AVGEN,Enable hardware averaging." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12. "MEMCTL_STIME,Selects the source of sample timer period between SCOMP0 and SCOMP1." "0: SEL_SCOMP0,1: SEL_SCOMP1"
|
|
bitfld.long 0x0 8.--9. "MEMCTL_VRSEL,Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected." "0: VDDA,1: EXTREF,2: INTREF,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "MEMCTL_CHANSEL,Input channel select."
|
|
repeat.end
|
|
rgroup.long 0x1340++0x3
|
|
line.long 0x0 "STATUS,Status Register"
|
|
bitfld.long 0x0 1. "STATUS_REFBUFRDY,Indicates reference buffer is powered up and ready." "0: NOTREADY,1: READY"
|
|
rbitfld.long 0x0 0. "STATUS_BUSY,Busy. This bit indicates that an active ADC sample or conversion operation is in progress." "0: IDLE,1: ACTIVE"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "AES (Advanced Encryption Standard Accelerator)"
|
|
base ad:0x40442000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_DMA2,DMA2 event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_DMA1,DMA1 event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_DMA0,DMA0 event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_AESRDY,AES ready interrupt set when the selected AES operation was completed and the result can be read from AESADOUT." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_DMA2,DMA2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_DMA1,DMA1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_DMA0,DMA0 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_AESRDY,AES ready interrupt set when the selected AES operation was completed and the result can be read from AESADOUT." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_DMA2,DMA2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_DMA1,DMA1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_DMA0,DMA0 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_AESRDY,AES ready interrupt set when the selected AES operation was completed and the result can be read from AESADOUT." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_DMA2,DMA2" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_DMA1,DMA1" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_DMA0,DMA0" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_AESRDY,AES ready interrupt set when the selected AES operation was completed and the result can be read from AESADOUT." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_DMA2,DMA2" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_DMA1,DMA1" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_DMA0,DMA0" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_AESRDY,AES ready interrupt set when the selected AES operation was completed and the result can be read from AESADOUT." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 1. "INT_EVENT1_IMASK_DMA0,DMA0 event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 1. "INT_EVENT1_RIS_DMA0,DMA0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 1. "INT_EVENT1_MIS_DMA0,DMA0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 1. "INT_EVENT1_ISET_DMA0,DMA0" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 1. "INT_EVENT1_ICLR_DMA0,DMA0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 2. "INT_EVENT2_IMASK_DMA1,DMA1 event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 2. "INT_EVENT2_RIS_DMA1,DMA1 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 2. "INT_EVENT2_MIS_DMA1,DMA1 event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 2. "INT_EVENT2_ISET_DMA1,DMA1 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 2. "INT_EVENT2_ICLR_DMA1,DMA1 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10B0++0x3
|
|
line.long 0x0 "INT_EVENT3_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT3_IIDX_STAT,Interrupt index status"
|
|
group.long 0x10B8++0x3
|
|
line.long 0x0 "INT_EVENT3_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT3_IMASK_DMA2,DMA2 event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x10C0++0x3
|
|
line.long 0x0 "INT_EVENT3_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT3_RIS_DMA2,DMA2 event" "0: CLR,1: SET"
|
|
rgroup.long 0x10C8++0x3
|
|
line.long 0x0 "INT_EVENT3_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT3_MIS_DMA2,DMA2 event" "0: CLR,1: SET"
|
|
wgroup.long 0x10D0++0x3
|
|
line.long 0x0 "INT_EVENT3_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT3_ISET_DMA2,DMA2 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10D8++0x3
|
|
line.long 0x0 "INT_EVENT3_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT3_ICLR_DMA2,DMA2 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 6.--7. "EVT_MODE_EVT3_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "AESACTL0,AES accelerator control register 0"
|
|
bitfld.long 0x0 15. "AESACTL0_CMEN,AESCMEN enables the support of the cipher modes ECB CBC OFB and CFB together with the DMA. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0." "0: No DMA triggers are generated,1: DMA cipher mode support operation is enabled and.."
|
|
bitfld.long 0x0 11. "AESACTL0_ERRFG,AES error flag." "0: NOERR,1: ERR"
|
|
newline
|
|
bitfld.long 0x0 7. "AESACTL0_SWRST,AES software reset." "0: NORST,1: RST"
|
|
bitfld.long 0x0 5.--6. "AESACTL0_CMX,AES cipher mode select. These bits are ignored for AESCMEN = 0. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0." "0: ECB,1: CBC,2: OFB,3: CFB"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "AESACTL0_KLX,AES key length." "0: AES128,?,2: AES256,?"
|
|
bitfld.long 0x0 0.--1. "AESACTL0_OPX,AES operation." "0: OP0,1: OP1,2: OP2,3: OP3"
|
|
line.long 0x4 "AESACTL1,AES accelerator control register 1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "AESACTL1_BLKCNTX,Cipher Block Counter. Number of blocks to be encrypted or decrypted with block cipher modes enabled (AESCMEN = 1). Ignored if AESCMEN = 0. The block counter decrements with each performed encryption or decryption. Writes are ignored when.."
|
|
line.long 0x8 "AESASTAT,aes accelerator status register"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AESASTAT_DOUTCNTX,Bytes read from AESADOUT. Reset when AESDOUTRD is reset. If AESDOUTCNTx = 0 and AESDOUTRD = 0 no bytes were read. If AESDOUTCNTx = 0 and AESDOUTRD = 1 all bytes were read."
|
|
hexmask.long.byte 0x8 8.--11. 1. "AESASTAT_DINCNTX,Bytes written to AESADIN AESAXDIN or AESAXIN. Reset when AESDINWR is reset. If AESDINCNTx = 0 and AESDINWR = 0 no bytes were written. If AESDINCNTx = 0 and AESDINWR = 1 all bytes were written."
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "AESASTAT_KEYCNTX,Bytes written to AESAKEY when AESKLx = 00 half-words written to AESAKEY if AESKLx = b10. Reset when AESKEYWR is reset. If AESKEYCNTx = 0 and AESKEYWR = 0 no bytes were written. If AESKEYCNTx = 0 and AESKEYWR = 1 all bytes were written."
|
|
rbitfld.long 0x8 3. "AESASTAT_DOUTRD,All 16 bytes read from AESADOUT. AESDOUTRD is reset by PUC AESSWRST an error condition changing AESOPx changing AESKLx when the AES accelerator is busy and when the output data is read again." "0: Not all bytes read,1: All bytes read"
|
|
newline
|
|
bitfld.long 0x8 2. "AESASTAT_DINWR,All 16 bytes written to AESADIN AESAXDIN or AESAXIN. Changing its state by software also resets the AESDINCNTx bits. AESDINWR is reset by PUC AESSWRST an error condition changing AESOPx changing AESKLx the start to (over)write the.." "0: Not all bytes written,1: All bytes written"
|
|
bitfld.long 0x8 1. "AESASTAT_KEYWR,All bytes written to AESAKEY. This bit can be modified by software but it must not be reset by software (10) if AESCMEN=1. Changing its state by software also resets the AESKEYCNTx bits. AESKEYWR is reset by PUC AESSWRST an error.." "0: NALL,1: ALL"
|
|
newline
|
|
rbitfld.long 0x8 0. "AESASTAT_BUSY,AES accelerator module busy; encryption decryption or key generation in progress." "0: Not busy,1: Busy"
|
|
wgroup.long 0x110C++0x7
|
|
line.long 0x0 "AESAKEY,aes accelerator key register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "AESAKEY_KEY3X,AES key byte n+3 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1."
|
|
hexmask.long.byte 0x0 16.--23. 1. "AESAKEY_KEY2X,AES key byte n+2 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "AESAKEY_KEY1X,AES key byte n+1 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1."
|
|
hexmask.long.byte 0x0 0.--7. 1. "AESAKEY_KEY0X,AES key byte n when AESAKEY is written as word. AES next key byte when AESAKEY is written as byte. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1."
|
|
line.long 0x4 "AESADIN,aes accelerator data in register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "AESADIN_DIN3X,AES data in byte n+3 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero."
|
|
hexmask.long.byte 0x4 16.--23. 1. "AESADIN_DIN2X,AES data in byte n+2 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "AESADIN_DIN1X,AES data in byte n+1 when AESADIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero."
|
|
hexmask.long.byte 0x4 0.--7. 1. "AESADIN_DIN0X,AES data in byte n when AESADIN is written as word. AES next data in byte when AESADIN is written as byte. Do not mix word and byte access. Always reads as zero."
|
|
rgroup.long 0x1114++0x3
|
|
line.long 0x0 "AESADOUT,aes accelerator data out register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "AESADOUT_DOUT3X,AES data out byte n+3 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access."
|
|
hexmask.long.byte 0x0 16.--23. 1. "AESADOUT_DOUT2X,AES data out byte n+2 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "AESADOUT_DOUT1X,AES data out byte n+1 when AESADOUT is read as word. Do not use these bits for byte access. Do not mix word and byte access."
|
|
hexmask.long.byte 0x0 0.--7. 1. "AESADOUT_DOUT0X,AES data out byte n when AESADOUT is read as word. AES next data out byte when AESADOUT is read as byte. Do not mix word and byte access."
|
|
wgroup.long 0x1118++0x7
|
|
line.long 0x0 "AESAXDIN,aes accelerator xored data in register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "AESAXDIN_XDIN3X,AES data in byte n+3 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero."
|
|
hexmask.long.byte 0x0 16.--23. 1. "AESAXDIN_XDIN2X,AES data in byte n+2 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "AESAXDIN_XDIN1X,AES data in byte n+1 when AESAXDIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero."
|
|
hexmask.long.byte 0x0 0.--7. 1. "AESAXDIN_XDIN0X,AES data in byte n when AESAXDIN is written as word. AES next data in byte when AESAXDIN is written as byte. Do not mix word and byte access. Always reads as zero."
|
|
line.long 0x4 "AESAXIN,aes accelerator xored data in register (no trigger)"
|
|
hexmask.long.byte 0x4 24.--31. 1. "AESAXIN_XIN3X,AES data in byte n+3 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero."
|
|
hexmask.long.byte 0x4 16.--23. 1. "AESAXIN_XIN2X,AES data in byte n+2 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "AESAXIN_XIN1X,AES data in byte n+1 when AESAXIN is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero."
|
|
hexmask.long.byte 0x4 0.--7. 1. "AESAXIN_XIN0X,AES data in byte n when AESAXIN is written as word. AES next data in byte when AESAXIN is written as byte. Do not mix word and byte access. Always reads as zero."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "AESADV"
|
|
base ad:0x40442000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "?,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_CNTXTRDY,This bit indicates that the context data registers can be overwritten and the CPU is permitted to write next context." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_SAVEDCNTXTRDY,This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the.." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_INPUTRDY,This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_OUTPUTRDY,This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_CNTXTRDY,This bit indicates that the context data registers can be overwritten and the CPU is permitted to write next context." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_SAVEDCNTXTRDY,This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the.." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_INPUTRDY,This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_OUTPUTRDY,This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_CNTXTRDY,This bit indicates that the context data registers can be overwritten and the CPU is permitted to write next context." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_SAVEDCNTXTRDY,This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the.." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_INPUTRDY,This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_OUTPUTRDY,This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_CNTXTRDY,This bit indicates that the context data registers can be overwritten and the CPU is permitted to write next context." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_SAVEDCNTXTRDY,This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the.." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_INPUTRDY,This indicates that the engine can take new input.This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_OUTPUTRDY,This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_CNTXTRDY,This bit indicates that the context data registers can be overwritten and the CPU is permitted to write next context." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_SAVEDCNTXTRDY,This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive with the.." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_INPUTRDY,This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_OUTPUTRDY,This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_TRIG0,TRIG0 event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_TRIG0,TRIG0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_TRIG0,TRIG0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_TRIG0,TRIG0" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_TRIG0,TRIG0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 0. "INT_EVENT2_IMASK_TRIG1,TRIG1 event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_EVENT2_RIS_TRIG1,TRIG1 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_EVENT2_MIS_TRIG1,TRIG1 event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_EVENT2_ISET_TRIG1,TRIG1 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_EVENT2_ICLR_TRIG1,TRIG1 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x1100++0x4F
|
|
line.long 0x0 "GCMCCM_TAG0,CBC-MAC third key (LSW) / GCM & CCM Intermediate TAG (LSW)"
|
|
hexmask.long 0x0 0.--31. 1. "GCMCCM_TAG0_DATA,Key data"
|
|
line.long 0x4 "GCMCCM_TAG1,CBC-MAC third key / GCM & CCM Intermediate TAG"
|
|
hexmask.long 0x4 0.--31. 1. "GCMCCM_TAG1_DATA,Key data"
|
|
line.long 0x8 "GCMCCM_TAG2,CBC-MAC third key / GCM & CCM Intermediate TAG"
|
|
hexmask.long 0x8 0.--31. 1. "GCMCCM_TAG2_DATA,Key data"
|
|
line.long 0xC "GCMCCM_TAG3,CBC-MAC third key (MSW) / GCM & CCM Intermediate TAG (MSW)"
|
|
hexmask.long 0xC 0.--31. 1. "GCMCCM_TAG3_DATA,Key data"
|
|
line.long 0x10 "GHASH_H0,CCM & CBC-MAC second key (LSW) / GCM Hash Key input (LSW)"
|
|
hexmask.long 0x10 0.--31. 1. "GHASH_H0_DATA,Key data"
|
|
line.long 0x14 "GHASH_H1,CCM & CBC-MAC second key / GCM Hash Key input"
|
|
hexmask.long 0x14 0.--31. 1. "GHASH_H1_DATA,Key data"
|
|
line.long 0x18 "GHASH_H2,CCM & CBC-MAC second key / GCM Hash Key input"
|
|
hexmask.long 0x18 0.--31. 1. "GHASH_H2_DATA,Key data"
|
|
line.long 0x1C "GHASH_H3,CCM & CBC-MAC second key (MSW) / GCM Hash Key input (MSW)"
|
|
hexmask.long 0x1C 0.--31. 1. "GHASH_H3_DATA,Key data"
|
|
line.long 0x20 "KEY0,KEY (LSW)"
|
|
hexmask.long 0x20 0.--31. 1. "KEY0_DATA,Key data"
|
|
line.long 0x24 "KEY1,KEY"
|
|
hexmask.long 0x24 0.--31. 1. "KEY1_DATA,Key data"
|
|
line.long 0x28 "KEY2,KEY"
|
|
hexmask.long 0x28 0.--31. 1. "KEY2_DATA,Key data"
|
|
line.long 0x2C "KEY3,KEY"
|
|
hexmask.long 0x2C 0.--31. 1. "KEY3_DATA,Key data"
|
|
line.long 0x30 "KEY4,KEY"
|
|
hexmask.long 0x30 0.--31. 1. "KEY4_DATA,Key data"
|
|
line.long 0x34 "KEY5,KEY"
|
|
hexmask.long 0x34 0.--31. 1. "KEY5_DATA,Key data"
|
|
line.long 0x38 "KEY6,KEY"
|
|
hexmask.long 0x38 0.--31. 1. "KEY6_DATA,Key data"
|
|
line.long 0x3C "KEY7,KEY (MSW)"
|
|
hexmask.long 0x3C 0.--31. 1. "KEY7_DATA,Key data"
|
|
line.long 0x40 "IV0,IV (LSW)"
|
|
hexmask.long 0x40 0.--31. 1. "IV0_DATA,Key data"
|
|
line.long 0x44 "IV1,IV"
|
|
hexmask.long 0x44 0.--31. 1. "IV1_DATA,Key data"
|
|
line.long 0x48 "IV2,IV"
|
|
hexmask.long 0x48 0.--31. 1. "IV2_DATA,Key data"
|
|
line.long 0x4C "IV3,IV"
|
|
hexmask.long 0x4C 0.--31. 1. "IV3_DATA,Key data"
|
|
group.long 0x1150++0x3
|
|
line.long 0x0 "CTRL,Input/Output Buffer Control and Mode selection"
|
|
rbitfld.long 0x0 31. "CTRL_CNTXT_RDY,If 1b this read-only status bit indicates that the context data registers can be overwritten and the CPU is permitted to write the next context." "0: NOTREADY,1: READY"
|
|
rbitfld.long 0x0 30. "CTRL_SAVED_CNTXT_RDY,If 1b this read-only status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the Host to retrieve. This bit is only asserted if the save_context bit is set to 1b. The bit is mutually exclusive.." "0: NOTREADY,1: READY"
|
|
newline
|
|
bitfld.long 0x0 29. "CTRL_SAVE_CNTXT,This bit is used to indicate that an authentication TAG or result IV needs to be stored as a result context. If this bit is set context output DMA and/or interrupt will be asserted if the operation is finished and related signals are.." "0: NO_EFFECT,1: ENABLE"
|
|
bitfld.long 0x0 28. "CTRL_GCM_CONT,Continue processing of an interrupted AES-GCM or AES-CCM operation in the crypto/payload phase." "0: NO_EFFECT,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 27. "CTRL_GET_DIGEST,Interrupt processing and generate an intermediate digest during an AES-GCM or AES-CCM operation." "0: NO_EFFECT,1: ENABLE"
|
|
bitfld.long 0x0 26. "CTRL_OFB_GCM_CCM_CONT,This bit has a dual use depending on the selection of CCM/GCM see bits [18:16]." "?,1: GCM_CCM_CONTINUE"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CTRL_CCMM,Defines M that indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one). Note: The EIP-39 always returns a 128-bit authentication field of which the M.." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 19.--21. "CTRL_CCML,Defines L that indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one. All values are supported." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 18. "CTRL_CCM,If set to 1b AES-CCM is selected this is a combined mode using AES for both authentication and encryption. In addition to the CCM bit the CTR mode bit must be set such that AES-CTR is enabled. Other combinations with CCM are invalid." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 16.--17. "CTRL_GCM,If not set to 00b AES-GCM mode is selected this is a combined mode using the Galois field multiplier GF(2128) for authentication and AES-CTR mode for encryption the bits specify the GCM mode: 01b = GHASH with H loaded and Y0-encrypted forced.." "?,1: FORCE_ZERO,2: LOAD_HASH_KEY,3: AUTONOMOUS"
|
|
newline
|
|
bitfld.long 0x0 15. "CTRL_CBCMAC,If set to 1b AES-CBC MAC is selected the Direction bit must be set to 1 for this mode." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 10. "CTRL_CFB,If set to 1b AES cipher feedback mode CFB is selected. Use the ctr_width field to specify the feedback width." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 9. "CTRL_ICM,When the CFB bit is set specifies the CFB mode feedback width:" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 7.--8. "CTRL_CTR_WIDTH,When the CTR bit is set specifies the counter width for AES-CTR mode." "0: CFB128,1: CTR64,2: CTR96,3: CTR128"
|
|
newline
|
|
bitfld.long 0x0 6. "CTRL_CTR,If set to 1b AES counter mode (CTR) is selected. Note: This bit must also be set for GCM and CCM when encryption/decryption is required." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "CTRL_CBC,If set to 1b cipher-block-chaining (CBC) mode is selected." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "CTRL_KEYSIZE,Specifies the encryption strength / key width" "?,1: K128,?,3: K256"
|
|
bitfld.long 0x0 2. "CTRL_DIR,Direction. If set to 1b an encrypt operation is performed. If set to 0b a decrypt operation is performed. Note: This bit must be written with a 1b when CBC-MAC is selected." "0: DECRYPT,1: ENCRYPT"
|
|
newline
|
|
rbitfld.long 0x0 1. "CTRL_INPUT_RDY,Ready for input. If 1b this read-only status bit indicates that the 16-byte input buffer is empty and the CPU is permitted to write the next block of data. After reset this bit is 0. After writing a context this bit will become 1b." "0: NOTEMPTY,1: EMPTY"
|
|
rbitfld.long 0x0 0. "CTRL_OUTPUT_RDY,Output Ready. If 1b this read-only status bit indicates that an AES output block is available for the CPU to retrieve." "0: NOTREADY,1: READY"
|
|
wgroup.long 0x1154++0xB
|
|
line.long 0x0 "C_LENGTH_0,Crypto data length (LSW)"
|
|
hexmask.long 0x0 0.--31. 1. "C_LENGTH_0_DATA,Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started this length decrements to zero. Data lengths up to (261-1) bytes are.."
|
|
line.long 0x4 "C_LENGTH_1,Crypto data length (MSW)"
|
|
hexmask.long 0x4 0.--28. 1. "C_LENGTH_1_DATA,Bits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started this length decrements to zero. Data lengths up to (261-1) bytes are.."
|
|
line.long 0x8 "AAD_LENGTH,AAD Data Length"
|
|
hexmask.long 0x8 0.--31. 1. "AAD_LENGTH_DATA,Bits [31:0] of the authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM)"
|
|
group.long 0x1160++0xF
|
|
line.long 0x0 "DATA0,Data input (LSW) / Data output (LSW)"
|
|
hexmask.long 0x0 0.--31. 1. "DATA0_DATA,Data"
|
|
line.long 0x4 "DATA1,Data input / Data output"
|
|
hexmask.long 0x4 0.--31. 1. "DATA1_DATA,Data"
|
|
line.long 0x8 "DATA2,Data input / Data output"
|
|
hexmask.long 0x8 0.--31. 1. "DATA2_DATA,Data"
|
|
line.long 0xC "DATA3,Data input (LSW) / Data output (MSW)"
|
|
hexmask.long 0xC 0.--31. 1. "DATA3_DATA,Data"
|
|
rgroup.long 0x1170++0x13
|
|
line.long 0x0 "TAG0,Hash result (LSW)"
|
|
hexmask.long 0x0 0.--31. 1. "TAG0_DATA,For a CPU read operation these registers contain the last 128-bit TAG output of the EIP-39; the TAG is available until the next context is written."
|
|
line.long 0x4 "TAG1,Hash result"
|
|
hexmask.long 0x4 0.--31. 1. "TAG1_DATA,For a CPU read operation these registers contain the last 128-bit TAG output of the EIP-39; the TAG is available until the next context is written."
|
|
line.long 0x8 "TAG2,Hash result"
|
|
hexmask.long 0x8 0.--31. 1. "TAG2_DATA,For a CPU read operation these registers contain the last 128-bit TAG output of the EIP-39; the TAG is available until the next context is written."
|
|
line.long 0xC "TAG3,Hash result (MSW)"
|
|
hexmask.long 0xC 0.--31. 1. "TAG3_DATA,For a CPU read operation these registers contain the last 128-bit TAG output of the EIP-39; the TAG is available until the next context is written."
|
|
line.long 0x10 "STATUS,Status"
|
|
bitfld.long 0x10 0. "STATUS_KEYWR,Key write status. 0 - user write to KEY register is allowed. 1 - user write to KEY register is ignored." "0: ENABLED,1: DISABLED"
|
|
wgroup.long 0x1184++0x3
|
|
line.long 0x0 "DATA_IN,Data in alias register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA_IN_DATA,Data input word"
|
|
rgroup.long 0x1188++0x3
|
|
line.long 0x0 "DATA_OUT,Data out alias register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA_OUT_DATA,Data output word"
|
|
wgroup.long 0x11D0++0x7
|
|
line.long 0x0 "FORCE_IN_AV,Data control register for input data"
|
|
hexmask.long 0x0 0.--31. 1. "FORCE_IN_AV_DATA,Any write to this register forces the input data buffer to valid and will force the engine to start processing this data. The data written here is not used. The core must be configured to have input and output data acknowledge be I/O.."
|
|
line.long 0x4 "CCM_ALN_WRD,AES-CCM AAD alignment data word"
|
|
hexmask.long 0x4 0.--31. 1. "CCM_ALN_WRD_DATA,This register provides a means to access an internal EIP-39 register that stores alignment data bytes during the AAD phase of AES-CCM processing. This register needs to be read and stored when an AES-CCM operation is interrupted during.."
|
|
group.long 0x11D8++0x7
|
|
line.long 0x0 "BLK_CNT0,Internal block counter (LSW)"
|
|
hexmask.long 0x0 0.--31. 1. "BLK_CNT0_DATA,Internal block counter for AES GCM and CCM operations."
|
|
line.long 0x4 "BLK_CNT1,Internal block counter (MSW)"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "BLK_CNT1_DATA,Internal block counter for AES GCM and CCM operations."
|
|
group.long 0x11F4++0x3
|
|
line.long 0x0 "DMA_HS,Control register for DMA handshaking"
|
|
bitfld.long 0x0 0. "DMA_HS_DMA_DATA_ACK,When this bit is 0b input and output data acknowledge is I/O register based as specified in the description of the AES_DATA_IN_n / AES_DATA_OUT_n registers." "0: DMA_DISABLE,1: DMA_ENABLE"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "CANFD (FD Controler Area Network)"
|
|
base ad:0x40508000
|
|
group.long 0x6800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
newline
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x6804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
newline
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x6814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x7000++0x7
|
|
line.long 0x0 "MCAN_CREL,MCAN Core Release Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "MCAN_CREL_REL,Core Release. One digit BCD-coded."
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "MCAN_CREL_STEP,Step of Core Release. One digit BCD-coded."
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "MCAN_CREL_SUBSTEP,Sub-Step of Core Release. One digit BCD-coded."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "MCAN_CREL_YEAR,Time Stamp Year. One digit BCD-coded."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MCAN_CREL_MON,Time Stamp Month. Two digits BCD-coded."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MCAN_CREL_DAY,Time Stamp Day. Two digits BCD-coded."
|
|
line.long 0x4 "MCAN_ENDN,MCAN Endian Register"
|
|
hexmask.long 0x4 0.--31. 1. "MCAN_ENDN_ETV,Endianess Test Value. Reading the constant value maintained in this register allows software to determine the endianess of the host CPU."
|
|
group.long 0x700C++0x23
|
|
line.long 0x0 "MCAN_DBTP,MCAN Data Bit Timing and Prescaler Register"
|
|
bitfld.long 0x0 23. "MCAN_DBTP_TDC,Transmitter Delay Compensation" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "MCAN_DBTP_DBRP,Data Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. The actual.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "MCAN_DBTP_DTSEG1,Data Time Segment Before Sample Point. Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "MCAN_DBTP_DTSEG2,Data Time Segment After Sample Point. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "MCAN_DBTP_DSJW,Data Resynchronization Jump Width. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
|
|
line.long 0x4 "MCAN_TEST,MCAN Test Register"
|
|
rbitfld.long 0x4 7. "MCAN_TEST_RX,Receive Pin. Monitors the actual value of the CAN receive pin." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5.--6. "MCAN_TEST_TX,Control of Transmit Pin" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4. "MCAN_TEST_LBCK,Loop Back Mode" "0,1"
|
|
line.long 0x8 "MCAN_RWD,MCAN RAM Watchdog"
|
|
hexmask.long.byte 0x8 8.--15. 1. "MCAN_RWD_WDV,Watchdog Value. Acutal Message RAM Watchdog Counter Value."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "MCAN_RWD_WDC,Watchdog Configuration. Start value of the Message RAM Watchdog Counter. With the reset value of "00" the counter is disabled."
|
|
line.long 0xC "MCAN_CCCR,MCAN CC Control Register"
|
|
bitfld.long 0xC 15. "MCAN_CCCR_NISO,Non ISO Operation. If this bit is set the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0." "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "MCAN_CCCR_TXP,Transmit Pause. If this bit is set the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame." "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "MCAN_CCCR_EFBI,Edge Filtering during Bus Integration" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "MCAN_CCCR_PXHD,Protocol Exception Handling Disable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "MCAN_CCCR_BRSE,Bit Rate Switch Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "MCAN_CCCR_FDOE,Flexible Datarate Operation Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "MCAN_CCCR_TEST,Test Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "MCAN_CCCR_DAR,Disable Automatic Retransmission" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "MCAN_CCCR_MON,Bus Monitoring Mode. Bit MON can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time." "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "MCAN_CCCR_CSR,Clock Stop Request" "0,1"
|
|
newline
|
|
rbitfld.long 0xC 3. "MCAN_CCCR_CSA,Clock Stop Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "MCAN_CCCR_ASM,Restricted Operation Mode. Bit ASM can only be set by SW when both CCE and INIT are set to '1'. The bit can be reset by SW at any time." "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "MCAN_CCCR_CCE,Configuration Change Enable" "0,1"
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bitfld.long 0xC 0. "MCAN_CCCR_INIT,Initialization" "0,1"
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line.long 0x10 "MCAN_NBTP,MCAN Nominal Bit Timing and Prescaler Register"
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hexmask.long.byte 0x10 25.--31. 1. "MCAN_NBTP_NSJW,Nominal (Re)Synchronization Jump Width. Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."
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hexmask.long.word 0x10 16.--24. 1. "MCAN_NBTP_NBRP,Nominal Bit Rate Prescaler. The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The.."
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hexmask.long.byte 0x10 8.--15. 1. "MCAN_NBTP_NTSEG1,Nominal Time Segment Before Sample Point. Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."
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hexmask.long.byte 0x10 0.--6. 1. "MCAN_NBTP_NTSEG2,Nominal Time Segment After Sample Point. Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."
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line.long 0x14 "MCAN_TSCC,MCAN Timestamp Counter Configuration"
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hexmask.long.byte 0x14 16.--19. 1. "MCAN_TSCC_TCP,Timestamp Counter Prescaler. Configures the timestamp and timeout counters time unit in multiples of CAN bit times. Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value.."
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bitfld.long 0x14 0.--1. "MCAN_TSCC_TSS,Timestamp Select" "0,1,2,3"
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line.long 0x18 "MCAN_TSCV,MCAN Timestamp Counter Value"
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hexmask.long.word 0x18 0.--15. 1. "MCAN_TSCV_TSC,Timestamp Counter. The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When TSCC.TSS = "01" the Timestamp Counter is incremented in multiples of CAN bit times (1...16) depending.."
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line.long 0x1C "MCAN_TOCC,MCAN Timeout Counter Configuration"
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hexmask.long.word 0x1C 16.--31. 1. "MCAN_TOCC_TOP,Timeout Period. Start value of the Timeout Counter (down-counter). Configures the Timeout Period."
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bitfld.long 0x1C 1.--2. "MCAN_TOCC_TOS,Timeout Select. When operating in Continuous mode a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs an empty FIFO presets the.." "0,1,2,3"
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bitfld.long 0x1C 0. "MCAN_TOCC_ETOC,Enable Timeout Counter" "0,1"
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line.long 0x20 "MCAN_TOCV,MCAN Timeout Counter Value"
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hexmask.long.word 0x20 0.--15. 1. "MCAN_TOCV_TOC,Timeout Counter. The Timeout Counter is decremented in multiples of CAN bit times (1...16) depending on the configuration of TSCC.TCP. When decremented to zero interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and.."
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rgroup.long 0x7040++0x7
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line.long 0x0 "MCAN_ECR,MCAN Error Counter Register"
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hexmask.long.byte 0x0 16.--23. 1. "MCAN_ECR_CEL,CAN Error Logging. The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next.."
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bitfld.long 0x0 15. "MCAN_ECR_RP,Receive Error Passive" "0,1"
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hexmask.long.byte 0x0 8.--14. 1. "MCAN_ECR_REC,Receive Error Counter. Actual state of the Receive Error Counter values between 0 and 127."
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hexmask.long.byte 0x0 0.--7. 1. "MCAN_ECR_TEC,Transmit Error Counter. Actual state of the Transmit Error Counter values between 0 and 255."
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line.long 0x4 "MCAN_PSR,MCAN Protocol Status Register"
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hexmask.long.byte 0x4 16.--22. 1. "MCAN_PSR_TDCV,Transmitter Delay Compensation Value. Position of the secondary sample point defined by the sum of the measured delay from the internal CAN TX signal to the internal CAN RX signal and TDCR.TDCO. The SSP position is in the data phase the.."
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bitfld.long 0x4 14. "MCAN_PSR_PXE,Protocol Exception Event" "0,1"
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bitfld.long 0x4 13. "MCAN_PSR_RFDF,Received a CAN FD Message. This bit is set independent of acceptance filtering." "0,1"
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bitfld.long 0x4 12. "MCAN_PSR_RBRS,BRS Flag of Last Received CAN FD Message. This bit is set together with RFDF independent of acceptance filtering." "0,1"
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bitfld.long 0x4 11. "MCAN_PSR_RESI,ESI Flag of Last Received CAN FD Message. This bit is set together with RFDF independent of acceptance filtering." "0,1"
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bitfld.long 0x4 8.--10. "MCAN_PSR_DLEC,Data Phase Last Error Code. Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 7. "MCAN_PSR_BO,Bus_Off Status" "0,1"
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bitfld.long 0x4 6. "MCAN_PSR_EW,Warning Status" "0,1"
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bitfld.long 0x4 5. "MCAN_PSR_EP,Error Passive" "0,1"
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bitfld.long 0x4 3.--4. "MCAN_PSR_ACT,Node Activity. Monitors the module's CAN communication state." "0,1,2,3"
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bitfld.long 0x4 0.--2. "MCAN_PSR_LEC,Last Error Code. The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error." "0,1,2,3,4,5,6,7"
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group.long 0x7048++0x3
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line.long 0x0 "MCAN_TDCR,MCAN Transmitter Delay Compensation Register"
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hexmask.long.byte 0x0 8.--14. 1. "MCAN_TDCR_TDCO,Transmitter Delay Compensation Offset. Offset value defining the distance between the measured delay from the internal CAN TX signal to the internal CAN RX signal and the secondary sample point. Valid values are 0 to 127 mtq."
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hexmask.long.byte 0x0 0.--6. 1. "MCAN_TDCR_TDCF,Transmitter Delay Compensation Filter Window Length. Defines the minimum value for the SSP position dominant edges on the internal CAN RX signal that would result in an earlier SSP position are ignored for transmitter delay measurement."
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group.long 0x7050++0xF
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line.long 0x0 "MCAN_IR,MCAN Interrupt Register"
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bitfld.long 0x0 29. "MCAN_IR_ARA,Access to Reserved Address" "0,1"
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bitfld.long 0x0 28. "MCAN_IR_PED,Protocol Error in Data Phase (Data Bit Time is used)" "0,1"
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bitfld.long 0x0 27. "MCAN_IR_PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0,1"
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bitfld.long 0x0 26. "MCAN_IR_WDI,Watchdog Interrupt" "0,1"
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bitfld.long 0x0 25. "MCAN_IR_BO,Bus_Off Status" "0,1"
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bitfld.long 0x0 24. "MCAN_IR_EW,Warning Status" "0,1"
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bitfld.long 0x0 23. "MCAN_IR_EP,Error Passive" "0,1"
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bitfld.long 0x0 22. "MCAN_IR_ELO,Error Logging Overflow" "0,1"
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bitfld.long 0x0 21. "MCAN_IR_BEU,Bit Error Uncorrected. Message RAM bit error detected uncorrected. This bit is set when a double bit error is detected by the ECC aggregator attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to '1'. This is.." "0,1"
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bitfld.long 0x0 19. "MCAN_IR_DRX,Message Stored to Dedicated Rx Buffer. The flag is set whenever a received message has been stored into a dedicated Rx Buffer." "0,1"
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bitfld.long 0x0 18. "MCAN_IR_TOO,Timeout Occurred" "0,1"
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bitfld.long 0x0 17. "MCAN_IR_MRAF,Message RAM Access Failure. The flag is set when the Rx Handler:" "0,1"
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bitfld.long 0x0 16. "MCAN_IR_TSW,Timestamp Wraparound" "0,1"
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bitfld.long 0x0 15. "MCAN_IR_TEFL,Tx Event FIFO Element Lost" "0,1"
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bitfld.long 0x0 14. "MCAN_IR_TEFF,Tx Event FIFO Full" "0,1"
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bitfld.long 0x0 13. "MCAN_IR_TEFW,Tx Event FIFO Watermark Reached" "0,1"
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bitfld.long 0x0 12. "MCAN_IR_TEFN,Tx Event FIFO New Entry" "0,1"
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bitfld.long 0x0 11. "MCAN_IR_TFE,Tx FIFO Empty" "0,1"
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bitfld.long 0x0 10. "MCAN_IR_TCF,Transmission Cancellation Finished" "0,1"
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bitfld.long 0x0 9. "MCAN_IR_TC,Transmission Completed" "0,1"
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bitfld.long 0x0 8. "MCAN_IR_HPM,High Priority Message" "0,1"
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bitfld.long 0x0 7. "MCAN_IR_RF1L,Rx FIFO 1 Message Lost" "0,1"
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bitfld.long 0x0 6. "MCAN_IR_RF1F,Rx FIFO 1 Full" "0,1"
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bitfld.long 0x0 5. "MCAN_IR_RF1W,Rx FIFO 1 Watermark Reached" "0,1"
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bitfld.long 0x0 4. "MCAN_IR_RF1N,Rx FIFO 1 New Message" "0,1"
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bitfld.long 0x0 3. "MCAN_IR_RF0L,Rx FIFO 0 Message Lost" "0,1"
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bitfld.long 0x0 2. "MCAN_IR_RF0F,Rx FIFO 0 Full" "0,1"
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bitfld.long 0x0 1. "MCAN_IR_RF0W,Rx FIFO 0 Watermark Reached" "0,1"
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bitfld.long 0x0 0. "MCAN_IR_RF0N,Rx FIFO 0 New Message" "0,1"
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line.long 0x4 "MCAN_IE,MCAN Interrupt Enable"
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bitfld.long 0x4 29. "MCAN_IE_ARAE,Access to Reserved Address Enable" "0,1"
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bitfld.long 0x4 28. "MCAN_IE_PEDE,Protocol Error in Data Phase Enable" "0,1"
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bitfld.long 0x4 27. "MCAN_IE_PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
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bitfld.long 0x4 26. "MCAN_IE_WDIE,Watchdog Interrupt Enable" "0,1"
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bitfld.long 0x4 25. "MCAN_IE_BOE,Bus_Off Status Enable" "0,1"
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bitfld.long 0x4 24. "MCAN_IE_EWE,Warning Status Enable" "0,1"
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bitfld.long 0x4 23. "MCAN_IE_EPE,Error Passive Enable" "0,1"
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bitfld.long 0x4 22. "MCAN_IE_ELOE,Error Logging Overflow Enable" "0,1"
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bitfld.long 0x4 21. "MCAN_IE_BEUE,Bit Error Uncorrected Enable" "0,1"
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bitfld.long 0x4 20. "MCAN_IE_BECE,Bit Error Corrected Enable" "0,1"
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bitfld.long 0x4 19. "MCAN_IE_DRXE,Message Stored to Dedicated Rx Buffer Enable" "0,1"
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bitfld.long 0x4 18. "MCAN_IE_TOOE,Timeout Occurred Enable" "0,1"
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bitfld.long 0x4 17. "MCAN_IE_MRAFE,Message RAM Access Failure Enable" "0,1"
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bitfld.long 0x4 16. "MCAN_IE_TSWE,Timestamp Wraparound Enable" "0,1"
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bitfld.long 0x4 15. "MCAN_IE_TEFLE,Tx Event FIFO Element Lost Enable" "0,1"
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bitfld.long 0x4 14. "MCAN_IE_TEFFE,Tx Event FIFO Full Enable" "0,1"
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bitfld.long 0x4 13. "MCAN_IE_TEFWE,Tx Event FIFO Watermark Reached Enable" "0,1"
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bitfld.long 0x4 12. "MCAN_IE_TEFNE,Tx Event FIFO New Entry Enable" "0,1"
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bitfld.long 0x4 11. "MCAN_IE_TFEE,Tx FIFO Empty Enable" "0,1"
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bitfld.long 0x4 10. "MCAN_IE_TCFE,Transmission Cancellation Finished Enable" "0,1"
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bitfld.long 0x4 9. "MCAN_IE_TCE,Transmission Completed Enable" "0,1"
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bitfld.long 0x4 8. "MCAN_IE_HPME,High Priority Message Enable" "0,1"
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bitfld.long 0x4 7. "MCAN_IE_RF1LE,Rx FIFO 1 Message Lost Enable" "0,1"
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bitfld.long 0x4 6. "MCAN_IE_RF1FE,Rx FIFO 1 Full Enable" "0,1"
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bitfld.long 0x4 5. "MCAN_IE_RF1WE,Rx FIFO 1 Watermark Reached Enable" "0,1"
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bitfld.long 0x4 4. "MCAN_IE_RF1NE,Rx FIFO 1 New Message Enable" "0,1"
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bitfld.long 0x4 3. "MCAN_IE_RF0LE,Rx FIFO 0 Message Lost Enable" "0,1"
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bitfld.long 0x4 2. "MCAN_IE_RF0FE,Rx FIFO 0 Full Enable" "0,1"
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bitfld.long 0x4 1. "MCAN_IE_RF0WE,Rx FIFO 0 Watermark Reached Enable" "0,1"
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bitfld.long 0x4 0. "MCAN_IE_RF0NE,Rx FIFO 0 New Message Enable" "0,1"
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line.long 0x8 "MCAN_ILS,MCAN Interrupt Line Select"
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bitfld.long 0x8 29. "MCAN_ILS_ARAL,Access to Reserved Address Line" "0,1"
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bitfld.long 0x8 28. "MCAN_ILS_PEDL,Protocol Error in Data Phase Line" "0,1"
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|
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bitfld.long 0x8 27. "MCAN_ILS_PEAL,Protocol Error in Arbitration Phase Line" "0,1"
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|
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bitfld.long 0x8 26. "MCAN_ILS_WDIL,Watchdog Interrupt Line" "0,1"
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|
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bitfld.long 0x8 25. "MCAN_ILS_BOL,Bus_Off Status Line" "0,1"
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|
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bitfld.long 0x8 24. "MCAN_ILS_EWL,Warning Status Line" "0,1"
|
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|
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bitfld.long 0x8 23. "MCAN_ILS_EPL,Error Passive Line" "0,1"
|
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|
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bitfld.long 0x8 22. "MCAN_ILS_ELOL,Error Logging Overflow Line" "0,1"
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|
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bitfld.long 0x8 21. "MCAN_ILS_BEUL,Bit Error Uncorrected Line" "0,1"
|
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|
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bitfld.long 0x8 20. "MCAN_ILS_BECL,Bit Error Corrected Line" "0,1"
|
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|
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bitfld.long 0x8 19. "MCAN_ILS_DRXL,Message Stored to Dedicated Rx Buffer Line" "0,1"
|
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|
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bitfld.long 0x8 18. "MCAN_ILS_TOOL,Timeout Occurred Line" "0,1"
|
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|
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bitfld.long 0x8 17. "MCAN_ILS_MRAFL,Message RAM Access Failure Line" "0,1"
|
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|
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bitfld.long 0x8 16. "MCAN_ILS_TSWL,Timestamp Wraparound Line" "0,1"
|
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|
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bitfld.long 0x8 15. "MCAN_ILS_TEFLL,Tx Event FIFO Element Lost Line" "0,1"
|
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|
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bitfld.long 0x8 14. "MCAN_ILS_TEFFL,Tx Event FIFO Full Line" "0,1"
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|
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bitfld.long 0x8 13. "MCAN_ILS_TEFWL,Tx Event FIFO Watermark Reached Line" "0,1"
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|
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bitfld.long 0x8 12. "MCAN_ILS_TEFNL,Tx Event FIFO New Entry Line" "0,1"
|
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|
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bitfld.long 0x8 11. "MCAN_ILS_TFEL,Tx FIFO Empty Line" "0,1"
|
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|
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bitfld.long 0x8 10. "MCAN_ILS_TCFL,Transmission Cancellation Finished Line" "0,1"
|
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|
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bitfld.long 0x8 9. "MCAN_ILS_TCL,Transmission Completed Line" "0,1"
|
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|
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bitfld.long 0x8 8. "MCAN_ILS_HPML,High Priority Message Line" "0,1"
|
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|
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bitfld.long 0x8 7. "MCAN_ILS_RF1LL,Rx FIFO 1 Message Lost Line" "0,1"
|
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|
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bitfld.long 0x8 6. "MCAN_ILS_RF1FL,Rx FIFO 1 Full Line" "0,1"
|
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|
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bitfld.long 0x8 5. "MCAN_ILS_RF1WL,Rx FIFO 1 Watermark Reached Line" "0,1"
|
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|
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bitfld.long 0x8 4. "MCAN_ILS_RF1NL,Rx FIFO 1 New Message Line" "0,1"
|
|
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|
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bitfld.long 0x8 3. "MCAN_ILS_RF0LL,Rx FIFO 0 Message Lost Line" "0,1"
|
|
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|
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bitfld.long 0x8 2. "MCAN_ILS_RF0FL,Rx FIFO 0 Full Line" "0,1"
|
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|
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bitfld.long 0x8 1. "MCAN_ILS_RF0WL,Rx FIFO 0 Watermark Reached Line" "0,1"
|
|
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|
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bitfld.long 0x8 0. "MCAN_ILS_RF0NL,Rx FIFO 0 New Message Line" "0,1"
|
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line.long 0xC "MCAN_ILE,MCAN Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "MCAN_ILE_EINT1,Enable Interrupt Line 1" "0,1"
|
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|
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bitfld.long 0xC 0. "MCAN_ILE_EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x7080++0xB
|
|
line.long 0x0 "MCAN_GFC,MCAN Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "MCAN_GFC_ANFS,Accept Non-matching Frames Standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated." "0,1,2,3"
|
|
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|
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bitfld.long 0x0 2.--3. "MCAN_GFC_ANFE,Accept Non-matching Frames Extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated." "0,1,2,3"
|
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|
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bitfld.long 0x0 1. "MCAN_GFC_RRFS,Reject Remote Frames Standard" "0,1"
|
|
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|
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bitfld.long 0x0 0. "MCAN_GFC_RRFE,Reject Remote Frames Extended" "0,1"
|
|
line.long 0x4 "MCAN_SIDFC,MCAN Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "MCAN_SIDFC_LSS,List Size Standard"
|
|
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|
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hexmask.long.word 0x4 2.--15. 1. "MCAN_SIDFC_FLSSA,Filter List Standard Start Address. Start address of standard Message ID filter list (32-bit word address)."
|
|
line.long 0x8 "MCAN_XIDFC,MCAN Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "MCAN_XIDFC_LSE,Filter List Extended Start Address. Start address of extended Message ID filter list (32-bit word address)."
|
|
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|
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hexmask.long.word 0x8 2.--15. 1. "MCAN_XIDFC_FLESA,List Size Extended"
|
|
group.long 0x7090++0x3
|
|
line.long 0x0 "MCAN_XIDAM,MCAN Extended ID and Mask"
|
|
hexmask.long 0x0 0.--28. 1. "MCAN_XIDAM_EIDM,Extended ID Mask. For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask.."
|
|
rgroup.long 0x7094++0x3
|
|
line.long 0x0 "MCAN_HPMS,MCAN High Priority Message Status"
|
|
bitfld.long 0x0 15. "MCAN_HPMS_FLST,Filter List. Indicates the filter list of the matching filter element." "0,1"
|
|
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|
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hexmask.long.byte 0x0 8.--14. 1. "MCAN_HPMS_FIDX,Filter Index. Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1."
|
|
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|
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bitfld.long 0x0 6.--7. "MCAN_HPMS_MSI,Message Storage Indicator" "0,1,2,3"
|
|
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|
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hexmask.long.byte 0x0 0.--5. 1. "MCAN_HPMS_BIDX,Buffer Index. Index of Rx FIFO element to which the message was stored. Only valid when MSI(1) = '1'."
|
|
group.long 0x7098++0xB
|
|
line.long 0x0 "MCAN_NDAT1,MCAN New Data 1"
|
|
bitfld.long 0x0 31. "MCAN_NDAT1_ND31,New Data RX Buffer 31" "0,1"
|
|
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|
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bitfld.long 0x0 30. "MCAN_NDAT1_ND30,New Data RX Buffer 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MCAN_NDAT1_ND29,New Data RX Buffer 29" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "MCAN_NDAT1_ND28,New Data RX Buffer 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCAN_NDAT1_ND27,New Data RX Buffer 27" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "MCAN_NDAT1_ND26,New Data RX Buffer 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCAN_NDAT1_ND25,New Data RX Buffer 25" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MCAN_NDAT1_ND24,New Data RX Buffer 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MCAN_NDAT1_ND23,New Data RX Buffer 23" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MCAN_NDAT1_ND22,New Data RX Buffer 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCAN_NDAT1_ND21,New Data RX Buffer 21" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "MCAN_NDAT1_ND20,New Data RX Buffer 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCAN_NDAT1_ND19,New Data RX Buffer 19" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MCAN_NDAT1_ND18,New Data RX Buffer 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCAN_NDAT1_ND17,New Data RX Buffer 17" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCAN_NDAT1_ND16,New Data RX Buffer 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MCAN_NDAT1_ND15,New Data RX Buffer 15" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MCAN_NDAT1_ND14,New Data RX Buffer 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MCAN_NDAT1_ND13,New Data RX Buffer 13" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MCAN_NDAT1_ND12,New Data RX Buffer 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MCAN_NDAT1_ND11,New Data RX Buffer 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MCAN_NDAT1_ND10,New Data RX Buffer 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MCAN_NDAT1_ND9,New Data RX Buffer 9" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MCAN_NDAT1_ND8,New Data RX Buffer 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MCAN_NDAT1_ND7,New Data RX Buffer 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MCAN_NDAT1_ND6,New Data RX Buffer 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MCAN_NDAT1_ND5,New Data RX Buffer 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MCAN_NDAT1_ND4,New Data RX Buffer 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MCAN_NDAT1_ND3,New Data RX Buffer 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MCAN_NDAT1_ND2,New Data RX Buffer 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MCAN_NDAT1_ND1,New Data RX Buffer 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MCAN_NDAT1_ND0,New Data RX Buffer 0" "0,1"
|
|
line.long 0x4 "MCAN_NDAT2,MCAN New Data 2"
|
|
bitfld.long 0x4 31. "MCAN_NDAT2_ND63,New Data RX Buffer 63" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "MCAN_NDAT2_ND62,New Data RX Buffer 62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "MCAN_NDAT2_ND61,New Data RX Buffer 61" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "MCAN_NDAT2_ND60,New Data RX Buffer 60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "MCAN_NDAT2_ND59,New Data RX Buffer 59" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "MCAN_NDAT2_ND58,New Data RX Buffer 58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "MCAN_NDAT2_ND57,New Data RX Buffer 57" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "MCAN_NDAT2_ND56,New Data RX Buffer 56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "MCAN_NDAT2_ND55,New Data RX Buffer 55" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "MCAN_NDAT2_ND54,New Data RX Buffer 54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "MCAN_NDAT2_ND53,New Data RX Buffer 53" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "MCAN_NDAT2_ND52,New Data RX Buffer 52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MCAN_NDAT2_ND51,New Data RX Buffer 51" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "MCAN_NDAT2_ND50,New Data RX Buffer 50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MCAN_NDAT2_ND49,New Data RX Buffer 49" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCAN_NDAT2_ND48,New Data RX Buffer 48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "MCAN_NDAT2_ND47,New Data RX Buffer 47" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "MCAN_NDAT2_ND46,New Data RX Buffer 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MCAN_NDAT2_ND45,New Data RX Buffer 45" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "MCAN_NDAT2_ND44,New Data RX Buffer 44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MCAN_NDAT2_ND43,New Data RX Buffer 43" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "MCAN_NDAT2_ND42,New Data RX Buffer 42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MCAN_NDAT2_ND41,New Data RX Buffer 41" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "MCAN_NDAT2_ND40,New Data RX Buffer 40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MCAN_NDAT2_ND39,New Data RX Buffer 39" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "MCAN_NDAT2_ND38,New Data RX Buffer 38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MCAN_NDAT2_ND37,New Data RX Buffer 37" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MCAN_NDAT2_ND36,New Data RX Buffer 36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCAN_NDAT2_ND35,New Data RX Buffer 35" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MCAN_NDAT2_ND34,New Data RX Buffer 34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MCAN_NDAT2_ND33,New Data RX Buffer 33" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MCAN_NDAT2_ND32,New Data RX Buffer 32" "0,1"
|
|
line.long 0x8 "MCAN_RXF0C,MCAN Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "MCAN_RXF0C_F0OM,FIFO 0 Operation Mode. FIFO 0 can be operated in blocking or in overwrite mode." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--30. 1. "MCAN_RXF0C_F0WM,Rx FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "MCAN_RXF0C_F0S,Rx FIFO 0 Size. The Rx FIFO 0 elements are indexed from 0 to F0S-1."
|
|
newline
|
|
hexmask.long.word 0x8 2.--15. 1. "MCAN_RXF0C_F0SA,Rx FIFO 0 Start Address. Start address of Rx FIFO 0 in Message RAM (32-bit word address)."
|
|
rgroup.long 0x70A4++0x3
|
|
line.long 0x0 "MCAN_RXF0S,MCAN Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "MCAN_RXF0S_RF0L,Rx FIFO 0 Message Lost. This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset this bit is also reset." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MCAN_RXF0S_F0F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "MCAN_RXF0S_F0PI,Rx FIFO 0 Put Index. Rx FIFO 0 write index pointer range 0 to 63."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "MCAN_RXF0S_F0GI,Rx FIFO 0 Get Index. Rx FIFO 0 read index pointer range 0 to 63."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "MCAN_RXF0S_F0FL,Rx FIFO 0 Fill Level. Number of elements stored in Rx FIFO 0 range 0 to 64."
|
|
group.long 0x70A8++0xB
|
|
line.long 0x0 "MCAN_RXF0A,MCAN Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MCAN_RXF0A_F0AI,Rx FIFO 0 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to.."
|
|
line.long 0x4 "MCAN_RXBC,MCAN Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 2.--15. 1. "MCAN_RXBC_RBSA,Rx Buffer Start Address. Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address)."
|
|
line.long 0x8 "MCAN_RXF1C,MCAN Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "MCAN_RXF1C_F1OM,FIFO 1 Operation Mode. FIFO 1 can be operated in blocking or in overwrite mode." "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--30. 1. "MCAN_RXF1C_F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "MCAN_RXF1C_F1S,Rx FIFO 1 Size. The Rx FIFO 1 elements are indexed from 0 to F1S - 1."
|
|
newline
|
|
hexmask.long.word 0x8 2.--15. 1. "MCAN_RXF1C_F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address)."
|
|
rgroup.long 0x70B4++0x3
|
|
line.long 0x0 "MCAN_RXF1S,MCAN Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "MCAN_RXF1S_DMS,Debug Message Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 25. "MCAN_RXF1S_RF1L,Rx FIFO 1 Message Lost. This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset this bit is also reset." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MCAN_RXF1S_F1F,Rx FIFO 1 Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "MCAN_RXF1S_F1PI,Rx FIFO 1 Put Index. Rx FIFO 1 write index pointer range 0 to 63."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "MCAN_RXF1S_F1GI,Rx FIFO 1 Get Index. Rx FIFO 1 read index pointer range 0 to 63."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "MCAN_RXF1S_F1FL,Rx FIFO 1 Fill Level. Number of elements stored in Rx FIFO 1 range 0 to 64."
|
|
group.long 0x70B8++0xB
|
|
line.long 0x0 "MCAN_RXF1A,MCAN Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MCAN_RXF1A_F1AI,Rx FIFO 1 Acknowledge Index. After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to.."
|
|
line.long 0x4 "MCAN_RXESC,MCAN Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "MCAN_RXESC_RBDS,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "MCAN_RXESC_F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "MCAN_RXESC_F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "MCAN_TXBC,MCAN Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "MCAN_TXBC_TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--29. 1. "MCAN_TXBC_TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "MCAN_TXBC_NDTB,Number of Dedicated Transmit Buffers"
|
|
newline
|
|
hexmask.long.word 0x8 2.--15. 1. "MCAN_TXBC_TBSA,Tx Buffers Start Address. Start address of Tx Buffers section in Message RAM (32-bit word address)."
|
|
rgroup.long 0x70C4++0x3
|
|
line.long 0x0 "MCAN_TXFQS,MCAN Tx FIFO / Queue Status"
|
|
bitfld.long 0x0 21. "MCAN_TXFQS_TFQF,Tx FIFO/Queue Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "MCAN_TXFQS_TFQP,Tx FIFO/Queue Put Index. Tx FIFO/Queue write index pointer range 0 to 31."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "MCAN_TXFQS_TFGI,Tx FIFO Get Index. Tx FIFO read index pointer range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1')."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "MCAN_TXFQS_TFFL,Tx FIFO Free Level. Number of consecutive free Tx FIFO elements starting from TFGI range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = '1')."
|
|
group.long 0x70C8++0x3
|
|
line.long 0x0 "MCAN_TXESC,MCAN Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "MCAN_TXESC_TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x70CC++0x3
|
|
line.long 0x0 "MCAN_TXBRP,MCAN Tx Buffer Request Pending"
|
|
bitfld.long 0x0 31. "MCAN_TXBRP_TRP31,Transmission Request Pending 31. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MCAN_TXBRP_TRP30,Transmission Request Pending 30. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MCAN_TXBRP_TRP29,Transmission Request Pending 29. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "MCAN_TXBRP_TRP28,Transmission Request Pending 28. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCAN_TXBRP_TRP27,Transmission Request Pending 27. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "MCAN_TXBRP_TRP26,Transmission Request Pending 26. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCAN_TXBRP_TRP25,Transmission Request Pending 25. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MCAN_TXBRP_TRP24,Transmission Request Pending 24. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MCAN_TXBRP_TRP23,Transmission Request Pending 23. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MCAN_TXBRP_TRP22,Transmission Request Pending 22. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCAN_TXBRP_TRP21,Transmission Request Pending 21. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "MCAN_TXBRP_TRP20,Transmission Request Pending 20. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCAN_TXBRP_TRP19,Transmission Request Pending 19. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MCAN_TXBRP_TRP18,Transmission Request Pending 18. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCAN_TXBRP_TRP17,Transmission Request Pending 17. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCAN_TXBRP_TRP16,Transmission Request Pending 16. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MCAN_TXBRP_TRP15,Transmission Request Pending 15. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MCAN_TXBRP_TRP14,Transmission Request Pending 14. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MCAN_TXBRP_TRP13,Transmission Request Pending 13. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MCAN_TXBRP_TRP12,Transmission Request Pending 12. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MCAN_TXBRP_TRP11,Transmission Request Pending 11. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MCAN_TXBRP_TRP10,Transmission Request Pending 10. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MCAN_TXBRP_TRP9,Transmission Request Pending 9. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MCAN_TXBRP_TRP8,Transmission Request Pending 8. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MCAN_TXBRP_TRP7,Transmission Request Pending 7. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MCAN_TXBRP_TRP6,Transmission Request Pending 6. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MCAN_TXBRP_TRP5,Transmission Request Pending 5. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MCAN_TXBRP_TRP4,Transmission Request Pending 4. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MCAN_TXBRP_TRP3,Transmission Request Pending 3. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MCAN_TXBRP_TRP2,Transmission Request Pending 2. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MCAN_TXBRP_TRP1,Transmission Request Pending 1. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MCAN_TXBRP_TRP0,Transmission Request Pending 0." "0,1"
|
|
group.long 0x70D0++0x7
|
|
line.long 0x0 "MCAN_TXBAR,MCAN Tx Buffer Add Request"
|
|
bitfld.long 0x0 31. "MCAN_TXBAR_AR31,Add Request 31. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MCAN_TXBAR_AR30,Add Request 30. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MCAN_TXBAR_AR29,Add Request 29. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "MCAN_TXBAR_AR28,Add Request 28. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCAN_TXBAR_AR27,Add Request 27. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "MCAN_TXBAR_AR26,Add Request 26. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCAN_TXBAR_AR25,Add Request 25. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MCAN_TXBAR_AR24,Add Request 24. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MCAN_TXBAR_AR23,Add Request 23. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MCAN_TXBAR_AR22,Add Request 22. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCAN_TXBAR_AR21,Add Request 21. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "MCAN_TXBAR_AR20,Add Request 20. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCAN_TXBAR_AR19,Add Request 19. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MCAN_TXBAR_AR18,Add Request 18. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCAN_TXBAR_AR17,Add Request 17. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCAN_TXBAR_AR16,Add Request 16. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MCAN_TXBAR_AR15,Add Request 15. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MCAN_TXBAR_AR14,Add Request 14. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MCAN_TXBAR_AR13,Add Request 13. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MCAN_TXBAR_AR12,Add Request 12. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MCAN_TXBAR_AR11,Add Request 11. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MCAN_TXBAR_AR10,Add Request 10. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MCAN_TXBAR_AR9,Add Request 9. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MCAN_TXBAR_AR8,Add Request 8. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MCAN_TXBAR_AR7,Add Request 7. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MCAN_TXBAR_AR6,Add Request 6. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MCAN_TXBAR_AR5,Add Request 5. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MCAN_TXBAR_AR4,Add Request 4. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MCAN_TXBAR_AR3,Add Request 3. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MCAN_TXBAR_AR2,Add Request 2. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MCAN_TXBAR_AR1,Add Request 1. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MCAN_TXBAR_AR0,Add Request 0." "0,1"
|
|
line.long 0x4 "MCAN_TXBCR,MCAN Tx Buffer Cancellation Request"
|
|
bitfld.long 0x4 31. "MCAN_TXBCR_CR31,Cancellation Request 31. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "MCAN_TXBCR_CR30,Cancellation Request 30. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "MCAN_TXBCR_CR29,Cancellation Request 29. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "MCAN_TXBCR_CR28,Cancellation Request 28. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "MCAN_TXBCR_CR27,Cancellation Request 27. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "MCAN_TXBCR_CR26,Cancellation Request 26. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "MCAN_TXBCR_CR25,Cancellation Request 25. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "MCAN_TXBCR_CR24,Cancellation Request 24. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "MCAN_TXBCR_CR23,Cancellation Request 23. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "MCAN_TXBCR_CR22,Cancellation Request 22. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "MCAN_TXBCR_CR21,Cancellation Request 21. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "MCAN_TXBCR_CR20,Cancellation Request 20. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MCAN_TXBCR_CR19,Cancellation Request 19. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "MCAN_TXBCR_CR18,Cancellation Request 18. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MCAN_TXBCR_CR17,Cancellation Request 17. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCAN_TXBCR_CR16,Cancellation Request 16. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "MCAN_TXBCR_CR15,Cancellation Request 15. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "MCAN_TXBCR_CR14,Cancellation Request 14. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MCAN_TXBCR_CR13,Cancellation Request 13. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "MCAN_TXBCR_CR12,Cancellation Request 12. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MCAN_TXBCR_CR11,Cancellation Request 11. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "MCAN_TXBCR_CR10,Cancellation Request 10. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MCAN_TXBCR_CR9,Cancellation Request 9. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "MCAN_TXBCR_CR8,Cancellation Request 8. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MCAN_TXBCR_CR7,Cancellation Request 7. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "MCAN_TXBCR_CR6,Cancellation Request 6. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MCAN_TXBCR_CR5,Cancellation Request 5. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MCAN_TXBCR_CR4,Cancellation Request 4. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCAN_TXBCR_CR3,Cancellation Request 3. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MCAN_TXBCR_CR2,Cancellation Request 2. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MCAN_TXBCR_CR1,Cancellation Request 1. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MCAN_TXBCR_CR0,Cancellation Request 0." "0,1"
|
|
rgroup.long 0x70D8++0x7
|
|
line.long 0x0 "MCAN_TXBTO,MCAN Tx Buffer Transmission Occurred"
|
|
bitfld.long 0x0 31. "MCAN_TXBTO_TO31,Transmission Occurred 31. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MCAN_TXBTO_TO30,Transmission Occurred 30. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MCAN_TXBTO_TO29,Transmission Occurred 29. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "MCAN_TXBTO_TO28,Transmission Occurred 28. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCAN_TXBTO_TO27,Transmission Occurred 27. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "MCAN_TXBTO_TO26,Transmission Occurred 26. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCAN_TXBTO_TO25,Transmission Occurred 25. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MCAN_TXBTO_TO24,Transmission Occurred 24. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MCAN_TXBTO_TO23,Transmission Occurred 23. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MCAN_TXBTO_TO22,Transmission Occurred 22. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCAN_TXBTO_TO21,Transmission Occurred 21. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "MCAN_TXBTO_TO20,Transmission Occurred 20. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCAN_TXBTO_TO19,Transmission Occurred 19. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MCAN_TXBTO_TO18,Transmission Occurred 18. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCAN_TXBTO_TO17,Transmission Occurred 17. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCAN_TXBTO_TO16,Transmission Occurred 16. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MCAN_TXBTO_TO15,Transmission Occurred 15. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MCAN_TXBTO_TO14,Transmission Occurred 14. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MCAN_TXBTO_TO13,Transmission Occurred 13. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MCAN_TXBTO_TO12,Transmission Occurred 12. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MCAN_TXBTO_TO11,Transmission Occurred 11. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MCAN_TXBTO_TO10,Transmission Occurred 10. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MCAN_TXBTO_TO9,Transmission Occurred 9. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "MCAN_TXBTO_TO8,Transmission Occurred 8. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MCAN_TXBTO_TO7,Transmission Occurred 7. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "MCAN_TXBTO_TO6,Transmission Occurred 6. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MCAN_TXBTO_TO5,Transmission Occurred 5. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MCAN_TXBTO_TO4,Transmission Occurred 4. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MCAN_TXBTO_TO3,Transmission Occurred 3. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MCAN_TXBTO_TO2,Transmission Occurred 2. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MCAN_TXBTO_TO1,Transmission Occurred 1. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MCAN_TXBTO_TO0,Transmission Occurred 0." "0,1"
|
|
line.long 0x4 "MCAN_TXBCF,MCAN Tx Buffer Cancellation Finished"
|
|
bitfld.long 0x4 31. "MCAN_TXBCF_CF31,Cancellation Finished 31. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "MCAN_TXBCF_CF30,Cancellation Finished 30. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "MCAN_TXBCF_CF29,Cancellation Finished 29. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "MCAN_TXBCF_CF28,Cancellation Finished 28. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "MCAN_TXBCF_CF27,Cancellation Finished 27. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "MCAN_TXBCF_CF26,Cancellation Finished 26. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "MCAN_TXBCF_CF25,Cancellation Finished 25. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "MCAN_TXBCF_CF24,Cancellation Finished 24. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "MCAN_TXBCF_CF23,Cancellation Finished 23. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "MCAN_TXBCF_CF22,Cancellation Finished 22. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "MCAN_TXBCF_CF21,Cancellation Finished 21. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "MCAN_TXBCF_CF20,Cancellation Finished 20. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MCAN_TXBCF_CF19,Cancellation Finished 19. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "MCAN_TXBCF_CF18,Cancellation Finished 18. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MCAN_TXBCF_CF17,Cancellation Finished 17. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCAN_TXBCF_CF16,Cancellation Finished 16. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "MCAN_TXBCF_CF15,Cancellation Finished 15. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "MCAN_TXBCF_CF14,Cancellation Finished 14. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MCAN_TXBCF_CF13,Cancellation Finished 13. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "MCAN_TXBCF_CF12,Cancellation Finished 12. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MCAN_TXBCF_CF11,Cancellation Finished 11. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "MCAN_TXBCF_CF10,Cancellation Finished 10. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MCAN_TXBCF_CF9,Cancellation Finished 9. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "MCAN_TXBCF_CF8,Cancellation Finished 8. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MCAN_TXBCF_CF7,Cancellation Finished 7. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "MCAN_TXBCF_CF6,Cancellation Finished 6. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MCAN_TXBCF_CF5,Cancellation Finished 5. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "MCAN_TXBCF_CF4,Cancellation Finished 4. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCAN_TXBCF_CF3,Cancellation Finished 3. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MCAN_TXBCF_CF2,Cancellation Finished 2. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MCAN_TXBCF_CF1,Cancellation Finished 1. See description for bit 0." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MCAN_TXBCF_CF0,Cancellation Finished 0." "0,1"
|
|
group.long 0x70E0++0x7
|
|
line.long 0x0 "MCAN_TXBTIE,MCAN Tx Buffer Transmission Interrupt Enable"
|
|
bitfld.long 0x0 31. "MCAN_TXBTIE_TIE31,Transmission Interrupt Enable 31. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MCAN_TXBTIE_TIE30,Transmission Interrupt Enable 30. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MCAN_TXBTIE_TIE29,Transmission Interrupt Enable 29. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "MCAN_TXBTIE_TIE28,Transmission Interrupt Enable 28. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCAN_TXBTIE_TIE27,Transmission Interrupt Enable 27. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "MCAN_TXBTIE_TIE26,Transmission Interrupt Enable 26. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCAN_TXBTIE_TIE25,Transmission Interrupt Enable 25. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "MCAN_TXBTIE_TIE24,Transmission Interrupt Enable 24. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MCAN_TXBTIE_TIE23,Transmission Interrupt Enable 23. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "MCAN_TXBTIE_TIE22,Transmission Interrupt Enable 22. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCAN_TXBTIE_TIE21,Transmission Interrupt Enable 21. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "MCAN_TXBTIE_TIE20,Transmission Interrupt Enable 20. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCAN_TXBTIE_TIE19,Transmission Interrupt Enable 19. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "MCAN_TXBTIE_TIE18,Transmission Interrupt Enable 18. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCAN_TXBTIE_TIE17,Transmission Interrupt Enable 17. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCAN_TXBTIE_TIE16,Transmission Interrupt Enable 16. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MCAN_TXBTIE_TIE15,Transmission Interrupt Enable 15. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "MCAN_TXBTIE_TIE14,Transmission Interrupt Enable 14. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MCAN_TXBTIE_TIE13,Transmission Interrupt Enable 13. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "MCAN_TXBTIE_TIE12,Transmission Interrupt Enable 12. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MCAN_TXBTIE_TIE11,Transmission Interrupt Enable 11. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "MCAN_TXBTIE_TIE10,Transmission Interrupt Enable 10. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MCAN_TXBTIE_TIE9,Transmission Interrupt Enable 9. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "MCAN_TXBTIE_TIE8,Transmission Interrupt Enable 8. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
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bitfld.long 0x0 7. "MCAN_TXBTIE_TIE7,Transmission Interrupt Enable 7. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
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bitfld.long 0x0 6. "MCAN_TXBTIE_TIE6,Transmission Interrupt Enable 6. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
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bitfld.long 0x0 5. "MCAN_TXBTIE_TIE5,Transmission Interrupt Enable 5. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
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bitfld.long 0x0 4. "MCAN_TXBTIE_TIE4,Transmission Interrupt Enable 4. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
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bitfld.long 0x0 3. "MCAN_TXBTIE_TIE3,Transmission Interrupt Enable 3. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
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bitfld.long 0x0 2. "MCAN_TXBTIE_TIE2,Transmission Interrupt Enable 2. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
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bitfld.long 0x0 1. "MCAN_TXBTIE_TIE1,Transmission Interrupt Enable 1. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
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bitfld.long 0x0 0. "MCAN_TXBTIE_TIE0,Transmission Interrupt Enable 0. Each Tx Buffer has its own Transmission Interrupt Enable bit." "0,1"
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line.long 0x4 "MCAN_TXBCIE,MCAN Tx Buffer Cancellation Finished Interrupt Enable"
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bitfld.long 0x4 31. "MCAN_TXBCIE_CFIE31,Cancellation Finished Interrupt Enable 31. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 30. "MCAN_TXBCIE_CFIE30,Cancellation Finished Interrupt Enable 30. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 29. "MCAN_TXBCIE_CFIE29,Cancellation Finished Interrupt Enable 29. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 28. "MCAN_TXBCIE_CFIE28,Cancellation Finished Interrupt Enable 28. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 27. "MCAN_TXBCIE_CFIE27,Cancellation Finished Interrupt Enable 27. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 26. "MCAN_TXBCIE_CFIE26,Cancellation Finished Interrupt Enable 26. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 25. "MCAN_TXBCIE_CFIE25,Cancellation Finished Interrupt Enable 25. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 24. "MCAN_TXBCIE_CFIE24,Cancellation Finished Interrupt Enable 24. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 23. "MCAN_TXBCIE_CFIE23,Cancellation Finished Interrupt Enable 23. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 22. "MCAN_TXBCIE_CFIE22,Cancellation Finished Interrupt Enable 22. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 21. "MCAN_TXBCIE_CFIE21,Cancellation Finished Interrupt Enable 21. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 20. "MCAN_TXBCIE_CFIE20,Cancellation Finished Interrupt Enable 20. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 19. "MCAN_TXBCIE_CFIE19,Cancellation Finished Interrupt Enable 19. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 18. "MCAN_TXBCIE_CFIE18,Cancellation Finished Interrupt Enable 18. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 17. "MCAN_TXBCIE_CFIE17,Cancellation Finished Interrupt Enable 17. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 16. "MCAN_TXBCIE_CFIE16,Cancellation Finished Interrupt Enable 16. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 15. "MCAN_TXBCIE_CFIE15,Cancellation Finished Interrupt Enable 15. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 14. "MCAN_TXBCIE_CFIE14,Cancellation Finished Interrupt Enable 14. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 13. "MCAN_TXBCIE_CFIE13,Cancellation Finished Interrupt Enable 13. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 12. "MCAN_TXBCIE_CFIE12,Cancellation Finished Interrupt Enable 12. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 11. "MCAN_TXBCIE_CFIE11,Cancellation Finished Interrupt Enable 11. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 10. "MCAN_TXBCIE_CFIE10,Cancellation Finished Interrupt Enable 10. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 9. "MCAN_TXBCIE_CFIE9,Cancellation Finished Interrupt Enable 9. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 8. "MCAN_TXBCIE_CFIE8,Cancellation Finished Interrupt Enable 8. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 7. "MCAN_TXBCIE_CFIE7,Cancellation Finished Interrupt Enable 7. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 6. "MCAN_TXBCIE_CFIE6,Cancellation Finished Interrupt Enable 6. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 5. "MCAN_TXBCIE_CFIE5,Cancellation Finished Interrupt Enable 5. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 4. "MCAN_TXBCIE_CFIE4,Cancellation Finished Interrupt Enable 4. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 3. "MCAN_TXBCIE_CFIE3,Cancellation Finished Interrupt Enable 3. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 2. "MCAN_TXBCIE_CFIE2,Cancellation Finished Interrupt Enable 2. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 1. "MCAN_TXBCIE_CFIE1,Cancellation Finished Interrupt Enable 1. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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bitfld.long 0x4 0. "MCAN_TXBCIE_CFIE0,Cancellation Finished Interrupt Enable 0. Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit." "0,1"
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group.long 0x70F0++0x3
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line.long 0x0 "MCAN_TXEFC,MCAN Tx Event FIFO Configuration"
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hexmask.long.byte 0x0 24.--29. 1. "MCAN_TXEFC_EFWM,Event FIFO Watermark"
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hexmask.long.byte 0x0 16.--21. 1. "MCAN_TXEFC_EFS,Event FIFO Size. The Tx Event FIFO elements are indexed from 0 to EFS - 1."
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hexmask.long.word 0x0 2.--15. 1. "MCAN_TXEFC_EFSA,Event FIFO Start Address. Start address of Tx Event FIFO in Message RAM (32-bit word address)."
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rgroup.long 0x70F4++0x3
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line.long 0x0 "MCAN_TXEFS,MCAN Tx Event FIFO Status"
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bitfld.long 0x0 25. "MCAN_TXEFS_TEFL,Tx Event FIFO Element Lost. This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset this bit is also reset." "0,1"
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bitfld.long 0x0 24. "MCAN_TXEFS_EFF,Event FIFO Full" "0,1"
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hexmask.long.byte 0x0 16.--20. 1. "MCAN_TXEFS_EFPI,Event FIFO Put Index.Tx Event FIFO write index pointer range 0 to 31."
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hexmask.long.byte 0x0 8.--12. 1. "MCAN_TXEFS_EFGI,Event FIFO Get Index. Tx Event FIFO read index pointer range 0 to 31."
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hexmask.long.byte 0x0 0.--5. 1. "MCAN_TXEFS_EFFL,Event FIFO Fill Level. Number of elements stored in Tx Event FIFO range 0 to 32."
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group.long 0x70F8++0x3
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line.long 0x0 "MCAN_TXEFA,MCAN Tx Event FIFO Acknowledge"
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hexmask.long.byte 0x0 0.--4. 1. "MCAN_TXEFA_EFAI,Event FIFO Acknowledge Index. After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index.."
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rgroup.long 0x7200++0x3
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line.long 0x0 "MCANSS_PID,MCAN Subsystem Revision Register"
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bitfld.long 0x0 30.--31. "MCANSS_PID_SCHEME,PID Register Scheme" "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "MCANSS_PID_MODULE_ID,Module Identification Number"
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bitfld.long 0x0 8.--10. "MCANSS_PID_MAJOR,Major Revision of the MCAN Subsystem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 0.--5. 1. "MCANSS_PID_MINOR,Minor Revision of the MCAN Subsystem"
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group.long 0x7204++0x3
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line.long 0x0 "MCANSS_CTRL,MCAN Subsystem Control Register"
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bitfld.long 0x0 6. "MCANSS_CTRL_EXT_TS_CNTR_EN,External Timestamp Counter Enable." "0,1"
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bitfld.long 0x0 5. "MCANSS_CTRL_AUTOWAKEUP,Automatic Wakeup Enable. Enables the MCANSS to automatically clear the MCAN CCCR.INIT bit fully waking the MCAN up on an enabled wakeup request." "0,1"
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bitfld.long 0x0 4. "MCANSS_CTRL_WAKEUPREQEN,Wakeup Request Enable. Enables the MCANSS to wakeup on CAN RXD activity." "0,1"
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bitfld.long 0x0 3. "MCANSS_CTRL_DBGSUSP_FREE,Debug Suspend Free Bit. Enables debug suspend." "0,1"
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rgroup.long 0x7208++0x3
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line.long 0x0 "MCANSS_STAT,MCAN Subsystem Status Register"
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bitfld.long 0x0 2. "MCANSS_STAT_ENABLE_FDOE,Flexible Datarate Operation Enable. Determines whether CAN FD operation may be enabled via the MCAN core CCCR.FDOE bit (bit 8) or if only standard CAN operation is possible with this instance of the MCAN." "0,1"
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bitfld.long 0x0 1. "MCANSS_STAT_MEM_INIT_DONE,Memory Initialization Done." "0,1"
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bitfld.long 0x0 0. "MCANSS_STAT_RESET,Soft Reset Status." "0,1"
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group.long 0x720C++0xF
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line.long 0x0 "MCANSS_ICS,MCAN Subsystem Interrupt Clear Shadow Register"
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bitfld.long 0x0 0. "MCANSS_ICS_EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status Clear. Reads always return a 0." "0,1"
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line.long 0x4 "MCANSS_IRS,MCAN Subsystem Interrupt Raw Satus Register"
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bitfld.long 0x4 0. "MCANSS_IRS_EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Status. This bit is set by HW or by a SW write of '1'. To clear use the MCANSS_ICS.EXT_TS_CNTR_OVFL bit." "0,1"
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line.long 0x8 "MCANSS_IECS,MCAN Subsystem Interrupt Enable Clear Shadow Register"
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bitfld.long 0x8 0. "MCANSS_IECS_EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable Clear. Reads always return a 0." "0,1"
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line.long 0xC "MCANSS_IE,MCAN Subsystem Interrupt Enable Register"
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bitfld.long 0xC 0. "MCANSS_IE_EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable. A write of '0' has no effect. A write of '1' sets the MCANSS_IES.EXT_TS_CNTR_OVFL bit." "0,1"
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rgroup.long 0x721C++0x3
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line.long 0x0 "MCANSS_IES,MCAN Subsystem Interrupt Enable Status"
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bitfld.long 0x0 0. "MCANSS_IES_EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow Interrupt Enable Status. To set use the CANSS_IE.EXT_TS_CNTR_OVFL bit. To clear use the MCANSS_IECS.EXT_TS_CNTR_OVFL bit." "0,1"
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group.long 0x7220++0x7
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line.long 0x0 "MCANSS_EOI,MCAN Subsystem End of Interrupt"
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hexmask.long.byte 0x0 0.--7. 1. "MCANSS_EOI_EOI,End of Interrupt. A write to this register will clear the associated interrupt. If the unserviced interrupt counter is > 1 another interrupt is generated."
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line.long 0x4 "MCANSS_EXT_TS_PRESCALER,MCAN Subsystem External Timestamp Prescaler 0"
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hexmask.long.tbyte 0x4 0.--23. 1. "MCANSS_EXT_TS_PRESCALER_PRESCALER,External Timestamp Prescaler Reload Value. The external timestamp count rate is the host (system) clock rate divided by this value except in the case of 0. A zero value in this bit field will act identically to a value.."
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rgroup.long 0x7228++0x3
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line.long 0x0 "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR,MCAN Subsystem External Timestamp Unserviced Interrupts Counter"
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hexmask.long.byte 0x0 0.--4. 1. "MCANSS_EXT_TS_UNSERVICED_INTR_CNTR_EXT_TS_INTR_CNTR,External Timestamp Counter Unserviced Rollover Interrupts. If this value is > 1 an MCANSS_EOI write of '1' to bit 0 will issue another interrupt."
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rgroup.long 0x7400++0x3
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line.long 0x0 "MCANERR_REV,MCAN Error Aggregator Revision Register"
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bitfld.long 0x0 30.--31. "MCANERR_REV_SCHEME,PID Register Scheme" "0,1,2,3"
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hexmask.long.word 0x0 16.--27. 1. "MCANERR_REV_MODULE_ID,Module Identification Number"
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bitfld.long 0x0 8.--10. "MCANERR_REV_REVMAJ,Major Revision of the Error Aggregator" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 0.--5. 1. "MCANERR_REV_REVMIN,Minor Revision of the Error Aggregator"
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group.long 0x7408++0x3
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line.long 0x0 "MCANERR_VECTOR,MCAN ECC Vector Register"
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rbitfld.long 0x0 24. "MCANERR_VECTOR_RD_SVBUS_DONE,Read Completion Flag" "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "MCANERR_VECTOR_RD_SVBUS_ADDRESS,Read Address Offset"
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bitfld.long 0x0 15. "MCANERR_VECTOR_RD_SVBUS,Read Trigger" "0,1"
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hexmask.long.word 0x0 0.--10. 1. "MCANERR_VECTOR_ECC_VECTOR,ECC RAM ID. Each error detection and correction (EDC) controller has a bank of error registers (offsets 0x10 - 0x3B) associated with it. These registers are accessed via an internal serial bus (SVBUS). To access them through the.."
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rgroup.long 0x740C++0x7
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line.long 0x0 "MCANERR_STAT,MCAN Error Misc Status"
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hexmask.long.word 0x0 0.--10. 1. "MCANERR_STAT_NUM_RAMS,Number of RAMs. Number of ECC RAMs serviced by the aggregator."
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line.long 0x4 "MCANERR_WRAP_REV,MCAN ECC Wrapper Revision Register"
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bitfld.long 0x4 30.--31. "MCANERR_WRAP_REV_SCHEME,PID Register Scheme" "0,1,2,3"
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hexmask.long.word 0x4 16.--27. 1. "MCANERR_WRAP_REV_MODULE_ID,Module Identification Number"
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bitfld.long 0x4 8.--10. "MCANERR_WRAP_REV_REVMAJ,Major Revision of the Error Aggregator" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 0.--5. 1. "MCANERR_WRAP_REV_REVMIN,Minor Revision of the Error Aggregator"
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group.long 0x7414++0xF
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line.long 0x0 "MCANERR_CTRL,MCAN ECC Control"
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bitfld.long 0x0 8. "MCANERR_CTRL_CHECK_SVBUS_TIMEOUT,Enables Serial VBUS timeout mechanism" "0,1"
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bitfld.long 0x0 6. "MCANERR_CTRL_ERROR_ONCE,If this bit is set the FORCE_SEC/FORCE_DED will inject an error to the specified row only once. The FORCE_SEC bit will be cleared once a writeback happens. If writeback is not enabled this error will be cleared the cycle.." "0,1"
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bitfld.long 0x0 5. "MCANERR_CTRL_FORCE_N_ROW,Enable single/double-bit error on the next RAM read regardless of the MCANERR_ERR_CTRL1.ECC_ROW setting. For write through mode this applies to writes as well as reads." "0,1"
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bitfld.long 0x0 4. "MCANERR_CTRL_FORCE_DED,Force double-bit error. Cleared the cycle following the error if ERROR_ONCE is asserted. For write through mode this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be configured prior to setting.." "0,1"
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bitfld.long 0x0 3. "MCANERR_CTRL_FORCE_SEC,Force single-bit error. Cleared on a writeback or the cycle following the error if ERROR_ONCE is asserted. For write through mode this applies to writes as well as reads. MCANERR_ERR_CTRL1 and MCANERR_ERR_CTRL2 should be.." "0,1"
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bitfld.long 0x0 2. "MCANERR_CTRL_ENABLE_RMW,Enable read-modify-write on partial word writes" "0,1"
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bitfld.long 0x0 1. "MCANERR_CTRL_ECC_CHECK,Enable ECC Check. ECC is completely bypassed if both ECC_ENABLE and ECC_CHECK are '0'." "0,1"
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bitfld.long 0x0 0. "MCANERR_CTRL_ECC_ENABLE,Enable ECC Generation" "0,1"
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line.long 0x4 "MCANERR_ERR_CTRL1,MCAN ECC Error Control 1 Register"
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hexmask.long 0x4 0.--31. 1. "MCANERR_ERR_CTRL1_ECC_ROW,Row address where FORCE_SEC or FORCE_DED needs to be applied. This is ignored if FORCE_N_ROW is set."
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line.long 0x8 "MCANERR_ERR_CTRL2,MCAN ECC Error Control 2 Register"
|
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hexmask.long.word 0x8 16.--31. 1. "MCANERR_ERR_CTRL2_ECC_BIT2,Second column/data bit that needs to be flipped when FORCE_DED is set"
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hexmask.long.word 0x8 0.--15. 1. "MCANERR_ERR_CTRL2_ECC_BIT1,Column/Data bit that needs to be flipped when FORCE_SEC or FORCE_DED is set"
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line.long 0xC "MCANERR_ERR_STAT1,MCAN ECC Error Status 1 Register"
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hexmask.long.word 0xC 16.--31. 1. "MCANERR_ERR_STAT1_ECC_BIT1,ECC Error Bit Position. Indicates the bit position in the RAM data that is in error on an SEC error. Only valid on an SEC error."
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bitfld.long 0xC 15. "MCANERR_ERR_STAT1_CLR_CTRL_REG_ERROR,Writing a '1' clears the CTRL_REG_ERROR bit" "0,1"
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bitfld.long 0xC 12. "MCANERR_ERR_STAT1_CLR_ECC_OTHER,Writing a '1' clears the ECC_OTHER bit." "0,1"
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bitfld.long 0xC 10.--11. "MCANERR_ERR_STAT1_CLR_ECC_DED,Clear ECC_DED. A write of a non-zero value to this bit field decrements the ECC_DED bit field by the value provided." "0,1,2,3"
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bitfld.long 0xC 8.--9. "MCANERR_ERR_STAT1_CLR_ECC_SEC,Clear ECC_SEC. A write of a non-zero value to this bit field decrements the ECC_SEC bit field by the value provided." "0,1,2,3"
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bitfld.long 0xC 7. "MCANERR_ERR_STAT1_CTRL_REG_ERROR,Control Register Error. A bit field in the control register is in an ambiguous state. This means that the redundancy registers have detected a state where not all values are the same and has defaulted to the reset state." "0,1"
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bitfld.long 0xC 4. "MCANERR_ERR_STAT1_ECC_OTHER,SEC While Writeback Error Status" "0,1"
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bitfld.long 0xC 2.--3. "MCANERR_ERR_STAT1_ECC_DED,Double Bit Error Detected Status. A 2-bit saturating counter of the number of DED errors that have occurred since last cleared." "0,1,2,3"
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bitfld.long 0xC 0.--1. "MCANERR_ERR_STAT1_ECC_SEC,Single Bit Error Corrected Status. A 2-bit saturating counter of the number of SEC errors that have occurred since last cleared." "0,1,2,3"
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rgroup.long 0x7424++0x3
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line.long 0x0 "MCANERR_ERR_STAT2,MCAN ECC Error Status 2 Register"
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hexmask.long 0x0 0.--31. 1. "MCANERR_ERR_STAT2_ECC_ROW,Indicates the row address where the single or double-bit error occurred. This value is address offset/4."
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group.long 0x7428++0x3
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line.long 0x0 "MCANERR_ERR_STAT3,MCAN ECC Error Status 3 Register"
|
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bitfld.long 0x0 9. "MCANERR_ERR_STAT3_CLR_SVBUS_TIMEOUT,Write 1 to clear the Serial VBUS Timeout Flag" "0,1"
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|
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bitfld.long 0x0 1. "MCANERR_ERR_STAT3_SVBUS_TIMEOUT,Serial VBUS Timeout Flag. Write 1 to set." "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "MCANERR_ERR_STAT3_WB_PEND,Delayed Write Back Pending Status" "0,1"
|
|
group.long 0x743C++0x3
|
|
line.long 0x0 "MCANERR_SEC_EOI,MCAN Single Error Corrected End of Interrupt Register"
|
|
bitfld.long 0x0 0. "MCANERR_SEC_EOI_EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host." "0,1"
|
|
rgroup.long 0x7440++0x3
|
|
line.long 0x0 "MCANERR_SEC_STATUS,MCAN Single Error Corrected Interrupt Status Register"
|
|
bitfld.long 0x0 0. "MCANERR_SEC_STATUS_MSGMEM_PEND,Message RAM SEC Interrupt Pending" "0,1"
|
|
group.long 0x7480++0x3
|
|
line.long 0x0 "MCANERR_SEC_ENABLE_SET,MCAN Single Error Corrected Interrupt Enable Set Register"
|
|
bitfld.long 0x0 0. "MCANERR_SEC_ENABLE_SET_MSGMEM_ENABLE_SET,Message RAM SEC Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1"
|
|
group.long 0x74C0++0x3
|
|
line.long 0x0 "MCANERR_SEC_ENABLE_CLR,MCAN Single Error Corrected Interrupt Enable Clear Register"
|
|
bitfld.long 0x0 0. "MCANERR_SEC_ENABLE_CLR_MSGMEM_ENABLE_CLR,Message RAM SEC Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM SEC error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1"
|
|
group.long 0x753C++0x3
|
|
line.long 0x0 "MCANERR_DED_EOI,MCAN Double Error Detected End of Interrupt Register"
|
|
bitfld.long 0x0 0. "MCANERR_DED_EOI_EOI_WR,Write to this register indicates that software has acknowledged the pending interrupt and the next interrupt can be sent to the host." "0,1"
|
|
rgroup.long 0x7540++0x3
|
|
line.long 0x0 "MCANERR_DED_STATUS,MCAN Double Error Detected Interrupt Status Register"
|
|
bitfld.long 0x0 0. "MCANERR_DED_STATUS_MSGMEM_PEND,Message RAM DED Interrupt Pending" "0,1"
|
|
group.long 0x7580++0x3
|
|
line.long 0x0 "MCANERR_DED_ENABLE_SET,MCAN Double Error Detected Interrupt Enable Set Register"
|
|
bitfld.long 0x0 0. "MCANERR_DED_ENABLE_SET_MSGMEM_ENABLE_SET,Message RAM DED Interrupt Pending Enable Set. Writing a 1 to this bit enables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1"
|
|
group.long 0x75C0++0x3
|
|
line.long 0x0 "MCANERR_DED_ENABLE_CLR,MCAN Double Error Detected Interrupt Enable Clear Register"
|
|
bitfld.long 0x0 0. "MCANERR_DED_ENABLE_CLR_MSGMEM_ENABLE_CLR,Message RAM DED Interrupt Pending Enable Clear. Writing a 1 to this bit disables the Message RAM DED error interrupts. Writing a 0 has no effect. Reads return the corresponding enable bit's current value." "0,1"
|
|
group.long 0x7600++0xF
|
|
line.long 0x0 "MCANERR_AGGR_ENABLE_SET,MCAN Error Aggregator Enable Set Register"
|
|
bitfld.long 0x0 1. "MCANERR_AGGR_ENABLE_SET_ENABLE_TIMEOUT_SET,Write 1 to enable timeout errors. Reads return the corresponding enable bit's current value." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MCANERR_AGGR_ENABLE_SET_ENABLE_PARITY_SET,Write 1 to enable parity errors. Reads return the corresponding enable bit's current value." "0,1"
|
|
line.long 0x4 "MCANERR_AGGR_ENABLE_CLR,MCAN Error Aggregator Enable Clear Register"
|
|
bitfld.long 0x4 1. "MCANERR_AGGR_ENABLE_CLR_ENABLE_TIMEOUT_CLR,Write 1 to disable timeout errors. Reads return the corresponding enable bit's current value." "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "MCANERR_AGGR_ENABLE_CLR_ENABLE_PARITY_CLR,Write 1 to disable parity errors. Reads return the corresponding enable bit's current value." "0,1"
|
|
line.long 0x8 "MCANERR_AGGR_STATUS_SET,MCAN Error Aggregator Status Set Register"
|
|
bitfld.long 0x8 2.--3. "MCANERR_AGGR_STATUS_SET_SVBUS_TIMEOUT,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "MCANERR_AGGR_STATUS_SET_AGGR_PARITY_ERR,Aggregator Parity Error Status" "0,1,2,3"
|
|
line.long 0xC "MCANERR_AGGR_STATUS_CLR,MCAN Error Aggregator Status Clear Register"
|
|
bitfld.long 0xC 2.--3. "MCANERR_AGGR_STATUS_CLR_SVBUS_TIMEOUT,Aggregator Serial VBUS Timeout Error Status" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "MCANERR_AGGR_STATUS_CLR_AGGR_PARITY_ERR,Aggregator Parity Error Status" "0,1,2,3"
|
|
rgroup.long 0x7820++0x3
|
|
line.long 0x0 "IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x7828++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 5. "IMASK_WAKEUP,Clock Stop Wake Up interrupt mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow interrupt mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "IMASK_DED,Massage RAM DED interrupt mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "IMASK_SEC,Message RAM SEC interrupt mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "IMASK_INTL1,MCAN Interrupt Line 1 mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_INTL0,MCAN Interrupt Line 0 mask." "0: CLR,1: SET"
|
|
rgroup.long 0x7830++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 5. "RIS_WAKEUP,Clock Stop Wake Up interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_EXT_TS_CNTR_OVFL,External Timestamp Counter Overflow interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "RIS_DED,Message RAM DED interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "RIS_SEC,Message RAM SEC interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "RIS_INTL1,MCAN Interrupt Line 1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_INTL0,MCAN Interrupt Line 0." "0: CLR,1: SET"
|
|
rgroup.long 0x7838++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 5. "MIS_WAKEUP,Masked Clock Stop Wake Up interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_EXT_TS_CNTR_OVFL,Masked External Timestamp Counter Overflow interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "MIS_DED,Masked Message RAM DED interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "MIS_SEC,Masked Message RAM SEC interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS_INTL1,Masked MCAN Interrupt Line 1." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_INTL0,Masked MCAN Interrupt Line 0." "0: CLR,1: SET"
|
|
wgroup.long 0x7840++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 5. "ISET_WAKEUP,Set Clock Stop Wake Up interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_EXT_TS_CNTR_OVFL,Set External Timestamp Counter Overflow interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "ISET_DED,Set Message RAM DED interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "ISET_SEC,Set Message RAM SEC interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_INTL1,Set MCAN Interrupt Line 1." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_INTL0,Set MCAN Interrupt Line 0." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x7848++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 5. "ICLR_WAKEUP,Clear Clock Stop Wake Up interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_EXT_TS_CNTR_OVFL,Clear External Timestamp Counter Overflow interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "ICLR_DED,Clear Message RAM DED interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "ICLR_SEC,Clear Message RAM SEC interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_INTL1,Clear MCAN Interrupt Line 1." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_INTL0,Clear MCAN Interrupt Line 0." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x78E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x78FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x7900++0xB
|
|
line.long 0x0 "MCANSS_CLKEN,MCAN module clock enable"
|
|
bitfld.long 0x0 0. "MCANSS_CLKEN_CLK_REQEN,MCAN functional and MCAN/MCANSS MMR clock request enable bit" "0: CLR,1: SET"
|
|
line.long 0x4 "MCANSS_CLKDIV,Clock divider"
|
|
bitfld.long 0x4 0.--1. "MCANSS_CLKDIV_RATIO,Clock divide ratio specification. Enables configuring clock divide settings for the MCAN functional clock input to the MCAN-SS." "0: DIV_BY_1_,1: DIV_BY_2_,2: DIV_BY_4_,?"
|
|
line.long 0x8 "MCANSS_CLKCTL,MCAN-SS clock stop control register"
|
|
bitfld.long 0x8 8. "MCANSS_CLKCTL_WKUP_GLTFLT_EN,Setting this bit enables the glitch filter on MCAN RXD input which wakes up the MCAN controller to exit clock gating." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "MCANSS_CLKCTL_WAKEUP_INT_EN,This bit contols enabling or disabling the MCAN IP clock stop wakeup interrupt (when MCANSS_CTRL.WAKEUPREQEN wakeup request is enabled to wakeup MCAN IP upon CAN RXD activity)" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 0. "MCANSS_CLKCTL_STOPREQ,This bit is used to enable/disable MCAN clock (both host clock and functional clock) gating request." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x790C++0x3
|
|
line.long 0x0 "MCANSS_CLKSTS,MCANSS clock stop status register"
|
|
bitfld.long 0x0 8. "MCANSS_CLKSTS_CCLKDONE,This bit indicates the status of MCAN contoller clock request from GPRCM." "0: RESET,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MCANSS_CLKSTS_STOPREQ_HW_OVR,MCANSS clock stop HW override status bit." "0: RESET,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MCANSS_CLKSTS_CLKSTOP_ACKSTS,Clock stop acknowledge status from MCAN IP" "0: RESET,1: SET"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*")||cpuis("MSPM0L122*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*")||cpuis("MSPM0L222*"))
|
|
tree "COMP (Comparator)"
|
|
base ad:0x0
|
|
sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*"))
|
|
tree "COMP0"
|
|
base ad:0x40008000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subscriber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher port 1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
bitfld.long 0x0 0.--1. "IIDX_STAT,Interrupt index status" "0: NO_INTR,1: OUTRDYIFG,2: COMPIFG,3: COMPINVIFG"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "IMASK_OUTRDYIFG,Masks OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "IMASK_COMPINVIFG,Masks COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_COMPIFG,Masks COMPIFG" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "RIS_OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "MIS_OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_COMPIFG,Masked interrupt status for COMPIFG" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "ISET_OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_COMPINVIFG,Sets COMPINVIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_COMPIFG,Sets COMPIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "ICLR_OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_COMPINVIFG,Clears COMPINVIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_COMPIFG,Clears COMPIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,Control 0"
|
|
bitfld.long 0x0 31. "CTL0_IMEN,Channel input enable for the negative terminal of the comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 16.--18. "CTL0_IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: CH_0,1: CH_1,2: CH_2,3: CH_3,4: CH_4,5: CH_5,6: CH_6,7: CH_7"
|
|
bitfld.long 0x0 15. "CTL0_IPEN,Channel input enable for the positive terminal of the comparator." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CTL0_IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: CH_0,1: CH_1,2: CH_2,3: CH_3,4: CH_4,5: CH_5,6: CH_6,7: CH_7"
|
|
line.long 0x4 "CTL1,Control 1"
|
|
bitfld.long 0x4 12. "CTL1_WINCOMPEN,This bit enables window comparator operation of comparator." "0: OFF,1: ON"
|
|
bitfld.long 0x4 9.--10. "CTL1_FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: DLY_0,1: DLY_1,2: DLY_2,3: DLY_3"
|
|
bitfld.long 0x4 8. "CTL1_FLTEN,This bit enables the analog filter at comparator output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 7. "CTL1_OUTPOL,This bit selects the comparator output polarity." "0: NON_INV,1: INV"
|
|
bitfld.long 0x4 5.--6. "CTL1_HYST,These bits select the hysteresis setting of the comparator." "0: NO_HYS,1: LOW_HYS,2: MED_HYS,3: HIGH_HYS"
|
|
bitfld.long 0x4 4. "CTL1_IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: RISING,1: FALLING"
|
|
newline
|
|
bitfld.long 0x4 3. "CTL1_SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: NO_SHT,1: SHT"
|
|
bitfld.long 0x4 2. "CTL1_EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: NO_EXC,1: EXC"
|
|
bitfld.long 0x4 1. "CTL1_MODE,This bit selects the comparator operating mode." "0: FAST,1: ULP"
|
|
newline
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: OFF,1: ON"
|
|
line.long 0x8 "CTL2,Control 2"
|
|
bitfld.long 0x8 24. "CTL2_SAMPMODE,Enable sampled mode of comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 17. "CTL2_DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0_SEL,1: DACCODE1_SEL"
|
|
bitfld.long 0x8 16. "CTL2_DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: COMPOUT_SEL,1: DACSW_SEL"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "CTL2_BLANKSRC,These bits select the blanking source for the comparator." "0: DISABLE,1: BLANKSRC1,2: BLANKSRC2,3: BLANKSRC3,4: BLANKSRC4,5: BLANKSRC5,6: BLANKSRC6,?"
|
|
bitfld.long 0x8 7. "CTL2_REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: POSITIVE,1: NEGATIVE"
|
|
bitfld.long 0x8 3.--4. "CTL2_REFSRC,These bits select the reference source for the comparator." "0: OFF,1: VDDA_DAC,2: VREF_DAC,3: VREF"
|
|
newline
|
|
bitfld.long 0x8 0. "CTL2_REFMODE,This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: STATIC,1: SAMPLED"
|
|
line.long 0xC "CTL3,Control 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CTL3_DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."
|
|
hexmask.long.byte 0xC 0.--7. 1. "CTL3_DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."
|
|
rgroup.long 0x1120++0x3
|
|
line.long 0x0 "STAT,Status"
|
|
bitfld.long 0x0 0. "STAT_OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: LOW,1: HIGH"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*"))
|
|
tree "COMP1"
|
|
base ad:0x4000A000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subscriber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher port 1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
bitfld.long 0x0 0.--1. "IIDX_STAT,Interrupt index status" "0: NO_INTR,1: OUTRDYIFG,2: COMPIFG,3: COMPINVIFG"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "IMASK_OUTRDYIFG,Masks OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "IMASK_COMPINVIFG,Masks COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_COMPIFG,Masks COMPIFG" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "RIS_OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "MIS_OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_COMPIFG,Masked interrupt status for COMPIFG" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "ISET_OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_COMPINVIFG,Sets COMPINVIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_COMPIFG,Sets COMPIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "ICLR_OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_COMPINVIFG,Clears COMPINVIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_COMPIFG,Clears COMPIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,Control 0"
|
|
bitfld.long 0x0 31. "CTL0_IMEN,Channel input enable for the negative terminal of the comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 16.--18. "CTL0_IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: CH_0,1: CH_1,2: CH_2,3: CH_3,4: CH_4,5: CH_5,6: CH_6,7: CH_7"
|
|
bitfld.long 0x0 15. "CTL0_IPEN,Channel input enable for the positive terminal of the comparator." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CTL0_IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: CH_0,1: CH_1,2: CH_2,3: CH_3,4: CH_4,5: CH_5,6: CH_6,7: CH_7"
|
|
line.long 0x4 "CTL1,Control 1"
|
|
bitfld.long 0x4 12. "CTL1_WINCOMPEN,This bit enables window comparator operation of comparator." "0: OFF,1: ON"
|
|
bitfld.long 0x4 9.--10. "CTL1_FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: DLY_0,1: DLY_1,2: DLY_2,3: DLY_3"
|
|
bitfld.long 0x4 8. "CTL1_FLTEN,This bit enables the analog filter at comparator output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 7. "CTL1_OUTPOL,This bit selects the comparator output polarity." "0: NON_INV,1: INV"
|
|
bitfld.long 0x4 5.--6. "CTL1_HYST,These bits select the hysteresis setting of the comparator." "0: NO_HYS,1: LOW_HYS,2: MED_HYS,3: HIGH_HYS"
|
|
bitfld.long 0x4 4. "CTL1_IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: RISING,1: FALLING"
|
|
newline
|
|
bitfld.long 0x4 3. "CTL1_SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: NO_SHT,1: SHT"
|
|
bitfld.long 0x4 2. "CTL1_EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: NO_EXC,1: EXC"
|
|
bitfld.long 0x4 1. "CTL1_MODE,This bit selects the comparator operating mode." "0: FAST,1: ULP"
|
|
newline
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: OFF,1: ON"
|
|
line.long 0x8 "CTL2,Control 2"
|
|
bitfld.long 0x8 24. "CTL2_SAMPMODE,Enable sampled mode of comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 17. "CTL2_DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0_SEL,1: DACCODE1_SEL"
|
|
bitfld.long 0x8 16. "CTL2_DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: COMPOUT_SEL,1: DACSW_SEL"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "CTL2_BLANKSRC,These bits select the blanking source for the comparator." "0: DISABLE,1: BLANKSRC1,2: BLANKSRC2,3: BLANKSRC3,4: BLANKSRC4,5: BLANKSRC5,6: BLANKSRC6,?"
|
|
bitfld.long 0x8 7. "CTL2_REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: POSITIVE,1: NEGATIVE"
|
|
bitfld.long 0x8 3.--4. "CTL2_REFSRC,These bits select the reference source for the comparator." "0: OFF,1: VDDA_DAC,2: VREF_DAC,3: VREF"
|
|
newline
|
|
bitfld.long 0x8 0. "CTL2_REFMODE,This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: STATIC,1: SAMPLED"
|
|
line.long 0xC "CTL3,Control 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CTL3_DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."
|
|
hexmask.long.byte 0xC 0.--7. 1. "CTL3_DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."
|
|
rgroup.long 0x1120++0x3
|
|
line.long 0x0 "STAT,Status"
|
|
bitfld.long 0x0 0. "STAT_OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: LOW,1: HIGH"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*"))
|
|
tree "COMP2"
|
|
base ad:0x4000C000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subscriber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher port 1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
bitfld.long 0x0 0.--1. "IIDX_STAT,Interrupt index status" "0: NO_INTR,1: OUTRDYIFG,2: COMPIFG,3: COMPINVIFG"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "IMASK_OUTRDYIFG,Masks OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "IMASK_COMPINVIFG,Masks COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_COMPIFG,Masks COMPIFG" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "RIS_OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "MIS_OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_COMPIFG,Masked interrupt status for COMPIFG" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "ISET_OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_COMPINVIFG,Sets COMPINVIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_COMPIFG,Sets COMPIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "ICLR_OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_COMPINVIFG,Clears COMPINVIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_COMPIFG,Clears COMPIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,Control 0"
|
|
bitfld.long 0x0 31. "CTL0_IMEN,Channel input enable for the negative terminal of the comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 16.--18. "CTL0_IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: CH_0,1: CH_1,2: CH_2,3: CH_3,4: CH_4,5: CH_5,6: CH_6,7: CH_7"
|
|
bitfld.long 0x0 15. "CTL0_IPEN,Channel input enable for the positive terminal of the comparator." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CTL0_IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: CH_0,1: CH_1,2: CH_2,3: CH_3,4: CH_4,5: CH_5,6: CH_6,7: CH_7"
|
|
line.long 0x4 "CTL1,Control 1"
|
|
bitfld.long 0x4 12. "CTL1_WINCOMPEN,This bit enables window comparator operation of comparator." "0: OFF,1: ON"
|
|
bitfld.long 0x4 9.--10. "CTL1_FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: DLY_0,1: DLY_1,2: DLY_2,3: DLY_3"
|
|
bitfld.long 0x4 8. "CTL1_FLTEN,This bit enables the analog filter at comparator output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 7. "CTL1_OUTPOL,This bit selects the comparator output polarity." "0: NON_INV,1: INV"
|
|
bitfld.long 0x4 5.--6. "CTL1_HYST,These bits select the hysteresis setting of the comparator." "0: NO_HYS,1: LOW_HYS,2: MED_HYS,3: HIGH_HYS"
|
|
bitfld.long 0x4 4. "CTL1_IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: RISING,1: FALLING"
|
|
newline
|
|
bitfld.long 0x4 3. "CTL1_SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: NO_SHT,1: SHT"
|
|
bitfld.long 0x4 2. "CTL1_EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: NO_EXC,1: EXC"
|
|
bitfld.long 0x4 1. "CTL1_MODE,This bit selects the comparator operating mode." "0: FAST,1: ULP"
|
|
newline
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: OFF,1: ON"
|
|
line.long 0x8 "CTL2,Control 2"
|
|
bitfld.long 0x8 24. "CTL2_SAMPMODE,Enable sampled mode of comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 17. "CTL2_DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0_SEL,1: DACCODE1_SEL"
|
|
bitfld.long 0x8 16. "CTL2_DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: COMPOUT_SEL,1: DACSW_SEL"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "CTL2_BLANKSRC,These bits select the blanking source for the comparator." "0: DISABLE,1: BLANKSRC1,2: BLANKSRC2,3: BLANKSRC3,4: BLANKSRC4,5: BLANKSRC5,6: BLANKSRC6,?"
|
|
bitfld.long 0x8 7. "CTL2_REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: POSITIVE,1: NEGATIVE"
|
|
bitfld.long 0x8 3.--4. "CTL2_REFSRC,These bits select the reference source for the comparator." "0: OFF,1: VDDA_DAC,2: VREF_DAC,3: VREF"
|
|
newline
|
|
bitfld.long 0x8 0. "CTL2_REFMODE,This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: STATIC,1: SAMPLED"
|
|
line.long 0xC "CTL3,Control 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CTL3_DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."
|
|
hexmask.long.byte 0xC 0.--7. 1. "CTL3_DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."
|
|
rgroup.long 0x1120++0x3
|
|
line.long 0x0 "STAT,Status"
|
|
bitfld.long 0x0 0. "STAT_OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: LOW,1: HIGH"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "COMP0"
|
|
base ad:0x40008000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subscriber Port 0"
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher port 1"
|
|
bitfld.long 0x0 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
bitfld.long 0x0 0.--1. "IIDX_STAT,Interrupt index status" "0: NO_INTR,1: OUTRDYIFG,2: COMPIFG,3: COMPINVIFG"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "IMASK_OUTRDYIFG,Masks OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "IMASK_COMPINVIFG,Masks COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_COMPIFG,Masks COMPIFG" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "RIS_OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "MIS_OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_COMPIFG,Masked interrupt status for COMPIFG" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "ISET_OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_COMPINVIFG,Sets COMPINVIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_COMPIFG,Sets COMPIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "ICLR_OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_COMPINVIFG,Clears COMPINVIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_COMPIFG,Clears COMPIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,Control 0"
|
|
bitfld.long 0x0 31. "CTL0_IMEN,Channel input enable for the negative terminal of the comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 16.--18. "CTL0_IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: CH_0,1: CH_1,2: CH_2,3: CH_3,4: CH_4,5: CH_5,6: CH_6,7: CH_7"
|
|
bitfld.long 0x0 15. "CTL0_IPEN,Channel input enable for the positive terminal of the comparator." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CTL0_IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: CH_0,1: CH_1,2: CH_2,3: CH_3,4: CH_4,5: CH_5,6: CH_6,7: CH_7"
|
|
line.long 0x4 "CTL1,Control 1"
|
|
bitfld.long 0x4 12. "CTL1_WINCOMPEN,This bit enables window comparator operation of comparator." "0: OFF,1: ON"
|
|
bitfld.long 0x4 9.--10. "CTL1_FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: DLY_0,1: DLY_1,2: DLY_2,3: DLY_3"
|
|
bitfld.long 0x4 8. "CTL1_FLTEN,This bit enables the analog filter at comparator output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 7. "CTL1_OUTPOL,This bit selects the comparator output polarity." "0: NON_INV,1: INV"
|
|
bitfld.long 0x4 5.--6. "CTL1_HYST,These bits select the hysteresis setting of the comparator." "0: NO_HYS,1: LOW_HYS,2: MED_HYS,3: HIGH_HYS"
|
|
bitfld.long 0x4 4. "CTL1_IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: RISING,1: FALLING"
|
|
newline
|
|
bitfld.long 0x4 3. "CTL1_SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: NO_SHT,1: SHT"
|
|
bitfld.long 0x4 2. "CTL1_EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: NO_EXC,1: EXC"
|
|
bitfld.long 0x4 1. "CTL1_MODE,This bit selects the comparator operating mode." "0: FAST,1: ULP"
|
|
newline
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: OFF,1: ON"
|
|
line.long 0x8 "CTL2,Control 2"
|
|
bitfld.long 0x8 24. "CTL2_SAMPMODE,Enable sampled mode of comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 17. "CTL2_DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0_SEL,1: DACCODE1_SEL"
|
|
bitfld.long 0x8 16. "CTL2_DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: COMPOUT_SEL,1: DACSW_SEL"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "CTL2_BLANKSRC,These bits select the blanking source for the comparator." "0: DISABLE,1: BLANKSRC1,2: BLANKSRC2,3: BLANKSRC3,4: BLANKSRC4,5: BLANKSRC5,6: BLANKSRC6,?"
|
|
bitfld.long 0x8 7. "CTL2_REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: POSITIVE,1: NEGATIVE"
|
|
bitfld.long 0x8 3.--4. "CTL2_REFSRC,These bits select the reference source for the comparator." "0: OFF,1: VDDA_DAC,2: VREF_DAC,3: VREF"
|
|
newline
|
|
bitfld.long 0x8 0. "CTL2_REFMODE,This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: STATIC,1: SAMPLED"
|
|
line.long 0xC "CTL3,Control 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CTL3_DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."
|
|
hexmask.long.byte 0xC 0.--7. 1. "CTL3_DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."
|
|
rgroup.long 0x1120++0x3
|
|
line.long 0x0 "STAT,Status"
|
|
bitfld.long 0x0 0. "STAT_OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: LOW,1: HIGH"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "COMP0"
|
|
base ad:0x40008000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subscriber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher port 1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "CPU_INT_IIDX,Interrupt index"
|
|
bitfld.long 0x0 0.--1. "CPU_INT_IIDX_STAT,Interrupt index status" "0: NO_INTR,?,2: COMPIFG,3: COMPINVIFG"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "CPU_INT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "CPU_INT_IMASK_OUTRDYIFG,Masks OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_IMASK_COMPINVIFG,Masks COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "CPU_INT_IMASK_COMPIFG,Masks COMPIFG" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "CPU_INT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "CPU_INT_RIS_OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_RIS_COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "CPU_INT_RIS_COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "CPU_INT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "CPU_INT_MIS_OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_MIS_COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "CPU_INT_MIS_COMPIFG,Masked interrupt status for COMPIFG" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "CPU_INT_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "CPU_INT_ISET_OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_ISET_COMPINVIFG,Sets COMPINVIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "CPU_INT_ISET_COMPIFG,Sets COMPIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "CPU_INT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "CPU_INT_ICLR_OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "CPU_INT_ICLR_COMPINVIFG,Clears COMPINVIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "CPU_INT_ICLR_COMPIFG,Clears COMPIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "GEN_EVENT_IIDX,Interrupt index"
|
|
bitfld.long 0x0 0.--1. "GEN_EVENT_IIDX_STAT,Interrupt index status" "0: NO_INTR,?,2: COMPIFG,3: COMPINVIFG"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "GEN_EVENT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "GEN_EVENT_IMASK_OUTRDYIFG,Masks OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_IMASK_COMPINVIFG,Masks COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT_IMASK_COMPIFG,Masks COMPIFG" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "GEN_EVENT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "GEN_EVENT_RIS_OUTRDYIFG,Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_RIS_COMPINVIFG,Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT_RIS_COMPIFG,Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "GEN_EVENT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "GEN_EVENT_MIS_OUTRDYIFG,Masked interrupt status for OUTRDYIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_MIS_COMPINVIFG,Masked interrupt status for COMPINVIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT_MIS_COMPIFG,Masked interrupt status for COMPIFG" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "GEN_EVENT_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "GEN_EVENT_ISET_OUTRDYIFG,Sets OUTRDYIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_ISET_COMPINVIFG,Sets COMPINVIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT_ISET_COMPIFG,Sets COMPIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "GEN_EVENT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "GEN_EVENT_ICLR_OUTRDYIFG,Clears OUTRDYIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "GEN_EVENT_ICLR_COMPINVIFG,Clears COMPINVIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "GEN_EVENT_ICLR_COMPIFG,Clears COMPIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to GEN_EVENT" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to CPU_INT" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,Control 0"
|
|
bitfld.long 0x0 31. "CTL0_IMEN,Channel input enable for the negative terminal of the comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 16.--18. "CTL0_IMSEL,Channel input selected for the negative terminal of the comparator if IMEN is set to 1." "0: CH_0,1: CH_1,2: CH_2,3: CH_3,4: CH_4,5: CH_5,6: CH_6,7: CH_7"
|
|
bitfld.long 0x0 15. "CTL0_IPEN,Channel input enable for the positive terminal of the comparator." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CTL0_IPSEL,Channel input selected for the positive terminal of the comparator if IPEN is set to 1." "0: CH_0,1: CH_1,2: CH_2,3: CH_3,4: CH_4,5: CH_5,6: CH_6,7: CH_7"
|
|
line.long 0x4 "CTL1,Control 1"
|
|
bitfld.long 0x4 12. "CTL1_WINCOMPEN,This bit enables window comparator operation of comparator." "0: OFF,1: ON"
|
|
bitfld.long 0x4 9.--10. "CTL1_FLTDLY,These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings." "0: DLY_0,1: DLY_1,2: DLY_2,3: DLY_3"
|
|
bitfld.long 0x4 8. "CTL1_FLTEN,This bit enables the analog filter at comparator output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 7. "CTL1_OUTPOL,This bit selects the comparator output polarity." "0: NON_INV,1: INV"
|
|
bitfld.long 0x4 5.--6. "CTL1_HYST,These bits select the hysteresis setting of the comparator." "0: NO_HYS,1: LOW_HYS,2: MED_HYS,3: HIGH_HYS"
|
|
bitfld.long 0x4 4. "CTL1_IES,This bit selected the interrupt edge for COMPIFG and COMPINVIFG." "0: RISING,1: FALLING"
|
|
newline
|
|
bitfld.long 0x4 3. "CTL1_SHORT,This bit shorts the positive and negative input terminals of the comparator." "0: NO_SHT,1: SHT"
|
|
bitfld.long 0x4 2. "CTL1_EXCH,This bit exchanges the comparator inputs and inverts the comparator output." "0: NO_EXC,1: EXC"
|
|
bitfld.long 0x4 1. "CTL1_MODE,This bit selects the comparator operating mode." "0: FAST,1: ULP"
|
|
newline
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,This bit turns on the comparator. When the comparator is turned off it consumes no power." "0: OFF,1: ON"
|
|
line.long 0x8 "CTL2,Control 2"
|
|
bitfld.long 0x8 24. "CTL2_SAMPMODE,Enable sampled mode of comparator." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 17. "CTL2_DACSW,This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1." "0: DACCODE0_SEL,1: DACCODE1_SEL"
|
|
bitfld.long 0x8 16. "CTL2_DACCTL,This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1." "0: COMPOUT_SEL,1: DACSW_SEL"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "CTL2_BLANKSRC,These bits select the blanking source for the comparator." "0: DISABLE,1: BLANKSRC1,2: BLANKSRC2,3: BLANKSRC3,4: BLANKSRC4,5: BLANKSRC5,6: BLANKSRC6,?"
|
|
bitfld.long 0x8 7. "CTL2_REFSEL,This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator." "0: POSITIVE,1: NEGATIVE"
|
|
bitfld.long 0x8 3.--5. "CTL2_REFSRC,These bits select the reference source for the comparator." "0: OFF,1: VDDA_DAC,2: VREF_DAC,3: VREF,?,5: VDDA,6: INTVREF_DAC,7: INTVREF"
|
|
newline
|
|
bitfld.long 0x8 0. "CTL2_REFMODE,This bit requests ULP_REF bandgap operation in fast mode(static) or low power mode (sampled). The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly." "0: STATIC,1: SAMPLED"
|
|
line.long 0xC "CTL3,Control 3"
|
|
hexmask.long.byte 0xC 16.--23. 1. "CTL3_DACCODE1,This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."
|
|
hexmask.long.byte 0xC 0.--7. 1. "CTL3_DACCODE0,This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."
|
|
rgroup.long 0x1120++0x3
|
|
line.long 0x0 "STAT,Status"
|
|
bitfld.long 0x0 0. "STAT_OUT,This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output." "0: LOW,1: HIGH"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "CPUSS (CPU Subsystem)"
|
|
base ad:0x40400000
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT_CFG,Event line mode select" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
rgroup.long 0x1100++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RIS_INT,Raw interrupt status for INT"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MIS_INT,Masked interrupt status for INT0"
|
|
wgroup.long 0x1120++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ISET_INT,Sets INT in RIS register"
|
|
wgroup.long 0x1128++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ICLR_INT,Clears INT in RIS register"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
rgroup.long 0x1100++0x3
|
|
line.long 0x0 "INT_GROUP0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "INT_GROUP0_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "INT_GROUP0_RIS,Raw interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_RIS_INT,Raw interrupt status for INT"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "INT_GROUP0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP0_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1120++0x3
|
|
line.long 0x0 "INT_GROUP0_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1128++0x3
|
|
line.long 0x0 "INT_GROUP0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "INT_GROUP1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1138++0x3
|
|
line.long 0x0 "INT_GROUP1_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1140++0x3
|
|
line.long 0x0 "INT_GROUP1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_RIS_INT,Raw interrupt status for INT" "0: CLR,1: SET"
|
|
rgroup.long 0x1148++0x3
|
|
line.long 0x0 "INT_GROUP1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1150++0x3
|
|
line.long 0x0 "INT_GROUP1_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1158++0x3
|
|
line.long 0x0 "INT_GROUP1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rgroup.long 0x1100++0x3
|
|
line.long 0x0 "INT_GROUP0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "INT_GROUP0_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "INT_GROUP0_RIS,Raw interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_RIS_INT,Raw interrupt status for INT"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "INT_GROUP0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP0_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1120++0x3
|
|
line.long 0x0 "INT_GROUP0_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1128++0x3
|
|
line.long 0x0 "INT_GROUP0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "INT_GROUP1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1138++0x3
|
|
line.long 0x0 "INT_GROUP1_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1140++0x3
|
|
line.long 0x0 "INT_GROUP1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_RIS_INT,Raw interrupt status for INT" "0: CLR,1: SET"
|
|
rgroup.long 0x1148++0x3
|
|
line.long 0x0 "INT_GROUP1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1150++0x3
|
|
line.long 0x0 "INT_GROUP1_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1158++0x3
|
|
line.long 0x0 "INT_GROUP1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rgroup.long 0x1100++0x3
|
|
line.long 0x0 "INT_GROUP0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "INT_GROUP0_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "INT_GROUP0_RIS,Raw interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_RIS_INT,Raw interrupt status for INT"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "INT_GROUP0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP0_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1120++0x3
|
|
line.long 0x0 "INT_GROUP0_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1128++0x3
|
|
line.long 0x0 "INT_GROUP0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "INT_GROUP1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1138++0x3
|
|
line.long 0x0 "INT_GROUP1_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1140++0x3
|
|
line.long 0x0 "INT_GROUP1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_RIS_INT,Raw interrupt status for INT" "0: CLR,1: SET"
|
|
rgroup.long 0x1148++0x3
|
|
line.long 0x0 "INT_GROUP1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1150++0x3
|
|
line.long 0x0 "INT_GROUP1_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1158++0x3
|
|
line.long 0x0 "INT_GROUP1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rgroup.long 0x1100++0x3
|
|
line.long 0x0 "INT_GROUP0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "INT_GROUP0_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "INT_GROUP0_RIS,Raw interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_RIS_INT,Raw interrupt status for INT"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "INT_GROUP0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP0_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1120++0x3
|
|
line.long 0x0 "INT_GROUP0_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1128++0x3
|
|
line.long 0x0 "INT_GROUP0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "INT_GROUP1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1138++0x3
|
|
line.long 0x0 "INT_GROUP1_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1140++0x3
|
|
line.long 0x0 "INT_GROUP1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_RIS_INT,Raw interrupt status for INT" "0: CLR,1: SET"
|
|
rgroup.long 0x1148++0x3
|
|
line.long 0x0 "INT_GROUP1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1150++0x3
|
|
line.long 0x0 "INT_GROUP1_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1158++0x3
|
|
line.long 0x0 "INT_GROUP1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
rgroup.long 0x1100++0x3
|
|
line.long 0x0 "INT_GROUP0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "INT_GROUP0_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "INT_GROUP0_RIS,Raw interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_RIS_INT,Raw interrupt status for INT"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "INT_GROUP0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP0_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1120++0x3
|
|
line.long 0x0 "INT_GROUP0_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1128++0x3
|
|
line.long 0x0 "INT_GROUP0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "INT_GROUP1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1138++0x3
|
|
line.long 0x0 "INT_GROUP1_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1140++0x3
|
|
line.long 0x0 "INT_GROUP1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_RIS_INT,Raw interrupt status for INT" "0: CLR,1: SET"
|
|
rgroup.long 0x1148++0x3
|
|
line.long 0x0 "INT_GROUP1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1150++0x3
|
|
line.long 0x0 "INT_GROUP1_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1158++0x3
|
|
line.long 0x0 "INT_GROUP1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
rgroup.long 0x1100++0x3
|
|
line.long 0x0 "INT_GROUP0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "INT_GROUP0_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "INT_GROUP0_RIS,Raw interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_RIS_INT,Raw interrupt status for INT"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "INT_GROUP0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP0_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1120++0x3
|
|
line.long 0x0 "INT_GROUP0_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1128++0x3
|
|
line.long 0x0 "INT_GROUP0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "INT_GROUP1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1138++0x3
|
|
line.long 0x0 "INT_GROUP1_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1140++0x3
|
|
line.long 0x0 "INT_GROUP1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_RIS_INT,Raw interrupt status for INT" "0: CLR,1: SET"
|
|
rgroup.long 0x1148++0x3
|
|
line.long 0x0 "INT_GROUP1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1150++0x3
|
|
line.long 0x0 "INT_GROUP1_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1158++0x3
|
|
line.long 0x0 "INT_GROUP1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
rgroup.long 0x1100++0x3
|
|
line.long 0x0 "INT_GROUP0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "INT_GROUP0_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "INT_GROUP0_RIS,Raw interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_RIS_INT,Raw interrupt status for INT"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "INT_GROUP0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP0_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1120++0x3
|
|
line.long 0x0 "INT_GROUP0_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1128++0x3
|
|
line.long 0x0 "INT_GROUP0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "INT_GROUP1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1138++0x3
|
|
line.long 0x0 "INT_GROUP1_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1140++0x3
|
|
line.long 0x0 "INT_GROUP1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_RIS_INT,Raw interrupt status for INT" "0: CLR,1: SET"
|
|
rgroup.long 0x1148++0x3
|
|
line.long 0x0 "INT_GROUP1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1150++0x3
|
|
line.long 0x0 "INT_GROUP1_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1158++0x3
|
|
line.long 0x0 "INT_GROUP1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rgroup.long 0x1100++0x3
|
|
line.long 0x0 "INT_GROUP0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "INT_GROUP0_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "INT_GROUP0_RIS,Raw interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_RIS_INT,Raw interrupt status for INT"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "INT_GROUP0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP0_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1120++0x3
|
|
line.long 0x0 "INT_GROUP0_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1128++0x3
|
|
line.long 0x0 "INT_GROUP0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "INT_GROUP1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1138++0x3
|
|
line.long 0x0 "INT_GROUP1_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1140++0x3
|
|
line.long 0x0 "INT_GROUP1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_RIS_INT,Raw interrupt status for INT" "0: CLR,1: SET"
|
|
rgroup.long 0x1148++0x3
|
|
line.long 0x0 "INT_GROUP1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1150++0x3
|
|
line.long 0x0 "INT_GROUP1_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1158++0x3
|
|
line.long 0x0 "INT_GROUP1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rgroup.long 0x1100++0x3
|
|
line.long 0x0 "INT_GROUP0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "INT_GROUP0_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "INT_GROUP0_RIS,Raw interrupt status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP0_RIS_INT,Raw interrupt status for INT"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "INT_GROUP0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP0_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1120++0x3
|
|
line.long 0x0 "INT_GROUP0_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1128++0x3
|
|
line.long 0x0 "INT_GROUP0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP0_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "INT_GROUP1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IIDX_STAT,Interrupt index status"
|
|
rgroup.long 0x1138++0x3
|
|
line.long 0x0 "INT_GROUP1_IMASK,Interrupt mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_GROUP1_IMASK_INT,Masks the corresponding interrupt"
|
|
rgroup.long 0x1140++0x3
|
|
line.long 0x0 "INT_GROUP1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_RIS_INT,Raw interrupt status for INT" "0: CLR,1: SET"
|
|
rgroup.long 0x1148++0x3
|
|
line.long 0x0 "INT_GROUP1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "INT_GROUP1_MIS_INT,Masked interrupt status for INT0" "0: CLR,1: SET"
|
|
wgroup.long 0x1150++0x3
|
|
line.long 0x0 "INT_GROUP1_ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ISET_INT,Sets INT in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1158++0x3
|
|
line.long 0x0 "INT_GROUP1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "INT_GROUP1_ICLR_INT,Clears INT in RIS register" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
group.long 0x1300++0x3
|
|
line.long 0x0 "CTL,Prefetch/Cache control"
|
|
bitfld.long 0x0 2. "CTL_LITEN,Literal caching and prefetch enable." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 1. "CTL_ICACHE,Used to enable/disable Instruction caching on flash access." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "CTL_PREFETCH,Used to enable/disable instruction prefetch to Flash." "0: DISABLE,1: ENABLE"
|
|
tree.end
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40440000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.tbyte 0x0 2.--23. 1. "RSTCTL_RESERVED1,Reserved"
|
|
endif
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.word 0x0 17.--31. 1. "STAT_RESERVED2,Reserved"
|
|
hexmask.long.word 0x0 0.--15. 1. "STAT_RESERVED1,Reserved"
|
|
endif
|
|
rbitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "CRCCTRL,CRC Control Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x0 5.--31. 1. "CRCCTRL_RESERVED2,Rserved"
|
|
rbitfld.long 0x0 3. "CRCCTRL_RESERVED1,Reserved" "0,1"
|
|
endif
|
|
bitfld.long 0x0 4. "CRCCTRL_OUTPUT_BYTESWAP,CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 2. "CRCCTRL_INPUT_ENDIANNESS,CRC Endian. This bit indicates the byte order within a word or half word of input data." "0: LITTLE_ENDIAN,1: BIG_ENDIAN"
|
|
bitfld.long 0x0 1. "CRCCTRL_BITREVERSE,CRC Bit Input and output Reverse. This bit indicates that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator and that the bit order of the calculated CRC is be reversed when.." "0: NOT_REVERSED,1: REVERSED"
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 0. "CRCCTRL_POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC32,1: CRC16"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 0. "CRCCTRL_POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC32,1: CRC16"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 0. "CRCCTRL_POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC32,1: CRC16"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 0. "CRCCTRL_POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC32,1: CRC16"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 0. "CRCCTRL_POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC32,1: CRC16"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 0. "CRCCTRL_POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC32,1: CRC16"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 0. "CRCCTRL_POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC32,1: CRC16"
|
|
endif
|
|
wgroup.long 0x1104++0x7
|
|
line.long 0x0 "CRCSEED,CRC Seed Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCSEED_SEED,Seed Data"
|
|
line.long 0x4 "CRCIN,CRC Input Data Register"
|
|
hexmask.long 0x4 0.--31. 1. "CRCIN_DATA,Input Data"
|
|
rgroup.long 0x110C++0x3
|
|
line.long 0x0 "CRCOUT,CRC Output Result Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCOUT_RESULT,Result"
|
|
repeat 512. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x1800)++0x3
|
|
line.long 0x0 "CRCIN_IDX[$1],CRC Input Data Array Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCIN_IDX_DATA,Input Data"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "CRCP0"
|
|
base ad:0x40440000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "CRCCTRL,CRC Control Register"
|
|
bitfld.long 0x0 4. "CRCCTRL_OUTPUT_BYTESWAP,CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CRCCTRL_INPUT_ENDIANNESS,CRC Endian. This bit indicates the byte order within a word or half word of input data." "0: LITTLE_ENDIAN,1: BIG_ENDIAN"
|
|
bitfld.long 0x0 1. "CRCCTRL_BITREVERSE,CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator and that the bit order of the calculated CRC is be reversed when.." "0: NOT_REVERSED,1: REVERSED"
|
|
newline
|
|
bitfld.long 0x0 0. "CRCCTRL_POLYSIZE,This bit indicates which CRC calculation is performed by the generator." "0: CRC32,1: CRC16"
|
|
wgroup.long 0x1104++0x7
|
|
line.long 0x0 "CRCSEED,CRC Seed Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCSEED_SEED,Seed Data"
|
|
line.long 0x4 "CRCIN,CRC Input Data Register"
|
|
hexmask.long 0x4 0.--31. 1. "CRCIN_DATA,Input Data"
|
|
rgroup.long 0x110C++0x3
|
|
line.long 0x0 "CRCOUT,CRC Output Result Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCOUT_RESULT,Result"
|
|
group.long 0x1110++0x3
|
|
line.long 0x0 "CRCPOLY,CRC Polynomial configuration register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY_DATA,Polynomial definition"
|
|
repeat 512. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x1800)++0x3
|
|
line.long 0x0 "CRCIN_IDX[$1],CRC Input Data Array Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCIN_IDX_DATA,Input Data"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*"))
|
|
tree "DAC0 (Digital-to-Analog Converter)"
|
|
base ad:0x40018000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subscriber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher port 1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--3. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 14. "IMASK_DMADONEIFG,Masks DMADONEIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "IMASK_FIFOURUNIFG,Masks FIFOURUNIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "IMASK_FIFOEMPTYIFG,Masks FIFOEMPTYIFG" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "IMASK_FIFO3B4IFG,Masks FIFO3B4IFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "IMASK_FIFO1B2IFG,Masks FIFO1B2IFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_FIFO1B4IFG,Masks FIFO1B4IFG" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_FIFOFULLIFG,Masks FIFOFULLIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_MODRDYIFG,Masks MODRDYIFG" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 14. "RIS_DMADONEIFG,Raw interrupt status for DMADONEIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "RIS_FIFOURUNIFG,Raw interrupt status for FIFOURUNIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "RIS_FIFOEMPTYIFG,Raw interrupt status for FIFOEMPTYIFG" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "RIS_FIFO3B4IFG,Raw interrupt status for FIFO3B4IFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "RIS_FIFO1B2IFG,Raw interrupt status for FIFO1B2IFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_FIFO1B4IFG,Raw interrupt status for FIFO1B4IFG" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_FIFOFULLIFG,Raw interrupt status for FIFOFULLIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_MODRDYIFG,Raw interrupt status for MODRDYIFG" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 14. "MIS_DMADONEIFG,Masked interrupt status for DMADONEIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "MIS_FIFOURUNIFG,Masked interrupt status for FIFOURUNIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "MIS_FIFOEMPTYIFG,Masked interrupt status for FIFOEMPTYIFG" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "MIS_FIFO3B4IFG,Masked interrupt status for FIFO3B4IFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "MIS_FIFO1B2IFG,Masked interrupt status for FIFO1B2IFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_FIFO1B4IFG,Masked interrupt status for FIFO1B4IFG" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_FIFOFULLIFG,Masked interrupt status for FIFOFULLIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_MODRDYIFG,Masked interrupt status for MODRDYIFG" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 14. "ISET_DMADONEIFG,Sets DMADONEIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "ISET_FIFOURUNIFG,Sets FIFOURUNIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "ISET_FIFOEMPTYIFG,Sets FIFOEMPTYIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "ISET_FIFO3B4IFG,Sets FIFO3B4IFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "ISET_FIFO1B2IFG,Sets FIFO1B2IFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_FIFO1B4IFG,Sets FIFO1B4IFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_FIFOFULLIFG,Sets FIFOFULLIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_MODRDYIFG,Sets MODRDYIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 14. "ICLR_DMADONEIFG,Clears DMADONEIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "ICLR_FIFOURUNIFG,Clears FIFOURUNIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "ICLR_FIFOEMPTYIFG,Clears FIFOEMPTYIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "ICLR_FIFO3B4IFG,Clears FIFO3B4IFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "ICLR_FIFO1B2IFG,Clears FIFO1B2IFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_FIFO1B4IFG,Clears FIFO1B4IFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_FIFOFULLIFG,Clears FIFOFULLIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_MODRDYIFG,Clears MODRDYIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "CTL0,Control 0"
|
|
bitfld.long 0x0 16. "CTL0_DFM,This bit defines the DAC input data format." "0: BINARY,1: TWOS_COMP"
|
|
bitfld.long 0x0 8. "CTL0_RES,These bits define the DAC output voltage resolution." "0: _8BITS,1: _12BITS"
|
|
bitfld.long 0x0 0. "CTL0_ENABLE,This bit enables the DAC module." "0: CLR,1: SET"
|
|
group.long 0x1110++0x3
|
|
line.long 0x0 "CTL1,Control 1"
|
|
bitfld.long 0x0 24. "CTL1_OPS,These bits select the DAC output on device pin." "0: NOC0,1: OUT0"
|
|
bitfld.long 0x0 9. "CTL1_REFSN,This bit selects the DAC voltage reference source + input." "0: VEREFN,1: VSSA"
|
|
bitfld.long 0x0 8. "CTL1_REFSP,This bit selects the DAC voltage reference source + input." "0: VDDA,1: VEREFP"
|
|
newline
|
|
bitfld.long 0x0 1. "CTL1_AMPHIZ,AMPHIZ - amplifier output value" "0: amplifier output is high impedance,1: amplifier output is pulled down to ground"
|
|
bitfld.long 0x0 0. "CTL1_AMPEN,AMP_EN - output amplifier enabled or disabled" "0: disabled,1: enabled"
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "CTL2,Control 2"
|
|
bitfld.long 0x0 24. "CTL2_DMATRIGEN,This bit enables the DMA trigger generation mechanism. When this bit is set along with FIFOEN the DMA trigger is generated based on the empty FIFO locations qualified by FIFOTH settings. This bit needs to be cleared by SW to stop further.." "0: CLR,1: SET"
|
|
bitfld.long 0x0 16.--17. "CTL2_FIFOTRIGSEL,These bits select the source for FIFO read trigger. When the selected FIFO read trigger is asserted the data from FIFO (as indicated by read pointer) is moved into internal DAC data register." "0: STIM,1: TRIG0,2: TRIG1,3: SPARE"
|
|
bitfld.long 0x0 8.--9. "CTL2_FIFOTH,These bits determine the FIFO threshold. In case of DMA based operation DAC generates new DMA trigger when the number of empty locations in FIFO match the selected FIFO threshold level." "0: LOW,1: MED,2: HIGH,3: SPARE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTL2_FIFOEN,This bit enables the FIFO and the FIFO hardware control state machine." "0: CLR,1: SET"
|
|
group.long 0x1130++0x3
|
|
line.long 0x0 "CTL3,Control 3"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CTL3_STIMCONFIG,These bits are used to configure the trigger rate from the sample time generator."
|
|
bitfld.long 0x0 0. "CTL3_STIMEN,This bit enables the sample time generator." "0: CLR,1: SET"
|
|
group.long 0x1140++0x3
|
|
line.long 0x0 "CALCTL,Calibration control"
|
|
bitfld.long 0x0 1. "CALCTL_CALSEL,This bit is used to select between factory trim or self calibration trim." "0: FACTORY_TRIM,1: SELF_CALIBRATION_TRIM"
|
|
bitfld.long 0x0 0. "CALCTL_CALON,This bit when set initiates the DAC offset error calibration sequence and is automatically reset when the offset error calibration completes." "0: INACTIVE,1: ACTIVE"
|
|
rgroup.long 0x1160++0x3
|
|
line.long 0x0 "CALDATA,Calibration data"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALDATA_DATA,DAC offset error calibration data. The DAC offset error calibration data is represented in twos complement format providing a range of 64 to +63."
|
|
group.long 0x1200++0x3
|
|
line.long 0x0 "DATA0,Data 0"
|
|
hexmask.long.word 0x0 0.--11. 1. "DATA0_DATA_VALUE,This is the data written for digital to analog conversion."
|
|
tree.end
|
|
endif
|
|
tree "DEBUGSS (Debug Subsystem)"
|
|
base ad:0x400C7000
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "IMASK_PWRDWNIFG,Masks PWRDWNIFG in MIS register" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "IMASK_PWRUPIFG,Masks PWRUPIFG in MIS register" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_RXIFG,Masks RXIFG in MIS register" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_TXIFG,Masks TXIFG in MIS register" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "RIS_PWRDWNIFG,Raw interrupt status for PWRDWNIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_PWRUPIFG,Raw interrupt status for PWRUPIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_RXIFG,Raw interrupt status for RXIFG" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_TXIFG,Raw interrupt status for TXIFG" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "MIS_PWRDWNIFG,Masked interrupt status for PWRDWNIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_PWRUPIFG,Masked interrupt status for PWRUPIFG" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_RXIFG,Masked interrupt status for RXIFG" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_TXIFG,Masked interrupt status for TXIFG" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "ISET_PWRDWNIFG,Sets PWRDWNIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_PWRUPIFG,Sets PWRUPIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_RXIFG,Sets RXIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_TXIFG,Sets TXIFG in RIS register" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "ICLR_PWRDWNIFG,Clears PWRDWNIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_PWRUPIFG,Clears PWRUPIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_RXIFG,Clears RXIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_TXIFG,Clears TXIFG in RIS register" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for peripheral events" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0xB
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
line.long 0x4 "TXD,Transmit data register"
|
|
hexmask.long 0x4 0.--31. 1. "TXD_TX_DATA,Contains data written by an external debug tool to the SEC-AP TXDATA register"
|
|
line.long 0x8 "TXCTL,Transmit control register"
|
|
hexmask.long 0x8 1.--31. 1. "TXCTL_TRANSMIT_FLAGS,Generic TX flags that can be set by external debug tool. Functionality is defined by SW."
|
|
bitfld.long 0x8 0. "TXCTL_TRANSMIT,Indicates data request in DSSM.TXD set on write via Debug AP to DSSM.TXD." "0: EMPTY,1: FULL"
|
|
group.long 0x1108++0x7
|
|
line.long 0x0 "RXD,Receive data register"
|
|
hexmask.long 0x0 0.--31. 1. "RXD_RX_DATA,Contains data written by SM/OW."
|
|
line.long 0x4 "RXCTL,Receive control register"
|
|
hexmask.long.byte 0x4 1.--7. 1. "RXCTL_RECEIVE_FLAGS,Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW."
|
|
rbitfld.long 0x4 0. "RXCTL_RECEIVE,Indicates SW write to the DSSM.RXD register." "0: EMPTY,1: FULL"
|
|
rgroup.long 0x1200++0x3
|
|
line.long 0x0 "SPECIAL_AUTH,Special enable authorization register"
|
|
bitfld.long 0x0 6. "SPECIAL_AUTH_PWRAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "SPECIAL_AUTH_AHBAPEN,Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "SPECIAL_AUTH_CFGAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Config-AP to read device configuration information. When deasserted a DAPBUS firewall will isolate the AP and prevent access to the.." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 3. "SPECIAL_AUTH_ETAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "SPECIAL_AUTH_DFTAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted a DAPBUS firewall will isolate the AP and prevent access." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 1. "SPECIAL_AUTH_SWDPORTEN,When asserted the SW-DP functions normally." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "SPECIAL_AUTH_SECAPEN,An active high input. When asserted (and SWD access is also permitted) the debug tools can use the Security-AP to communicate with security control logic. When deasserted a DAPBUS firewall will isolate the AP and prevent access to.." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1210++0x3
|
|
line.long 0x0 "APP_AUTH,Application CPU0 authorization register"
|
|
bitfld.long 0x0 3. "APP_AUTH_SPNIDEN,Secure non-invasive debug enable." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "APP_AUTH_SPIDEN,Secure invasive debug enable." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 1. "APP_AUTH_NIDEN,Controls non-invasive debug enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "APP_AUTH_DBGEN,Controls invasive debug enable." "0: DISABLE,1: ENABLE"
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x4042A000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subscriber Port 0"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
endif
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_1,Publisher Port 0"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
bitfld.long 0x0 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "IMASK_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 18. "IMASK_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "IMASK_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 18. "IMASK_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "IMASK_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 18. "IMASK_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "IMASK_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 18. "IMASK_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "IMASK_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 16. "IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 16. "IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 16. "IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 6. "IMASK_DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "IMASK_DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "IMASK_DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "IMASK_DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 6. "IMASK_DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "IMASK_DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "IMASK_DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "IMASK_DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 6. "IMASK_DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "IMASK_DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "IMASK_DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "IMASK_DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 6. "IMASK_DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "IMASK_DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "IMASK_DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "IMASK_DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 2. "IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 2. "IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 2. "IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 0. "IMASK_DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "RIS_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 18. "RIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "RIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 18. "RIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "RIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 18. "RIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "RIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 18. "RIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "RIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 16. "RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 16. "RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 16. "RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 6. "RIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "RIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "RIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "RIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 6. "RIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "RIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "RIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "RIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 6. "RIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "RIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "RIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "RIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 6. "RIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "RIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "RIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "RIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 2. "RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 2. "RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 2. "RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
bitfld.long 0x0 0. "RIS_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "MIS_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 18. "MIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "MIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 18. "MIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "MIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 18. "MIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "MIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 18. "MIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "MIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 16. "MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 16. "MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 16. "MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 6. "MIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "MIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "MIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "MIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 6. "MIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "MIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "MIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "MIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 6. "MIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "MIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "MIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "MIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 6. "MIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "MIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "MIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "MIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 2. "MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 2. "MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 2. "MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
endif
|
|
bitfld.long 0x0 0. "MIS_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "ISET_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 18. "ISET_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "ISET_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 18. "ISET_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "ISET_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 18. "ISET_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "ISET_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 18. "ISET_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "ISET_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 16. "ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 16. "ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 16. "ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 6. "ISET_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "ISET_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "ISET_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "ISET_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 6. "ISET_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "ISET_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "ISET_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "ISET_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 6. "ISET_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "ISET_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "ISET_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "ISET_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 6. "ISET_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "ISET_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "ISET_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "ISET_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 2. "ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 2. "ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 2. "ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
endif
|
|
bitfld.long 0x0 0. "ISET_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "ICLR_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 18. "ICLR_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "ICLR_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 18. "ICLR_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "ICLR_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 18. "ICLR_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "ICLR_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 18. "ICLR_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "ICLR_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 16. "ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 16. "ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 16. "ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 6. "ICLR_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "ICLR_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "ICLR_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "ICLR_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 6. "ICLR_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "ICLR_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "ICLR_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "ICLR_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 6. "ICLR_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "ICLR_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "ICLR_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "ICLR_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 6. "ICLR_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "ICLR_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "ICLR_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "ICLR_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 2. "ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 2. "ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 2. "ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
bitfld.long 0x0 0. "ICLR_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "CPU_INT_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPU_INT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "CPU_INT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "CPU_INT_IMASK_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_IMASK_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "CPU_INT_IMASK_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_IMASK_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_IMASK_DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_IMASK_DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_IMASK_DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU_INT_IMASK_DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_IMASK_DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "CPU_INT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "CPU_INT_RIS_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_RIS_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "CPU_INT_RIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_RIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_RIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_RIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_RIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU_INT_RIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_RIS_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "CPU_INT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "CPU_INT_MIS_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_MIS_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "CPU_INT_MIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_MIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_MIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_MIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_MIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU_INT_MIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_MIS_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "CPU_INT_ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "CPU_INT_ISET_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_ISET_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "CPU_INT_ISET_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_ISET_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_ISET_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_ISET_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_ISET_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU_INT_ISET_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_ISET_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "CPU_INT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "CPU_INT_ICLR_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_ICLR_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "CPU_INT_ICLR_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_ICLR_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_ICLR_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_ICLR_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "CPU_INT_ICLR_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU_INT_ICLR_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "CPU_INT_ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "CPU_INT_ICLR_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "GEN_EVENT_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "GEN_EVENT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "GEN_EVENT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "GEN_EVENT_IMASK_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT_IMASK_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "GEN_EVENT_IMASK_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT_IMASK_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT_IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_IMASK_DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_IMASK_DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_IMASK_DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT_IMASK_DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "GEN_EVENT_IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_IMASK_DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "GEN_EVENT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "GEN_EVENT_RIS_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT_RIS_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "GEN_EVENT_RIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT_RIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT_RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_RIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_RIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_RIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT_RIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "GEN_EVENT_RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_RIS_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "GEN_EVENT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "GEN_EVENT_MIS_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT_MIS_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "GEN_EVENT_MIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT_MIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT_MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_MIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_MIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_MIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT_MIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "GEN_EVENT_MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_MIS_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "GEN_EVENT_ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "GEN_EVENT_ISET_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT_ISET_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "GEN_EVENT_ISET_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT_ISET_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT_ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_ISET_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_ISET_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_ISET_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT_ISET_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "GEN_EVENT_ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_ISET_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "GEN_EVENT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "GEN_EVENT_ICLR_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT_ICLR_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "GEN_EVENT_ICLR_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT_ICLR_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT_ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_ICLR_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_ICLR_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "GEN_EVENT_ICLR_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT_ICLR_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "GEN_EVENT_ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "GEN_EVENT_ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "GEN_EVENT_ICLR_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "CPU_INT_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPU_INT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "CPU_INT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "CPU_INT_IMASK_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_IMASK_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "CPU_INT_IMASK_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_IMASK_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_IMASK_DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_IMASK_DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_IMASK_DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU_INT_IMASK_DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_IMASK_DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "CPU_INT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "CPU_INT_RIS_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_RIS_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "CPU_INT_RIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_RIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_RIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_RIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_RIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU_INT_RIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_RIS_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "CPU_INT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "CPU_INT_MIS_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_MIS_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "CPU_INT_MIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_MIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_MIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_MIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_MIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU_INT_MIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_MIS_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "CPU_INT_ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "CPU_INT_ISET_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_ISET_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "CPU_INT_ISET_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_ISET_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_ISET_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_ISET_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_ISET_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU_INT_ISET_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_ISET_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "CPU_INT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "CPU_INT_ICLR_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_ICLR_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "CPU_INT_ICLR_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_ICLR_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_ICLR_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_ICLR_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "CPU_INT_ICLR_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "CPU_INT_ICLR_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "CPU_INT_ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "CPU_INT_ICLR_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "GEN_EVENT_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "GEN_EVENT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "GEN_EVENT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "GEN_EVENT_IMASK_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT_IMASK_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "GEN_EVENT_IMASK_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT_IMASK_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT_IMASK_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_IMASK_DMACH6,DMA Channel 6 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_IMASK_DMACH5,DMA Channel 5 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_IMASK_DMACH4,DMA Channel 4 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT_IMASK_DMACH3,DMA Channel 3 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_IMASK_DMACH2,DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "GEN_EVENT_IMASK_DMACH1,DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_IMASK_DMACH0,DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "GEN_EVENT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "GEN_EVENT_RIS_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT_RIS_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "GEN_EVENT_RIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT_RIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT_RIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_RIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_RIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_RIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT_RIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_RIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "GEN_EVENT_RIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_RIS_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "GEN_EVENT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "GEN_EVENT_MIS_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT_MIS_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "GEN_EVENT_MIS_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT_MIS_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT_MIS_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_MIS_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_MIS_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_MIS_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT_MIS_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_MIS_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "GEN_EVENT_MIS_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_MIS_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "GEN_EVENT_ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "GEN_EVENT_ISET_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT_ISET_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "GEN_EVENT_ISET_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT_ISET_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT_ISET_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_ISET_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_ISET_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_ISET_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT_ISET_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT_ISET_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "GEN_EVENT_ISET_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_ISET_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "GEN_EVENT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "GEN_EVENT_ICLR_DATAERR,DMA data error SRC data might be corrupted (PAR or ECC error)." "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT_ICLR_ADDRERR,DMA address error SRC address not reachable." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "GEN_EVENT_ICLR_PREIRQCH2,Pre-IRQ for Channel 2. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT_ICLR_PREIRQCH1,Pre-IRQ for Channel 1. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT_ICLR_PREIRQCH0,Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_ICLR_DMACH6,DMA Channel 6 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_ICLR_DMACH5,DMA Channel 5 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "GEN_EVENT_ICLR_DMACH4,DMA Channel 4 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT_ICLR_DMACH3,DMA Channel 3 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "GEN_EVENT_ICLR_DMACH2,DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "GEN_EVENT_ICLR_DMACH1,DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "GEN_EVENT_ICLR_DMACH0,DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)." "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to generic event INT_EVENT[1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to interrupt event INT_EVENT[0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the DMA: number of DMA channel minus one (e.g. 0->1ch 2->3ch 15->16ch)."
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "DMAPRIO,DMA Channel Priority Control"
|
|
bitfld.long 0x0 16.--17. "DMAPRIO_BURSTSZ,Define the burst size of a block transfer before the priority is re-evaluated" "0: INFINITI,1: BURST_8,2: BUSRT_16,3: BURST_32"
|
|
bitfld.long 0x0 0. "DMAPRIO_ROUNDROBIN,Round robin. This bit enables the round-robin DMA channel priorities." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1110++0x3
|
|
line.long 0x0 "DMATCTL,DMA Trigger Select"
|
|
bitfld.long 0x0 7. "DMATCTL_DMATINT,DMA Trigger by Internal Channel" "0: EXTERNAL,1: INTERNAL"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMATCTL_DMATSEL,DMA Trigger Select"
|
|
group.long 0x1200++0xF
|
|
line.long 0x0 "DMACTL,DMA Channel Control"
|
|
bitfld.long 0x0 28.--29. "DMACTL_DMATM,DMA transfer mode register" "0: SINGLE,1: BLOCK,2: RPTSNGL,3: RPTBLCK"
|
|
bitfld.long 0x0 24.--25. "DMACTL_DMAEM,DMA extended mode" "0: NORMAL,?,2: FILLMODE,3: TABLEMODE"
|
|
hexmask.long.byte 0x0 20.--23. 1. "DMACTL_DMADSTINCR,DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an.."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "DMACTL_DMASRCINCR,DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1.."
|
|
bitfld.long 0x0 12.--13. "DMACTL_DMADSTWDTH,DMA destination width. This bit selects the destination as a byte half word word or long word." "0: BYTE,1: HALF,2: WORD,3: LONG"
|
|
bitfld.long 0x0 8.--9. "DMACTL_DMASRCWDTH,DMA source width. This bit selects the source data width as a byte half word word or long word." "0: BYTE,1: HALF,2: WORD,3: LONG"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "DMACTL_DMAPREIRQ,Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete." "0: PREIRQ_DISABLE,1: PREIRQ_1,2: PREIRQ_2,3: PREIRQ_4,4: PREIRQ_8,5: PREIRQ_32,6: PREIRQ_64,7: PREIRQ_HALF"
|
|
bitfld.long 0x0 1. "DMACTL_DMAEN,DMA enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "DMACTL_DMAREQ,DMA request. Software-controlled DMA start. DMAREQ is reset automatically." "0: IDLE,1: REQUEST"
|
|
line.long 0x4 "DMASA,DMA Channel Source Address"
|
|
hexmask.long 0x4 0.--31. 1. "DMASA_ADDR,DMA Channel Source Address"
|
|
line.long 0x8 "DMADA,DMA Channel Destination Address"
|
|
hexmask.long 0x8 0.--31. 1. "DMADA_ADDR,DMA Channel Destination Address"
|
|
line.long 0xC "DMASZ,DMA Channel Size"
|
|
hexmask.long.word 0xC 0.--15. 1. "DMASZ_SIZE,DMA Channel Size in number of transfers"
|
|
tree.end
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0L110*")||cpuis("MSPM0L122*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*")||cpuis("MSPM0L222*"))
|
|
tree "FLASHCTL (Flash Controller)"
|
|
base ad:0x400CD000
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt Index Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x0 1.--31. 1. "IIDX_RESERVED_31_1,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x0 1.--31. 1. "IIDX_RESERVED_31_1,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x0 1.--31. 1. "IIDX_RESERVED_31_1,Reserved"
|
|
endif
|
|
bitfld.long 0x0 0. "IIDX_STAT,Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read only one interrupt is indicated. On a read the current interrupt (highest priority) is automatically cleared by the hardware and the.." "0: NO_INTR,1: DONE"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt Mask Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x0 1.--31. 1. "IMASK_RESERVED_31_1,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x0 1.--31. 1. "IMASK_RESERVED_31_1,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x0 1.--31. 1. "IMASK_RESERVED_31_1,Reserved"
|
|
endif
|
|
bitfld.long 0x0 0. "IMASK_DONE,Interrupt mask for DONE:" "0: Interrupt is disabled in MIS register,1: Interrupt is enabled in MIS register"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw Interrupt Status Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x0 1.--31. 1. "RIS_RESERVED_31_1,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x0 1.--31. 1. "RIS_RESERVED_31_1,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x0 1.--31. 1. "RIS_RESERVED_31_1,Reserved"
|
|
endif
|
|
bitfld.long 0x0 0. "RIS_DONE,Flash wrapper operation completed." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked Interrupt Status Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x0 1.--31. 1. "MIS_RESERVED_31_1,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x0 1.--31. 1. "MIS_RESERVED_31_1,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x0 1.--31. 1. "MIS_RESERVED_31_1,Reserved"
|
|
endif
|
|
bitfld.long 0x0 0. "MIS_DONE,Flash wrapper operation completed." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt Set Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x0 1.--31. 1. "ISET_RESERVED_31_1,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x0 1.--31. 1. "ISET_RESERVED_31_1,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x0 1.--31. 1. "ISET_RESERVED_31_1,Reserved"
|
|
endif
|
|
bitfld.long 0x0 0. "ISET_DONE,0: No effect" "0: No effect,1: Set the DONE interrupt in the RIS register"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt Clear Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x0 1.--31. 1. "ICLR_RESERVED_31_1,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x0 1.--31. 1. "ICLR_RESERVED_31_1,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x0 1.--31. 1. "ICLR_RESERVED_31_1,Reserved"
|
|
endif
|
|
bitfld.long 0x0 0. "ICLR_DONE,0: No effect" "0: No effect,1: Clear the DONE interrupt in the RIS register"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x0 2.--31. 1. "EVT_MODE_RESERVED_31_2,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x0 2.--31. 1. "EVT_MODE_RESERVED_31_2,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x0 2.--31. 1. "EVT_MODE_RESERVED_31_2,Reserved"
|
|
endif
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for peripheral event" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Hardware Version Description Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module ID"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature set"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance number"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major Revision"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor Revision"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CMDEXEC,Command Execute Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x0 1.--31. 1. "CMDEXEC_RESERVED_31_1,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x0 1.--31. 1. "CMDEXEC_RESERVED_31_1,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x0 1.--31. 1. "CMDEXEC_RESERVED_31_1,Reserved"
|
|
endif
|
|
bitfld.long 0x0 0. "CMDEXEC_VAL,Command Execute value" "0: NOEXECUTE,1: EXECUTE"
|
|
line.long 0x4 "CMDTYPE,Command Type Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x4 7.--31. 1. "CMDTYPE_RESERVED_31_7,Reserved"
|
|
bitfld.long 0x4 3. "CMDTYPE_RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x4 7.--31. 1. "CMDTYPE_RESERVED_31_7,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x4 7.--31. 1. "CMDTYPE_RESERVED_31_7,Reserved"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 4.--6. "CMDTYPE_SIZE,Command size" "0: ONEWORD,1: TWOWORD,2: FOURWORD,3: EIGHTWORD,4: SECTOR,5: BANK,?,?"
|
|
sif (cpuis("MSPM0L122*"))
|
|
newline
|
|
bitfld.long 0x4 3. "CMDTYPE_RESERVED_3,Reserved" "0,1"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x4 3. "CMDTYPE_RESERVED_3,Reserved" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CMDTYPE_COMMAND,Command type" "0: NOOP,1: PROGRAM,2: ERASE,3: READVERIFY,4: MODECHANGE,5: CLEARSTATUS,6: BLANKVERIFY,?"
|
|
line.long 0x8 "CMDCTL,Command Control Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.word 0x8 22.--31. 1. "CMDCTL_RESERVED_31_22,Reserved"
|
|
bitfld.long 0x8 13. "CMDCTL_RESERVED_13,Reserved" "0,1"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.word 0x8 22.--31. 1. "CMDCTL_RESERVED_31_22,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.word 0x8 22.--31. 1. "CMDCTL_RESERVED_31_22,Reserved"
|
|
endif
|
|
newline
|
|
bitfld.long 0x8 21. "CMDCTL_DATAVEREN,Enable invalid data verify." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 20. "CMDCTL_SSERASEDIS,Disable Stair-Step Erase. If set the default VHV trim voltage setting will be used" "0: ENABLE,1: DISABLE"
|
|
newline
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x8 17. "CMDCTL_ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: NOOVERRIDE,1: OVERRIDE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x8 17. "CMDCTL_ECCGENOVR,Override hardware generation of ECC data for program. Use data written to" "0: NOOVERRIDE,1: OVERRIDE"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 16. "CMDCTL_ADDRXLATEOVR,Override hardware address translation of address in CMDADDR from a" "0: NOOVERRIDE,1: OVERRIDE"
|
|
sif (cpuis("MSPM0L122*"))
|
|
newline
|
|
bitfld.long 0x8 13. "CMDCTL_RESERVED_13,Reserved" "0,1"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x8 13. "CMDCTL_RESERVED_13,Reserved" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x8 9.--12. 1. "CMDCTL_REGIONSEL,Bank Region"
|
|
newline
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.byte 0x8 4.--8. 1. "CMDCTL_BANKSEL,Bank Select"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.byte 0x8 4.--8. 1. "CMDCTL_BANKSEL,Bank Select"
|
|
newline
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "CMDCTL_MODESEL,Mode"
|
|
group.long 0x1120++0x7
|
|
line.long 0x0 "CMDADDR,Command Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "CMDADDR_VAL,Address value"
|
|
line.long 0x4 "CMDBYTEN,Command Program Byte Enable Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.word 0x4 18.--31. 1. "CMDBYTEN_RESERVED_31_18,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.word 0x4 18.--31. 1. "CMDBYTEN_RESERVED_31_18,Reserved"
|
|
newline
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "CMDBYTEN_VAL,Command Byte Enable value."
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.word 0x4 18.--31. 1. "CMDBYTEN_RESERVED_31_18,Reserved"
|
|
newline
|
|
hexmask.long.tbyte 0x4 0.--17. 1. "CMDBYTEN_VAL,Command Byte Enable value."
|
|
endif
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
hexmask.long.byte 0x4 0.--7. 1. "CMDBYTEN_VAL,Command Byte Enable value."
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
group.long 0x112C++0x3
|
|
line.long 0x0 "CMDDATAINDEX,Command Data Index Register"
|
|
hexmask.long 0x0 3.--31. 1. "CMDDATAINDEX_RESERVED_31_3,Reserved"
|
|
bitfld.long 0x0 0.--2. "CMDDATAINDEX_VAL,Data register index" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1138++0x97
|
|
line.long 0x0 "CMDDATA2,Command Data Register 2"
|
|
hexmask.long 0x0 0.--31. 1. "CMDDATA2_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x4 "CMDDATA3,Command Data Register Bits 127:96"
|
|
hexmask.long 0x4 0.--31. 1. "CMDDATA3_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x8 "CMDDATA4,Command Data Register 4"
|
|
hexmask.long 0x8 0.--31. 1. "CMDDATA4_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0xC "CMDDATA5,Command Data Register 5"
|
|
hexmask.long 0xC 0.--31. 1. "CMDDATA5_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x10 "CMDDATA6,Command Data Register 6"
|
|
hexmask.long 0x10 0.--31. 1. "CMDDATA6_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x14 "CMDDATA7,Command Data Register 7"
|
|
hexmask.long 0x14 0.--31. 1. "CMDDATA7_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x18 "CMDDATA8,Command Data Register 8"
|
|
hexmask.long 0x18 0.--31. 1. "CMDDATA8_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x1C "CMDDATA9,Command Data Register 9"
|
|
hexmask.long 0x1C 0.--31. 1. "CMDDATA9_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x20 "CMDDATA10,Command Data Register 10"
|
|
hexmask.long 0x20 0.--31. 1. "CMDDATA10_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x24 "CMDDATA11,Command Data Register 11"
|
|
hexmask.long 0x24 0.--31. 1. "CMDDATA11_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x28 "CMDDATA12,Command Data Register 12"
|
|
hexmask.long 0x28 0.--31. 1. "CMDDATA12_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x2C "CMDDATA13,Command Data Register 13"
|
|
hexmask.long 0x2C 0.--31. 1. "CMDDATA13_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x30 "CMDDATA14,Command Data Register 14"
|
|
hexmask.long 0x30 0.--31. 1. "CMDDATA14_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x34 "CMDDATA15,Command Data Register 15"
|
|
hexmask.long 0x34 0.--31. 1. "CMDDATA15_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x38 "CMDDATA16,Command Data Register 16"
|
|
hexmask.long 0x38 0.--31. 1. "CMDDATA16_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x3C "CMDDATA17,Command Data Register 17"
|
|
hexmask.long 0x3C 0.--31. 1. "CMDDATA17_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x40 "CMDDATA18,Command Data Register 18"
|
|
hexmask.long 0x40 0.--31. 1. "CMDDATA18_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x44 "CMDDATA19,Command Data Register 19"
|
|
hexmask.long 0x44 0.--31. 1. "CMDDATA19_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x48 "CMDDATA20,Command Data Register 20"
|
|
hexmask.long 0x48 0.--31. 1. "CMDDATA20_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x4C "CMDDATA21,Command Data Register 21"
|
|
hexmask.long 0x4C 0.--31. 1. "CMDDATA21_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x50 "CMDDATA22,Command Data Register 22"
|
|
hexmask.long 0x50 0.--31. 1. "CMDDATA22_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x54 "CMDDATA23,Command Data Register 23"
|
|
hexmask.long 0x54 0.--31. 1. "CMDDATA23_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x58 "CMDDATA24,Command Data Register 24"
|
|
hexmask.long 0x58 0.--31. 1. "CMDDATA24_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x5C "CMDDATA25,Command Data Register 25"
|
|
hexmask.long 0x5C 0.--31. 1. "CMDDATA25_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x60 "CMDDATA26,Command Data Register 26"
|
|
hexmask.long 0x60 0.--31. 1. "CMDDATA26_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x64 "CMDDATA27,Command Data Register 27"
|
|
hexmask.long 0x64 0.--31. 1. "CMDDATA27_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x68 "CMDDATA28,Command Data Register 28"
|
|
hexmask.long 0x68 0.--31. 1. "CMDDATA28_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x6C "CMDDATA29,Command Data Register 29"
|
|
hexmask.long 0x6C 0.--31. 1. "CMDDATA29_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x70 "CMDDATA30,Command Data Register 30"
|
|
hexmask.long 0x70 0.--31. 1. "CMDDATA30_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x74 "CMDDATA31,Command Data Register 31"
|
|
hexmask.long 0x74 0.--31. 1. "CMDDATA31_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x78 "CMDDATAECC0,Command Data Register ECC 0"
|
|
hexmask.long.word 0x78 16.--31. 1. "CMDDATAECC0_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x78 8.--15. 1. "CMDDATAECC0_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x78 0.--7. 1. "CMDDATAECC0_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x7C "CMDDATAECC1,Command Data Register ECC 1"
|
|
hexmask.long.word 0x7C 16.--31. 1. "CMDDATAECC1_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x7C 8.--15. 1. "CMDDATAECC1_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--7. 1. "CMDDATAECC1_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x80 "CMDDATAECC2,Command Data Register ECC 2"
|
|
hexmask.long.word 0x80 16.--31. 1. "CMDDATAECC2_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x80 8.--15. 1. "CMDDATAECC2_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x80 0.--7. 1. "CMDDATAECC2_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x84 "CMDDATAECC3,Command Data Register ECC 3"
|
|
hexmask.long.word 0x84 16.--31. 1. "CMDDATAECC3_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x84 8.--15. 1. "CMDDATAECC3_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x84 0.--7. 1. "CMDDATAECC3_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x88 "CMDDATAECC4,Command Data Register ECC 4"
|
|
hexmask.long.word 0x88 16.--31. 1. "CMDDATAECC4_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x88 8.--15. 1. "CMDDATAECC4_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x88 0.--7. 1. "CMDDATAECC4_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x8C "CMDDATAECC5,Command Data Register ECC 5"
|
|
hexmask.long.word 0x8C 16.--31. 1. "CMDDATAECC5_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x8C 8.--15. 1. "CMDDATAECC5_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--7. 1. "CMDDATAECC5_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x90 "CMDDATAECC6,Command Data Register ECC 6"
|
|
hexmask.long.word 0x90 16.--31. 1. "CMDDATAECC6_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x90 8.--15. 1. "CMDDATAECC6_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x90 0.--7. 1. "CMDDATAECC6_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x94 "CMDDATAECC7,Command Data Register ECC 7"
|
|
hexmask.long.word 0x94 16.--31. 1. "CMDDATAECC7_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x94 8.--15. 1. "CMDDATAECC7_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x94 0.--7. 1. "CMDDATAECC7_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
group.long 0x112C++0x3
|
|
line.long 0x0 "CMDDATAINDEX,Command Data Index Register"
|
|
hexmask.long 0x0 3.--31. 1. "CMDDATAINDEX_RESERVED_31_3,Reserved"
|
|
bitfld.long 0x0 0.--2. "CMDDATAINDEX_VAL,Data register index" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1138++0x97
|
|
line.long 0x0 "CMDDATA2,Command Data Register 2"
|
|
hexmask.long 0x0 0.--31. 1. "CMDDATA2_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x4 "CMDDATA3,Command Data Register Bits 127:96"
|
|
hexmask.long 0x4 0.--31. 1. "CMDDATA3_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x8 "CMDDATA4,Command Data Register 4"
|
|
hexmask.long 0x8 0.--31. 1. "CMDDATA4_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0xC "CMDDATA5,Command Data Register 5"
|
|
hexmask.long 0xC 0.--31. 1. "CMDDATA5_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x10 "CMDDATA6,Command Data Register 6"
|
|
hexmask.long 0x10 0.--31. 1. "CMDDATA6_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x14 "CMDDATA7,Command Data Register 7"
|
|
hexmask.long 0x14 0.--31. 1. "CMDDATA7_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x18 "CMDDATA8,Command Data Register 8"
|
|
hexmask.long 0x18 0.--31. 1. "CMDDATA8_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x1C "CMDDATA9,Command Data Register 9"
|
|
hexmask.long 0x1C 0.--31. 1. "CMDDATA9_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x20 "CMDDATA10,Command Data Register 10"
|
|
hexmask.long 0x20 0.--31. 1. "CMDDATA10_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x24 "CMDDATA11,Command Data Register 11"
|
|
hexmask.long 0x24 0.--31. 1. "CMDDATA11_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x28 "CMDDATA12,Command Data Register 12"
|
|
hexmask.long 0x28 0.--31. 1. "CMDDATA12_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x2C "CMDDATA13,Command Data Register 13"
|
|
hexmask.long 0x2C 0.--31. 1. "CMDDATA13_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x30 "CMDDATA14,Command Data Register 14"
|
|
hexmask.long 0x30 0.--31. 1. "CMDDATA14_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x34 "CMDDATA15,Command Data Register 15"
|
|
hexmask.long 0x34 0.--31. 1. "CMDDATA15_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x38 "CMDDATA16,Command Data Register 16"
|
|
hexmask.long 0x38 0.--31. 1. "CMDDATA16_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x3C "CMDDATA17,Command Data Register 17"
|
|
hexmask.long 0x3C 0.--31. 1. "CMDDATA17_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x40 "CMDDATA18,Command Data Register 18"
|
|
hexmask.long 0x40 0.--31. 1. "CMDDATA18_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x44 "CMDDATA19,Command Data Register 19"
|
|
hexmask.long 0x44 0.--31. 1. "CMDDATA19_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x48 "CMDDATA20,Command Data Register 20"
|
|
hexmask.long 0x48 0.--31. 1. "CMDDATA20_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x4C "CMDDATA21,Command Data Register 21"
|
|
hexmask.long 0x4C 0.--31. 1. "CMDDATA21_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x50 "CMDDATA22,Command Data Register 22"
|
|
hexmask.long 0x50 0.--31. 1. "CMDDATA22_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x54 "CMDDATA23,Command Data Register 23"
|
|
hexmask.long 0x54 0.--31. 1. "CMDDATA23_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x58 "CMDDATA24,Command Data Register 24"
|
|
hexmask.long 0x58 0.--31. 1. "CMDDATA24_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x5C "CMDDATA25,Command Data Register 25"
|
|
hexmask.long 0x5C 0.--31. 1. "CMDDATA25_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x60 "CMDDATA26,Command Data Register 26"
|
|
hexmask.long 0x60 0.--31. 1. "CMDDATA26_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x64 "CMDDATA27,Command Data Register 27"
|
|
hexmask.long 0x64 0.--31. 1. "CMDDATA27_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x68 "CMDDATA28,Command Data Register 28"
|
|
hexmask.long 0x68 0.--31. 1. "CMDDATA28_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x6C "CMDDATA29,Command Data Register 29"
|
|
hexmask.long 0x6C 0.--31. 1. "CMDDATA29_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x70 "CMDDATA30,Command Data Register 30"
|
|
hexmask.long 0x70 0.--31. 1. "CMDDATA30_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x74 "CMDDATA31,Command Data Register 31"
|
|
hexmask.long 0x74 0.--31. 1. "CMDDATA31_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x78 "CMDDATAECC0,Command Data Register ECC 0"
|
|
hexmask.long.word 0x78 16.--31. 1. "CMDDATAECC0_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x78 8.--15. 1. "CMDDATAECC0_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x78 0.--7. 1. "CMDDATAECC0_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x7C "CMDDATAECC1,Command Data Register ECC 1"
|
|
hexmask.long.word 0x7C 16.--31. 1. "CMDDATAECC1_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x7C 8.--15. 1. "CMDDATAECC1_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x7C 0.--7. 1. "CMDDATAECC1_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x80 "CMDDATAECC2,Command Data Register ECC 2"
|
|
hexmask.long.word 0x80 16.--31. 1. "CMDDATAECC2_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x80 8.--15. 1. "CMDDATAECC2_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x80 0.--7. 1. "CMDDATAECC2_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x84 "CMDDATAECC3,Command Data Register ECC 3"
|
|
hexmask.long.word 0x84 16.--31. 1. "CMDDATAECC3_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x84 8.--15. 1. "CMDDATAECC3_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x84 0.--7. 1. "CMDDATAECC3_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x88 "CMDDATAECC4,Command Data Register ECC 4"
|
|
hexmask.long.word 0x88 16.--31. 1. "CMDDATAECC4_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x88 8.--15. 1. "CMDDATAECC4_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x88 0.--7. 1. "CMDDATAECC4_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x8C "CMDDATAECC5,Command Data Register ECC 5"
|
|
hexmask.long.word 0x8C 16.--31. 1. "CMDDATAECC5_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x8C 8.--15. 1. "CMDDATAECC5_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x8C 0.--7. 1. "CMDDATAECC5_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x90 "CMDDATAECC6,Command Data Register ECC 6"
|
|
hexmask.long.word 0x90 16.--31. 1. "CMDDATAECC6_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x90 8.--15. 1. "CMDDATAECC6_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x90 0.--7. 1. "CMDDATAECC6_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
line.long 0x94 "CMDDATAECC7,Command Data Register ECC 7"
|
|
hexmask.long.word 0x94 16.--31. 1. "CMDDATAECC7_RESERVED_31_16,Reserved"
|
|
hexmask.long.byte 0x94 8.--15. 1. "CMDDATAECC7_VAL1,ECC data for bits 127:64 of the data is placed here."
|
|
newline
|
|
hexmask.long.byte 0x94 0.--7. 1. "CMDDATAECC7_VAL0,ECC data for bits 63:0 of the data is placed here."
|
|
rgroup.long 0x1410++0x7
|
|
line.long 0x0 "BANK1INFO0,Bank Information Register 0 for Bank 1"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK1INFO0_RESERVED_31_12,Reserved"
|
|
hexmask.long.word 0x0 0.--11. 1. "BANK1INFO0_MAINSIZE,Main region size in sectors"
|
|
line.long 0x4 "BANK1INFO1,Bank Information Register 1 for Bank 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK1INFO1_RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BANK1INFO1_ENGRSIZE,Engr region size in sectors"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "BANK1INFO1_TRIMSIZE,Trim region size in sectors"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BANK1INFO1_NONMAINSIZE,Non-main region size in sectors"
|
|
rgroup.long 0x1420++0x7
|
|
line.long 0x0 "BANK2INFO0,Bank Information Register 0 for Bank 2"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK2INFO0_RESERVED_31_12,Reserved"
|
|
hexmask.long.word 0x0 0.--11. 1. "BANK2INFO0_MAINSIZE,Main region size in sectors"
|
|
line.long 0x4 "BANK2INFO1,Bank Information Register 1 for Bank 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK2INFO1_RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BANK2INFO1_ENGRSIZE,Engr region size in sectors"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "BANK2INFO1_TRIMSIZE,Trim region size in sectors"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BANK2INFO1_NONMAINSIZE,Non-main region size in sectors"
|
|
rgroup.long 0x1430++0x7
|
|
line.long 0x0 "BANK3INFO0,Bank Information Register 0 for Bank 3"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK3INFO0_RESERVED_31_12,Reserved"
|
|
hexmask.long.word 0x0 0.--11. 1. "BANK3INFO0_MAINSIZE,Main region size in sectors"
|
|
line.long 0x4 "BANK3INFO1,Bank Information Register 1 for Bank 3"
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK3INFO1_RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BANK3INFO1_ENGRSIZE,Engr region size in sectors"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "BANK3INFO1_TRIMSIZE,Trim region size in sectors"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BANK3INFO1_NONMAINSIZE,Non-main region size in sectors"
|
|
rgroup.long 0x1440++0x3
|
|
line.long 0x0 "BANK4INFO0,Bank Information Register 0 for Bank 4"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK4INFO0_RESERVED_31_12,Reserved"
|
|
hexmask.long.word 0x0 0.--11. 1. "BANK4INFO0_MAINSIZE,Main region size in sectors"
|
|
endif
|
|
group.long 0x1130++0x7
|
|
line.long 0x0 "CMDDATA0,Command Data Register 0"
|
|
hexmask.long 0x0 0.--31. 1. "CMDDATA0_VAL,A 32-bit data value is placed in this field."
|
|
line.long 0x4 "CMDDATA1,Command Data Register 1"
|
|
hexmask.long 0x4 0.--31. 1. "CMDDATA1_VAL,A 32-bit data value is placed in this field."
|
|
group.long 0x11D0++0xB
|
|
line.long 0x0 "CMDWEPROTA,Command Write Erase Protect A Register"
|
|
hexmask.long 0x0 0.--31. 1. "CMDWEPROTA_VAL,Each bit protects 1 sector."
|
|
line.long 0x4 "CMDWEPROTB,Command Write Erase Protect B Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "CMDWEPROTB_VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x4 0.--31. 1. "CMDWEPROTB_VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x4 0.--31. 1. "CMDWEPROTB_VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors"
|
|
endif
|
|
line.long 0x8 "CMDWEPROTC,Command Write Erase Protect C Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.byte 0x8 0.--3. 1. "CMDWEPROTC_VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x8 0. "CMDWEPROTC_VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x8 0. "CMDWEPROTC_VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors" "0,1"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
hexmask.long.byte 0x8 0.--3. 1. "CMDWEPROTC_VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x8 0.--31. 1. "CMDWEPROTC_VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x8 0.--31. 1. "CMDWEPROTC_VAL,Each bit protects a group of 8 sectors. When a bit is 1 the associated 8 sectors"
|
|
endif
|
|
group.long 0x1210++0xB
|
|
line.long 0x0 "CMDWEPROTNM,Command Write Erase Protect Non-Main Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 0. "CMDWEPROTNM_VAL,Each bit protects 1 sector." "0,1"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x0 0.--31. 1. "CMDWEPROTNM_VAL,Each bit protects 1 sector."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x0 0.--31. 1. "CMDWEPROTNM_VAL,Each bit protects 1 sector."
|
|
endif
|
|
line.long 0x4 "CMDWEPROTTR,Command Write Erase Protect Trim Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
bitfld.long 0x4 0. "CMDWEPROTTR_VAL,Each bit protects 1 sector." "0,1"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x4 0.--31. 1. "CMDWEPROTTR_VAL,Each bit protects 1 sector."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x4 0.--31. 1. "CMDWEPROTTR_VAL,Each bit protects 1 sector."
|
|
endif
|
|
line.long 0x8 "CMDWEPROTEN,Command Write Erase Protect Engr Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
bitfld.long 0x8 0.--1. "CMDWEPROTEN_VAL,Each bit protects 1 sector." "0,1,2,3"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x8 0.--31. 1. "CMDWEPROTEN_VAL,Each bit protects 1 sector."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x8 0.--31. 1. "CMDWEPROTEN_VAL,Each bit protects 1 sector."
|
|
endif
|
|
group.long 0x13B0++0x7
|
|
line.long 0x0 "CFGCMD,Command Configuration Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x0 7.--31. 1. "CFGCMD_RESERVED_31_7,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x0 7.--31. 1. "CFGCMD_RESERVED_31_7,Reserved"
|
|
newline
|
|
bitfld.long 0x0 6. "CFGCMD_HOLDCLKSTREN,Enable pulse stretching for the clocking of the hold latches for inputs to the" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "CFGCMD_CTRLCLKSTREN,Enable pulse stretching when generating a control clock to the flash bank from the" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 4. "CFGCMD_RDCLKSTREN,Enable pulse stretching when generating a read clock to the flash bank from the" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x0 7.--31. 1. "CFGCMD_RESERVED_31_7,Reserved"
|
|
newline
|
|
bitfld.long 0x0 6. "CFGCMD_HOLDCLKSTREN,Enable pulse stretching for the clocking of the hold latches for inputs to the" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "CFGCMD_CTRLCLKSTREN,Enable pulse stretching when generating a control clock to the flash bank from the" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 4. "CFGCMD_RDCLKSTREN,Enable pulse stretching when generating a read clock to the flash bank from the" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFGCMD_WAITSTATE,Wait State setting for program verify erase verify and read verify"
|
|
line.long 0x4 "CFGPCNT,Pulse Counter Configuration Register"
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.word 0x4 20.--31. 1. "CFGPCNT_MAXERSPCNTVAL,Override maximum pulse count for erase with this value."
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.word 0x4 20.--31. 1. "CFGPCNT_MAXERSPCNTVAL,Override maximum pulse count for erase with this value."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
bitfld.long 0x4 17.--19. "CFGPCNT_RESERVED_17_19,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CFGPCNT_RESERVED_15_12,Reserved"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CFGPCNT_RESERVED_3_1,Reserved" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x4 17.--19. "CFGPCNT_RESERVED_17_19,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 16. "CFGPCNT_MAXERSPCNTOVR,Override hard-wired maximum pulse count for erase. If set then the value" "0: DEFAULT,1: OVERRIDE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x4 17.--19. "CFGPCNT_RESERVED_17_19,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 16. "CFGPCNT_MAXERSPCNTOVR,Override hard-wired maximum pulse count for erase. If set then the value" "0: DEFAULT,1: OVERRIDE"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.byte 0x4 12.--15. 1. "CFGPCNT_RESERVED_15_12,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.byte 0x4 12.--15. 1. "CFGPCNT_RESERVED_15_12,Reserved"
|
|
endif
|
|
hexmask.long.byte 0x4 4.--11. 1. "CFGPCNT_MAXPCNTVAL,Override maximum pulse counter with this value."
|
|
newline
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x4 1.--3. "CFGPCNT_RESERVED_3_1,Reserved" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x4 1.--3. "CFGPCNT_RESERVED_3_1,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 0. "CFGPCNT_MAXPCNTOVR,Override hard-wired maximum pulse count. If MAXERSPCNTOVR" "0: DEFAULT,1: OVERRIDE"
|
|
rgroup.long 0x13D0++0xF
|
|
line.long 0x0 "STATCMD,Command Status Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.tbyte 0x0 13.--31. 1. "STATCMD_RESERVED_31_13,Reserved"
|
|
rbitfld.long 0x0 9.--11. "STATCMD_RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x0 3. "STATCMD_RESERVED_3,Reserved" "0,1"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.tbyte 0x0 13.--31. 1. "STATCMD_RESERVED_31_13,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.tbyte 0x0 13.--31. 1. "STATCMD_RESERVED_31_13,Reserved"
|
|
endif
|
|
rbitfld.long 0x0 12. "STATCMD_FAILMISC,Command failed due to error other than write/erase protect violation or verify" "0: STATNOFAIL,1: STATFAIL"
|
|
newline
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 9.--11. "STATCMD_RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 9.--11. "STATCMD_RESERVED_11_9,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
newline
|
|
rbitfld.long 0x0 8. "STATCMD_FAILINVDATA,Program command failed because an attempt was made to program a stored" "0: STATNOFAIL,1: STATFAIL"
|
|
rbitfld.long 0x0 7. "STATCMD_FAILMODE,Command failed because a bank has been set to a mode other than READ." "0: STATNOFAIL,1: STATFAIL"
|
|
newline
|
|
rbitfld.long 0x0 6. "STATCMD_FAILILLADDR,Command failed due to the use of an illegal address" "0: STATNOFAIL,1: STATFAIL"
|
|
rbitfld.long 0x0 5. "STATCMD_FAILVERIFY,Command failed due to verify error" "0: STATNOFAIL,1: STATFAIL"
|
|
newline
|
|
rbitfld.long 0x0 4. "STATCMD_FAILWEPROT,Command failed due to Write/Erase Protect Sector Violation" "0: STATNOFAIL,1: STATFAIL"
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 3. "STATCMD_RESERVED_3,Reserved" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 3. "STATCMD_RESERVED_3,Reserved" "0,1"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x0 2. "STATCMD_CMDINPROGRESS,Command In Progress" "0: STATCOMPLETE,1: STATINPROGRESS"
|
|
newline
|
|
rbitfld.long 0x0 1. "STATCMD_CMDPASS,Command Pass - valid when CMD_DONE field is 1" "0: STATFAIL,1: STATPASS"
|
|
rbitfld.long 0x0 0. "STATCMD_CMDDONE,Command Done" "0: STATNOTDONE,1: STATDONE"
|
|
line.long 0x4 "STATADDR,Address Status Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.byte 0x4 26.--31. 1. "STATADDR_RESERVED_31_26,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.byte 0x4 26.--31. 1. "STATADDR_RESERVED_31_26,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.byte 0x4 26.--31. 1. "STATADDR_RESERVED_31_26,Reserved"
|
|
endif
|
|
hexmask.long.byte 0x4 21.--25. 1. "STATADDR_BANKID,Current Bank ID"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "STATADDR_REGIONID,Current Region ID"
|
|
hexmask.long.word 0x4 0.--15. 1. "STATADDR_BANKADDR,Current Bank Address"
|
|
line.long 0x8 "STATPCNT,Pulse Count Status Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.tbyte 0x8 12.--31. 1. "STATPCNT_RESERVED_31_12,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.tbyte 0x8 12.--31. 1. "STATPCNT_RESERVED_31_12,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.tbyte 0x8 12.--31. 1. "STATPCNT_RESERVED_31_12,Reserved"
|
|
endif
|
|
hexmask.long.word 0x8 0.--11. 1. "STATPCNT_PULSECNT,Current Pulse Counter Value"
|
|
line.long 0xC "STATMODE,Mode Status Register"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.word 0xC 18.--31. 1. "STATMODE_RESERVED_31_18,Reserved"
|
|
hexmask.long.byte 0xC 12.--15. 1. "STATMODE_RESERVED_15_12,Reserved"
|
|
newline
|
|
rbitfld.long 0xC 5.--7. "STATMODE_RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.word 0xC 18.--31. 1. "STATMODE_RESERVED_31_18,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.word 0xC 18.--31. 1. "STATMODE_RESERVED_31_18,Reserved"
|
|
endif
|
|
rbitfld.long 0xC 17. "STATMODE_BANK1TRDY,Bank 1T Ready." "0: FALSE,1: TRUE"
|
|
newline
|
|
rbitfld.long 0xC 16. "STATMODE_BANK2TRDY,Bank 2T Ready." "0: FALSE,1: TRUE"
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.byte 0xC 12.--15. 1. "STATMODE_RESERVED_15_12,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.byte 0xC 12.--15. 1. "STATMODE_RESERVED_15_12,Reserved"
|
|
endif
|
|
hexmask.long.byte 0xC 8.--11. 1. "STATMODE_BANKMODE,Indicates mode of bank(s) that are not in READ mode"
|
|
newline
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0xC 5.--7. "STATMODE_RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 0.--4. 1. "STATMODE_BANKNOTINRD,Bank not in read mode."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0xC 5.--7. "STATMODE_RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 0.--4. 1. "STATMODE_BANKNOTINRD,Bank not in read mode."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
rbitfld.long 0xC 0. "STATMODE_BANKNOTINRD,Bank not in read mode." "?,1: BANK0"
|
|
endif
|
|
rgroup.long 0x13F0++0xB
|
|
line.long 0x0 "GBLINFO0,Global Information Register 0"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.word 0x0 19.--31. 1. "GBLINFO0_RESERVED_31_19,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.word 0x0 19.--31. 1. "GBLINFO0_RESERVED_31_19,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.word 0x0 19.--31. 1. "GBLINFO0_RESERVED_31_19,Reserved"
|
|
endif
|
|
bitfld.long 0x0 16.--18. "GBLINFO0_NUMBANKS,Number of banks instantiated" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "GBLINFO0_SECTORSIZE,Sector size in bytes"
|
|
line.long 0x4 "GBLINFO1,Global Information Register 1"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.word 0x4 19.--31. 1. "GBLINFO1_RESERVED_31_19,Reserved"
|
|
rbitfld.long 0x4 13.--15. "GBLINFO1_RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.word 0x4 19.--31. 1. "GBLINFO1_RESERVED_31_19,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.word 0x4 19.--31. 1. "GBLINFO1_RESERVED_31_19,Reserved"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x4 16.--18. "GBLINFO1_REDWIDTH,Redundant data width in bits" "0: W0BIT,?,2: W2BIT,?,4: W4BIT,?,?,?"
|
|
sif (cpuis("MSPM0L122*"))
|
|
newline
|
|
rbitfld.long 0x4 13.--15. "GBLINFO1_RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x4 13.--15. "GBLINFO1_RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
hexmask.long.byte 0x4 8.--12. 1. "GBLINFO1_ECCWIDTH,ECC data width in bits"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "GBLINFO1_DATAWIDTH,Data width in bits"
|
|
line.long 0x8 "GBLINFO2,Global Information Register 2"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long 0x8 4.--31. 1. "GBLINFO2_RESERVED_31_4,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long 0x8 4.--31. 1. "GBLINFO2_RESERVED_31_4,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long 0x8 4.--31. 1. "GBLINFO2_RESERVED_31_4,Reserved"
|
|
endif
|
|
hexmask.long.byte 0x8 0.--3. 1. "GBLINFO2_DATAREGISTERS,Number of data registers present."
|
|
rgroup.long 0x1400++0x7
|
|
line.long 0x0 "BANK0INFO0,Bank Information Register 0 for Bank 0"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK0INFO0_RESERVED_31_12,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK0INFO0_RESERVED_31_12,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK0INFO0_RESERVED_31_12,Reserved"
|
|
endif
|
|
hexmask.long.word 0x0 0.--11. 1. "BANK0INFO0_MAINSIZE,Main region size in sectors"
|
|
line.long 0x4 "BANK0INFO1,Bank Information Register 1 for Bank 0"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK0INFO1_RESERVED_31_24,Reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK0INFO1_RESERVED_31_24,Reserved"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK0INFO1_RESERVED_31_24,Reserved"
|
|
endif
|
|
hexmask.long.byte 0x4 16.--23. 1. "BANK0INFO1_ENGRSIZE,Engr region size in sectors"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "BANK0INFO1_TRIMSIZE,Trim region size in sectors"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BANK0INFO1_NONMAINSIZE,Non-main region size in sectors"
|
|
sif (cpuis("MSPM0L122*"))
|
|
rgroup.long 0x1410++0x7
|
|
line.long 0x0 "BANK1INFO0,Bank Information Register 0 for Bank 1"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK1INFO0_RESERVED_31_12,Reserved"
|
|
hexmask.long.word 0x0 0.--11. 1. "BANK1INFO0_MAINSIZE,Main region size in sectors"
|
|
line.long 0x4 "BANK1INFO1,Bank Information Register 1 for Bank 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK1INFO1_RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BANK1INFO1_ENGRSIZE,Engr region size in sectors"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "BANK1INFO1_TRIMSIZE,Trim region size in sectors"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BANK1INFO1_NONMAINSIZE,Non-main region size in sectors"
|
|
rgroup.long 0x1420++0x7
|
|
line.long 0x0 "BANK2INFO0,Bank Information Register 0 for Bank 2"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK2INFO0_RESERVED_31_12,Reserved"
|
|
hexmask.long.word 0x0 0.--11. 1. "BANK2INFO0_MAINSIZE,Main region size in sectors"
|
|
line.long 0x4 "BANK2INFO1,Bank Information Register 1 for Bank 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK2INFO1_RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BANK2INFO1_ENGRSIZE,Engr region size in sectors"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "BANK2INFO1_TRIMSIZE,Trim region size in sectors"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BANK2INFO1_NONMAINSIZE,Non-main region size in sectors"
|
|
rgroup.long 0x1430++0x7
|
|
line.long 0x0 "BANK3INFO0,Bank Information Register 0 for Bank 3"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK3INFO0_RESERVED_31_12,Reserved"
|
|
hexmask.long.word 0x0 0.--11. 1. "BANK3INFO0_MAINSIZE,Main region size in sectors"
|
|
line.long 0x4 "BANK3INFO1,Bank Information Register 1 for Bank 3"
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK3INFO1_RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BANK3INFO1_ENGRSIZE,Engr region size in sectors"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "BANK3INFO1_TRIMSIZE,Trim region size in sectors"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BANK3INFO1_NONMAINSIZE,Non-main region size in sectors"
|
|
rgroup.long 0x1440++0x7
|
|
line.long 0x0 "BANK4INFO0,Bank Information Register 0 for Bank 4"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "BANK4INFO0_RESERVED_31_12,Reserved"
|
|
hexmask.long.word 0x0 0.--11. 1. "BANK4INFO0_MAINSIZE,Main region size in sectors"
|
|
line.long 0x4 "BANK4INFO1,Bank Information Register 1 for Bank 4"
|
|
hexmask.long.byte 0x4 24.--31. 1. "BANK4INFO1_RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BANK4INFO1_ENGRSIZE,Engr region size in sectors"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--15. 1. "BANK4INFO1_TRIMSIZE,Trim region size in sectors"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BANK4INFO1_NONMAINSIZE,Non-main region size in sectors"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rgroup.long 0x1444++0x3
|
|
line.long 0x0 "BANK4INFO1,Bank Information Register 1 for Bank 4"
|
|
hexmask.long.byte 0x0 24.--31. 1. "BANK4INFO1_RESERVED_31_24,Reserved"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BANK4INFO1_ENGRSIZE,Engr region size in sectors"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BANK4INFO1_TRIMSIZE,Trim region size in sectors"
|
|
hexmask.long.byte 0x0 0.--7. 1. "BANK4INFO1_NONMAINSIZE,Non-main region size in sectors"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "GPIO (General Purpose Input/Output)"
|
|
base ad:0x0
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "GPIOA"
|
|
base ad:0x400A0000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
bitfld.long 0x0 0.--1. "FPUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
bitfld.long 0x4 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1010++0x3
|
|
line.long 0x0 "CLKOVR,Clock Override"
|
|
bitfld.long 0x0 1. "CLKOVR_RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: RUN,1: STOP"
|
|
bitfld.long 0x0 0. "CLKOVR_OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT0_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "INT_EVENT0_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "INT_EVENT0_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "INT_EVENT0_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "INT_EVENT0_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "INT_EVENT0_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "INT_EVENT0_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "INT_EVENT0_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "INT_EVENT0_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "INT_EVENT0_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "INT_EVENT0_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 15. "INT_EVENT1_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 15. "INT_EVENT1_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 15. "INT_EVENT1_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 15. "INT_EVENT1_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 15. "INT_EVENT1_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT1_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "INT_EVENT1_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT1_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "INT_EVENT1_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT1_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT1_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT2_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT2_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT2_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "INT_EVENT2_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "INT_EVENT2_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "INT_EVENT2_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "INT_EVENT2_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "INT_EVENT2_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "INT_EVENT2_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "INT_EVENT2_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "INT_EVENT2_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "INT_EVENT2_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "INT_EVENT2_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 19. "INT_EVENT2_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 16. "INT_EVENT2_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
wgroup.long 0x1200++0x1F
|
|
line.long 0x0 "DOUT3_0,Data output 3 to 0"
|
|
bitfld.long 0x0 24. "DOUT3_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 16. "DOUT3_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 8. "DOUT3_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 0. "DOUT3_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
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line.long 0x4 "DOUT7_4,Data output 7 to 4"
|
|
bitfld.long 0x4 24. "DOUT7_4_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x4 16. "DOUT7_4_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 8. "DOUT7_4_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x4 0. "DOUT7_4_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
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line.long 0x8 "DOUT11_8,Data output 11 to 8"
|
|
bitfld.long 0x8 24. "DOUT11_8_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 16. "DOUT11_8_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 8. "DOUT11_8_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x8 0. "DOUT11_8_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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line.long 0xC "DOUT15_12,Data output 15 to 12"
|
|
bitfld.long 0xC 24. "DOUT15_12_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "DOUT15_12_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "DOUT15_12_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0xC 0. "DOUT15_12_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DOUT19_16,Data output 19 to 16"
|
|
bitfld.long 0x10 24. "DOUT19_16_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DOUT19_16_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DOUT19_16_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x10 0. "DOUT19_16_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DOUT23_20,Data output 23 to 20"
|
|
bitfld.long 0x14 24. "DOUT23_20_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 16. "DOUT23_20_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DOUT23_20_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x14 0. "DOUT23_20_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x18 "DOUT27_24,Data output 27 to 24"
|
|
bitfld.long 0x18 24. "DOUT27_24_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 16. "DOUT27_24_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DOUT27_24_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x18 0. "DOUT27_24_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x1C "DOUT31_28,Data output 31 to 28"
|
|
bitfld.long 0x1C 24. "DOUT31_28_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 16. "DOUT31_28_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 8. "DOUT31_28_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x1C 0. "DOUT31_28_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
group.long 0x1280++0x3
|
|
line.long 0x0 "DOUT31_0,Data output 31 to 0"
|
|
bitfld.long 0x0 31. "DOUT31_0_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 30. "DOUT31_0_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 29. "DOUT31_0_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x0 28. "DOUT31_0_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 27. "DOUT31_0_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 26. "DOUT31_0_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 25. "DOUT31_0_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 24. "DOUT31_0_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 23. "DOUT31_0_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 22. "DOUT31_0_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 21. "DOUT31_0_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 20. "DOUT31_0_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 19. "DOUT31_0_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 18. "DOUT31_0_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 17. "DOUT31_0_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DOUT31_0_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 15. "DOUT31_0_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 14. "DOUT31_0_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 13. "DOUT31_0_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 12. "DOUT31_0_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 11. "DOUT31_0_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 10. "DOUT31_0_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 9. "DOUT31_0_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DOUT31_0_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 7. "DOUT31_0_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 6. "DOUT31_0_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 5. "DOUT31_0_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 4. "DOUT31_0_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 3. "DOUT31_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 2. "DOUT31_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 1. "DOUT31_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DOUT31_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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wgroup.long 0x1290++0x3
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line.long 0x0 "DOUTSET31_0,Data output set 31 to 0"
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bitfld.long 0x0 31. "DOUTSET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOUTSET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOUTSET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOUTSET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOUTSET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOUTSET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOUTSET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOUTSET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOUTSET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOUTSET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOUTSET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOUTSET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOUTSET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOUTSET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOUTSET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOUTSET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOUTSET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOUTSET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOUTSET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOUTSET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOUTSET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOUTSET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOUTSET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOUTSET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOUTSET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOUTSET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOUTSET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOUTSET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOUTSET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOUTSET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOUTSET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOUTSET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12A0++0x3
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line.long 0x0 "DOUTCLR31_0,Data output clear 31 to 0"
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bitfld.long 0x0 31. "DOUTCLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOUTCLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOUTCLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOUTCLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOUTCLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOUTCLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOUTCLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOUTCLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOUTCLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOUTCLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOUTCLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOUTCLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOUTCLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOUTCLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOUTCLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOUTCLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOUTCLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOUTCLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOUTCLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOUTCLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOUTCLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOUTCLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOUTCLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOUTCLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOUTCLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOUTCLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOUTCLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOUTCLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOUTCLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOUTCLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOUTCLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOUTCLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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wgroup.long 0x12B0++0x3
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line.long 0x0 "DOUTTGL31_0,Data output toggle 31 to 0"
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bitfld.long 0x0 31. "DOUTTGL31_0_DIO31,This bit is used to toggle DIO31 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 30. "DOUTTGL31_0_DIO30,This bit is used to toggle DIO30 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 29. "DOUTTGL31_0_DIO29,This bit is used to toggle DIO29 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 28. "DOUTTGL31_0_DIO28,This bit is used to toggle DIO28 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 27. "DOUTTGL31_0_DIO27,This bit is used to toggle DIO27 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 26. "DOUTTGL31_0_DIO26,This bit is used to toggle DIO26 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 25. "DOUTTGL31_0_DIO25,This bit is used to toggle DIO25 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 24. "DOUTTGL31_0_DIO24,This bit is used to toggle DIO24 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 23. "DOUTTGL31_0_DIO23,This bit is used to toggle DIO23 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 22. "DOUTTGL31_0_DIO22,This bit is used to toggle DIO22 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 21. "DOUTTGL31_0_DIO21,This bit is used to toggle DIO21 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 20. "DOUTTGL31_0_DIO20,This bit is used to toggle DIO20 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 19. "DOUTTGL31_0_DIO19,This bit is used to toggle DIO19 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 18. "DOUTTGL31_0_DIO18,This bit is used to toggle DIO18 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 17. "DOUTTGL31_0_DIO17,This bit is used to toggle DIO17 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 16. "DOUTTGL31_0_DIO16,This bit is used to toggle DIO16 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 15. "DOUTTGL31_0_DIO15,This bit is used to toggle DIO15 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 14. "DOUTTGL31_0_DIO14,This bit is used to toggle DIO14 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 13. "DOUTTGL31_0_DIO13,This bit is used to toggle DIO13 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 12. "DOUTTGL31_0_DIO12,This bit is used to toggle DIO12 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 11. "DOUTTGL31_0_DIO11,This bit is used to toggle DIO11 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 10. "DOUTTGL31_0_DIO10,This bit is used to toggle DIO10 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 9. "DOUTTGL31_0_DIO9,This bit is used to toggle DIO9 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 8. "DOUTTGL31_0_DIO8,This bit is used to toggle DIO8 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 7. "DOUTTGL31_0_DIO7,This bit is used to toggle DIO7 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 6. "DOUTTGL31_0_DIO6,This bit is used to toggle DIO6 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 5. "DOUTTGL31_0_DIO5,This bit is used to toggle DIO5 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 4. "DOUTTGL31_0_DIO4,This bit is used to toggle DIO4 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 3. "DOUTTGL31_0_DIO3,This bit is used to toggle DIO3 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 2. "DOUTTGL31_0_DIO2,This bit is used to toggle DIO2 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 1. "DOUTTGL31_0_DIO1,This bit is used to toggle DIO1 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 0. "DOUTTGL31_0_DIO0,This bit is used to toggle DIO0 output." "0: NO_EFFECT,1: TOGGLE"
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group.long 0x12C0++0x3
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line.long 0x0 "DOE31_0,Data output enable 31 to 0"
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bitfld.long 0x0 31. "DOE31_0_DIO31,Enables data output for DIO31." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 30. "DOE31_0_DIO30,Enables data output for DIO30." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 29. "DOE31_0_DIO29,Enables data output for DIO29." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 28. "DOE31_0_DIO28,Enables data output for DIO28." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 27. "DOE31_0_DIO27,Enables data output for DIO27." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 26. "DOE31_0_DIO26,Enables data output for DIO26." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 25. "DOE31_0_DIO25,Enables data output for DIO25." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 24. "DOE31_0_DIO24,Enables data output for DIO24." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 23. "DOE31_0_DIO23,Enables data output for DIO23." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 22. "DOE31_0_DIO22,Enables data output for DIO22." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 21. "DOE31_0_DIO21,Enables data output for DIO21." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 20. "DOE31_0_DIO20,Enables data output for DIO20." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 19. "DOE31_0_DIO19,Enables data output for DIO19." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 18. "DOE31_0_DIO18,Enables data output for DIO18." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 17. "DOE31_0_DIO17,Enables data output for DIO17." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 16. "DOE31_0_DIO16,Enables data output for DIO16." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 15. "DOE31_0_DIO15,Enables data output for DIO15." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 14. "DOE31_0_DIO14,Enables data output for DIO14." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 13. "DOE31_0_DIO13,Enables data output for DIO13." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "DOE31_0_DIO12,Enables data output for DIO12." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 11. "DOE31_0_DIO11,Enables data output for DIO11." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 10. "DOE31_0_DIO10,Enables data output for DIO10." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 9. "DOE31_0_DIO9,Enables data output for DIO9." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 8. "DOE31_0_DIO8,Enables data output for DIO8." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 7. "DOE31_0_DIO7,Enables data output for DIO7." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 6. "DOE31_0_DIO6,Enables data output for DIO6." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 5. "DOE31_0_DIO5,Enables data output for DIO5." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 4. "DOE31_0_DIO4,Enables data output for DIO4." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "DOE31_0_DIO3,Enables data output for DIO3." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "DOE31_0_DIO2,Enables data output for DIO2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 1. "DOE31_0_DIO1,Enables data output for DIO1." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "DOE31_0_DIO0,Enables data output for DIO0." "0: DISABLE,1: ENABLE"
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wgroup.long 0x12D0++0x3
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line.long 0x0 "DOESET31_0,Data output enable set 31 to 0"
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bitfld.long 0x0 31. "DOESET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOESET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOESET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOESET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOESET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOESET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOESET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOESET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOESET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOESET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOESET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOESET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOESET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOESET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOESET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOESET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOESET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOESET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOESET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOESET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOESET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOESET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOESET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOESET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOESET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOESET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOESET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOESET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOESET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOESET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOESET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOESET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12E0++0x3
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line.long 0x0 "DOECLR31_0,Data output enable clear 31 to 0"
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bitfld.long 0x0 31. "DOECLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOECLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOECLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOECLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOECLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOECLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOECLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOECLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOECLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOECLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOECLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOECLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOECLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOECLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOECLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOECLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOECLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOECLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOECLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOECLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOECLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOECLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOECLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOECLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOECLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOECLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOECLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOECLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOECLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOECLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOECLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOECLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1300++0x1F
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line.long 0x0 "DIN3_0,Data input 3 to 0"
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bitfld.long 0x0 24. "DIN3_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DIN3_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DIN3_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DIN3_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
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line.long 0x4 "DIN7_4,Data input 7 to 4"
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bitfld.long 0x4 24. "DIN7_4_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
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bitfld.long 0x4 16. "DIN7_4_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
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bitfld.long 0x4 8. "DIN7_4_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
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bitfld.long 0x4 0. "DIN7_4_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
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line.long 0x8 "DIN11_8,Data input 11 to 8"
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bitfld.long 0x8 24. "DIN11_8_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
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bitfld.long 0x8 16. "DIN11_8_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
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bitfld.long 0x8 8. "DIN11_8_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
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bitfld.long 0x8 0. "DIN11_8_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
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line.long 0xC "DIN15_12,Data input 15 to 12"
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bitfld.long 0xC 24. "DIN15_12_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
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bitfld.long 0xC 16. "DIN15_12_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
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bitfld.long 0xC 8. "DIN15_12_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
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bitfld.long 0xC 0. "DIN15_12_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
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line.long 0x10 "DIN19_16,Data input 19 to 16"
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bitfld.long 0x10 24. "DIN19_16_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
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bitfld.long 0x10 16. "DIN19_16_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
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bitfld.long 0x10 8. "DIN19_16_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x10 0. "DIN19_16_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DIN23_20,Data input 23 to 20"
|
|
bitfld.long 0x14 24. "DIN23_20_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
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|
bitfld.long 0x14 16. "DIN23_20_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DIN23_20_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x14 0. "DIN23_20_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
|
|
line.long 0x18 "DIN27_24,Data input 27 to 24"
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|
bitfld.long 0x18 24. "DIN27_24_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 16. "DIN27_24_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DIN27_24_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x18 0. "DIN27_24_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
|
|
line.long 0x1C "DIN31_28,Data input 31 to 28"
|
|
bitfld.long 0x1C 24. "DIN31_28_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 16. "DIN31_28_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
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|
bitfld.long 0x1C 8. "DIN31_28_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x1C 0. "DIN31_28_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
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|
rgroup.long 0x1380++0x3
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|
line.long 0x0 "DIN31_0,Data input 31 to 0"
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|
bitfld.long 0x0 31. "DIN31_0_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 30. "DIN31_0_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 29. "DIN31_0_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x0 28. "DIN31_0_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 27. "DIN31_0_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 26. "DIN31_0_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 25. "DIN31_0_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 24. "DIN31_0_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 23. "DIN31_0_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 22. "DIN31_0_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 21. "DIN31_0_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 20. "DIN31_0_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
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|
newline
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|
bitfld.long 0x0 19. "DIN31_0_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 18. "DIN31_0_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 17. "DIN31_0_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x0 16. "DIN31_0_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 15. "DIN31_0_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 14. "DIN31_0_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 13. "DIN31_0_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 12. "DIN31_0_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 11. "DIN31_0_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x0 10. "DIN31_0_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 9. "DIN31_0_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "DIN31_0_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 7. "DIN31_0_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 6. "DIN31_0_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 5. "DIN31_0_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 4. "DIN31_0_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 3. "DIN31_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 2. "DIN31_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x0 1. "DIN31_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 0. "DIN31_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
|
|
group.long 0x1390++0x3
|
|
line.long 0x0 "POLARITY15_0,Polarity 15 to 0"
|
|
bitfld.long 0x0 30.--31. "POLARITY15_0_DIO15,Enables and configures edge detection polarity for DIO15." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 28.--29. "POLARITY15_0_DIO14,Enables and configures edge detection polarity for DIO14." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 26.--27. "POLARITY15_0_DIO13,Enables and configures edge detection polarity for DIO13." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "POLARITY15_0_DIO12,Enables and configures edge detection polarity for DIO12." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
bitfld.long 0x0 22.--23. "POLARITY15_0_DIO11,Enables and configures edge detection polarity for DIO11." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 20.--21. "POLARITY15_0_DIO10,Enables and configures edge detection polarity for DIO10." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
newline
|
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bitfld.long 0x0 18.--19. "POLARITY15_0_DIO9,Enables and configures edge detection polarity for DIO9." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 16.--17. "POLARITY15_0_DIO8,Enables and configures edge detection polarity for DIO8." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
bitfld.long 0x0 14.--15. "POLARITY15_0_DIO7,Enables and configures edge detection polarity for DIO7." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "POLARITY15_0_DIO6,Enables and configures edge detection polarity for DIO6." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
bitfld.long 0x0 10.--11. "POLARITY15_0_DIO5,Enables and configures edge detection polarity for DIO5." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 8.--9. "POLARITY15_0_DIO4,Enables and configures edge detection polarity for DIO4." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
newline
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bitfld.long 0x0 6.--7. "POLARITY15_0_DIO3,Enables and configures edge detection polarity for DIO3." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 4.--5. "POLARITY15_0_DIO2,Enables and configures edge detection polarity for DIO2." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 2.--3. "POLARITY15_0_DIO1,Enables and configures edge detection polarity for DIO1." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
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bitfld.long 0x0 0.--1. "POLARITY15_0_DIO0,Enables and configures edge detection polarity for DIO0." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
group.long 0x13A0++0x3
|
|
line.long 0x0 "POLARITY31_16,Polarity 31 to 16"
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bitfld.long 0x0 30.--31. "POLARITY31_16_DIO31,Enables and configures edge detection polarity for DIO31." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 28.--29. "POLARITY31_16_DIO30,Enables and configures edge detection polarity for DIO30." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 26.--27. "POLARITY31_16_DIO29,Enables and configures edge detection polarity for DIO29." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 24.--25. "POLARITY31_16_DIO28,Enables and configures edge detection polarity for DIO28." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 22.--23. "POLARITY31_16_DIO27,Enables and configures edge detection polarity for DIO27." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 20.--21. "POLARITY31_16_DIO26,Enables and configures edge detection polarity for DIO26." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 18.--19. "POLARITY31_16_DIO25,Enables and configures edge detection polarity for DIO25." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 16.--17. "POLARITY31_16_DIO24,Enables and configures edge detection polarity for DIO24." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 14.--15. "POLARITY31_16_DIO23,Enables and configures edge detection polarity for DIO23." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 12.--13. "POLARITY31_16_DIO22,Enables and configures edge detection polarity for DIO22." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 10.--11. "POLARITY31_16_DIO21,Enables and configures edge detection polarity for DIO21." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 8.--9. "POLARITY31_16_DIO20,Enables and configures edge detection polarity for DIO20." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 6.--7. "POLARITY31_16_DIO19,Enables and configures edge detection polarity for DIO19." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
bitfld.long 0x0 4.--5. "POLARITY31_16_DIO18,Enables and configures edge detection polarity for DIO18." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 2.--3. "POLARITY31_16_DIO17,Enables and configures edge detection polarity for DIO17." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 0.--1. "POLARITY31_16_DIO16,Enables and configures edge detection polarity for DIO16." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
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group.long 0x1400++0x7
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line.long 0x0 "CTL,FAST WAKE GLOBAL EN"
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bitfld.long 0x0 0. "CTL_FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: NOT_GLOBAL_EN,1: GLOBAL_EN"
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line.long 0x4 "FASTWAKE,FAST WAKE ENABLE"
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bitfld.long 0x4 31. "FASTWAKE_DIN31,Enable fastwake feature for DIN31" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 30. "FASTWAKE_DIN30,Enable fastwake feature for DIN30" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 29. "FASTWAKE_DIN29,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 28. "FASTWAKE_DIN28,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 27. "FASTWAKE_DIN27,Enable fastwake feature for DIN27" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 26. "FASTWAKE_DIN26,Enable fastwake feature for DIN26" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 25. "FASTWAKE_DIN25,Enable fastwake feature for DIN25" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 24. "FASTWAKE_DIN24,Enable fastwake feature for DIN24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 23. "FASTWAKE_DIN23,Enable fastwake feature for DIN23" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 22. "FASTWAKE_DIN22,Enable fastwake feature for DIN22" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 21. "FASTWAKE_DIN21,Enable fastwake feature for DIN21" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 20. "FASTWAKE_DIN20,Enable fastwake feature for DIN20" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 19. "FASTWAKE_DIN19,Enable fastwake feature for DIN19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 18. "FASTWAKE_DIN18,Enable fastwake feature for DIN18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 17. "FASTWAKE_DIN17,Enable fastwake feature for DIN17" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 16. "FASTWAKE_DIN16,Enable fastwake feature for DIN16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 15. "FASTWAKE_DIN15,Enable fastwake feature for DIN15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 14. "FASTWAKE_DIN14,Enable fastwake feature for DIN14" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 13. "FASTWAKE_DIN13,Enable fastwake feature for DIN13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 12. "FASTWAKE_DIN12,Enable fastwake feature for DIN12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 11. "FASTWAKE_DIN11,Enable fastwake feature for DIN11" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 10. "FASTWAKE_DIN10,Enable fastwake feature for DIN10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 9. "FASTWAKE_DIN9,Enable fastwake feature for DIN9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "FASTWAKE_DIN8,Enable fastwake feature for DIN8" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 7. "FASTWAKE_DIN7,Enable fastwake feature for DIN7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "FASTWAKE_DIN6,Enable fastwake feature for DIN6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "FASTWAKE_DIN5,Enable fastwake feature for DIN5" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 4. "FASTWAKE_DIN4,Enable fastwake feature for DIN4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 3. "FASTWAKE_DIN3,Enable fastwake feature for DIN3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "FASTWAKE_DIN2,Enable fastwake feature for DIN2" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 1. "FASTWAKE_DIN1,Enable fastwake feature for DIN1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "FASTWAKE_DIN0,Enable fastwake feature for DIN0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "SUB0CFG,Subscriber 0 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB0CFG_INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB0CFG_OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB0CFG_ENABLE,This bit is used to enable subscriber 0 event." "0: CLR,1: SET"
|
|
group.long 0x1508++0xB
|
|
line.long 0x0 "FILTEREN15_0,Filter Enable 15 to 0"
|
|
bitfld.long 0x0 30.--31. "FILTEREN15_0_DIN15,Programmable counter length of digital glitch filter for DIN15" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 28.--29. "FILTEREN15_0_DIN14,Programmable counter length of digital glitch filter for DIN14" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 26.--27. "FILTEREN15_0_DIN13,Programmable counter length of digital glitch filter for DIN13" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
|
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bitfld.long 0x0 24.--25. "FILTEREN15_0_DIN12,Programmable counter length of digital glitch filter for DIN12" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 22.--23. "FILTEREN15_0_DIN11,Programmable counter length of digital glitch filter for DIN11" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 20.--21. "FILTEREN15_0_DIN10,Programmable counter length of digital glitch filter for DIN10" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
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bitfld.long 0x0 18.--19. "FILTEREN15_0_DIN9,Programmable counter length of digital glitch filter for DIN9" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 16.--17. "FILTEREN15_0_DIN8,Programmable counter length of digital glitch filter for DIN8" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 14.--15. "FILTEREN15_0_DIN7,Programmable counter length of digital glitch filter for DIN7" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
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bitfld.long 0x0 12.--13. "FILTEREN15_0_DIN6,Programmable counter length of digital glitch filter for DIN6" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 10.--11. "FILTEREN15_0_DIN5,Programmable counter length of digital glitch filter for DIN5" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 8.--9. "FILTEREN15_0_DIN4,Programmable counter length of digital glitch filter for DIN4" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
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bitfld.long 0x0 6.--7. "FILTEREN15_0_DIN3,Programmable counter length of digital glitch filter for DIN3" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 4.--5. "FILTEREN15_0_DIN2,Programmable counter length of digital glitch filter for DIN2" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 2.--3. "FILTEREN15_0_DIN1,Programmable counter length of digital glitch filter for DIN1" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "FILTEREN15_0_DIN0,Programmable counter length of digital glitch filter for DIN0" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
line.long 0x4 "FILTEREN31_16,Filter Enable 31 to 16"
|
|
bitfld.long 0x4 30.--31. "FILTEREN31_16_DIN31,Programmable counter length of digital glitch filter for DIN31" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 28.--29. "FILTEREN31_16_DIN30,Programmable counter length of digital glitch filter for DIN30" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 26.--27. "FILTEREN31_16_DIN29,Programmable counter length of digital glitch filter for DIN29" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "FILTEREN31_16_DIN28,Programmable counter length of digital glitch filter for DIN28" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 22.--23. "FILTEREN31_16_DIN27,Programmable counter length of digital glitch filter for DIN27" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 20.--21. "FILTEREN31_16_DIN26,Programmable counter length of digital glitch filter for DIN26" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 18.--19. "FILTEREN31_16_DIN25,Programmable counter length of digital glitch filter for DIN25" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 16.--17. "FILTEREN31_16_DIN24,Programmable counter length of digital glitch filter for DIN24" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 14.--15. "FILTEREN31_16_DIN23,Programmable counter length of digital glitch filter for DIN23" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "FILTEREN31_16_DIN22,Programmable counter length of digital glitch filter for DIN22" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 10.--11. "FILTEREN31_16_DIN21,Programmable counter length of digital glitch filter for DIN21" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 8.--9. "FILTEREN31_16_DIN20,Programmable counter length of digital glitch filter for DIN20" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FILTEREN31_16_DIN19,Programmable counter length of digital glitch filter for DIN19" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 4.--5. "FILTEREN31_16_DIN18,Programmable counter length of digital glitch filter for DIN18" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 2.--3. "FILTEREN31_16_DIN17,Programmable counter length of digital glitch filter for DIN17" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "FILTEREN31_16_DIN16,Programmable counter length of digital glitch filter for DIN16" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
line.long 0x8 "DMAMASK,DMA Write MASK"
|
|
bitfld.long 0x8 31. "DMAMASK_DOUT31,DMA is allowed to modify DOUT31" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 30. "DMAMASK_DOUT30,DMA is allowed to modify DOUT30" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 29. "DMAMASK_DOUT29,DMA is allowed to modify DOUT29" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 28. "DMAMASK_DOUT28,DMA is allowed to modify DOUT28" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 27. "DMAMASK_DOUT27,DMA is allowed to modify DOUT27" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 26. "DMAMASK_DOUT26,DMA is allowed to modify DOUT26" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 25. "DMAMASK_DOUT25,DMA is allowed to modify DOUT25" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 24. "DMAMASK_DOUT24,DMA is allowed to modify DOUT24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 23. "DMAMASK_DOUT23,DMA is allowed to modify DOUT23" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 22. "DMAMASK_DOUT22,DMA is allowed to modify DOUT22" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 21. "DMAMASK_DOUT21,DMA is allowed to modify DOUT21" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 20. "DMAMASK_DOUT20,DMA is allowed to modify DOUT20" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 19. "DMAMASK_DOUT19,DMA is allowed to modify DOUT19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 18. "DMAMASK_DOUT18,DMA is allowed to modify DOUT18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 17. "DMAMASK_DOUT17,DMA is allowed to modify DOUT17" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 16. "DMAMASK_DOUT16,DMA is allowed to modify DOUT16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 15. "DMAMASK_DOUT15,DMA is allowed to modify DOUT15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 14. "DMAMASK_DOUT14,DMA is allowed to modify DOUT14" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 13. "DMAMASK_DOUT13,DMA is allowed to modify DOUT13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 12. "DMAMASK_DOUT12,DMA is allowed to modify DOUT12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 11. "DMAMASK_DOUT11,DMA is allowed to modify DOUT11" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 10. "DMAMASK_DOUT10,DMA is allowed to modify DOUT10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 9. "DMAMASK_DOUT9,DMA is allowed to modify DOUT9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "DMAMASK_DOUT8,DMA is allowed to modify DOUT8" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAMASK_DOUT7,DMA is allowed to modify DOUT7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 6. "DMAMASK_DOUT6,DMA is allowed to modify DOUT6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 5. "DMAMASK_DOUT5,DMA is allowed to modify DOUT5" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "DMAMASK_DOUT4,DMA is allowed to modify DOUT4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 3. "DMAMASK_DOUT3,DMA is allowed to modify DOUT3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 2. "DMAMASK_DOUT2,DMA is allowed to modify DOUT2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "DMAMASK_DOUT1,DMA is allowed to modify DOUT1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 0. "DMAMASK_DOUT0,DMA is allowed to modify DOUT0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1520++0x3
|
|
line.long 0x0 "SUB1CFG,Subscriber 1 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB1CFG_INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB1CFG_OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB1CFG_ENABLE,This bit is used to enable subscriber 1 event." "0: CLR,1: SET"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "GPIOA"
|
|
base ad:0x400A0000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1010++0x3
|
|
line.long 0x0 "CLKOVR,Clock Override"
|
|
bitfld.long 0x0 1. "CLKOVR_RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: RUN,1: STOP"
|
|
bitfld.long 0x0 0. "CLKOVR_OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT0_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "INT_EVENT0_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "INT_EVENT0_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "INT_EVENT0_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "INT_EVENT0_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "INT_EVENT0_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "INT_EVENT0_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "INT_EVENT0_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "INT_EVENT0_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "INT_EVENT0_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "INT_EVENT0_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 15. "INT_EVENT1_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 15. "INT_EVENT1_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 15. "INT_EVENT1_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 15. "INT_EVENT1_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 15. "INT_EVENT1_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT1_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "INT_EVENT1_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT1_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "INT_EVENT1_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT1_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT1_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT2_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT2_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT2_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "INT_EVENT2_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "INT_EVENT2_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "INT_EVENT2_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "INT_EVENT2_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "INT_EVENT2_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "INT_EVENT2_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "INT_EVENT2_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "INT_EVENT2_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "INT_EVENT2_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "INT_EVENT2_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
wgroup.long 0x1200++0x1F
|
|
line.long 0x0 "DOUT3_0,Data output 3 to 0"
|
|
bitfld.long 0x0 24. "DOUT3_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 16. "DOUT3_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 8. "DOUT3_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 0. "DOUT3_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x4 "DOUT7_4,Data output 7 to 4"
|
|
bitfld.long 0x4 24. "DOUT7_4_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 16. "DOUT7_4_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 8. "DOUT7_4_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x4 0. "DOUT7_4_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
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line.long 0x8 "DOUT11_8,Data output 11 to 8"
|
|
bitfld.long 0x8 24. "DOUT11_8_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 16. "DOUT11_8_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 8. "DOUT11_8_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x8 0. "DOUT11_8_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0xC "DOUT15_12,Data output 15 to 12"
|
|
bitfld.long 0xC 24. "DOUT15_12_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "DOUT15_12_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "DOUT15_12_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0xC 0. "DOUT15_12_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DOUT19_16,Data output 19 to 16"
|
|
bitfld.long 0x10 24. "DOUT19_16_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DOUT19_16_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DOUT19_16_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x10 0. "DOUT19_16_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DOUT23_20,Data output 23 to 20"
|
|
bitfld.long 0x14 24. "DOUT23_20_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 16. "DOUT23_20_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DOUT23_20_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x14 0. "DOUT23_20_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x18 "DOUT27_24,Data output 27 to 24"
|
|
bitfld.long 0x18 24. "DOUT27_24_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 16. "DOUT27_24_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DOUT27_24_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x18 0. "DOUT27_24_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x1C "DOUT31_28,Data output 31 to 28"
|
|
bitfld.long 0x1C 24. "DOUT31_28_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 16. "DOUT31_28_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 8. "DOUT31_28_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x1C 0. "DOUT31_28_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
group.long 0x1280++0x3
|
|
line.long 0x0 "DOUT31_0,Data output 31 to 0"
|
|
bitfld.long 0x0 31. "DOUT31_0_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 30. "DOUT31_0_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 29. "DOUT31_0_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 28. "DOUT31_0_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 27. "DOUT31_0_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 26. "DOUT31_0_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 25. "DOUT31_0_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 24. "DOUT31_0_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 23. "DOUT31_0_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 22. "DOUT31_0_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 21. "DOUT31_0_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 20. "DOUT31_0_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 19. "DOUT31_0_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 18. "DOUT31_0_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 17. "DOUT31_0_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DOUT31_0_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 15. "DOUT31_0_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 14. "DOUT31_0_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 13. "DOUT31_0_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 12. "DOUT31_0_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 11. "DOUT31_0_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 10. "DOUT31_0_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 9. "DOUT31_0_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DOUT31_0_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 7. "DOUT31_0_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 6. "DOUT31_0_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 5. "DOUT31_0_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 4. "DOUT31_0_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 3. "DOUT31_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 2. "DOUT31_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 1. "DOUT31_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DOUT31_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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wgroup.long 0x1290++0x3
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line.long 0x0 "DOUTSET31_0,Data output set 31 to 0"
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bitfld.long 0x0 31. "DOUTSET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOUTSET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOUTSET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOUTSET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOUTSET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOUTSET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOUTSET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOUTSET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOUTSET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOUTSET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOUTSET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOUTSET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOUTSET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOUTSET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOUTSET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOUTSET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOUTSET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOUTSET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOUTSET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOUTSET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOUTSET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOUTSET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOUTSET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOUTSET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOUTSET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOUTSET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOUTSET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOUTSET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOUTSET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOUTSET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOUTSET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOUTSET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12A0++0x3
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line.long 0x0 "DOUTCLR31_0,Data output clear 31 to 0"
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bitfld.long 0x0 31. "DOUTCLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOUTCLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOUTCLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOUTCLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOUTCLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOUTCLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOUTCLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOUTCLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOUTCLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOUTCLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOUTCLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOUTCLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOUTCLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOUTCLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOUTCLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOUTCLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOUTCLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOUTCLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOUTCLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOUTCLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOUTCLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOUTCLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOUTCLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOUTCLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOUTCLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOUTCLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOUTCLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOUTCLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOUTCLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOUTCLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOUTCLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOUTCLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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wgroup.long 0x12B0++0x3
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line.long 0x0 "DOUTTGL31_0,Data output toggle 31 to 0"
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bitfld.long 0x0 31. "DOUTTGL31_0_DIO31,This bit is used to toggle DIO31 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 30. "DOUTTGL31_0_DIO30,This bit is used to toggle DIO30 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 29. "DOUTTGL31_0_DIO29,This bit is used to toggle DIO29 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 28. "DOUTTGL31_0_DIO28,This bit is used to toggle DIO28 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 27. "DOUTTGL31_0_DIO27,This bit is used to toggle DIO27 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 26. "DOUTTGL31_0_DIO26,This bit is used to toggle DIO26 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 25. "DOUTTGL31_0_DIO25,This bit is used to toggle DIO25 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 24. "DOUTTGL31_0_DIO24,This bit is used to toggle DIO24 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 23. "DOUTTGL31_0_DIO23,This bit is used to toggle DIO23 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 22. "DOUTTGL31_0_DIO22,This bit is used to toggle DIO22 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 21. "DOUTTGL31_0_DIO21,This bit is used to toggle DIO21 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 20. "DOUTTGL31_0_DIO20,This bit is used to toggle DIO20 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 19. "DOUTTGL31_0_DIO19,This bit is used to toggle DIO19 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 18. "DOUTTGL31_0_DIO18,This bit is used to toggle DIO18 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 17. "DOUTTGL31_0_DIO17,This bit is used to toggle DIO17 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 16. "DOUTTGL31_0_DIO16,This bit is used to toggle DIO16 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 15. "DOUTTGL31_0_DIO15,This bit is used to toggle DIO15 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 14. "DOUTTGL31_0_DIO14,This bit is used to toggle DIO14 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 13. "DOUTTGL31_0_DIO13,This bit is used to toggle DIO13 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 12. "DOUTTGL31_0_DIO12,This bit is used to toggle DIO12 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 11. "DOUTTGL31_0_DIO11,This bit is used to toggle DIO11 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 10. "DOUTTGL31_0_DIO10,This bit is used to toggle DIO10 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 9. "DOUTTGL31_0_DIO9,This bit is used to toggle DIO9 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 8. "DOUTTGL31_0_DIO8,This bit is used to toggle DIO8 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 7. "DOUTTGL31_0_DIO7,This bit is used to toggle DIO7 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 6. "DOUTTGL31_0_DIO6,This bit is used to toggle DIO6 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 5. "DOUTTGL31_0_DIO5,This bit is used to toggle DIO5 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 4. "DOUTTGL31_0_DIO4,This bit is used to toggle DIO4 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 3. "DOUTTGL31_0_DIO3,This bit is used to toggle DIO3 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 2. "DOUTTGL31_0_DIO2,This bit is used to toggle DIO2 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 1. "DOUTTGL31_0_DIO1,This bit is used to toggle DIO1 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 0. "DOUTTGL31_0_DIO0,This bit is used to toggle DIO0 output." "0: NO_EFFECT,1: TOGGLE"
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group.long 0x12C0++0x3
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line.long 0x0 "DOE31_0,Data output enable 31 to 0"
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bitfld.long 0x0 31. "DOE31_0_DIO31,Enables data output for DIO31." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 30. "DOE31_0_DIO30,Enables data output for DIO30." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 29. "DOE31_0_DIO29,Enables data output for DIO29." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 28. "DOE31_0_DIO28,Enables data output for DIO28." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 27. "DOE31_0_DIO27,Enables data output for DIO27." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 26. "DOE31_0_DIO26,Enables data output for DIO26." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 25. "DOE31_0_DIO25,Enables data output for DIO25." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 24. "DOE31_0_DIO24,Enables data output for DIO24." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 23. "DOE31_0_DIO23,Enables data output for DIO23." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 22. "DOE31_0_DIO22,Enables data output for DIO22." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 21. "DOE31_0_DIO21,Enables data output for DIO21." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 20. "DOE31_0_DIO20,Enables data output for DIO20." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 19. "DOE31_0_DIO19,Enables data output for DIO19." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 18. "DOE31_0_DIO18,Enables data output for DIO18." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 17. "DOE31_0_DIO17,Enables data output for DIO17." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 16. "DOE31_0_DIO16,Enables data output for DIO16." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 15. "DOE31_0_DIO15,Enables data output for DIO15." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 14. "DOE31_0_DIO14,Enables data output for DIO14." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 13. "DOE31_0_DIO13,Enables data output for DIO13." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "DOE31_0_DIO12,Enables data output for DIO12." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 11. "DOE31_0_DIO11,Enables data output for DIO11." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 10. "DOE31_0_DIO10,Enables data output for DIO10." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 9. "DOE31_0_DIO9,Enables data output for DIO9." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 8. "DOE31_0_DIO8,Enables data output for DIO8." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 7. "DOE31_0_DIO7,Enables data output for DIO7." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 6. "DOE31_0_DIO6,Enables data output for DIO6." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 5. "DOE31_0_DIO5,Enables data output for DIO5." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 4. "DOE31_0_DIO4,Enables data output for DIO4." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "DOE31_0_DIO3,Enables data output for DIO3." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "DOE31_0_DIO2,Enables data output for DIO2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 1. "DOE31_0_DIO1,Enables data output for DIO1." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "DOE31_0_DIO0,Enables data output for DIO0." "0: DISABLE,1: ENABLE"
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wgroup.long 0x12D0++0x3
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line.long 0x0 "DOESET31_0,Data output enable set 31 to 0"
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bitfld.long 0x0 31. "DOESET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOESET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOESET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOESET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOESET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOESET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOESET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOESET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOESET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOESET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOESET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOESET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOESET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOESET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOESET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOESET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOESET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOESET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOESET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOESET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOESET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOESET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOESET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOESET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOESET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOESET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOESET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOESET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOESET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOESET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOESET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOESET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12E0++0x3
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line.long 0x0 "DOECLR31_0,Data output enable clear 31 to 0"
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bitfld.long 0x0 31. "DOECLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOECLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOECLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOECLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOECLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOECLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOECLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOECLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOECLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOECLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOECLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOECLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOECLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOECLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOECLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOECLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOECLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOECLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOECLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOECLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOECLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOECLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOECLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOECLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOECLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOECLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOECLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOECLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOECLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOECLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOECLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOECLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1300++0x1F
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line.long 0x0 "DIN3_0,Data input 3 to 0"
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bitfld.long 0x0 24. "DIN3_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DIN3_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DIN3_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DIN3_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
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line.long 0x4 "DIN7_4,Data input 7 to 4"
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bitfld.long 0x4 24. "DIN7_4_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
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bitfld.long 0x4 16. "DIN7_4_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
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bitfld.long 0x4 8. "DIN7_4_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
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bitfld.long 0x4 0. "DIN7_4_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
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line.long 0x8 "DIN11_8,Data input 11 to 8"
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bitfld.long 0x8 24. "DIN11_8_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
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bitfld.long 0x8 16. "DIN11_8_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
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bitfld.long 0x8 8. "DIN11_8_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
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bitfld.long 0x8 0. "DIN11_8_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
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line.long 0xC "DIN15_12,Data input 15 to 12"
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bitfld.long 0xC 24. "DIN15_12_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
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bitfld.long 0xC 16. "DIN15_12_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
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bitfld.long 0xC 8. "DIN15_12_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0xC 0. "DIN15_12_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DIN19_16,Data input 19 to 16"
|
|
bitfld.long 0x10 24. "DIN19_16_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DIN19_16_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DIN19_16_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x10 0. "DIN19_16_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DIN23_20,Data input 23 to 20"
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|
bitfld.long 0x14 24. "DIN23_20_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
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|
bitfld.long 0x14 16. "DIN23_20_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DIN23_20_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
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|
newline
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|
bitfld.long 0x14 0. "DIN23_20_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
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|
line.long 0x18 "DIN27_24,Data input 27 to 24"
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|
bitfld.long 0x18 24. "DIN27_24_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
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|
bitfld.long 0x18 16. "DIN27_24_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
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|
bitfld.long 0x18 8. "DIN27_24_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x18 0. "DIN27_24_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
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|
line.long 0x1C "DIN31_28,Data input 31 to 28"
|
|
bitfld.long 0x1C 24. "DIN31_28_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
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|
bitfld.long 0x1C 16. "DIN31_28_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
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|
bitfld.long 0x1C 8. "DIN31_28_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
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|
newline
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|
bitfld.long 0x1C 0. "DIN31_28_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
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|
rgroup.long 0x1380++0x3
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|
line.long 0x0 "DIN31_0,Data input 31 to 0"
|
|
bitfld.long 0x0 31. "DIN31_0_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 30. "DIN31_0_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 29. "DIN31_0_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 28. "DIN31_0_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 27. "DIN31_0_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 26. "DIN31_0_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 25. "DIN31_0_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 24. "DIN31_0_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 23. "DIN31_0_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 22. "DIN31_0_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 21. "DIN31_0_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 20. "DIN31_0_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
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|
newline
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|
bitfld.long 0x0 19. "DIN31_0_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 18. "DIN31_0_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 17. "DIN31_0_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
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newline
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bitfld.long 0x0 16. "DIN31_0_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 15. "DIN31_0_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 14. "DIN31_0_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 13. "DIN31_0_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 12. "DIN31_0_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 11. "DIN31_0_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 10. "DIN31_0_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 9. "DIN31_0_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "DIN31_0_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 7. "DIN31_0_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 6. "DIN31_0_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 5. "DIN31_0_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 4. "DIN31_0_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 3. "DIN31_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 2. "DIN31_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 1. "DIN31_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 0. "DIN31_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
|
|
group.long 0x1390++0x3
|
|
line.long 0x0 "POLARITY15_0,Polarity 15 to 0"
|
|
bitfld.long 0x0 30.--31. "POLARITY15_0_DIO15,Enables and configures edge detection polarity for DIO15." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 28.--29. "POLARITY15_0_DIO14,Enables and configures edge detection polarity for DIO14." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 26.--27. "POLARITY15_0_DIO13,Enables and configures edge detection polarity for DIO13." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
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bitfld.long 0x0 24.--25. "POLARITY15_0_DIO12,Enables and configures edge detection polarity for DIO12." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 22.--23. "POLARITY15_0_DIO11,Enables and configures edge detection polarity for DIO11." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 20.--21. "POLARITY15_0_DIO10,Enables and configures edge detection polarity for DIO10." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
newline
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bitfld.long 0x0 18.--19. "POLARITY15_0_DIO9,Enables and configures edge detection polarity for DIO9." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 16.--17. "POLARITY15_0_DIO8,Enables and configures edge detection polarity for DIO8." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 14.--15. "POLARITY15_0_DIO7,Enables and configures edge detection polarity for DIO7." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 12.--13. "POLARITY15_0_DIO6,Enables and configures edge detection polarity for DIO6." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 10.--11. "POLARITY15_0_DIO5,Enables and configures edge detection polarity for DIO5." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 8.--9. "POLARITY15_0_DIO4,Enables and configures edge detection polarity for DIO4." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 6.--7. "POLARITY15_0_DIO3,Enables and configures edge detection polarity for DIO3." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 4.--5. "POLARITY15_0_DIO2,Enables and configures edge detection polarity for DIO2." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 2.--3. "POLARITY15_0_DIO1,Enables and configures edge detection polarity for DIO1." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
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bitfld.long 0x0 0.--1. "POLARITY15_0_DIO0,Enables and configures edge detection polarity for DIO0." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
group.long 0x13A0++0x3
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line.long 0x0 "POLARITY31_16,Polarity 31 to 16"
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bitfld.long 0x0 30.--31. "POLARITY31_16_DIO31,Enables and configures edge detection polarity for DIO31." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 28.--29. "POLARITY31_16_DIO30,Enables and configures edge detection polarity for DIO30." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 26.--27. "POLARITY31_16_DIO29,Enables and configures edge detection polarity for DIO29." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 24.--25. "POLARITY31_16_DIO28,Enables and configures edge detection polarity for DIO28." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 22.--23. "POLARITY31_16_DIO27,Enables and configures edge detection polarity for DIO27." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 20.--21. "POLARITY31_16_DIO26,Enables and configures edge detection polarity for DIO26." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 18.--19. "POLARITY31_16_DIO25,Enables and configures edge detection polarity for DIO25." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 16.--17. "POLARITY31_16_DIO24,Enables and configures edge detection polarity for DIO24." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 14.--15. "POLARITY31_16_DIO23,Enables and configures edge detection polarity for DIO23." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 12.--13. "POLARITY31_16_DIO22,Enables and configures edge detection polarity for DIO22." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 10.--11. "POLARITY31_16_DIO21,Enables and configures edge detection polarity for DIO21." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 8.--9. "POLARITY31_16_DIO20,Enables and configures edge detection polarity for DIO20." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
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bitfld.long 0x0 6.--7. "POLARITY31_16_DIO19,Enables and configures edge detection polarity for DIO19." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 4.--5. "POLARITY31_16_DIO18,Enables and configures edge detection polarity for DIO18." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 2.--3. "POLARITY31_16_DIO17,Enables and configures edge detection polarity for DIO17." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 0.--1. "POLARITY31_16_DIO16,Enables and configures edge detection polarity for DIO16." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
group.long 0x1400++0x7
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line.long 0x0 "CTL,FAST WAKE GLOBAL EN"
|
|
bitfld.long 0x0 0. "CTL_FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: NOT_GLOBAL_EN,1: GLOBAL_EN"
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line.long 0x4 "FASTWAKE,FAST WAKE ENABLE"
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bitfld.long 0x4 31. "FASTWAKE_DIN31,Enable fastwake feature for DIN31" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 30. "FASTWAKE_DIN30,Enable fastwake feature for DIN30" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 29. "FASTWAKE_DIN29,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 28. "FASTWAKE_DIN28,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 27. "FASTWAKE_DIN27,Enable fastwake feature for DIN27" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 26. "FASTWAKE_DIN26,Enable fastwake feature for DIN26" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 25. "FASTWAKE_DIN25,Enable fastwake feature for DIN25" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 24. "FASTWAKE_DIN24,Enable fastwake feature for DIN24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 23. "FASTWAKE_DIN23,Enable fastwake feature for DIN23" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 22. "FASTWAKE_DIN22,Enable fastwake feature for DIN22" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 21. "FASTWAKE_DIN21,Enable fastwake feature for DIN21" "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x4 20. "FASTWAKE_DIN20,Enable fastwake feature for DIN20" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 19. "FASTWAKE_DIN19,Enable fastwake feature for DIN19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 18. "FASTWAKE_DIN18,Enable fastwake feature for DIN18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 17. "FASTWAKE_DIN17,Enable fastwake feature for DIN17" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 16. "FASTWAKE_DIN16,Enable fastwake feature for DIN16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 15. "FASTWAKE_DIN15,Enable fastwake feature for DIN15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 14. "FASTWAKE_DIN14,Enable fastwake feature for DIN14" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 13. "FASTWAKE_DIN13,Enable fastwake feature for DIN13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 12. "FASTWAKE_DIN12,Enable fastwake feature for DIN12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 11. "FASTWAKE_DIN11,Enable fastwake feature for DIN11" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 10. "FASTWAKE_DIN10,Enable fastwake feature for DIN10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 9. "FASTWAKE_DIN9,Enable fastwake feature for DIN9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "FASTWAKE_DIN8,Enable fastwake feature for DIN8" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 7. "FASTWAKE_DIN7,Enable fastwake feature for DIN7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "FASTWAKE_DIN6,Enable fastwake feature for DIN6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "FASTWAKE_DIN5,Enable fastwake feature for DIN5" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 4. "FASTWAKE_DIN4,Enable fastwake feature for DIN4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 3. "FASTWAKE_DIN3,Enable fastwake feature for DIN3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "FASTWAKE_DIN2,Enable fastwake feature for DIN2" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 1. "FASTWAKE_DIN1,Enable fastwake feature for DIN1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "FASTWAKE_DIN0,Enable fastwake feature for DIN0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "SUB0CFG,Subscriber 0 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB0CFG_INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB0CFG_OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB0CFG_ENABLE,This bit is used to enable subscriber 0 event." "0: CLR,1: SET"
|
|
group.long 0x1508++0xB
|
|
line.long 0x0 "FILTEREN15_0,Filter Enable 15 to 0"
|
|
bitfld.long 0x0 30.--31. "FILTEREN15_0_DIN15,Programmable counter length of digital glitch filter for DIN15" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 28.--29. "FILTEREN15_0_DIN14,Programmable counter length of digital glitch filter for DIN14" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 26.--27. "FILTEREN15_0_DIN13,Programmable counter length of digital glitch filter for DIN13" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
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bitfld.long 0x0 24.--25. "FILTEREN15_0_DIN12,Programmable counter length of digital glitch filter for DIN12" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 22.--23. "FILTEREN15_0_DIN11,Programmable counter length of digital glitch filter for DIN11" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 20.--21. "FILTEREN15_0_DIN10,Programmable counter length of digital glitch filter for DIN10" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
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bitfld.long 0x0 18.--19. "FILTEREN15_0_DIN9,Programmable counter length of digital glitch filter for DIN9" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 16.--17. "FILTEREN15_0_DIN8,Programmable counter length of digital glitch filter for DIN8" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 14.--15. "FILTEREN15_0_DIN7,Programmable counter length of digital glitch filter for DIN7" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
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bitfld.long 0x0 12.--13. "FILTEREN15_0_DIN6,Programmable counter length of digital glitch filter for DIN6" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 10.--11. "FILTEREN15_0_DIN5,Programmable counter length of digital glitch filter for DIN5" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 8.--9. "FILTEREN15_0_DIN4,Programmable counter length of digital glitch filter for DIN4" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "FILTEREN15_0_DIN3,Programmable counter length of digital glitch filter for DIN3" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 4.--5. "FILTEREN15_0_DIN2,Programmable counter length of digital glitch filter for DIN2" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 2.--3. "FILTEREN15_0_DIN1,Programmable counter length of digital glitch filter for DIN1" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "FILTEREN15_0_DIN0,Programmable counter length of digital glitch filter for DIN0" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
line.long 0x4 "FILTEREN31_16,Filter Enable 31 to 16"
|
|
bitfld.long 0x4 30.--31. "FILTEREN31_16_DIN31,Programmable counter length of digital glitch filter for DIN31" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 28.--29. "FILTEREN31_16_DIN30,Programmable counter length of digital glitch filter for DIN30" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 26.--27. "FILTEREN31_16_DIN29,Programmable counter length of digital glitch filter for DIN29" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "FILTEREN31_16_DIN28,Programmable counter length of digital glitch filter for DIN28" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 22.--23. "FILTEREN31_16_DIN27,Programmable counter length of digital glitch filter for DIN27" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 20.--21. "FILTEREN31_16_DIN26,Programmable counter length of digital glitch filter for DIN26" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 18.--19. "FILTEREN31_16_DIN25,Programmable counter length of digital glitch filter for DIN25" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 16.--17. "FILTEREN31_16_DIN24,Programmable counter length of digital glitch filter for DIN24" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 14.--15. "FILTEREN31_16_DIN23,Programmable counter length of digital glitch filter for DIN23" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "FILTEREN31_16_DIN22,Programmable counter length of digital glitch filter for DIN22" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 10.--11. "FILTEREN31_16_DIN21,Programmable counter length of digital glitch filter for DIN21" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 8.--9. "FILTEREN31_16_DIN20,Programmable counter length of digital glitch filter for DIN20" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FILTEREN31_16_DIN19,Programmable counter length of digital glitch filter for DIN19" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 4.--5. "FILTEREN31_16_DIN18,Programmable counter length of digital glitch filter for DIN18" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 2.--3. "FILTEREN31_16_DIN17,Programmable counter length of digital glitch filter for DIN17" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "FILTEREN31_16_DIN16,Programmable counter length of digital glitch filter for DIN16" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
line.long 0x8 "DMAMASK,DMA Write MASK"
|
|
bitfld.long 0x8 31. "DMAMASK_DOUT31,DMA is allowed to modify DOUT31" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 30. "DMAMASK_DOUT30,DMA is allowed to modify DOUT30" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 29. "DMAMASK_DOUT29,DMA is allowed to modify DOUT29" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 28. "DMAMASK_DOUT28,DMA is allowed to modify DOUT28" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 27. "DMAMASK_DOUT27,DMA is allowed to modify DOUT27" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 26. "DMAMASK_DOUT26,DMA is allowed to modify DOUT26" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 25. "DMAMASK_DOUT25,DMA is allowed to modify DOUT25" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 24. "DMAMASK_DOUT24,DMA is allowed to modify DOUT24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 23. "DMAMASK_DOUT23,DMA is allowed to modify DOUT23" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 22. "DMAMASK_DOUT22,DMA is allowed to modify DOUT22" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 21. "DMAMASK_DOUT21,DMA is allowed to modify DOUT21" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 20. "DMAMASK_DOUT20,DMA is allowed to modify DOUT20" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 19. "DMAMASK_DOUT19,DMA is allowed to modify DOUT19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 18. "DMAMASK_DOUT18,DMA is allowed to modify DOUT18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 17. "DMAMASK_DOUT17,DMA is allowed to modify DOUT17" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 16. "DMAMASK_DOUT16,DMA is allowed to modify DOUT16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 15. "DMAMASK_DOUT15,DMA is allowed to modify DOUT15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 14. "DMAMASK_DOUT14,DMA is allowed to modify DOUT14" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 13. "DMAMASK_DOUT13,DMA is allowed to modify DOUT13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 12. "DMAMASK_DOUT12,DMA is allowed to modify DOUT12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 11. "DMAMASK_DOUT11,DMA is allowed to modify DOUT11" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 10. "DMAMASK_DOUT10,DMA is allowed to modify DOUT10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 9. "DMAMASK_DOUT9,DMA is allowed to modify DOUT9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "DMAMASK_DOUT8,DMA is allowed to modify DOUT8" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAMASK_DOUT7,DMA is allowed to modify DOUT7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 6. "DMAMASK_DOUT6,DMA is allowed to modify DOUT6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 5. "DMAMASK_DOUT5,DMA is allowed to modify DOUT5" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "DMAMASK_DOUT4,DMA is allowed to modify DOUT4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 3. "DMAMASK_DOUT3,DMA is allowed to modify DOUT3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 2. "DMAMASK_DOUT2,DMA is allowed to modify DOUT2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "DMAMASK_DOUT1,DMA is allowed to modify DOUT1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 0. "DMAMASK_DOUT0,DMA is allowed to modify DOUT0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1520++0x3
|
|
line.long 0x0 "SUB1CFG,Subscriber 1 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB1CFG_INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB1CFG_OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB1CFG_ENABLE,This bit is used to enable subscriber 1 event." "0: CLR,1: SET"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "GPIOA"
|
|
base ad:0x400A0000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1010++0x3
|
|
line.long 0x0 "CLKOVR,Clock Override"
|
|
bitfld.long 0x0 1. "CLKOVR_RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: RUN,1: STOP"
|
|
bitfld.long 0x0 0. "CLKOVR_OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "CPU_INT_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPU_INT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "CPU_INT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "CPU_INT_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "CPU_INT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "CPU_INT_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "CPU_INT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "CPU_INT_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "CPU_INT_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "CPU_INT_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "CPU_INT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "CPU_INT_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "CPU_INT_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "CPU_INT_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "CPU_INT_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "CPU_INT_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "CPU_INT_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "CPU_INT_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "CPU_INT_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "CPU_INT_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "CPU_INT_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "CPU_INT_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "CPU_INT_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "CPU_INT_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "CPU_INT_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "CPU_INT_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "CPU_INT_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "CPU_INT_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "CPU_INT_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "CPU_INT_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "CPU_INT_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "CPU_INT_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "CPU_INT_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "GEN_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "GEN_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "GEN_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "GEN_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "GEN_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "GEN_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "GEN_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "GEN_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "GEN_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "GEN_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "GEN_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "GEN_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "GEN_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "GEN_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
wgroup.long 0x1200++0x1F
|
|
line.long 0x0 "DOUT3_0,Data output 3 to 0"
|
|
bitfld.long 0x0 24. "DOUT3_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 16. "DOUT3_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "DOUT3_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x0 0. "DOUT3_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x4 "DOUT7_4,Data output 7 to 4"
|
|
bitfld.long 0x4 24. "DOUT7_4_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 16. "DOUT7_4_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 8. "DOUT7_4_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x4 0. "DOUT7_4_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x8 "DOUT11_8,Data output 11 to 8"
|
|
bitfld.long 0x8 24. "DOUT11_8_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 16. "DOUT11_8_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 8. "DOUT11_8_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x8 0. "DOUT11_8_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0xC "DOUT15_12,Data output 15 to 12"
|
|
bitfld.long 0xC 24. "DOUT15_12_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "DOUT15_12_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "DOUT15_12_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0xC 0. "DOUT15_12_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DOUT19_16,Data output 19 to 16"
|
|
bitfld.long 0x10 24. "DOUT19_16_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DOUT19_16_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DOUT19_16_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x10 0. "DOUT19_16_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DOUT23_20,Data output 23 to 20"
|
|
bitfld.long 0x14 24. "DOUT23_20_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 16. "DOUT23_20_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DOUT23_20_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x14 0. "DOUT23_20_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x18 "DOUT27_24,Data output 27 to 24"
|
|
bitfld.long 0x18 24. "DOUT27_24_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 16. "DOUT27_24_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DOUT27_24_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x18 0. "DOUT27_24_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x1C "DOUT31_28,Data output 31 to 28"
|
|
bitfld.long 0x1C 24. "DOUT31_28_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 16. "DOUT31_28_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 8. "DOUT31_28_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x1C 0. "DOUT31_28_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
group.long 0x1280++0x3
|
|
line.long 0x0 "DOUT31_0,Data output 31 to 0"
|
|
bitfld.long 0x0 31. "DOUT31_0_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 30. "DOUT31_0_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 29. "DOUT31_0_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 28. "DOUT31_0_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 27. "DOUT31_0_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 26. "DOUT31_0_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 25. "DOUT31_0_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 24. "DOUT31_0_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 23. "DOUT31_0_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 22. "DOUT31_0_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 21. "DOUT31_0_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 20. "DOUT31_0_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 19. "DOUT31_0_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 18. "DOUT31_0_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 17. "DOUT31_0_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DOUT31_0_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 15. "DOUT31_0_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 14. "DOUT31_0_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 13. "DOUT31_0_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 12. "DOUT31_0_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 11. "DOUT31_0_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 10. "DOUT31_0_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 9. "DOUT31_0_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DOUT31_0_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 7. "DOUT31_0_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 6. "DOUT31_0_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 5. "DOUT31_0_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 4. "DOUT31_0_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 3. "DOUT31_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 2. "DOUT31_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 1. "DOUT31_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DOUT31_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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wgroup.long 0x1290++0x3
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line.long 0x0 "DOUTSET31_0,Data output set 31 to 0"
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bitfld.long 0x0 31. "DOUTSET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOUTSET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOUTSET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOUTSET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOUTSET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOUTSET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOUTSET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOUTSET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOUTSET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOUTSET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOUTSET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOUTSET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOUTSET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOUTSET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOUTSET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOUTSET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOUTSET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOUTSET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOUTSET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOUTSET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOUTSET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOUTSET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOUTSET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOUTSET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOUTSET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOUTSET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOUTSET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOUTSET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOUTSET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOUTSET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOUTSET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOUTSET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12A0++0x3
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line.long 0x0 "DOUTCLR31_0,Data output clear 31 to 0"
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bitfld.long 0x0 31. "DOUTCLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOUTCLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOUTCLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOUTCLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOUTCLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOUTCLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOUTCLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOUTCLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOUTCLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOUTCLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOUTCLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOUTCLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOUTCLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOUTCLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOUTCLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOUTCLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOUTCLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOUTCLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOUTCLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOUTCLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOUTCLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOUTCLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOUTCLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOUTCLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOUTCLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOUTCLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOUTCLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOUTCLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOUTCLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOUTCLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOUTCLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOUTCLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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wgroup.long 0x12B0++0x3
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line.long 0x0 "DOUTTGL31_0,Data output toggle 31 to 0"
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bitfld.long 0x0 31. "DOUTTGL31_0_DIO31,This bit is used to toggle DIO31 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 30. "DOUTTGL31_0_DIO30,This bit is used to toggle DIO30 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 29. "DOUTTGL31_0_DIO29,This bit is used to toggle DIO29 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 28. "DOUTTGL31_0_DIO28,This bit is used to toggle DIO28 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 27. "DOUTTGL31_0_DIO27,This bit is used to toggle DIO27 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 26. "DOUTTGL31_0_DIO26,This bit is used to toggle DIO26 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 25. "DOUTTGL31_0_DIO25,This bit is used to toggle DIO25 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 24. "DOUTTGL31_0_DIO24,This bit is used to toggle DIO24 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 23. "DOUTTGL31_0_DIO23,This bit is used to toggle DIO23 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 22. "DOUTTGL31_0_DIO22,This bit is used to toggle DIO22 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 21. "DOUTTGL31_0_DIO21,This bit is used to toggle DIO21 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 20. "DOUTTGL31_0_DIO20,This bit is used to toggle DIO20 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 19. "DOUTTGL31_0_DIO19,This bit is used to toggle DIO19 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 18. "DOUTTGL31_0_DIO18,This bit is used to toggle DIO18 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 17. "DOUTTGL31_0_DIO17,This bit is used to toggle DIO17 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 16. "DOUTTGL31_0_DIO16,This bit is used to toggle DIO16 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 15. "DOUTTGL31_0_DIO15,This bit is used to toggle DIO15 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 14. "DOUTTGL31_0_DIO14,This bit is used to toggle DIO14 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 13. "DOUTTGL31_0_DIO13,This bit is used to toggle DIO13 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 12. "DOUTTGL31_0_DIO12,This bit is used to toggle DIO12 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 11. "DOUTTGL31_0_DIO11,This bit is used to toggle DIO11 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 10. "DOUTTGL31_0_DIO10,This bit is used to toggle DIO10 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 9. "DOUTTGL31_0_DIO9,This bit is used to toggle DIO9 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 8. "DOUTTGL31_0_DIO8,This bit is used to toggle DIO8 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 7. "DOUTTGL31_0_DIO7,This bit is used to toggle DIO7 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 6. "DOUTTGL31_0_DIO6,This bit is used to toggle DIO6 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 5. "DOUTTGL31_0_DIO5,This bit is used to toggle DIO5 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 4. "DOUTTGL31_0_DIO4,This bit is used to toggle DIO4 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 3. "DOUTTGL31_0_DIO3,This bit is used to toggle DIO3 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 2. "DOUTTGL31_0_DIO2,This bit is used to toggle DIO2 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 1. "DOUTTGL31_0_DIO1,This bit is used to toggle DIO1 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 0. "DOUTTGL31_0_DIO0,This bit is used to toggle DIO0 output." "0: NO_EFFECT,1: TOGGLE"
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group.long 0x12C0++0x3
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line.long 0x0 "DOE31_0,Data output enable 31 to 0"
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bitfld.long 0x0 31. "DOE31_0_DIO31,Enables data output for DIO31." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 30. "DOE31_0_DIO30,Enables data output for DIO30." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 29. "DOE31_0_DIO29,Enables data output for DIO29." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 28. "DOE31_0_DIO28,Enables data output for DIO28." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 27. "DOE31_0_DIO27,Enables data output for DIO27." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 26. "DOE31_0_DIO26,Enables data output for DIO26." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 25. "DOE31_0_DIO25,Enables data output for DIO25." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 24. "DOE31_0_DIO24,Enables data output for DIO24." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 23. "DOE31_0_DIO23,Enables data output for DIO23." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 22. "DOE31_0_DIO22,Enables data output for DIO22." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 21. "DOE31_0_DIO21,Enables data output for DIO21." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 20. "DOE31_0_DIO20,Enables data output for DIO20." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 19. "DOE31_0_DIO19,Enables data output for DIO19." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 18. "DOE31_0_DIO18,Enables data output for DIO18." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 17. "DOE31_0_DIO17,Enables data output for DIO17." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 16. "DOE31_0_DIO16,Enables data output for DIO16." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 15. "DOE31_0_DIO15,Enables data output for DIO15." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 14. "DOE31_0_DIO14,Enables data output for DIO14." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 13. "DOE31_0_DIO13,Enables data output for DIO13." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "DOE31_0_DIO12,Enables data output for DIO12." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 11. "DOE31_0_DIO11,Enables data output for DIO11." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 10. "DOE31_0_DIO10,Enables data output for DIO10." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 9. "DOE31_0_DIO9,Enables data output for DIO9." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 8. "DOE31_0_DIO8,Enables data output for DIO8." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 7. "DOE31_0_DIO7,Enables data output for DIO7." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 6. "DOE31_0_DIO6,Enables data output for DIO6." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 5. "DOE31_0_DIO5,Enables data output for DIO5." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 4. "DOE31_0_DIO4,Enables data output for DIO4." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "DOE31_0_DIO3,Enables data output for DIO3." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "DOE31_0_DIO2,Enables data output for DIO2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 1. "DOE31_0_DIO1,Enables data output for DIO1." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "DOE31_0_DIO0,Enables data output for DIO0." "0: DISABLE,1: ENABLE"
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wgroup.long 0x12D0++0x3
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line.long 0x0 "DOESET31_0,Data output enable set 31 to 0"
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bitfld.long 0x0 31. "DOESET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOESET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOESET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOESET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOESET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOESET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOESET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOESET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOESET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOESET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOESET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOESET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOESET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOESET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOESET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOESET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOESET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOESET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOESET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOESET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOESET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOESET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOESET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOESET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOESET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOESET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOESET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOESET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOESET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOESET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOESET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOESET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12E0++0x3
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line.long 0x0 "DOECLR31_0,Data output enable clear 31 to 0"
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bitfld.long 0x0 31. "DOECLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOECLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOECLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOECLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOECLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOECLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOECLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOECLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOECLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOECLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOECLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOECLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOECLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOECLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOECLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOECLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOECLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOECLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOECLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOECLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOECLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOECLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOECLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOECLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOECLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOECLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOECLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOECLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOECLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOECLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOECLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOECLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1300++0x1F
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line.long 0x0 "DIN3_0,Data input 3 to 0"
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bitfld.long 0x0 24. "DIN3_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DIN3_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DIN3_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DIN3_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
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line.long 0x4 "DIN7_4,Data input 7 to 4"
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bitfld.long 0x4 24. "DIN7_4_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
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bitfld.long 0x4 16. "DIN7_4_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
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bitfld.long 0x4 8. "DIN7_4_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
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bitfld.long 0x4 0. "DIN7_4_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
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line.long 0x8 "DIN11_8,Data input 11 to 8"
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bitfld.long 0x8 24. "DIN11_8_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
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bitfld.long 0x8 16. "DIN11_8_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
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bitfld.long 0x8 8. "DIN11_8_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
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bitfld.long 0x8 0. "DIN11_8_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
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line.long 0xC "DIN15_12,Data input 15 to 12"
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bitfld.long 0xC 24. "DIN15_12_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
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bitfld.long 0xC 16. "DIN15_12_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "DIN15_12_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0xC 0. "DIN15_12_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DIN19_16,Data input 19 to 16"
|
|
bitfld.long 0x10 24. "DIN19_16_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DIN19_16_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DIN19_16_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x10 0. "DIN19_16_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DIN23_20,Data input 23 to 20"
|
|
bitfld.long 0x14 24. "DIN23_20_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 16. "DIN23_20_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DIN23_20_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x14 0. "DIN23_20_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
|
|
line.long 0x18 "DIN27_24,Data input 27 to 24"
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|
bitfld.long 0x18 24. "DIN27_24_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
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|
bitfld.long 0x18 16. "DIN27_24_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DIN27_24_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x18 0. "DIN27_24_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
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|
line.long 0x1C "DIN31_28,Data input 31 to 28"
|
|
bitfld.long 0x1C 24. "DIN31_28_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 16. "DIN31_28_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 8. "DIN31_28_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x1C 0. "DIN31_28_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
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|
rgroup.long 0x1380++0x3
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|
line.long 0x0 "DIN31_0,Data input 31 to 0"
|
|
bitfld.long 0x0 31. "DIN31_0_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 30. "DIN31_0_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 29. "DIN31_0_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 28. "DIN31_0_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 27. "DIN31_0_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 26. "DIN31_0_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 25. "DIN31_0_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 24. "DIN31_0_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 23. "DIN31_0_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 22. "DIN31_0_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 21. "DIN31_0_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 20. "DIN31_0_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 19. "DIN31_0_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 18. "DIN31_0_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 17. "DIN31_0_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 16. "DIN31_0_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 15. "DIN31_0_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 14. "DIN31_0_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 13. "DIN31_0_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 12. "DIN31_0_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 11. "DIN31_0_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x0 10. "DIN31_0_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 9. "DIN31_0_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "DIN31_0_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 7. "DIN31_0_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 6. "DIN31_0_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 5. "DIN31_0_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 4. "DIN31_0_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 3. "DIN31_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 2. "DIN31_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 1. "DIN31_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 0. "DIN31_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
|
|
group.long 0x1390++0x3
|
|
line.long 0x0 "POLARITY15_0,Polarity 15 to 0"
|
|
bitfld.long 0x0 30.--31. "POLARITY15_0_DIO15,Enables and configures edge detection polarity for DIO15." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 28.--29. "POLARITY15_0_DIO14,Enables and configures edge detection polarity for DIO14." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
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bitfld.long 0x0 26.--27. "POLARITY15_0_DIO13,Enables and configures edge detection polarity for DIO13." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
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bitfld.long 0x0 24.--25. "POLARITY15_0_DIO12,Enables and configures edge detection polarity for DIO12." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
bitfld.long 0x0 22.--23. "POLARITY15_0_DIO11,Enables and configures edge detection polarity for DIO11." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 20.--21. "POLARITY15_0_DIO10,Enables and configures edge detection polarity for DIO10." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
newline
|
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bitfld.long 0x0 18.--19. "POLARITY15_0_DIO9,Enables and configures edge detection polarity for DIO9." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 16.--17. "POLARITY15_0_DIO8,Enables and configures edge detection polarity for DIO8." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
bitfld.long 0x0 14.--15. "POLARITY15_0_DIO7,Enables and configures edge detection polarity for DIO7." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 12.--13. "POLARITY15_0_DIO6,Enables and configures edge detection polarity for DIO6." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 10.--11. "POLARITY15_0_DIO5,Enables and configures edge detection polarity for DIO5." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 8.--9. "POLARITY15_0_DIO4,Enables and configures edge detection polarity for DIO4." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
newline
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bitfld.long 0x0 6.--7. "POLARITY15_0_DIO3,Enables and configures edge detection polarity for DIO3." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 4.--5. "POLARITY15_0_DIO2,Enables and configures edge detection polarity for DIO2." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 2.--3. "POLARITY15_0_DIO1,Enables and configures edge detection polarity for DIO1." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
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bitfld.long 0x0 0.--1. "POLARITY15_0_DIO0,Enables and configures edge detection polarity for DIO0." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
group.long 0x13A0++0x3
|
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line.long 0x0 "POLARITY31_16,Polarity 31 to 16"
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bitfld.long 0x0 30.--31. "POLARITY31_16_DIO31,Enables and configures edge detection polarity for DIO31." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 28.--29. "POLARITY31_16_DIO30,Enables and configures edge detection polarity for DIO30." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 26.--27. "POLARITY31_16_DIO29,Enables and configures edge detection polarity for DIO29." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
newline
|
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bitfld.long 0x0 24.--25. "POLARITY31_16_DIO28,Enables and configures edge detection polarity for DIO28." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 22.--23. "POLARITY31_16_DIO27,Enables and configures edge detection polarity for DIO27." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 20.--21. "POLARITY31_16_DIO26,Enables and configures edge detection polarity for DIO26." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
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bitfld.long 0x0 18.--19. "POLARITY31_16_DIO25,Enables and configures edge detection polarity for DIO25." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 16.--17. "POLARITY31_16_DIO24,Enables and configures edge detection polarity for DIO24." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 14.--15. "POLARITY31_16_DIO23,Enables and configures edge detection polarity for DIO23." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 12.--13. "POLARITY31_16_DIO22,Enables and configures edge detection polarity for DIO22." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 10.--11. "POLARITY31_16_DIO21,Enables and configures edge detection polarity for DIO21." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 8.--9. "POLARITY31_16_DIO20,Enables and configures edge detection polarity for DIO20." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
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bitfld.long 0x0 6.--7. "POLARITY31_16_DIO19,Enables and configures edge detection polarity for DIO19." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 4.--5. "POLARITY31_16_DIO18,Enables and configures edge detection polarity for DIO18." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 2.--3. "POLARITY31_16_DIO17,Enables and configures edge detection polarity for DIO17." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 0.--1. "POLARITY31_16_DIO16,Enables and configures edge detection polarity for DIO16." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
group.long 0x1400++0x7
|
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line.long 0x0 "CTL,FAST WAKE GLOBAL EN"
|
|
bitfld.long 0x0 0. "CTL_FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: NOT_GLOBAL_EN,1: GLOBAL_EN"
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line.long 0x4 "FASTWAKE,FAST WAKE ENABLE"
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bitfld.long 0x4 31. "FASTWAKE_DIN31,Enable fastwake feature for DIN31" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 30. "FASTWAKE_DIN30,Enable fastwake feature for DIN30" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 29. "FASTWAKE_DIN29,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 28. "FASTWAKE_DIN28,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 27. "FASTWAKE_DIN27,Enable fastwake feature for DIN27" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 26. "FASTWAKE_DIN26,Enable fastwake feature for DIN26" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 25. "FASTWAKE_DIN25,Enable fastwake feature for DIN25" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 24. "FASTWAKE_DIN24,Enable fastwake feature for DIN24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 23. "FASTWAKE_DIN23,Enable fastwake feature for DIN23" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 22. "FASTWAKE_DIN22,Enable fastwake feature for DIN22" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 21. "FASTWAKE_DIN21,Enable fastwake feature for DIN21" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 20. "FASTWAKE_DIN20,Enable fastwake feature for DIN20" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 19. "FASTWAKE_DIN19,Enable fastwake feature for DIN19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 18. "FASTWAKE_DIN18,Enable fastwake feature for DIN18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 17. "FASTWAKE_DIN17,Enable fastwake feature for DIN17" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 16. "FASTWAKE_DIN16,Enable fastwake feature for DIN16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 15. "FASTWAKE_DIN15,Enable fastwake feature for DIN15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 14. "FASTWAKE_DIN14,Enable fastwake feature for DIN14" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 13. "FASTWAKE_DIN13,Enable fastwake feature for DIN13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 12. "FASTWAKE_DIN12,Enable fastwake feature for DIN12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 11. "FASTWAKE_DIN11,Enable fastwake feature for DIN11" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 10. "FASTWAKE_DIN10,Enable fastwake feature for DIN10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 9. "FASTWAKE_DIN9,Enable fastwake feature for DIN9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "FASTWAKE_DIN8,Enable fastwake feature for DIN8" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 7. "FASTWAKE_DIN7,Enable fastwake feature for DIN7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "FASTWAKE_DIN6,Enable fastwake feature for DIN6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "FASTWAKE_DIN5,Enable fastwake feature for DIN5" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 4. "FASTWAKE_DIN4,Enable fastwake feature for DIN4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 3. "FASTWAKE_DIN3,Enable fastwake feature for DIN3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "FASTWAKE_DIN2,Enable fastwake feature for DIN2" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 1. "FASTWAKE_DIN1,Enable fastwake feature for DIN1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "FASTWAKE_DIN0,Enable fastwake feature for DIN0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "SUB0CFG,Subscriber 0 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB0CFG_INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB0CFG_OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB0CFG_ENABLE,This bit is used to enable subscriber 0 event." "0: CLR,1: SET"
|
|
group.long 0x1508++0xB
|
|
line.long 0x0 "FILTEREN15_0,Filter Enable 15 to 0"
|
|
bitfld.long 0x0 30.--31. "FILTEREN15_0_DIN15,Programmable counter length of digital glitch filter for DIN15" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
bitfld.long 0x0 28.--29. "FILTEREN15_0_DIN14,Programmable counter length of digital glitch filter for DIN14" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 26.--27. "FILTEREN15_0_DIN13,Programmable counter length of digital glitch filter for DIN13" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
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bitfld.long 0x0 24.--25. "FILTEREN15_0_DIN12,Programmable counter length of digital glitch filter for DIN12" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 22.--23. "FILTEREN15_0_DIN11,Programmable counter length of digital glitch filter for DIN11" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 20.--21. "FILTEREN15_0_DIN10,Programmable counter length of digital glitch filter for DIN10" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
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bitfld.long 0x0 18.--19. "FILTEREN15_0_DIN9,Programmable counter length of digital glitch filter for DIN9" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 16.--17. "FILTEREN15_0_DIN8,Programmable counter length of digital glitch filter for DIN8" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 14.--15. "FILTEREN15_0_DIN7,Programmable counter length of digital glitch filter for DIN7" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
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bitfld.long 0x0 12.--13. "FILTEREN15_0_DIN6,Programmable counter length of digital glitch filter for DIN6" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 10.--11. "FILTEREN15_0_DIN5,Programmable counter length of digital glitch filter for DIN5" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 8.--9. "FILTEREN15_0_DIN4,Programmable counter length of digital glitch filter for DIN4" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "FILTEREN15_0_DIN3,Programmable counter length of digital glitch filter for DIN3" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 4.--5. "FILTEREN15_0_DIN2,Programmable counter length of digital glitch filter for DIN2" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 2.--3. "FILTEREN15_0_DIN1,Programmable counter length of digital glitch filter for DIN1" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "FILTEREN15_0_DIN0,Programmable counter length of digital glitch filter for DIN0" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
line.long 0x4 "FILTEREN31_16,Filter Enable 31 to 16"
|
|
bitfld.long 0x4 30.--31. "FILTEREN31_16_DIN31,Programmable counter length of digital glitch filter for DIN31" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 28.--29. "FILTEREN31_16_DIN30,Programmable counter length of digital glitch filter for DIN30" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 26.--27. "FILTEREN31_16_DIN29,Programmable counter length of digital glitch filter for DIN29" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "FILTEREN31_16_DIN28,Programmable counter length of digital glitch filter for DIN28" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 22.--23. "FILTEREN31_16_DIN27,Programmable counter length of digital glitch filter for DIN27" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 20.--21. "FILTEREN31_16_DIN26,Programmable counter length of digital glitch filter for DIN26" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 18.--19. "FILTEREN31_16_DIN25,Programmable counter length of digital glitch filter for DIN25" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 16.--17. "FILTEREN31_16_DIN24,Programmable counter length of digital glitch filter for DIN24" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 14.--15. "FILTEREN31_16_DIN23,Programmable counter length of digital glitch filter for DIN23" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "FILTEREN31_16_DIN22,Programmable counter length of digital glitch filter for DIN22" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 10.--11. "FILTEREN31_16_DIN21,Programmable counter length of digital glitch filter for DIN21" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 8.--9. "FILTEREN31_16_DIN20,Programmable counter length of digital glitch filter for DIN20" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FILTEREN31_16_DIN19,Programmable counter length of digital glitch filter for DIN19" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 4.--5. "FILTEREN31_16_DIN18,Programmable counter length of digital glitch filter for DIN18" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 2.--3. "FILTEREN31_16_DIN17,Programmable counter length of digital glitch filter for DIN17" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "FILTEREN31_16_DIN16,Programmable counter length of digital glitch filter for DIN16" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
line.long 0x8 "DMAMASK,DMA Write MASK"
|
|
bitfld.long 0x8 31. "DMAMASK_DOUT31,DMA is allowed to modify DOUT31" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 30. "DMAMASK_DOUT30,DMA is allowed to modify DOUT30" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 29. "DMAMASK_DOUT29,DMA is allowed to modify DOUT29" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 28. "DMAMASK_DOUT28,DMA is allowed to modify DOUT28" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 27. "DMAMASK_DOUT27,DMA is allowed to modify DOUT27" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 26. "DMAMASK_DOUT26,DMA is allowed to modify DOUT26" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 25. "DMAMASK_DOUT25,DMA is allowed to modify DOUT25" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 24. "DMAMASK_DOUT24,DMA is allowed to modify DOUT24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 23. "DMAMASK_DOUT23,DMA is allowed to modify DOUT23" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 22. "DMAMASK_DOUT22,DMA is allowed to modify DOUT22" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 21. "DMAMASK_DOUT21,DMA is allowed to modify DOUT21" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 20. "DMAMASK_DOUT20,DMA is allowed to modify DOUT20" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 19. "DMAMASK_DOUT19,DMA is allowed to modify DOUT19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 18. "DMAMASK_DOUT18,DMA is allowed to modify DOUT18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 17. "DMAMASK_DOUT17,DMA is allowed to modify DOUT17" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 16. "DMAMASK_DOUT16,DMA is allowed to modify DOUT16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 15. "DMAMASK_DOUT15,DMA is allowed to modify DOUT15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 14. "DMAMASK_DOUT14,DMA is allowed to modify DOUT14" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 13. "DMAMASK_DOUT13,DMA is allowed to modify DOUT13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 12. "DMAMASK_DOUT12,DMA is allowed to modify DOUT12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 11. "DMAMASK_DOUT11,DMA is allowed to modify DOUT11" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 10. "DMAMASK_DOUT10,DMA is allowed to modify DOUT10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 9. "DMAMASK_DOUT9,DMA is allowed to modify DOUT9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "DMAMASK_DOUT8,DMA is allowed to modify DOUT8" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAMASK_DOUT7,DMA is allowed to modify DOUT7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 6. "DMAMASK_DOUT6,DMA is allowed to modify DOUT6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 5. "DMAMASK_DOUT5,DMA is allowed to modify DOUT5" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "DMAMASK_DOUT4,DMA is allowed to modify DOUT4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 3. "DMAMASK_DOUT3,DMA is allowed to modify DOUT3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 2. "DMAMASK_DOUT2,DMA is allowed to modify DOUT2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "DMAMASK_DOUT1,DMA is allowed to modify DOUT1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 0. "DMAMASK_DOUT0,DMA is allowed to modify DOUT0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1520++0x3
|
|
line.long 0x0 "SUB1CFG,Subscriber 1 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB1CFG_INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB1CFG_OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB1CFG_ENABLE,This bit is used to enable subscriber 1 event." "0: CLR,1: SET"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "GPIOB"
|
|
base ad:0x400A2000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1010++0x3
|
|
line.long 0x0 "CLKOVR,Clock Override"
|
|
bitfld.long 0x0 1. "CLKOVR_RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: RUN,1: STOP"
|
|
bitfld.long 0x0 0. "CLKOVR_OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "CPU_INT_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPU_INT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "CPU_INT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "CPU_INT_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "CPU_INT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "CPU_INT_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "CPU_INT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "CPU_INT_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "CPU_INT_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "CPU_INT_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "CPU_INT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "CPU_INT_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "CPU_INT_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "CPU_INT_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "CPU_INT_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "CPU_INT_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "CPU_INT_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "CPU_INT_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "CPU_INT_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "CPU_INT_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "CPU_INT_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "CPU_INT_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "CPU_INT_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "CPU_INT_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "CPU_INT_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "CPU_INT_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "CPU_INT_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "CPU_INT_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "CPU_INT_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "CPU_INT_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "CPU_INT_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "CPU_INT_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "CPU_INT_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "GEN_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "GEN_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "GEN_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "GEN_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "GEN_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "GEN_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "GEN_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "GEN_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "GEN_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "GEN_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "GEN_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "GEN_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "GEN_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "GEN_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
wgroup.long 0x1200++0x1F
|
|
line.long 0x0 "DOUT3_0,Data output 3 to 0"
|
|
bitfld.long 0x0 24. "DOUT3_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 16. "DOUT3_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "DOUT3_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x0 0. "DOUT3_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x4 "DOUT7_4,Data output 7 to 4"
|
|
bitfld.long 0x4 24. "DOUT7_4_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 16. "DOUT7_4_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 8. "DOUT7_4_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x4 0. "DOUT7_4_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x8 "DOUT11_8,Data output 11 to 8"
|
|
bitfld.long 0x8 24. "DOUT11_8_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 16. "DOUT11_8_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 8. "DOUT11_8_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x8 0. "DOUT11_8_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0xC "DOUT15_12,Data output 15 to 12"
|
|
bitfld.long 0xC 24. "DOUT15_12_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "DOUT15_12_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "DOUT15_12_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0xC 0. "DOUT15_12_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DOUT19_16,Data output 19 to 16"
|
|
bitfld.long 0x10 24. "DOUT19_16_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DOUT19_16_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DOUT19_16_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x10 0. "DOUT19_16_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DOUT23_20,Data output 23 to 20"
|
|
bitfld.long 0x14 24. "DOUT23_20_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 16. "DOUT23_20_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DOUT23_20_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x14 0. "DOUT23_20_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x18 "DOUT27_24,Data output 27 to 24"
|
|
bitfld.long 0x18 24. "DOUT27_24_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 16. "DOUT27_24_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DOUT27_24_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x18 0. "DOUT27_24_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x1C "DOUT31_28,Data output 31 to 28"
|
|
bitfld.long 0x1C 24. "DOUT31_28_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 16. "DOUT31_28_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 8. "DOUT31_28_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x1C 0. "DOUT31_28_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
group.long 0x1280++0x3
|
|
line.long 0x0 "DOUT31_0,Data output 31 to 0"
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bitfld.long 0x0 31. "DOUT31_0_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 30. "DOUT31_0_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 29. "DOUT31_0_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 28. "DOUT31_0_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 27. "DOUT31_0_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 26. "DOUT31_0_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 25. "DOUT31_0_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 24. "DOUT31_0_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 23. "DOUT31_0_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 22. "DOUT31_0_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 21. "DOUT31_0_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 20. "DOUT31_0_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 19. "DOUT31_0_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 18. "DOUT31_0_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 17. "DOUT31_0_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DOUT31_0_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 15. "DOUT31_0_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 14. "DOUT31_0_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 13. "DOUT31_0_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 12. "DOUT31_0_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 11. "DOUT31_0_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 10. "DOUT31_0_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 9. "DOUT31_0_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DOUT31_0_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 7. "DOUT31_0_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 6. "DOUT31_0_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 5. "DOUT31_0_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 4. "DOUT31_0_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 3. "DOUT31_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 2. "DOUT31_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 1. "DOUT31_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DOUT31_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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wgroup.long 0x1290++0x3
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line.long 0x0 "DOUTSET31_0,Data output set 31 to 0"
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bitfld.long 0x0 31. "DOUTSET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOUTSET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOUTSET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOUTSET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOUTSET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOUTSET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOUTSET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOUTSET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOUTSET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOUTSET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOUTSET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOUTSET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOUTSET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOUTSET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOUTSET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOUTSET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOUTSET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOUTSET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOUTSET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOUTSET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOUTSET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOUTSET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOUTSET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOUTSET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOUTSET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOUTSET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOUTSET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOUTSET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOUTSET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOUTSET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOUTSET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOUTSET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12A0++0x3
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line.long 0x0 "DOUTCLR31_0,Data output clear 31 to 0"
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bitfld.long 0x0 31. "DOUTCLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOUTCLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOUTCLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOUTCLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOUTCLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOUTCLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOUTCLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOUTCLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOUTCLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOUTCLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOUTCLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOUTCLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOUTCLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOUTCLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOUTCLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOUTCLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOUTCLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOUTCLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOUTCLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOUTCLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOUTCLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOUTCLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOUTCLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOUTCLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOUTCLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOUTCLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOUTCLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOUTCLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOUTCLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOUTCLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOUTCLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOUTCLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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wgroup.long 0x12B0++0x3
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line.long 0x0 "DOUTTGL31_0,Data output toggle 31 to 0"
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bitfld.long 0x0 31. "DOUTTGL31_0_DIO31,This bit is used to toggle DIO31 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 30. "DOUTTGL31_0_DIO30,This bit is used to toggle DIO30 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 29. "DOUTTGL31_0_DIO29,This bit is used to toggle DIO29 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 28. "DOUTTGL31_0_DIO28,This bit is used to toggle DIO28 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 27. "DOUTTGL31_0_DIO27,This bit is used to toggle DIO27 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 26. "DOUTTGL31_0_DIO26,This bit is used to toggle DIO26 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 25. "DOUTTGL31_0_DIO25,This bit is used to toggle DIO25 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 24. "DOUTTGL31_0_DIO24,This bit is used to toggle DIO24 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 23. "DOUTTGL31_0_DIO23,This bit is used to toggle DIO23 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 22. "DOUTTGL31_0_DIO22,This bit is used to toggle DIO22 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 21. "DOUTTGL31_0_DIO21,This bit is used to toggle DIO21 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 20. "DOUTTGL31_0_DIO20,This bit is used to toggle DIO20 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 19. "DOUTTGL31_0_DIO19,This bit is used to toggle DIO19 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 18. "DOUTTGL31_0_DIO18,This bit is used to toggle DIO18 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 17. "DOUTTGL31_0_DIO17,This bit is used to toggle DIO17 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 16. "DOUTTGL31_0_DIO16,This bit is used to toggle DIO16 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 15. "DOUTTGL31_0_DIO15,This bit is used to toggle DIO15 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 14. "DOUTTGL31_0_DIO14,This bit is used to toggle DIO14 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 13. "DOUTTGL31_0_DIO13,This bit is used to toggle DIO13 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 12. "DOUTTGL31_0_DIO12,This bit is used to toggle DIO12 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 11. "DOUTTGL31_0_DIO11,This bit is used to toggle DIO11 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 10. "DOUTTGL31_0_DIO10,This bit is used to toggle DIO10 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 9. "DOUTTGL31_0_DIO9,This bit is used to toggle DIO9 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 8. "DOUTTGL31_0_DIO8,This bit is used to toggle DIO8 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 7. "DOUTTGL31_0_DIO7,This bit is used to toggle DIO7 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 6. "DOUTTGL31_0_DIO6,This bit is used to toggle DIO6 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 5. "DOUTTGL31_0_DIO5,This bit is used to toggle DIO5 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 4. "DOUTTGL31_0_DIO4,This bit is used to toggle DIO4 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 3. "DOUTTGL31_0_DIO3,This bit is used to toggle DIO3 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 2. "DOUTTGL31_0_DIO2,This bit is used to toggle DIO2 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 1. "DOUTTGL31_0_DIO1,This bit is used to toggle DIO1 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 0. "DOUTTGL31_0_DIO0,This bit is used to toggle DIO0 output." "0: NO_EFFECT,1: TOGGLE"
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group.long 0x12C0++0x3
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line.long 0x0 "DOE31_0,Data output enable 31 to 0"
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bitfld.long 0x0 31. "DOE31_0_DIO31,Enables data output for DIO31." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 30. "DOE31_0_DIO30,Enables data output for DIO30." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 29. "DOE31_0_DIO29,Enables data output for DIO29." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 28. "DOE31_0_DIO28,Enables data output for DIO28." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 27. "DOE31_0_DIO27,Enables data output for DIO27." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 26. "DOE31_0_DIO26,Enables data output for DIO26." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 25. "DOE31_0_DIO25,Enables data output for DIO25." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 24. "DOE31_0_DIO24,Enables data output for DIO24." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 23. "DOE31_0_DIO23,Enables data output for DIO23." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 22. "DOE31_0_DIO22,Enables data output for DIO22." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 21. "DOE31_0_DIO21,Enables data output for DIO21." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 20. "DOE31_0_DIO20,Enables data output for DIO20." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 19. "DOE31_0_DIO19,Enables data output for DIO19." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 18. "DOE31_0_DIO18,Enables data output for DIO18." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 17. "DOE31_0_DIO17,Enables data output for DIO17." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 16. "DOE31_0_DIO16,Enables data output for DIO16." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 15. "DOE31_0_DIO15,Enables data output for DIO15." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 14. "DOE31_0_DIO14,Enables data output for DIO14." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 13. "DOE31_0_DIO13,Enables data output for DIO13." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "DOE31_0_DIO12,Enables data output for DIO12." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 11. "DOE31_0_DIO11,Enables data output for DIO11." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 10. "DOE31_0_DIO10,Enables data output for DIO10." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 9. "DOE31_0_DIO9,Enables data output for DIO9." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 8. "DOE31_0_DIO8,Enables data output for DIO8." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 7. "DOE31_0_DIO7,Enables data output for DIO7." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 6. "DOE31_0_DIO6,Enables data output for DIO6." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 5. "DOE31_0_DIO5,Enables data output for DIO5." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 4. "DOE31_0_DIO4,Enables data output for DIO4." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "DOE31_0_DIO3,Enables data output for DIO3." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "DOE31_0_DIO2,Enables data output for DIO2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 1. "DOE31_0_DIO1,Enables data output for DIO1." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "DOE31_0_DIO0,Enables data output for DIO0." "0: DISABLE,1: ENABLE"
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wgroup.long 0x12D0++0x3
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line.long 0x0 "DOESET31_0,Data output enable set 31 to 0"
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bitfld.long 0x0 31. "DOESET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOESET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOESET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOESET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOESET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOESET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOESET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOESET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOESET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOESET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOESET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOESET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOESET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOESET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOESET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOESET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOESET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOESET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOESET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOESET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOESET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOESET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOESET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOESET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOESET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOESET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOESET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOESET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOESET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOESET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOESET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOESET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12E0++0x3
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line.long 0x0 "DOECLR31_0,Data output enable clear 31 to 0"
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bitfld.long 0x0 31. "DOECLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOECLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOECLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOECLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOECLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOECLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOECLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOECLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOECLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOECLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOECLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOECLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOECLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOECLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOECLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOECLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOECLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOECLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOECLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOECLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOECLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOECLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOECLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOECLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOECLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOECLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOECLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOECLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOECLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOECLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOECLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOECLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1300++0x1F
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line.long 0x0 "DIN3_0,Data input 3 to 0"
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bitfld.long 0x0 24. "DIN3_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DIN3_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DIN3_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DIN3_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
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line.long 0x4 "DIN7_4,Data input 7 to 4"
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bitfld.long 0x4 24. "DIN7_4_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
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bitfld.long 0x4 16. "DIN7_4_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
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bitfld.long 0x4 8. "DIN7_4_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
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bitfld.long 0x4 0. "DIN7_4_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
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line.long 0x8 "DIN11_8,Data input 11 to 8"
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bitfld.long 0x8 24. "DIN11_8_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
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bitfld.long 0x8 16. "DIN11_8_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
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bitfld.long 0x8 8. "DIN11_8_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
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bitfld.long 0x8 0. "DIN11_8_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
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line.long 0xC "DIN15_12,Data input 15 to 12"
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bitfld.long 0xC 24. "DIN15_12_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "DIN15_12_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "DIN15_12_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0xC 0. "DIN15_12_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DIN19_16,Data input 19 to 16"
|
|
bitfld.long 0x10 24. "DIN19_16_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DIN19_16_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DIN19_16_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x10 0. "DIN19_16_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DIN23_20,Data input 23 to 20"
|
|
bitfld.long 0x14 24. "DIN23_20_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 16. "DIN23_20_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DIN23_20_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
|
|
newline
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|
bitfld.long 0x14 0. "DIN23_20_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
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|
line.long 0x18 "DIN27_24,Data input 27 to 24"
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|
bitfld.long 0x18 24. "DIN27_24_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 16. "DIN27_24_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DIN27_24_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x18 0. "DIN27_24_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
|
|
line.long 0x1C "DIN31_28,Data input 31 to 28"
|
|
bitfld.long 0x1C 24. "DIN31_28_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 16. "DIN31_28_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 8. "DIN31_28_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
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|
newline
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|
bitfld.long 0x1C 0. "DIN31_28_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
|
|
rgroup.long 0x1380++0x3
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|
line.long 0x0 "DIN31_0,Data input 31 to 0"
|
|
bitfld.long 0x0 31. "DIN31_0_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 30. "DIN31_0_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 29. "DIN31_0_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 28. "DIN31_0_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 27. "DIN31_0_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 26. "DIN31_0_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 25. "DIN31_0_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 24. "DIN31_0_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 23. "DIN31_0_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 22. "DIN31_0_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 21. "DIN31_0_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 20. "DIN31_0_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 19. "DIN31_0_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 18. "DIN31_0_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 17. "DIN31_0_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 16. "DIN31_0_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 15. "DIN31_0_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 14. "DIN31_0_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 13. "DIN31_0_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 12. "DIN31_0_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 11. "DIN31_0_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 10. "DIN31_0_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 9. "DIN31_0_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "DIN31_0_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 7. "DIN31_0_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 6. "DIN31_0_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
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|
bitfld.long 0x0 5. "DIN31_0_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 4. "DIN31_0_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 3. "DIN31_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 2. "DIN31_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 1. "DIN31_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 0. "DIN31_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
|
|
group.long 0x1390++0x3
|
|
line.long 0x0 "POLARITY15_0,Polarity 15 to 0"
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|
bitfld.long 0x0 30.--31. "POLARITY15_0_DIO15,Enables and configures edge detection polarity for DIO15." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 28.--29. "POLARITY15_0_DIO14,Enables and configures edge detection polarity for DIO14." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
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bitfld.long 0x0 26.--27. "POLARITY15_0_DIO13,Enables and configures edge detection polarity for DIO13." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
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bitfld.long 0x0 24.--25. "POLARITY15_0_DIO12,Enables and configures edge detection polarity for DIO12." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
bitfld.long 0x0 22.--23. "POLARITY15_0_DIO11,Enables and configures edge detection polarity for DIO11." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 20.--21. "POLARITY15_0_DIO10,Enables and configures edge detection polarity for DIO10." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
newline
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bitfld.long 0x0 18.--19. "POLARITY15_0_DIO9,Enables and configures edge detection polarity for DIO9." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 16.--17. "POLARITY15_0_DIO8,Enables and configures edge detection polarity for DIO8." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 14.--15. "POLARITY15_0_DIO7,Enables and configures edge detection polarity for DIO7." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
newline
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bitfld.long 0x0 12.--13. "POLARITY15_0_DIO6,Enables and configures edge detection polarity for DIO6." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 10.--11. "POLARITY15_0_DIO5,Enables and configures edge detection polarity for DIO5." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 8.--9. "POLARITY15_0_DIO4,Enables and configures edge detection polarity for DIO4." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
newline
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bitfld.long 0x0 6.--7. "POLARITY15_0_DIO3,Enables and configures edge detection polarity for DIO3." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 4.--5. "POLARITY15_0_DIO2,Enables and configures edge detection polarity for DIO2." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 2.--3. "POLARITY15_0_DIO1,Enables and configures edge detection polarity for DIO1." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
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bitfld.long 0x0 0.--1. "POLARITY15_0_DIO0,Enables and configures edge detection polarity for DIO0." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
group.long 0x13A0++0x3
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line.long 0x0 "POLARITY31_16,Polarity 31 to 16"
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bitfld.long 0x0 30.--31. "POLARITY31_16_DIO31,Enables and configures edge detection polarity for DIO31." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 28.--29. "POLARITY31_16_DIO30,Enables and configures edge detection polarity for DIO30." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 26.--27. "POLARITY31_16_DIO29,Enables and configures edge detection polarity for DIO29." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 24.--25. "POLARITY31_16_DIO28,Enables and configures edge detection polarity for DIO28." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 22.--23. "POLARITY31_16_DIO27,Enables and configures edge detection polarity for DIO27." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 20.--21. "POLARITY31_16_DIO26,Enables and configures edge detection polarity for DIO26." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
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bitfld.long 0x0 18.--19. "POLARITY31_16_DIO25,Enables and configures edge detection polarity for DIO25." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 16.--17. "POLARITY31_16_DIO24,Enables and configures edge detection polarity for DIO24." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 14.--15. "POLARITY31_16_DIO23,Enables and configures edge detection polarity for DIO23." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
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bitfld.long 0x0 12.--13. "POLARITY31_16_DIO22,Enables and configures edge detection polarity for DIO22." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 10.--11. "POLARITY31_16_DIO21,Enables and configures edge detection polarity for DIO21." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 8.--9. "POLARITY31_16_DIO20,Enables and configures edge detection polarity for DIO20." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 6.--7. "POLARITY31_16_DIO19,Enables and configures edge detection polarity for DIO19." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
bitfld.long 0x0 4.--5. "POLARITY31_16_DIO18,Enables and configures edge detection polarity for DIO18." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
bitfld.long 0x0 2.--3. "POLARITY31_16_DIO17,Enables and configures edge detection polarity for DIO17." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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newline
|
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bitfld.long 0x0 0.--1. "POLARITY31_16_DIO16,Enables and configures edge detection polarity for DIO16." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
group.long 0x1400++0x7
|
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line.long 0x0 "CTL,FAST WAKE GLOBAL EN"
|
|
bitfld.long 0x0 0. "CTL_FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: NOT_GLOBAL_EN,1: GLOBAL_EN"
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line.long 0x4 "FASTWAKE,FAST WAKE ENABLE"
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bitfld.long 0x4 31. "FASTWAKE_DIN31,Enable fastwake feature for DIN31" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 30. "FASTWAKE_DIN30,Enable fastwake feature for DIN30" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 29. "FASTWAKE_DIN29,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 28. "FASTWAKE_DIN28,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 27. "FASTWAKE_DIN27,Enable fastwake feature for DIN27" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 26. "FASTWAKE_DIN26,Enable fastwake feature for DIN26" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 25. "FASTWAKE_DIN25,Enable fastwake feature for DIN25" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x4 24. "FASTWAKE_DIN24,Enable fastwake feature for DIN24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 23. "FASTWAKE_DIN23,Enable fastwake feature for DIN23" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 22. "FASTWAKE_DIN22,Enable fastwake feature for DIN22" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 21. "FASTWAKE_DIN21,Enable fastwake feature for DIN21" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 20. "FASTWAKE_DIN20,Enable fastwake feature for DIN20" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 19. "FASTWAKE_DIN19,Enable fastwake feature for DIN19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 18. "FASTWAKE_DIN18,Enable fastwake feature for DIN18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 17. "FASTWAKE_DIN17,Enable fastwake feature for DIN17" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 16. "FASTWAKE_DIN16,Enable fastwake feature for DIN16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 15. "FASTWAKE_DIN15,Enable fastwake feature for DIN15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 14. "FASTWAKE_DIN14,Enable fastwake feature for DIN14" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 13. "FASTWAKE_DIN13,Enable fastwake feature for DIN13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 12. "FASTWAKE_DIN12,Enable fastwake feature for DIN12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 11. "FASTWAKE_DIN11,Enable fastwake feature for DIN11" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 10. "FASTWAKE_DIN10,Enable fastwake feature for DIN10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 9. "FASTWAKE_DIN9,Enable fastwake feature for DIN9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "FASTWAKE_DIN8,Enable fastwake feature for DIN8" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 7. "FASTWAKE_DIN7,Enable fastwake feature for DIN7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "FASTWAKE_DIN6,Enable fastwake feature for DIN6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "FASTWAKE_DIN5,Enable fastwake feature for DIN5" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 4. "FASTWAKE_DIN4,Enable fastwake feature for DIN4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 3. "FASTWAKE_DIN3,Enable fastwake feature for DIN3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "FASTWAKE_DIN2,Enable fastwake feature for DIN2" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 1. "FASTWAKE_DIN1,Enable fastwake feature for DIN1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "FASTWAKE_DIN0,Enable fastwake feature for DIN0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "SUB0CFG,Subscriber 0 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB0CFG_INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB0CFG_OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB0CFG_ENABLE,This bit is used to enable subscriber 0 event." "0: CLR,1: SET"
|
|
group.long 0x1508++0xB
|
|
line.long 0x0 "FILTEREN15_0,Filter Enable 15 to 0"
|
|
bitfld.long 0x0 30.--31. "FILTEREN15_0_DIN15,Programmable counter length of digital glitch filter for DIN15" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
bitfld.long 0x0 28.--29. "FILTEREN15_0_DIN14,Programmable counter length of digital glitch filter for DIN14" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 26.--27. "FILTEREN15_0_DIN13,Programmable counter length of digital glitch filter for DIN13" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
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bitfld.long 0x0 24.--25. "FILTEREN15_0_DIN12,Programmable counter length of digital glitch filter for DIN12" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
bitfld.long 0x0 22.--23. "FILTEREN15_0_DIN11,Programmable counter length of digital glitch filter for DIN11" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 20.--21. "FILTEREN15_0_DIN10,Programmable counter length of digital glitch filter for DIN10" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
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bitfld.long 0x0 18.--19. "FILTEREN15_0_DIN9,Programmable counter length of digital glitch filter for DIN9" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
bitfld.long 0x0 16.--17. "FILTEREN15_0_DIN8,Programmable counter length of digital glitch filter for DIN8" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 14.--15. "FILTEREN15_0_DIN7,Programmable counter length of digital glitch filter for DIN7" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
|
|
bitfld.long 0x0 12.--13. "FILTEREN15_0_DIN6,Programmable counter length of digital glitch filter for DIN6" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 10.--11. "FILTEREN15_0_DIN5,Programmable counter length of digital glitch filter for DIN5" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
bitfld.long 0x0 8.--9. "FILTEREN15_0_DIN4,Programmable counter length of digital glitch filter for DIN4" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "FILTEREN15_0_DIN3,Programmable counter length of digital glitch filter for DIN3" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 4.--5. "FILTEREN15_0_DIN2,Programmable counter length of digital glitch filter for DIN2" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 2.--3. "FILTEREN15_0_DIN1,Programmable counter length of digital glitch filter for DIN1" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "FILTEREN15_0_DIN0,Programmable counter length of digital glitch filter for DIN0" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
line.long 0x4 "FILTEREN31_16,Filter Enable 31 to 16"
|
|
bitfld.long 0x4 30.--31. "FILTEREN31_16_DIN31,Programmable counter length of digital glitch filter for DIN31" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 28.--29. "FILTEREN31_16_DIN30,Programmable counter length of digital glitch filter for DIN30" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 26.--27. "FILTEREN31_16_DIN29,Programmable counter length of digital glitch filter for DIN29" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "FILTEREN31_16_DIN28,Programmable counter length of digital glitch filter for DIN28" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 22.--23. "FILTEREN31_16_DIN27,Programmable counter length of digital glitch filter for DIN27" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
bitfld.long 0x4 20.--21. "FILTEREN31_16_DIN26,Programmable counter length of digital glitch filter for DIN26" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
|
|
bitfld.long 0x4 18.--19. "FILTEREN31_16_DIN25,Programmable counter length of digital glitch filter for DIN25" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 16.--17. "FILTEREN31_16_DIN24,Programmable counter length of digital glitch filter for DIN24" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 14.--15. "FILTEREN31_16_DIN23,Programmable counter length of digital glitch filter for DIN23" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "FILTEREN31_16_DIN22,Programmable counter length of digital glitch filter for DIN22" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 10.--11. "FILTEREN31_16_DIN21,Programmable counter length of digital glitch filter for DIN21" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 8.--9. "FILTEREN31_16_DIN20,Programmable counter length of digital glitch filter for DIN20" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FILTEREN31_16_DIN19,Programmable counter length of digital glitch filter for DIN19" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 4.--5. "FILTEREN31_16_DIN18,Programmable counter length of digital glitch filter for DIN18" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 2.--3. "FILTEREN31_16_DIN17,Programmable counter length of digital glitch filter for DIN17" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
|
|
bitfld.long 0x4 0.--1. "FILTEREN31_16_DIN16,Programmable counter length of digital glitch filter for DIN16" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
line.long 0x8 "DMAMASK,DMA Write MASK"
|
|
bitfld.long 0x8 31. "DMAMASK_DOUT31,DMA is allowed to modify DOUT31" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 30. "DMAMASK_DOUT30,DMA is allowed to modify DOUT30" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 29. "DMAMASK_DOUT29,DMA is allowed to modify DOUT29" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 28. "DMAMASK_DOUT28,DMA is allowed to modify DOUT28" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 27. "DMAMASK_DOUT27,DMA is allowed to modify DOUT27" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 26. "DMAMASK_DOUT26,DMA is allowed to modify DOUT26" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 25. "DMAMASK_DOUT25,DMA is allowed to modify DOUT25" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 24. "DMAMASK_DOUT24,DMA is allowed to modify DOUT24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 23. "DMAMASK_DOUT23,DMA is allowed to modify DOUT23" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 22. "DMAMASK_DOUT22,DMA is allowed to modify DOUT22" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 21. "DMAMASK_DOUT21,DMA is allowed to modify DOUT21" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 20. "DMAMASK_DOUT20,DMA is allowed to modify DOUT20" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 19. "DMAMASK_DOUT19,DMA is allowed to modify DOUT19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 18. "DMAMASK_DOUT18,DMA is allowed to modify DOUT18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 17. "DMAMASK_DOUT17,DMA is allowed to modify DOUT17" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 16. "DMAMASK_DOUT16,DMA is allowed to modify DOUT16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 15. "DMAMASK_DOUT15,DMA is allowed to modify DOUT15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 14. "DMAMASK_DOUT14,DMA is allowed to modify DOUT14" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 13. "DMAMASK_DOUT13,DMA is allowed to modify DOUT13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 12. "DMAMASK_DOUT12,DMA is allowed to modify DOUT12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 11. "DMAMASK_DOUT11,DMA is allowed to modify DOUT11" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 10. "DMAMASK_DOUT10,DMA is allowed to modify DOUT10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 9. "DMAMASK_DOUT9,DMA is allowed to modify DOUT9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "DMAMASK_DOUT8,DMA is allowed to modify DOUT8" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAMASK_DOUT7,DMA is allowed to modify DOUT7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 6. "DMAMASK_DOUT6,DMA is allowed to modify DOUT6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 5. "DMAMASK_DOUT5,DMA is allowed to modify DOUT5" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "DMAMASK_DOUT4,DMA is allowed to modify DOUT4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 3. "DMAMASK_DOUT3,DMA is allowed to modify DOUT3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 2. "DMAMASK_DOUT2,DMA is allowed to modify DOUT2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "DMAMASK_DOUT1,DMA is allowed to modify DOUT1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 0. "DMAMASK_DOUT0,DMA is allowed to modify DOUT0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1520++0x3
|
|
line.long 0x0 "SUB1CFG,Subscriber 1 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB1CFG_INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB1CFG_OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB1CFG_ENABLE,This bit is used to enable subscriber 1 event." "0: CLR,1: SET"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "GPIOB"
|
|
base ad:0x400A2000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1010++0x3
|
|
line.long 0x0 "CLKOVR,Clock Override"
|
|
bitfld.long 0x0 1. "CLKOVR_RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: RUN,1: STOP"
|
|
bitfld.long 0x0 0. "CLKOVR_OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT0_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "INT_EVENT0_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT0_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT0_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT0_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT0_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT0_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT0_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT0_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT0_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "INT_EVENT0_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "INT_EVENT0_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "INT_EVENT0_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "INT_EVENT0_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "INT_EVENT0_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "INT_EVENT0_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "INT_EVENT0_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "INT_EVENT0_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "INT_EVENT0_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT0_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 15. "INT_EVENT1_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 15. "INT_EVENT1_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 15. "INT_EVENT1_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 15. "INT_EVENT1_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT1_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "INT_EVENT1_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "INT_EVENT1_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "INT_EVENT1_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT1_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 15. "INT_EVENT1_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT1_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "INT_EVENT1_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT1_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "INT_EVENT1_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT1_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT1_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "INT_EVENT1_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT1_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT1_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT1_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT2_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT2_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT2_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "INT_EVENT2_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "INT_EVENT2_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "INT_EVENT2_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "INT_EVENT2_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "INT_EVENT2_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "INT_EVENT2_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "INT_EVENT2_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "INT_EVENT2_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "INT_EVENT2_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "INT_EVENT2_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "INT_EVENT2_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "INT_EVENT2_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT2_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "INT_EVENT2_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "INT_EVENT2_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT2_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "INT_EVENT2_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "INT_EVENT2_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT2_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "INT_EVENT2_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "INT_EVENT2_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT2_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "INT_EVENT2_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "INT_EVENT2_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT2_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
wgroup.long 0x1200++0x1F
|
|
line.long 0x0 "DOUT3_0,Data output 3 to 0"
|
|
bitfld.long 0x0 24. "DOUT3_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 16. "DOUT3_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "DOUT3_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x0 0. "DOUT3_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x4 "DOUT7_4,Data output 7 to 4"
|
|
bitfld.long 0x4 24. "DOUT7_4_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 16. "DOUT7_4_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 8. "DOUT7_4_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x4 0. "DOUT7_4_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x8 "DOUT11_8,Data output 11 to 8"
|
|
bitfld.long 0x8 24. "DOUT11_8_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 16. "DOUT11_8_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 8. "DOUT11_8_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x8 0. "DOUT11_8_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0xC "DOUT15_12,Data output 15 to 12"
|
|
bitfld.long 0xC 24. "DOUT15_12_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "DOUT15_12_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "DOUT15_12_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0xC 0. "DOUT15_12_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DOUT19_16,Data output 19 to 16"
|
|
bitfld.long 0x10 24. "DOUT19_16_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DOUT19_16_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DOUT19_16_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x10 0. "DOUT19_16_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DOUT23_20,Data output 23 to 20"
|
|
bitfld.long 0x14 24. "DOUT23_20_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 16. "DOUT23_20_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DOUT23_20_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x14 0. "DOUT23_20_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x18 "DOUT27_24,Data output 27 to 24"
|
|
bitfld.long 0x18 24. "DOUT27_24_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 16. "DOUT27_24_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DOUT27_24_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x18 0. "DOUT27_24_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x1C "DOUT31_28,Data output 31 to 28"
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bitfld.long 0x1C 24. "DOUT31_28_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x1C 16. "DOUT31_28_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x1C 8. "DOUT31_28_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x1C 0. "DOUT31_28_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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group.long 0x1280++0x3
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line.long 0x0 "DOUT31_0,Data output 31 to 0"
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bitfld.long 0x0 31. "DOUT31_0_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 30. "DOUT31_0_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 29. "DOUT31_0_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 28. "DOUT31_0_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 27. "DOUT31_0_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 26. "DOUT31_0_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 25. "DOUT31_0_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 24. "DOUT31_0_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 23. "DOUT31_0_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 22. "DOUT31_0_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 21. "DOUT31_0_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 20. "DOUT31_0_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 19. "DOUT31_0_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 18. "DOUT31_0_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 17. "DOUT31_0_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DOUT31_0_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 15. "DOUT31_0_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 14. "DOUT31_0_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 13. "DOUT31_0_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 12. "DOUT31_0_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 11. "DOUT31_0_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 10. "DOUT31_0_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 9. "DOUT31_0_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DOUT31_0_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 7. "DOUT31_0_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 6. "DOUT31_0_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 5. "DOUT31_0_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 4. "DOUT31_0_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 3. "DOUT31_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 2. "DOUT31_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 1. "DOUT31_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DOUT31_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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wgroup.long 0x1290++0x3
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line.long 0x0 "DOUTSET31_0,Data output set 31 to 0"
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bitfld.long 0x0 31. "DOUTSET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOUTSET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOUTSET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOUTSET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOUTSET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOUTSET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOUTSET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOUTSET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOUTSET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOUTSET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOUTSET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOUTSET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOUTSET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOUTSET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOUTSET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOUTSET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOUTSET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOUTSET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOUTSET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOUTSET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOUTSET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOUTSET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOUTSET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOUTSET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOUTSET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOUTSET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOUTSET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOUTSET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOUTSET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOUTSET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOUTSET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOUTSET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12A0++0x3
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line.long 0x0 "DOUTCLR31_0,Data output clear 31 to 0"
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bitfld.long 0x0 31. "DOUTCLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOUTCLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOUTCLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOUTCLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOUTCLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOUTCLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOUTCLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOUTCLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOUTCLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOUTCLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOUTCLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOUTCLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOUTCLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOUTCLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOUTCLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOUTCLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOUTCLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOUTCLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOUTCLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOUTCLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOUTCLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOUTCLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOUTCLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOUTCLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOUTCLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOUTCLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOUTCLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOUTCLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOUTCLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOUTCLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOUTCLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOUTCLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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wgroup.long 0x12B0++0x3
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line.long 0x0 "DOUTTGL31_0,Data output toggle 31 to 0"
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bitfld.long 0x0 31. "DOUTTGL31_0_DIO31,This bit is used to toggle DIO31 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 30. "DOUTTGL31_0_DIO30,This bit is used to toggle DIO30 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 29. "DOUTTGL31_0_DIO29,This bit is used to toggle DIO29 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 28. "DOUTTGL31_0_DIO28,This bit is used to toggle DIO28 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 27. "DOUTTGL31_0_DIO27,This bit is used to toggle DIO27 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 26. "DOUTTGL31_0_DIO26,This bit is used to toggle DIO26 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 25. "DOUTTGL31_0_DIO25,This bit is used to toggle DIO25 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 24. "DOUTTGL31_0_DIO24,This bit is used to toggle DIO24 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 23. "DOUTTGL31_0_DIO23,This bit is used to toggle DIO23 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 22. "DOUTTGL31_0_DIO22,This bit is used to toggle DIO22 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 21. "DOUTTGL31_0_DIO21,This bit is used to toggle DIO21 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 20. "DOUTTGL31_0_DIO20,This bit is used to toggle DIO20 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 19. "DOUTTGL31_0_DIO19,This bit is used to toggle DIO19 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 18. "DOUTTGL31_0_DIO18,This bit is used to toggle DIO18 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 17. "DOUTTGL31_0_DIO17,This bit is used to toggle DIO17 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 16. "DOUTTGL31_0_DIO16,This bit is used to toggle DIO16 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 15. "DOUTTGL31_0_DIO15,This bit is used to toggle DIO15 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 14. "DOUTTGL31_0_DIO14,This bit is used to toggle DIO14 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 13. "DOUTTGL31_0_DIO13,This bit is used to toggle DIO13 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 12. "DOUTTGL31_0_DIO12,This bit is used to toggle DIO12 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 11. "DOUTTGL31_0_DIO11,This bit is used to toggle DIO11 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 10. "DOUTTGL31_0_DIO10,This bit is used to toggle DIO10 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 9. "DOUTTGL31_0_DIO9,This bit is used to toggle DIO9 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 8. "DOUTTGL31_0_DIO8,This bit is used to toggle DIO8 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 7. "DOUTTGL31_0_DIO7,This bit is used to toggle DIO7 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 6. "DOUTTGL31_0_DIO6,This bit is used to toggle DIO6 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 5. "DOUTTGL31_0_DIO5,This bit is used to toggle DIO5 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 4. "DOUTTGL31_0_DIO4,This bit is used to toggle DIO4 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 3. "DOUTTGL31_0_DIO3,This bit is used to toggle DIO3 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 2. "DOUTTGL31_0_DIO2,This bit is used to toggle DIO2 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 1. "DOUTTGL31_0_DIO1,This bit is used to toggle DIO1 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 0. "DOUTTGL31_0_DIO0,This bit is used to toggle DIO0 output." "0: NO_EFFECT,1: TOGGLE"
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group.long 0x12C0++0x3
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line.long 0x0 "DOE31_0,Data output enable 31 to 0"
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bitfld.long 0x0 31. "DOE31_0_DIO31,Enables data output for DIO31." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 30. "DOE31_0_DIO30,Enables data output for DIO30." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 29. "DOE31_0_DIO29,Enables data output for DIO29." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 28. "DOE31_0_DIO28,Enables data output for DIO28." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 27. "DOE31_0_DIO27,Enables data output for DIO27." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 26. "DOE31_0_DIO26,Enables data output for DIO26." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 25. "DOE31_0_DIO25,Enables data output for DIO25." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 24. "DOE31_0_DIO24,Enables data output for DIO24." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 23. "DOE31_0_DIO23,Enables data output for DIO23." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 22. "DOE31_0_DIO22,Enables data output for DIO22." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 21. "DOE31_0_DIO21,Enables data output for DIO21." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 20. "DOE31_0_DIO20,Enables data output for DIO20." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 19. "DOE31_0_DIO19,Enables data output for DIO19." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 18. "DOE31_0_DIO18,Enables data output for DIO18." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 17. "DOE31_0_DIO17,Enables data output for DIO17." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 16. "DOE31_0_DIO16,Enables data output for DIO16." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 15. "DOE31_0_DIO15,Enables data output for DIO15." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 14. "DOE31_0_DIO14,Enables data output for DIO14." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 13. "DOE31_0_DIO13,Enables data output for DIO13." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "DOE31_0_DIO12,Enables data output for DIO12." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 11. "DOE31_0_DIO11,Enables data output for DIO11." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 10. "DOE31_0_DIO10,Enables data output for DIO10." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 9. "DOE31_0_DIO9,Enables data output for DIO9." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 8. "DOE31_0_DIO8,Enables data output for DIO8." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 7. "DOE31_0_DIO7,Enables data output for DIO7." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 6. "DOE31_0_DIO6,Enables data output for DIO6." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 5. "DOE31_0_DIO5,Enables data output for DIO5." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 4. "DOE31_0_DIO4,Enables data output for DIO4." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "DOE31_0_DIO3,Enables data output for DIO3." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "DOE31_0_DIO2,Enables data output for DIO2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 1. "DOE31_0_DIO1,Enables data output for DIO1." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "DOE31_0_DIO0,Enables data output for DIO0." "0: DISABLE,1: ENABLE"
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wgroup.long 0x12D0++0x3
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line.long 0x0 "DOESET31_0,Data output enable set 31 to 0"
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bitfld.long 0x0 31. "DOESET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOESET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOESET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOESET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOESET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOESET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOESET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOESET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOESET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOESET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOESET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOESET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOESET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOESET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOESET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOESET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOESET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOESET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOESET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOESET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOESET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOESET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOESET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOESET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOESET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOESET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOESET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOESET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOESET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOESET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOESET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOESET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12E0++0x3
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line.long 0x0 "DOECLR31_0,Data output enable clear 31 to 0"
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bitfld.long 0x0 31. "DOECLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOECLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOECLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOECLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOECLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOECLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOECLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOECLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOECLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOECLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOECLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOECLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOECLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOECLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOECLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOECLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOECLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOECLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOECLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOECLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOECLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOECLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOECLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOECLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOECLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOECLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOECLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOECLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOECLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOECLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOECLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOECLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1300++0x1F
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line.long 0x0 "DIN3_0,Data input 3 to 0"
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bitfld.long 0x0 24. "DIN3_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DIN3_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DIN3_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DIN3_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
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line.long 0x4 "DIN7_4,Data input 7 to 4"
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bitfld.long 0x4 24. "DIN7_4_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
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bitfld.long 0x4 16. "DIN7_4_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
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bitfld.long 0x4 8. "DIN7_4_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
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bitfld.long 0x4 0. "DIN7_4_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
|
|
line.long 0x8 "DIN11_8,Data input 11 to 8"
|
|
bitfld.long 0x8 24. "DIN11_8_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 16. "DIN11_8_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 8. "DIN11_8_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x8 0. "DIN11_8_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
|
|
line.long 0xC "DIN15_12,Data input 15 to 12"
|
|
bitfld.long 0xC 24. "DIN15_12_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "DIN15_12_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "DIN15_12_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0xC 0. "DIN15_12_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DIN19_16,Data input 19 to 16"
|
|
bitfld.long 0x10 24. "DIN19_16_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DIN19_16_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DIN19_16_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x10 0. "DIN19_16_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DIN23_20,Data input 23 to 20"
|
|
bitfld.long 0x14 24. "DIN23_20_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 16. "DIN23_20_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DIN23_20_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x14 0. "DIN23_20_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
|
|
line.long 0x18 "DIN27_24,Data input 27 to 24"
|
|
bitfld.long 0x18 24. "DIN27_24_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 16. "DIN27_24_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DIN27_24_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x18 0. "DIN27_24_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
|
|
line.long 0x1C "DIN31_28,Data input 31 to 28"
|
|
bitfld.long 0x1C 24. "DIN31_28_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 16. "DIN31_28_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 8. "DIN31_28_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x1C 0. "DIN31_28_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
|
|
rgroup.long 0x1380++0x3
|
|
line.long 0x0 "DIN31_0,Data input 31 to 0"
|
|
bitfld.long 0x0 31. "DIN31_0_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 30. "DIN31_0_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 29. "DIN31_0_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 28. "DIN31_0_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 27. "DIN31_0_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 26. "DIN31_0_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x0 25. "DIN31_0_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 24. "DIN31_0_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 23. "DIN31_0_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 22. "DIN31_0_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 21. "DIN31_0_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 20. "DIN31_0_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 19. "DIN31_0_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 18. "DIN31_0_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 17. "DIN31_0_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 16. "DIN31_0_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 15. "DIN31_0_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 14. "DIN31_0_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 13. "DIN31_0_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 12. "DIN31_0_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 11. "DIN31_0_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 10. "DIN31_0_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 9. "DIN31_0_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "DIN31_0_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 7. "DIN31_0_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 6. "DIN31_0_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 5. "DIN31_0_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 4. "DIN31_0_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 3. "DIN31_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 2. "DIN31_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 1. "DIN31_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 0. "DIN31_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
|
|
group.long 0x1390++0x3
|
|
line.long 0x0 "POLARITY15_0,Polarity 15 to 0"
|
|
bitfld.long 0x0 30.--31. "POLARITY15_0_DIO15,Enables and configures edge detection polarity for DIO15." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 28.--29. "POLARITY15_0_DIO14,Enables and configures edge detection polarity for DIO14." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 26.--27. "POLARITY15_0_DIO13,Enables and configures edge detection polarity for DIO13." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "POLARITY15_0_DIO12,Enables and configures edge detection polarity for DIO12." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 22.--23. "POLARITY15_0_DIO11,Enables and configures edge detection polarity for DIO11." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 20.--21. "POLARITY15_0_DIO10,Enables and configures edge detection polarity for DIO10." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "POLARITY15_0_DIO9,Enables and configures edge detection polarity for DIO9." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 16.--17. "POLARITY15_0_DIO8,Enables and configures edge detection polarity for DIO8." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 14.--15. "POLARITY15_0_DIO7,Enables and configures edge detection polarity for DIO7." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "POLARITY15_0_DIO6,Enables and configures edge detection polarity for DIO6." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 10.--11. "POLARITY15_0_DIO5,Enables and configures edge detection polarity for DIO5." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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|
bitfld.long 0x0 8.--9. "POLARITY15_0_DIO4,Enables and configures edge detection polarity for DIO4." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "POLARITY15_0_DIO3,Enables and configures edge detection polarity for DIO3." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 4.--5. "POLARITY15_0_DIO2,Enables and configures edge detection polarity for DIO2." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
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bitfld.long 0x0 2.--3. "POLARITY15_0_DIO1,Enables and configures edge detection polarity for DIO1." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "POLARITY15_0_DIO0,Enables and configures edge detection polarity for DIO0." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
group.long 0x13A0++0x3
|
|
line.long 0x0 "POLARITY31_16,Polarity 31 to 16"
|
|
bitfld.long 0x0 30.--31. "POLARITY31_16_DIO31,Enables and configures edge detection polarity for DIO31." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 28.--29. "POLARITY31_16_DIO30,Enables and configures edge detection polarity for DIO30." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 26.--27. "POLARITY31_16_DIO29,Enables and configures edge detection polarity for DIO29." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "POLARITY31_16_DIO28,Enables and configures edge detection polarity for DIO28." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 22.--23. "POLARITY31_16_DIO27,Enables and configures edge detection polarity for DIO27." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 20.--21. "POLARITY31_16_DIO26,Enables and configures edge detection polarity for DIO26." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "POLARITY31_16_DIO25,Enables and configures edge detection polarity for DIO25." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 16.--17. "POLARITY31_16_DIO24,Enables and configures edge detection polarity for DIO24." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 14.--15. "POLARITY31_16_DIO23,Enables and configures edge detection polarity for DIO23." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "POLARITY31_16_DIO22,Enables and configures edge detection polarity for DIO22." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 10.--11. "POLARITY31_16_DIO21,Enables and configures edge detection polarity for DIO21." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 8.--9. "POLARITY31_16_DIO20,Enables and configures edge detection polarity for DIO20." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "POLARITY31_16_DIO19,Enables and configures edge detection polarity for DIO19." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 4.--5. "POLARITY31_16_DIO18,Enables and configures edge detection polarity for DIO18." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 2.--3. "POLARITY31_16_DIO17,Enables and configures edge detection polarity for DIO17." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
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bitfld.long 0x0 0.--1. "POLARITY31_16_DIO16,Enables and configures edge detection polarity for DIO16." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
group.long 0x1400++0x7
|
|
line.long 0x0 "CTL,FAST WAKE GLOBAL EN"
|
|
bitfld.long 0x0 0. "CTL_FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: NOT_GLOBAL_EN,1: GLOBAL_EN"
|
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line.long 0x4 "FASTWAKE,FAST WAKE ENABLE"
|
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bitfld.long 0x4 31. "FASTWAKE_DIN31,Enable fastwake feature for DIN31" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 30. "FASTWAKE_DIN30,Enable fastwake feature for DIN30" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 29. "FASTWAKE_DIN29,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 28. "FASTWAKE_DIN28,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 27. "FASTWAKE_DIN27,Enable fastwake feature for DIN27" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 26. "FASTWAKE_DIN26,Enable fastwake feature for DIN26" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 25. "FASTWAKE_DIN25,Enable fastwake feature for DIN25" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 24. "FASTWAKE_DIN24,Enable fastwake feature for DIN24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 23. "FASTWAKE_DIN23,Enable fastwake feature for DIN23" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 22. "FASTWAKE_DIN22,Enable fastwake feature for DIN22" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 21. "FASTWAKE_DIN21,Enable fastwake feature for DIN21" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 20. "FASTWAKE_DIN20,Enable fastwake feature for DIN20" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 19. "FASTWAKE_DIN19,Enable fastwake feature for DIN19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 18. "FASTWAKE_DIN18,Enable fastwake feature for DIN18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 17. "FASTWAKE_DIN17,Enable fastwake feature for DIN17" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 16. "FASTWAKE_DIN16,Enable fastwake feature for DIN16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 15. "FASTWAKE_DIN15,Enable fastwake feature for DIN15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 14. "FASTWAKE_DIN14,Enable fastwake feature for DIN14" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 13. "FASTWAKE_DIN13,Enable fastwake feature for DIN13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 12. "FASTWAKE_DIN12,Enable fastwake feature for DIN12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 11. "FASTWAKE_DIN11,Enable fastwake feature for DIN11" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 10. "FASTWAKE_DIN10,Enable fastwake feature for DIN10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 9. "FASTWAKE_DIN9,Enable fastwake feature for DIN9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "FASTWAKE_DIN8,Enable fastwake feature for DIN8" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 7. "FASTWAKE_DIN7,Enable fastwake feature for DIN7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "FASTWAKE_DIN6,Enable fastwake feature for DIN6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "FASTWAKE_DIN5,Enable fastwake feature for DIN5" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4. "FASTWAKE_DIN4,Enable fastwake feature for DIN4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 3. "FASTWAKE_DIN3,Enable fastwake feature for DIN3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "FASTWAKE_DIN2,Enable fastwake feature for DIN2" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 1. "FASTWAKE_DIN1,Enable fastwake feature for DIN1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "FASTWAKE_DIN0,Enable fastwake feature for DIN0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "SUB0CFG,Subscriber 0 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB0CFG_INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB0CFG_OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB0CFG_ENABLE,This bit is used to enable subscriber 0 event." "0: CLR,1: SET"
|
|
group.long 0x1508++0xB
|
|
line.long 0x0 "FILTEREN15_0,Filter Enable 15 to 0"
|
|
bitfld.long 0x0 30.--31. "FILTEREN15_0_DIN15,Programmable counter length of digital glitch filter for DIN15" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 28.--29. "FILTEREN15_0_DIN14,Programmable counter length of digital glitch filter for DIN14" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 26.--27. "FILTEREN15_0_DIN13,Programmable counter length of digital glitch filter for DIN13" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
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bitfld.long 0x0 24.--25. "FILTEREN15_0_DIN12,Programmable counter length of digital glitch filter for DIN12" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 22.--23. "FILTEREN15_0_DIN11,Programmable counter length of digital glitch filter for DIN11" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 20.--21. "FILTEREN15_0_DIN10,Programmable counter length of digital glitch filter for DIN10" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "FILTEREN15_0_DIN9,Programmable counter length of digital glitch filter for DIN9" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 16.--17. "FILTEREN15_0_DIN8,Programmable counter length of digital glitch filter for DIN8" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 14.--15. "FILTEREN15_0_DIN7,Programmable counter length of digital glitch filter for DIN7" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "FILTEREN15_0_DIN6,Programmable counter length of digital glitch filter for DIN6" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 10.--11. "FILTEREN15_0_DIN5,Programmable counter length of digital glitch filter for DIN5" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 8.--9. "FILTEREN15_0_DIN4,Programmable counter length of digital glitch filter for DIN4" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "FILTEREN15_0_DIN3,Programmable counter length of digital glitch filter for DIN3" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 4.--5. "FILTEREN15_0_DIN2,Programmable counter length of digital glitch filter for DIN2" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 2.--3. "FILTEREN15_0_DIN1,Programmable counter length of digital glitch filter for DIN1" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "FILTEREN15_0_DIN0,Programmable counter length of digital glitch filter for DIN0" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
line.long 0x4 "FILTEREN31_16,Filter Enable 31 to 16"
|
|
bitfld.long 0x4 30.--31. "FILTEREN31_16_DIN31,Programmable counter length of digital glitch filter for DIN31" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 28.--29. "FILTEREN31_16_DIN30,Programmable counter length of digital glitch filter for DIN30" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 26.--27. "FILTEREN31_16_DIN29,Programmable counter length of digital glitch filter for DIN29" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "FILTEREN31_16_DIN28,Programmable counter length of digital glitch filter for DIN28" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 22.--23. "FILTEREN31_16_DIN27,Programmable counter length of digital glitch filter for DIN27" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 20.--21. "FILTEREN31_16_DIN26,Programmable counter length of digital glitch filter for DIN26" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 18.--19. "FILTEREN31_16_DIN25,Programmable counter length of digital glitch filter for DIN25" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 16.--17. "FILTEREN31_16_DIN24,Programmable counter length of digital glitch filter for DIN24" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 14.--15. "FILTEREN31_16_DIN23,Programmable counter length of digital glitch filter for DIN23" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "FILTEREN31_16_DIN22,Programmable counter length of digital glitch filter for DIN22" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 10.--11. "FILTEREN31_16_DIN21,Programmable counter length of digital glitch filter for DIN21" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 8.--9. "FILTEREN31_16_DIN20,Programmable counter length of digital glitch filter for DIN20" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "FILTEREN31_16_DIN19,Programmable counter length of digital glitch filter for DIN19" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 4.--5. "FILTEREN31_16_DIN18,Programmable counter length of digital glitch filter for DIN18" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x4 2.--3. "FILTEREN31_16_DIN17,Programmable counter length of digital glitch filter for DIN17" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "FILTEREN31_16_DIN16,Programmable counter length of digital glitch filter for DIN16" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
line.long 0x8 "DMAMASK,DMA Write MASK"
|
|
bitfld.long 0x8 31. "DMAMASK_DOUT31,DMA is allowed to modify DOUT31" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 30. "DMAMASK_DOUT30,DMA is allowed to modify DOUT30" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 29. "DMAMASK_DOUT29,DMA is allowed to modify DOUT29" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 28. "DMAMASK_DOUT28,DMA is allowed to modify DOUT28" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 27. "DMAMASK_DOUT27,DMA is allowed to modify DOUT27" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 26. "DMAMASK_DOUT26,DMA is allowed to modify DOUT26" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 25. "DMAMASK_DOUT25,DMA is allowed to modify DOUT25" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 24. "DMAMASK_DOUT24,DMA is allowed to modify DOUT24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 23. "DMAMASK_DOUT23,DMA is allowed to modify DOUT23" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 22. "DMAMASK_DOUT22,DMA is allowed to modify DOUT22" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 21. "DMAMASK_DOUT21,DMA is allowed to modify DOUT21" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 20. "DMAMASK_DOUT20,DMA is allowed to modify DOUT20" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 19. "DMAMASK_DOUT19,DMA is allowed to modify DOUT19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 18. "DMAMASK_DOUT18,DMA is allowed to modify DOUT18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 17. "DMAMASK_DOUT17,DMA is allowed to modify DOUT17" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 16. "DMAMASK_DOUT16,DMA is allowed to modify DOUT16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 15. "DMAMASK_DOUT15,DMA is allowed to modify DOUT15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 14. "DMAMASK_DOUT14,DMA is allowed to modify DOUT14" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 13. "DMAMASK_DOUT13,DMA is allowed to modify DOUT13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 12. "DMAMASK_DOUT12,DMA is allowed to modify DOUT12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 11. "DMAMASK_DOUT11,DMA is allowed to modify DOUT11" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 10. "DMAMASK_DOUT10,DMA is allowed to modify DOUT10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 9. "DMAMASK_DOUT9,DMA is allowed to modify DOUT9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "DMAMASK_DOUT8,DMA is allowed to modify DOUT8" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 7. "DMAMASK_DOUT7,DMA is allowed to modify DOUT7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 6. "DMAMASK_DOUT6,DMA is allowed to modify DOUT6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 5. "DMAMASK_DOUT5,DMA is allowed to modify DOUT5" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "DMAMASK_DOUT4,DMA is allowed to modify DOUT4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 3. "DMAMASK_DOUT3,DMA is allowed to modify DOUT3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 2. "DMAMASK_DOUT2,DMA is allowed to modify DOUT2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "DMAMASK_DOUT1,DMA is allowed to modify DOUT1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 0. "DMAMASK_DOUT0,DMA is allowed to modify DOUT0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1520++0x3
|
|
line.long 0x0 "SUB1CFG,Subscriber 1 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB1CFG_INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB1CFG_OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB1CFG_ENABLE,This bit is used to enable subscriber 1 event." "0: CLR,1: SET"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "GPIOC"
|
|
base ad:0x400A4000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1010++0x3
|
|
line.long 0x0 "CLKOVR,Clock Override"
|
|
bitfld.long 0x0 1. "CLKOVR_RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: RUN,1: STOP"
|
|
bitfld.long 0x0 0. "CLKOVR_OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "CPU_INT_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPU_INT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "CPU_INT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "CPU_INT_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "CPU_INT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "CPU_INT_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "CPU_INT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "CPU_INT_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "CPU_INT_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "CPU_INT_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "CPU_INT_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "CPU_INT_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "CPU_INT_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "CPU_INT_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "CPU_INT_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "CPU_INT_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "CPU_INT_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "CPU_INT_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "CPU_INT_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "CPU_INT_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "CPU_INT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "CPU_INT_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "CPU_INT_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "CPU_INT_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "CPU_INT_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "CPU_INT_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "CPU_INT_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "CPU_INT_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "CPU_INT_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "CPU_INT_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "CPU_INT_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "CPU_INT_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "CPU_INT_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "CPU_INT_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "CPU_INT_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "CPU_INT_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "CPU_INT_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "CPU_INT_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "CPU_INT_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "CPU_INT_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "CPU_INT_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "CPU_INT_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "CPU_INT_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "CPU_INT_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "CPU_INT_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "CPU_INT_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "CPU_INT_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "CPU_INT_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "CPU_INT_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "CPU_INT_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "GEN_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "GEN_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "GEN_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_IMASK_DIO15,DIO15 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_IMASK_DIO14,DIO14 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_IMASK_DIO13,DIO13 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_IMASK_DIO12,DIO12 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_IMASK_DIO11,DIO11 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_IMASK_DIO10,DIO10 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_IMASK_DIO9,DIO9 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_IMASK_DIO8,DIO8 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_IMASK_DIO7,DIO7 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_IMASK_DIO6,DIO6 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_IMASK_DIO5,DIO5 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_IMASK_DIO4,DIO4 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_IMASK_DIO3,DIO3 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_IMASK_DIO2,DIO2 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_IMASK_DIO1,DIO1 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_IMASK_DIO0,DIO0 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "GEN_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_RIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_RIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_RIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_RIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_RIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_RIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_RIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_RIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_RIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_RIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_RIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_RIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_RIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_RIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_RIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_RIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "GEN_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_MIS_DIO15,DIO15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_MIS_DIO14,DIO14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_MIS_DIO13,DIO13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_MIS_DIO12,DIO12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_MIS_DIO11,DIO11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_MIS_DIO10,DIO10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_MIS_DIO9,DIO9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_MIS_DIO8,DIO8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_MIS_DIO7,DIO7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_MIS_DIO6,DIO6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_MIS_DIO5,DIO5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_MIS_DIO4,DIO4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_MIS_DIO3,DIO3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_MIS_DIO2,DIO2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_MIS_DIO1,DIO1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_MIS_DIO0,DIO0 event" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "GEN_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_ISET_DIO15,DIO15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_ISET_DIO14,DIO14 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_ISET_DIO13,DIO13 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_ISET_DIO12,DIO12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_ISET_DIO11,DIO11 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_ISET_DIO10,DIO10 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_ISET_DIO9,DIO9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_ISET_DIO8,DIO8 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_ISET_DIO7,DIO7 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_ISET_DIO6,DIO6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_ISET_DIO5,DIO5 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_ISET_DIO4,DIO4 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_ISET_DIO3,DIO3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_ISET_DIO2,DIO2 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_ISET_DIO1,DIO1 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_ISET_DIO0,DIO0 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "GEN_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 15. "GEN_EVENT0_ICLR_DIO15,DIO15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "GEN_EVENT0_ICLR_DIO14,DIO14 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "GEN_EVENT0_ICLR_DIO13,DIO13 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "GEN_EVENT0_ICLR_DIO12,DIO12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "GEN_EVENT0_ICLR_DIO11,DIO11 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "GEN_EVENT0_ICLR_DIO10,DIO10 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 9. "GEN_EVENT0_ICLR_DIO9,DIO9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "GEN_EVENT0_ICLR_DIO8,DIO8 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "GEN_EVENT0_ICLR_DIO7,DIO7 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "GEN_EVENT0_ICLR_DIO6,DIO6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "GEN_EVENT0_ICLR_DIO5,DIO5 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "GEN_EVENT0_ICLR_DIO4,DIO4 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "GEN_EVENT0_ICLR_DIO3,DIO3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "GEN_EVENT0_ICLR_DIO2,DIO2 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "GEN_EVENT0_ICLR_DIO1,DIO1 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "GEN_EVENT0_ICLR_DIO0,DIO0 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "GEN_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "GEN_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "GEN_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_IMASK_DIO31,DIO31 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_IMASK_DIO30,DIO30 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_IMASK_DIO29,DIO29 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_IMASK_DIO28,DIO28 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_IMASK_DIO27,DIO27 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_IMASK_DIO26,DIO26 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_IMASK_DIO25,DIO25 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_IMASK_DIO24,DIO24 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_IMASK_DIO23,DIO23 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_IMASK_DIO22,DIO22 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_IMASK_DIO21,DIO21 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_IMASK_DIO20,DIO20 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_IMASK_DIO19,DIO19 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_IMASK_DIO18,DIO18 event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_IMASK_DIO17,DIO17 event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_IMASK_DIO16,DIO16 event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "GEN_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_RIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_RIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_RIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_RIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_RIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_RIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_RIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_RIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_RIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_RIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_RIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_RIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_RIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_RIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_RIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_RIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "GEN_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_MIS_DIO31,DIO31 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_MIS_DIO30,DIO30 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_MIS_DIO29,DIO29 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_MIS_DIO28,DIO28 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_MIS_DIO27,DIO27 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_MIS_DIO26,DIO26 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_MIS_DIO25,DIO25 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_MIS_DIO24,DIO24 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_MIS_DIO23,DIO23 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_MIS_DIO22,DIO22 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_MIS_DIO21,DIO21 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_MIS_DIO20,DIO20 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_MIS_DIO19,DIO19 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_MIS_DIO18,DIO18 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_MIS_DIO17,DIO17 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_MIS_DIO16,DIO16 event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "GEN_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_ISET_DIO31,DIO31 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_ISET_DIO30,DIO30 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_ISET_DIO29,DIO29 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_ISET_DIO28,DIO28 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_ISET_DIO27,DIO27 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_ISET_DIO26,DIO26 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_ISET_DIO25,DIO25 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_ISET_DIO24,DIO24 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_ISET_DIO23,DIO23 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_ISET_DIO22,DIO22 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_ISET_DIO21,DIO21 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_ISET_DIO20,DIO20 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_ISET_DIO19,DIO19 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_ISET_DIO18,DIO18 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_ISET_DIO17,DIO17 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_ISET_DIO16,DIO16 event" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "GEN_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "GEN_EVENT1_ICLR_DIO31,DIO31 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 30. "GEN_EVENT1_ICLR_DIO30,DIO30 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 29. "GEN_EVENT1_ICLR_DIO29,DIO29 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "GEN_EVENT1_ICLR_DIO28,DIO28 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "GEN_EVENT1_ICLR_DIO27,DIO27 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 26. "GEN_EVENT1_ICLR_DIO26,DIO26 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "GEN_EVENT1_ICLR_DIO25,DIO25 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "GEN_EVENT1_ICLR_DIO24,DIO24 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 23. "GEN_EVENT1_ICLR_DIO23,DIO23 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "GEN_EVENT1_ICLR_DIO22,DIO22 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "GEN_EVENT1_ICLR_DIO21,DIO21 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 20. "GEN_EVENT1_ICLR_DIO20,DIO20 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 19. "GEN_EVENT1_ICLR_DIO19,DIO19 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "GEN_EVENT1_ICLR_DIO18,DIO18 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 17. "GEN_EVENT1_ICLR_DIO17,DIO17 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "GEN_EVENT1_ICLR_DIO16,DIO16 event" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.GEN_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.CPU_INT]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
wgroup.long 0x1200++0x1F
|
|
line.long 0x0 "DOUT3_0,Data output 3 to 0"
|
|
bitfld.long 0x0 24. "DOUT3_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 16. "DOUT3_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "DOUT3_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x0 0. "DOUT3_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x4 "DOUT7_4,Data output 7 to 4"
|
|
bitfld.long 0x4 24. "DOUT7_4_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 16. "DOUT7_4_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 8. "DOUT7_4_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x4 0. "DOUT7_4_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x8 "DOUT11_8,Data output 11 to 8"
|
|
bitfld.long 0x8 24. "DOUT11_8_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 16. "DOUT11_8_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 8. "DOUT11_8_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x8 0. "DOUT11_8_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0xC "DOUT15_12,Data output 15 to 12"
|
|
bitfld.long 0xC 24. "DOUT15_12_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "DOUT15_12_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "DOUT15_12_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0xC 0. "DOUT15_12_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DOUT19_16,Data output 19 to 16"
|
|
bitfld.long 0x10 24. "DOUT19_16_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DOUT19_16_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DOUT19_16_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x10 0. "DOUT19_16_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DOUT23_20,Data output 23 to 20"
|
|
bitfld.long 0x14 24. "DOUT23_20_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 16. "DOUT23_20_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DOUT23_20_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x14 0. "DOUT23_20_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
line.long 0x18 "DOUT27_24,Data output 27 to 24"
|
|
bitfld.long 0x18 24. "DOUT27_24_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 16. "DOUT27_24_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DOUT27_24_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x18 0. "DOUT27_24_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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line.long 0x1C "DOUT31_28,Data output 31 to 28"
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bitfld.long 0x1C 24. "DOUT31_28_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x1C 16. "DOUT31_28_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x1C 8. "DOUT31_28_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x1C 0. "DOUT31_28_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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group.long 0x1280++0x3
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line.long 0x0 "DOUT31_0,Data output 31 to 0"
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bitfld.long 0x0 31. "DOUT31_0_DIO31,This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 30. "DOUT31_0_DIO30,This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 29. "DOUT31_0_DIO29,This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 28. "DOUT31_0_DIO28,This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 27. "DOUT31_0_DIO27,This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 26. "DOUT31_0_DIO26,This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 25. "DOUT31_0_DIO25,This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 24. "DOUT31_0_DIO24,This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 23. "DOUT31_0_DIO23,This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 22. "DOUT31_0_DIO22,This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 21. "DOUT31_0_DIO21,This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 20. "DOUT31_0_DIO20,This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 19. "DOUT31_0_DIO19,This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 18. "DOUT31_0_DIO18,This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 17. "DOUT31_0_DIO17,This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DOUT31_0_DIO16,This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 15. "DOUT31_0_DIO15,This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 14. "DOUT31_0_DIO14,This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 13. "DOUT31_0_DIO13,This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 12. "DOUT31_0_DIO12,This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 11. "DOUT31_0_DIO11,This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 10. "DOUT31_0_DIO10,This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 9. "DOUT31_0_DIO9,This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DOUT31_0_DIO8,This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 7. "DOUT31_0_DIO7,This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 6. "DOUT31_0_DIO6,This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 5. "DOUT31_0_DIO5,This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 4. "DOUT31_0_DIO4,This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 3. "DOUT31_0_DIO3,This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 2. "DOUT31_0_DIO2,This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 1. "DOUT31_0_DIO1,This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DOUT31_0_DIO0,This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register." "0: ZERO,1: ONE"
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wgroup.long 0x1290++0x3
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line.long 0x0 "DOUTSET31_0,Data output set 31 to 0"
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bitfld.long 0x0 31. "DOUTSET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOUTSET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOUTSET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOUTSET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOUTSET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOUTSET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOUTSET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOUTSET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOUTSET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOUTSET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOUTSET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOUTSET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOUTSET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOUTSET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOUTSET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOUTSET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOUTSET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOUTSET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOUTSET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOUTSET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOUTSET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOUTSET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOUTSET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOUTSET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOUTSET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOUTSET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOUTSET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOUTSET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOUTSET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOUTSET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOUTSET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOUTSET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12A0++0x3
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line.long 0x0 "DOUTCLR31_0,Data output clear 31 to 0"
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bitfld.long 0x0 31. "DOUTCLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOUTCLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOUTCLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOUTCLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOUTCLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOUTCLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOUTCLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOUTCLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOUTCLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOUTCLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOUTCLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOUTCLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOUTCLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOUTCLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOUTCLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOUTCLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOUTCLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOUTCLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOUTCLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOUTCLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOUTCLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOUTCLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOUTCLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOUTCLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOUTCLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOUTCLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOUTCLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOUTCLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOUTCLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOUTCLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOUTCLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOUTCLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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wgroup.long 0x12B0++0x3
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line.long 0x0 "DOUTTGL31_0,Data output toggle 31 to 0"
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bitfld.long 0x0 31. "DOUTTGL31_0_DIO31,This bit is used to toggle DIO31 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 30. "DOUTTGL31_0_DIO30,This bit is used to toggle DIO30 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 29. "DOUTTGL31_0_DIO29,This bit is used to toggle DIO29 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 28. "DOUTTGL31_0_DIO28,This bit is used to toggle DIO28 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 27. "DOUTTGL31_0_DIO27,This bit is used to toggle DIO27 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 26. "DOUTTGL31_0_DIO26,This bit is used to toggle DIO26 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 25. "DOUTTGL31_0_DIO25,This bit is used to toggle DIO25 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 24. "DOUTTGL31_0_DIO24,This bit is used to toggle DIO24 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 23. "DOUTTGL31_0_DIO23,This bit is used to toggle DIO23 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 22. "DOUTTGL31_0_DIO22,This bit is used to toggle DIO22 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 21. "DOUTTGL31_0_DIO21,This bit is used to toggle DIO21 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 20. "DOUTTGL31_0_DIO20,This bit is used to toggle DIO20 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 19. "DOUTTGL31_0_DIO19,This bit is used to toggle DIO19 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 18. "DOUTTGL31_0_DIO18,This bit is used to toggle DIO18 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 17. "DOUTTGL31_0_DIO17,This bit is used to toggle DIO17 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 16. "DOUTTGL31_0_DIO16,This bit is used to toggle DIO16 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 15. "DOUTTGL31_0_DIO15,This bit is used to toggle DIO15 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 14. "DOUTTGL31_0_DIO14,This bit is used to toggle DIO14 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 13. "DOUTTGL31_0_DIO13,This bit is used to toggle DIO13 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 12. "DOUTTGL31_0_DIO12,This bit is used to toggle DIO12 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 11. "DOUTTGL31_0_DIO11,This bit is used to toggle DIO11 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 10. "DOUTTGL31_0_DIO10,This bit is used to toggle DIO10 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 9. "DOUTTGL31_0_DIO9,This bit is used to toggle DIO9 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 8. "DOUTTGL31_0_DIO8,This bit is used to toggle DIO8 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 7. "DOUTTGL31_0_DIO7,This bit is used to toggle DIO7 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 6. "DOUTTGL31_0_DIO6,This bit is used to toggle DIO6 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 5. "DOUTTGL31_0_DIO5,This bit is used to toggle DIO5 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 4. "DOUTTGL31_0_DIO4,This bit is used to toggle DIO4 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 3. "DOUTTGL31_0_DIO3,This bit is used to toggle DIO3 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 2. "DOUTTGL31_0_DIO2,This bit is used to toggle DIO2 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 1. "DOUTTGL31_0_DIO1,This bit is used to toggle DIO1 output." "0: NO_EFFECT,1: TOGGLE"
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bitfld.long 0x0 0. "DOUTTGL31_0_DIO0,This bit is used to toggle DIO0 output." "0: NO_EFFECT,1: TOGGLE"
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group.long 0x12C0++0x3
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line.long 0x0 "DOE31_0,Data output enable 31 to 0"
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bitfld.long 0x0 31. "DOE31_0_DIO31,Enables data output for DIO31." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 30. "DOE31_0_DIO30,Enables data output for DIO30." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 29. "DOE31_0_DIO29,Enables data output for DIO29." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 28. "DOE31_0_DIO28,Enables data output for DIO28." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 27. "DOE31_0_DIO27,Enables data output for DIO27." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 26. "DOE31_0_DIO26,Enables data output for DIO26." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 25. "DOE31_0_DIO25,Enables data output for DIO25." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 24. "DOE31_0_DIO24,Enables data output for DIO24." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 23. "DOE31_0_DIO23,Enables data output for DIO23." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 22. "DOE31_0_DIO22,Enables data output for DIO22." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 21. "DOE31_0_DIO21,Enables data output for DIO21." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 20. "DOE31_0_DIO20,Enables data output for DIO20." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 19. "DOE31_0_DIO19,Enables data output for DIO19." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 18. "DOE31_0_DIO18,Enables data output for DIO18." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 17. "DOE31_0_DIO17,Enables data output for DIO17." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 16. "DOE31_0_DIO16,Enables data output for DIO16." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 15. "DOE31_0_DIO15,Enables data output for DIO15." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 14. "DOE31_0_DIO14,Enables data output for DIO14." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 13. "DOE31_0_DIO13,Enables data output for DIO13." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "DOE31_0_DIO12,Enables data output for DIO12." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 11. "DOE31_0_DIO11,Enables data output for DIO11." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 10. "DOE31_0_DIO10,Enables data output for DIO10." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 9. "DOE31_0_DIO9,Enables data output for DIO9." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 8. "DOE31_0_DIO8,Enables data output for DIO8." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 7. "DOE31_0_DIO7,Enables data output for DIO7." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 6. "DOE31_0_DIO6,Enables data output for DIO6." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 5. "DOE31_0_DIO5,Enables data output for DIO5." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 4. "DOE31_0_DIO4,Enables data output for DIO4." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "DOE31_0_DIO3,Enables data output for DIO3." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "DOE31_0_DIO2,Enables data output for DIO2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 1. "DOE31_0_DIO1,Enables data output for DIO1." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "DOE31_0_DIO0,Enables data output for DIO0." "0: DISABLE,1: ENABLE"
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wgroup.long 0x12D0++0x3
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line.long 0x0 "DOESET31_0,Data output enable set 31 to 0"
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bitfld.long 0x0 31. "DOESET31_0_DIO31,Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 30. "DOESET31_0_DIO30,Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 29. "DOESET31_0_DIO29,Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 28. "DOESET31_0_DIO28,Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 27. "DOESET31_0_DIO27,Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 26. "DOESET31_0_DIO26,Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 25. "DOESET31_0_DIO25,Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 24. "DOESET31_0_DIO24,Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 23. "DOESET31_0_DIO23,Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 22. "DOESET31_0_DIO22,Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 21. "DOESET31_0_DIO21,Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 20. "DOESET31_0_DIO20,Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 19. "DOESET31_0_DIO19,Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 18. "DOESET31_0_DIO18,Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 17. "DOESET31_0_DIO17,Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "DOESET31_0_DIO16,Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "DOESET31_0_DIO15,Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "DOESET31_0_DIO14,Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "DOESET31_0_DIO13,Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "DOESET31_0_DIO12,Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "DOESET31_0_DIO11,Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "DOESET31_0_DIO10,Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "DOESET31_0_DIO9,Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "DOESET31_0_DIO8,Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "DOESET31_0_DIO7,Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "DOESET31_0_DIO6,Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "DOESET31_0_DIO5,Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "DOESET31_0_DIO4,Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "DOESET31_0_DIO3,Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "DOESET31_0_DIO2,Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "DOESET31_0_DIO1,Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "DOESET31_0_DIO0,Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: SET"
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wgroup.long 0x12E0++0x3
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line.long 0x0 "DOECLR31_0,Data output enable clear 31 to 0"
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bitfld.long 0x0 31. "DOECLR31_0_DIO31,Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 30. "DOECLR31_0_DIO30,Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 29. "DOECLR31_0_DIO29,Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 28. "DOECLR31_0_DIO28,Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 27. "DOECLR31_0_DIO27,Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 26. "DOECLR31_0_DIO26,Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 25. "DOECLR31_0_DIO25,Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 24. "DOECLR31_0_DIO24,Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 23. "DOECLR31_0_DIO23,Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 22. "DOECLR31_0_DIO22,Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 21. "DOECLR31_0_DIO21,Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "DOECLR31_0_DIO20,Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "DOECLR31_0_DIO19,Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "DOECLR31_0_DIO18,Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 17. "DOECLR31_0_DIO17,Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "DOECLR31_0_DIO16,Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "DOECLR31_0_DIO15,Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "DOECLR31_0_DIO14,Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "DOECLR31_0_DIO13,Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "DOECLR31_0_DIO12,Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "DOECLR31_0_DIO11,Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "DOECLR31_0_DIO10,Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "DOECLR31_0_DIO9,Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "DOECLR31_0_DIO8,Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "DOECLR31_0_DIO7,Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "DOECLR31_0_DIO6,Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "DOECLR31_0_DIO5,Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "DOECLR31_0_DIO4,Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "DOECLR31_0_DIO3,Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "DOECLR31_0_DIO2,Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "DOECLR31_0_DIO1,Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "DOECLR31_0_DIO0,Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1300++0x1F
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line.long 0x0 "DIN3_0,Data input 3 to 0"
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bitfld.long 0x0 24. "DIN3_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
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bitfld.long 0x0 16. "DIN3_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
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bitfld.long 0x0 8. "DIN3_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
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bitfld.long 0x0 0. "DIN3_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
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line.long 0x4 "DIN7_4,Data input 7 to 4"
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bitfld.long 0x4 24. "DIN7_4_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
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bitfld.long 0x4 16. "DIN7_4_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 8. "DIN7_4_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x4 0. "DIN7_4_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
|
|
line.long 0x8 "DIN11_8,Data input 11 to 8"
|
|
bitfld.long 0x8 24. "DIN11_8_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 16. "DIN11_8_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 8. "DIN11_8_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x8 0. "DIN11_8_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
|
|
line.long 0xC "DIN15_12,Data input 15 to 12"
|
|
bitfld.long 0xC 24. "DIN15_12_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "DIN15_12_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "DIN15_12_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0xC 0. "DIN15_12_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
|
|
line.long 0x10 "DIN19_16,Data input 19 to 16"
|
|
bitfld.long 0x10 24. "DIN19_16_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 16. "DIN19_16_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
|
|
bitfld.long 0x10 8. "DIN19_16_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x10 0. "DIN19_16_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
|
|
line.long 0x14 "DIN23_20,Data input 23 to 20"
|
|
bitfld.long 0x14 24. "DIN23_20_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 16. "DIN23_20_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
|
|
bitfld.long 0x14 8. "DIN23_20_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x14 0. "DIN23_20_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
|
|
line.long 0x18 "DIN27_24,Data input 27 to 24"
|
|
bitfld.long 0x18 24. "DIN27_24_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 16. "DIN27_24_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
|
|
bitfld.long 0x18 8. "DIN27_24_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x18 0. "DIN27_24_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
|
|
line.long 0x1C "DIN31_28,Data input 31 to 28"
|
|
bitfld.long 0x1C 24. "DIN31_28_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 16. "DIN31_28_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
|
|
bitfld.long 0x1C 8. "DIN31_28_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x1C 0. "DIN31_28_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
|
|
rgroup.long 0x1380++0x3
|
|
line.long 0x0 "DIN31_0,Data input 31 to 0"
|
|
bitfld.long 0x0 31. "DIN31_0_DIO31,This bit reads the data input value of DIO31." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 30. "DIN31_0_DIO30,This bit reads the data input value of DIO30." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 29. "DIN31_0_DIO29,This bit reads the data input value of DIO29." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 28. "DIN31_0_DIO28,This bit reads the data input value of DIO28." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 27. "DIN31_0_DIO27,This bit reads the data input value of DIO27." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 26. "DIN31_0_DIO26,This bit reads the data input value of DIO26." "0: ZERO,1: ONE"
|
|
newline
|
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bitfld.long 0x0 25. "DIN31_0_DIO25,This bit reads the data input value of DIO25." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 24. "DIN31_0_DIO24,This bit reads the data input value of DIO24." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 23. "DIN31_0_DIO23,This bit reads the data input value of DIO23." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 22. "DIN31_0_DIO22,This bit reads the data input value of DIO22." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 21. "DIN31_0_DIO21,This bit reads the data input value of DIO21." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 20. "DIN31_0_DIO20,This bit reads the data input value of DIO20." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 19. "DIN31_0_DIO19,This bit reads the data input value of DIO19." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 18. "DIN31_0_DIO18,This bit reads the data input value of DIO18." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 17. "DIN31_0_DIO17,This bit reads the data input value of DIO17." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 16. "DIN31_0_DIO16,This bit reads the data input value of DIO16." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 15. "DIN31_0_DIO15,This bit reads the data input value of DIO15." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 14. "DIN31_0_DIO14,This bit reads the data input value of DIO14." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 13. "DIN31_0_DIO13,This bit reads the data input value of DIO13." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 12. "DIN31_0_DIO12,This bit reads the data input value of DIO12." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 11. "DIN31_0_DIO11,This bit reads the data input value of DIO11." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 10. "DIN31_0_DIO10,This bit reads the data input value of DIO10." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 9. "DIN31_0_DIO9,This bit reads the data input value of DIO9." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "DIN31_0_DIO8,This bit reads the data input value of DIO8." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 7. "DIN31_0_DIO7,This bit reads the data input value of DIO7." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 6. "DIN31_0_DIO6,This bit reads the data input value of DIO6." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 5. "DIN31_0_DIO5,This bit reads the data input value of DIO5." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 4. "DIN31_0_DIO4,This bit reads the data input value of DIO4." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 3. "DIN31_0_DIO3,This bit reads the data input value of DIO3." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 2. "DIN31_0_DIO2,This bit reads the data input value of DIO2." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 1. "DIN31_0_DIO1,This bit reads the data input value of DIO1." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 0. "DIN31_0_DIO0,This bit reads the data input value of DIO0." "0: ZERO,1: ONE"
|
|
group.long 0x1390++0x3
|
|
line.long 0x0 "POLARITY15_0,Polarity 15 to 0"
|
|
bitfld.long 0x0 30.--31. "POLARITY15_0_DIO15,Enables and configures edge detection polarity for DIO15." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 28.--29. "POLARITY15_0_DIO14,Enables and configures edge detection polarity for DIO14." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 26.--27. "POLARITY15_0_DIO13,Enables and configures edge detection polarity for DIO13." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "POLARITY15_0_DIO12,Enables and configures edge detection polarity for DIO12." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 22.--23. "POLARITY15_0_DIO11,Enables and configures edge detection polarity for DIO11." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 20.--21. "POLARITY15_0_DIO10,Enables and configures edge detection polarity for DIO10." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "POLARITY15_0_DIO9,Enables and configures edge detection polarity for DIO9." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 16.--17. "POLARITY15_0_DIO8,Enables and configures edge detection polarity for DIO8." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 14.--15. "POLARITY15_0_DIO7,Enables and configures edge detection polarity for DIO7." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "POLARITY15_0_DIO6,Enables and configures edge detection polarity for DIO6." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 10.--11. "POLARITY15_0_DIO5,Enables and configures edge detection polarity for DIO5." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 8.--9. "POLARITY15_0_DIO4,Enables and configures edge detection polarity for DIO4." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "POLARITY15_0_DIO3,Enables and configures edge detection polarity for DIO3." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 4.--5. "POLARITY15_0_DIO2,Enables and configures edge detection polarity for DIO2." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 2.--3. "POLARITY15_0_DIO1,Enables and configures edge detection polarity for DIO1." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
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bitfld.long 0x0 0.--1. "POLARITY15_0_DIO0,Enables and configures edge detection polarity for DIO0." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
group.long 0x13A0++0x3
|
|
line.long 0x0 "POLARITY31_16,Polarity 31 to 16"
|
|
bitfld.long 0x0 30.--31. "POLARITY31_16_DIO31,Enables and configures edge detection polarity for DIO31." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 28.--29. "POLARITY31_16_DIO30,Enables and configures edge detection polarity for DIO30." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 26.--27. "POLARITY31_16_DIO29,Enables and configures edge detection polarity for DIO29." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "POLARITY31_16_DIO28,Enables and configures edge detection polarity for DIO28." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 22.--23. "POLARITY31_16_DIO27,Enables and configures edge detection polarity for DIO27." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 20.--21. "POLARITY31_16_DIO26,Enables and configures edge detection polarity for DIO26." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "POLARITY31_16_DIO25,Enables and configures edge detection polarity for DIO25." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 16.--17. "POLARITY31_16_DIO24,Enables and configures edge detection polarity for DIO24." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 14.--15. "POLARITY31_16_DIO23,Enables and configures edge detection polarity for DIO23." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "POLARITY31_16_DIO22,Enables and configures edge detection polarity for DIO22." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 10.--11. "POLARITY31_16_DIO21,Enables and configures edge detection polarity for DIO21." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 8.--9. "POLARITY31_16_DIO20,Enables and configures edge detection polarity for DIO20." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "POLARITY31_16_DIO19,Enables and configures edge detection polarity for DIO19." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 4.--5. "POLARITY31_16_DIO18,Enables and configures edge detection polarity for DIO18." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
bitfld.long 0x0 2.--3. "POLARITY31_16_DIO17,Enables and configures edge detection polarity for DIO17." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "POLARITY31_16_DIO16,Enables and configures edge detection polarity for DIO16." "0: DISABLE,1: RISE,2: FALL,3: RISE_FALL"
|
|
group.long 0x1400++0x7
|
|
line.long 0x0 "CTL,FAST WAKE GLOBAL EN"
|
|
bitfld.long 0x0 0. "CTL_FASTWAKEONLY,FASTWAKEONLY for the global control of fastwake" "0: NOT_GLOBAL_EN,1: GLOBAL_EN"
|
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line.long 0x4 "FASTWAKE,FAST WAKE ENABLE"
|
|
bitfld.long 0x4 31. "FASTWAKE_DIN31,Enable fastwake feature for DIN31" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 30. "FASTWAKE_DIN30,Enable fastwake feature for DIN30" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 29. "FASTWAKE_DIN29,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 28. "FASTWAKE_DIN28,Enable fastwake feature for DIN29" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 27. "FASTWAKE_DIN27,Enable fastwake feature for DIN27" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 26. "FASTWAKE_DIN26,Enable fastwake feature for DIN26" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 25. "FASTWAKE_DIN25,Enable fastwake feature for DIN25" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 24. "FASTWAKE_DIN24,Enable fastwake feature for DIN24" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 23. "FASTWAKE_DIN23,Enable fastwake feature for DIN23" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 22. "FASTWAKE_DIN22,Enable fastwake feature for DIN22" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 21. "FASTWAKE_DIN21,Enable fastwake feature for DIN21" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 20. "FASTWAKE_DIN20,Enable fastwake feature for DIN20" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 19. "FASTWAKE_DIN19,Enable fastwake feature for DIN19" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 18. "FASTWAKE_DIN18,Enable fastwake feature for DIN18" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 17. "FASTWAKE_DIN17,Enable fastwake feature for DIN17" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 16. "FASTWAKE_DIN16,Enable fastwake feature for DIN16" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 15. "FASTWAKE_DIN15,Enable fastwake feature for DIN15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 14. "FASTWAKE_DIN14,Enable fastwake feature for DIN14" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 13. "FASTWAKE_DIN13,Enable fastwake feature for DIN13" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 12. "FASTWAKE_DIN12,Enable fastwake feature for DIN12" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 11. "FASTWAKE_DIN11,Enable fastwake feature for DIN11" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 10. "FASTWAKE_DIN10,Enable fastwake feature for DIN10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 9. "FASTWAKE_DIN9,Enable fastwake feature for DIN9" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "FASTWAKE_DIN8,Enable fastwake feature for DIN8" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 7. "FASTWAKE_DIN7,Enable fastwake feature for DIN7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "FASTWAKE_DIN6,Enable fastwake feature for DIN6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "FASTWAKE_DIN5,Enable fastwake feature for DIN5" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4. "FASTWAKE_DIN4,Enable fastwake feature for DIN4" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 3. "FASTWAKE_DIN3,Enable fastwake feature for DIN3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "FASTWAKE_DIN2,Enable fastwake feature for DIN2" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 1. "FASTWAKE_DIN1,Enable fastwake feature for DIN1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "FASTWAKE_DIN0,Enable fastwake feature for DIN0" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "SUB0CFG,Subscriber 0 configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SUB0CFG_INDEX,Indicates the specific bit among lower 16 bits that is targeted by the subscriber action"
|
|
bitfld.long 0x0 8.--9. "SUB0CFG_OUTPOLICY,These bits configure the output policy for subscriber 0 event." "0: SET,1: CLR,2: TOGGLE,?"
|
|
bitfld.long 0x0 0. "SUB0CFG_ENABLE,This bit is used to enable subscriber 0 event." "0: CLR,1: SET"
|
|
group.long 0x1508++0xB
|
|
line.long 0x0 "FILTEREN15_0,Filter Enable 15 to 0"
|
|
bitfld.long 0x0 30.--31. "FILTEREN15_0_DIN15,Programmable counter length of digital glitch filter for DIN15" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 28.--29. "FILTEREN15_0_DIN14,Programmable counter length of digital glitch filter for DIN14" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 26.--27. "FILTEREN15_0_DIN13,Programmable counter length of digital glitch filter for DIN13" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
newline
|
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bitfld.long 0x0 24.--25. "FILTEREN15_0_DIN12,Programmable counter length of digital glitch filter for DIN12" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
|
|
bitfld.long 0x0 22.--23. "FILTEREN15_0_DIN11,Programmable counter length of digital glitch filter for DIN11" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
bitfld.long 0x0 20.--21. "FILTEREN15_0_DIN10,Programmable counter length of digital glitch filter for DIN10" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
|
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bitfld.long 0x0 18.--19. "FILTEREN15_0_DIN9,Programmable counter length of digital glitch filter for DIN9" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
bitfld.long 0x0 16.--17. "FILTEREN15_0_DIN8,Programmable counter length of digital glitch filter for DIN8" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x0 14.--15. "FILTEREN15_0_DIN7,Programmable counter length of digital glitch filter for DIN7" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
|
|
bitfld.long 0x0 12.--13. "FILTEREN15_0_DIN6,Programmable counter length of digital glitch filter for DIN6" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
bitfld.long 0x0 10.--11. "FILTEREN15_0_DIN5,Programmable counter length of digital glitch filter for DIN5" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
bitfld.long 0x0 8.--9. "FILTEREN15_0_DIN4,Programmable counter length of digital glitch filter for DIN4" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
|
|
bitfld.long 0x0 6.--7. "FILTEREN15_0_DIN3,Programmable counter length of digital glitch filter for DIN3" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x0 4.--5. "FILTEREN15_0_DIN2,Programmable counter length of digital glitch filter for DIN2" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x0 2.--3. "FILTEREN15_0_DIN1,Programmable counter length of digital glitch filter for DIN1" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
newline
|
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bitfld.long 0x0 0.--1. "FILTEREN15_0_DIN0,Programmable counter length of digital glitch filter for DIN0" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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|
line.long 0x4 "FILTEREN31_16,Filter Enable 31 to 16"
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bitfld.long 0x4 30.--31. "FILTEREN31_16_DIN31,Programmable counter length of digital glitch filter for DIN31" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x4 28.--29. "FILTEREN31_16_DIN30,Programmable counter length of digital glitch filter for DIN30" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x4 26.--27. "FILTEREN31_16_DIN29,Programmable counter length of digital glitch filter for DIN29" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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newline
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bitfld.long 0x4 24.--25. "FILTEREN31_16_DIN28,Programmable counter length of digital glitch filter for DIN28" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x4 22.--23. "FILTEREN31_16_DIN27,Programmable counter length of digital glitch filter for DIN27" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x4 20.--21. "FILTEREN31_16_DIN26,Programmable counter length of digital glitch filter for DIN26" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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newline
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bitfld.long 0x4 18.--19. "FILTEREN31_16_DIN25,Programmable counter length of digital glitch filter for DIN25" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x4 16.--17. "FILTEREN31_16_DIN24,Programmable counter length of digital glitch filter for DIN24" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x4 14.--15. "FILTEREN31_16_DIN23,Programmable counter length of digital glitch filter for DIN23" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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newline
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bitfld.long 0x4 12.--13. "FILTEREN31_16_DIN22,Programmable counter length of digital glitch filter for DIN22" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x4 10.--11. "FILTEREN31_16_DIN21,Programmable counter length of digital glitch filter for DIN21" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x4 8.--9. "FILTEREN31_16_DIN20,Programmable counter length of digital glitch filter for DIN20" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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newline
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bitfld.long 0x4 6.--7. "FILTEREN31_16_DIN19,Programmable counter length of digital glitch filter for DIN19" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x4 4.--5. "FILTEREN31_16_DIN18,Programmable counter length of digital glitch filter for DIN18" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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bitfld.long 0x4 2.--3. "FILTEREN31_16_DIN17,Programmable counter length of digital glitch filter for DIN17" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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newline
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bitfld.long 0x4 0.--1. "FILTEREN31_16_DIN16,Programmable counter length of digital glitch filter for DIN16" "0: DISABLE,1: ONE_CYCLE,2: THREE_CYCLE,3: EIGHT_CYCLE"
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line.long 0x8 "DMAMASK,DMA Write MASK"
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|
bitfld.long 0x8 31. "DMAMASK_DOUT31,DMA is allowed to modify DOUT31" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 30. "DMAMASK_DOUT30,DMA is allowed to modify DOUT30" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 29. "DMAMASK_DOUT29,DMA is allowed to modify DOUT29" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x8 28. "DMAMASK_DOUT28,DMA is allowed to modify DOUT28" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 27. "DMAMASK_DOUT27,DMA is allowed to modify DOUT27" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 26. "DMAMASK_DOUT26,DMA is allowed to modify DOUT26" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x8 25. "DMAMASK_DOUT25,DMA is allowed to modify DOUT25" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 24. "DMAMASK_DOUT24,DMA is allowed to modify DOUT24" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 23. "DMAMASK_DOUT23,DMA is allowed to modify DOUT23" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x8 22. "DMAMASK_DOUT22,DMA is allowed to modify DOUT22" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 21. "DMAMASK_DOUT21,DMA is allowed to modify DOUT21" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 20. "DMAMASK_DOUT20,DMA is allowed to modify DOUT20" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x8 19. "DMAMASK_DOUT19,DMA is allowed to modify DOUT19" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 18. "DMAMASK_DOUT18,DMA is allowed to modify DOUT18" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 17. "DMAMASK_DOUT17,DMA is allowed to modify DOUT17" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x8 16. "DMAMASK_DOUT16,DMA is allowed to modify DOUT16" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 15. "DMAMASK_DOUT15,DMA is allowed to modify DOUT15" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 14. "DMAMASK_DOUT14,DMA is allowed to modify DOUT14" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x8 13. "DMAMASK_DOUT13,DMA is allowed to modify DOUT13" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 12. "DMAMASK_DOUT12,DMA is allowed to modify DOUT12" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 11. "DMAMASK_DOUT11,DMA is allowed to modify DOUT11" "0: DISABLE,1: ENABLE"
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newline
|
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bitfld.long 0x8 10. "DMAMASK_DOUT10,DMA is allowed to modify DOUT10" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 9. "DMAMASK_DOUT9,DMA is allowed to modify DOUT9" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 8. "DMAMASK_DOUT8,DMA is allowed to modify DOUT8" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x8 7. "DMAMASK_DOUT7,DMA is allowed to modify DOUT7" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 6. "DMAMASK_DOUT6,DMA is allowed to modify DOUT6" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 5. "DMAMASK_DOUT5,DMA is allowed to modify DOUT5" "0: DISABLE,1: ENABLE"
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|
newline
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bitfld.long 0x8 4. "DMAMASK_DOUT4,DMA is allowed to modify DOUT4" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 3. "DMAMASK_DOUT3,DMA is allowed to modify DOUT3" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 2. "DMAMASK_DOUT2,DMA is allowed to modify DOUT2" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x8 1. "DMAMASK_DOUT1,DMA is allowed to modify DOUT1" "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 0. "DMAMASK_DOUT0,DMA is allowed to modify DOUT0" "0: DISABLE,1: ENABLE"
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group.long 0x1520++0x3
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line.long 0x0 "SUB1CFG,Subscriber 1 configuration"
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hexmask.long.byte 0x0 16.--19. 1. "SUB1CFG_INDEX,indicates the specific bit in the upper 16 bits that is targeted by the subscriber action"
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bitfld.long 0x0 8.--9. "SUB1CFG_OUTPOLICY,These bits configure the output policy for subscriber 1 event." "0: SET,1: CLR,2: TOGGLE,?"
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bitfld.long 0x0 0. "SUB1CFG_ENABLE,This bit is used to enable subscriber 1 event." "0: CLR,1: SET"
|
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tree.end
|
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endif
|
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tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
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base ad:0x0
|
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sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
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tree "I2C0"
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base ad:0x400F0000
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group.long 0x800++0x3
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line.long 0x0 "PWREN,Power enable"
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hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
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newline
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bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
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wgroup.long 0x804++0x3
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line.long 0x0 "RSTCTL,Reset Control"
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hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
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newline
|
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bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
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newline
|
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bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
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group.long 0x808++0x3
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line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
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hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
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newline
|
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bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
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rgroup.long 0x814++0x3
|
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line.long 0x0 "STAT,Status Register"
|
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bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
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group.long 0x1000++0x7
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line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
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line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
newline
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT0_IMASK_INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_IMASK_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_IMASK_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_IMASK_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_IMASK_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_IMASK_SDMA_DONE_RX,Slave DMA Done on Event Channel RX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_IMASK_SDMA_DONE_TX,Slave DMA Done on Event Channel TX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_IMASK_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_IMASK_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_IMASK_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_IMASK_STXEMPTY,Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_IMASK_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an Slave RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_MSTART,START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_RIS_INTR_OVFL,Interrupt overflow interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_RIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_RIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_RIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_RIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_RIS_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_RIS_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_RIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_RIS_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_RIS_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_RIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_RIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 17. "INT_EVENT0_RIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_RIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_RIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_RIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_RIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_RIS_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_RIS_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_RIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_RIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_RIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_RIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_RIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_RIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_RIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_RIS_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
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rgroup.long 0x1038++0x3
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line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
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bitfld.long 0x0 31. "INT_EVENT0_MIS_INTR_OVFL,Interrupt overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_MIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_MIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 28. "INT_EVENT0_MIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_MIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_MIS_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_MIS_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_MIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_MIS_SSTOP,Slave STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_MIS_SSTART,Slave START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_MIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_MIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_MIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_MIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_MIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_MIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_MIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_MIS_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_MIS_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_MIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_MIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_MIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_MIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_MIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_MIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_MIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_MIS_MRXDONE,Master Receive Data Interrupt" "0: CLR,1: SET"
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wgroup.long 0x1040++0x3
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line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
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bitfld.long 0x0 31. "INT_EVENT0_ISET_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_ISET_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_ISET_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 28. "INT_EVENT0_ISET_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_ISET_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_ISET_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_ISET_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_ISET_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_ISET_SSTOP,Stop Condition Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_ISET_SSTART,Start Condition Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_ISET_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_ISET_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_ISET_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_ISET_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_ISET_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_ISET_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 13. "INT_EVENT0_ISET_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 12. "INT_EVENT0_ISET_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_ISET_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 10. "INT_EVENT0_ISET_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_ISET_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_ISET_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_ISET_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_ISET_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_ISET_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT0_ISET_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_ISET_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: SET"
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wgroup.long 0x1048++0x3
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line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
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bitfld.long 0x0 31. "INT_EVENT0_ICLR_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_ICLR_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 29. "INT_EVENT0_ICLR_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 28. "INT_EVENT0_ICLR_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_ICLR_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_ICLR_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_ICLR_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_ICLR_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_ICLR_SSTOP,Slave STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_ICLR_SSTART,Slave START Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_ICLR_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_ICLR_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_ICLR_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_ICLR_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_ICLR_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_ICLR_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_ICLR_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_ICLR_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_ICLR_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_ICLR_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_ICLR_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_ICLR_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 5. "INT_EVENT0_ICLR_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_ICLR_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 3. "INT_EVENT0_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_ICLR_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_ICLR_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1050++0x3
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line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
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group.long 0x1058++0x3
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line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
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bitfld.long 0x0 3. "INT_EVENT1_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT1_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 0. "INT_EVENT1_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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rgroup.long 0x1060++0x3
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line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
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bitfld.long 0x0 3. "INT_EVENT1_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT1_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 0. "INT_EVENT1_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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rgroup.long 0x1068++0x3
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line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
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bitfld.long 0x0 3. "INT_EVENT1_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 2. "INT_EVENT1_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT1_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT1_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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wgroup.long 0x1070++0x3
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line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
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bitfld.long 0x0 3. "INT_EVENT1_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT1_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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|
newline
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bitfld.long 0x0 0. "INT_EVENT1_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
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|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT2_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT2_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
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rgroup.long 0x1090++0x3
|
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line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT2_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT2_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT2_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
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bitfld.long 0x0 0. "INT_EVENT2_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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|
rgroup.long 0x10E0++0x3
|
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line.long 0x0 "EVT_MODE,Event Mode"
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bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
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newline
|
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bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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wgroup.long 0x10E4++0x3
|
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line.long 0x0 "INTCTL,Interrupt control register"
|
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bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
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rgroup.long 0x10FC++0x3
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line.long 0x0 "DESC,Module Description"
|
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hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
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newline
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hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
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newline
|
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hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
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group.long 0x1200++0x7
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line.long 0x0 "GFCTL,I2C Glitch Filter Control"
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bitfld.long 0x0 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
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bitfld.long 0x0 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x0 0.--2. "GFCTL_DGFSEL,Glitch Suppression Pulse Width" "0: DISABLED,1: CLK_1,2: CLK_2,3: CLK_3,4: CLK_4,5: CLK_8,6: CLK_16,7: CLK_31"
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line.long 0x4 "TIMEOUT_CTL,I2C Timeout Count Control Register"
|
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bitfld.long 0x4 31. "TIMEOUT_CTL_TCNTBEN,Timeout Counter B Enable" "0: DISABLE,1: ENABLE"
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newline
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hexmask.long.byte 0x4 16.--23. 1. "TIMEOUT_CTL_TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h."
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newline
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bitfld.long 0x4 15. "TIMEOUT_CTL_TCNTAEN,Timeout Counter A Enable" "0: DISABLE,1: ENABLE"
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|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TIMEOUT_CTL_TCNTLA,Timeout counter A load value"
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rgroup.long 0x1208++0x3
|
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line.long 0x0 "TIMEOUT_CNT,I2C Timeout Count Register"
|
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hexmask.long.byte 0x0 16.--23. 1. "TIMEOUT_CNT_TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"
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|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TIMEOUT_CNT_TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"
|
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group.long 0x1210++0x7
|
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line.long 0x0 "MSA,I2C Master Slave Address Register"
|
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bitfld.long 0x0 15. "MSA_MMODE,This bit selects the adressing mode to be used in master mode" "0: MODE7,1: MODE10"
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newline
|
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hexmask.long.word 0x0 1.--10. 1. "MSA_SADDR,I2C Slave Address This field specifies bits A9 through A0 of the slave address."
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newline
|
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bitfld.long 0x0 0. "MSA_DIR,Receive/Send" "0: TRANSMIT,1: RECEIVE"
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line.long 0x4 "MCTR,I2C Master Control Register"
|
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hexmask.long.word 0x4 16.--27. 1. "MCTR_MBLEN,I2C transaction length"
|
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newline
|
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bitfld.long 0x4 5. "MCTR_RD_ON_TXEMPTY,Read on TX Empty" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 4. "MCTR_MACKOEN,Master ACK overrride Enable" "0: DISABLE,1: ENABLE"
|
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newline
|
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bitfld.long 0x4 3. "MCTR_ACK,Data Acknowledge Enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 2. "MCTR_STOP,Generate STOP" "0: DISABLE,1: ENABLE"
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newline
|
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bitfld.long 0x4 1. "MCTR_START,Generate START" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 0. "MCTR_BURSTRUN,I2C Master Enable" "0: DISABLE,1: ENABLE"
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rgroup.long 0x1218++0x7
|
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line.long 0x0 "MSR,I2C Master Status Register"
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|
hexmask.long.word 0x0 16.--27. 1. "MSR_MBCNT,I2C Master Transaction Count"
|
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newline
|
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bitfld.long 0x0 6. "MSR_BUSBSY,I2C Bus is Busy" "0: CLEARED,1: SET"
|
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newline
|
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bitfld.long 0x0 5. "MSR_IDLE,I2C Idle" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 4. "MSR_ARBLST,Arbitration Lost" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 3. "MSR_DATACK,Acknowledge Data" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "MSR_ADRACK,Acknowledge Address" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "MSR_ERR,Error" "0: CLEARED,1: SET"
|
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newline
|
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bitfld.long 0x0 0. "MSR_BUSY,I2C Master FSM Busy" "0: CLEARED,1: SET"
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line.long 0x4 "MRXDATA,I2C Master RXData"
|
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hexmask.long.byte 0x4 0.--7. 1. "MRXDATA_VALUE,Received Data."
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group.long 0x1220++0xB
|
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line.long 0x0 "MTXDATA,I2C Master TXData"
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hexmask.long.byte 0x0 0.--7. 1. "MTXDATA_VALUE,Transmit Data"
|
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line.long 0x4 "MTPR,I2C Master Timer Period"
|
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hexmask.long.byte 0x4 0.--6. 1. "MTPR_TPR,Timer Period"
|
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line.long 0x8 "MCR,I2C Master Configuration"
|
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bitfld.long 0x8 8. "MCR_LPBK,I2C Loopback" "0: DISABLE,1: ENABLE"
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newline
|
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bitfld.long 0x8 2. "MCR_CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: DISABLE,1: ENABLE"
|
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newline
|
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bitfld.long 0x8 1. "MCR_MMST,Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: DISABLE,1: ENABLE"
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newline
|
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bitfld.long 0x8 0. "MCR_ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: DISABLE,1: ENABLE"
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rgroup.long 0x1234++0x3
|
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line.long 0x0 "MBMON,I2C Master Bus Monitor"
|
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bitfld.long 0x0 1. "MBMON_SDA,I2C SDA Status" "0: CLEARED,1: SET"
|
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newline
|
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bitfld.long 0x0 0. "MBMON_SCL,I2C SCL Status" "0: CLEARED,1: SET"
|
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group.long 0x1238++0x3
|
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line.long 0x0 "MFIFOCTL,I2C Master FIFO Control"
|
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bitfld.long 0x0 15. "MFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
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newline
|
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bitfld.long 0x0 8.--10. "MFIFOCTL_RXTRIG,RX FIFO Trigger" "0: LEVEL_1,1: LEVEL_2,2: LEVEL_3,3: LEVEL_4,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
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newline
|
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bitfld.long 0x0 7. "MFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
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newline
|
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bitfld.long 0x0 0.--2. "MFIFOCTL_TXTRIG,TX FIFO Trigger" "0: EMPTY,1: LEVEL_1,2: LEVEL_2,3: LEVEL_3,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
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rgroup.long 0x123C++0x3
|
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line.long 0x0 "MFIFOSR,I2C Master FIFO Status Register"
|
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bitfld.long 0x0 15. "MFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
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newline
|
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hexmask.long.byte 0x0 8.--11. 1. "MFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
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newline
|
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bitfld.long 0x0 7. "MFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "MFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
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group.long 0x1240++0x3
|
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line.long 0x0 "MASTER_I2CPECCTL,I2C master PEC control register"
|
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bitfld.long 0x0 12. "MASTER_I2CPECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "MASTER_I2CPECCTL_PECCNT,PEC Count"
|
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rgroup.long 0x1244++0x3
|
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line.long 0x0 "MASTER_PECSR,I2C master PEC status register"
|
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bitfld.long 0x0 17. "MASTER_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 16. "MASTER_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "MASTER_PECSR_PECBYTECNT,PEC Byte Count"
|
|
group.long 0x1250++0xB
|
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line.long 0x0 "SOAR,I2C Slave Own Address"
|
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bitfld.long 0x0 15. "SOAR_SMODE,This bit selects the adressing mode to be used in slave mode." "0: MODE7,1: MODE10"
|
|
newline
|
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bitfld.long 0x0 14. "SOAR_OAREN,I2C Slave Own Address Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.word 0x0 0.--9. 1. "SOAR_OAR,I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address."
|
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line.long 0x4 "SOAR2,I2C Slave Own Address 2"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SOAR2_OAR2_MASK,I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address."
|
|
newline
|
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bitfld.long 0x4 7. "SOAR2_OAR2EN,I2C Slave Own Address 2 Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.byte 0x4 0.--6. 1. "SOAR2_OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "SCTR,I2C Slave Control Register"
|
|
bitfld.long 0x8 10. "SCTR_SWUEN,Slave Wakeup Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 9. "SCTR_EN_DEFDEVADR,Enable Deault device address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 8. "SCTR_EN_ALRESPADR,Enable Alert Response Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 7. "SCTR_EN_DEFHOSTADR,Enable Default Host Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 6. "SCTR_RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 5. "SCTR_TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "SCTR_TXTRIG_TXMODE,Tx Trigger when slave FSM is in Tx Mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 3. "SCTR_TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 2. "SCTR_SCLKSTRETCH,Slave Clock Stretch Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "SCTR_GENCALL,General call response enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 0. "SCTR_ACTIVE,Device Active. Setting this bit enables the slave functionality." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x125C++0x7
|
|
line.long 0x0 "SSR,I2C Slave Status Register"
|
|
hexmask.long.word 0x0 9.--18. 1. "SSR_ADDRMATCH,Indicates the address for which slave address match happened"
|
|
newline
|
|
bitfld.long 0x0 8. "SSR_STALE_TXFIFO,Stale Tx FIFO" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "SSR_TXMODE,Slave FSM is in TX MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "SSR_BUSBSY,I2C bus is busy" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 5. "SSR_QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read"
|
|
newline
|
|
rbitfld.long 0x0 4. "SSR_QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.."
|
|
newline
|
|
rbitfld.long 0x0 3. "SSR_OAR2SEL,OAR2 Address Matched" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "SSR_RXMODE,Slave FSM is in Rx MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 1. "SSR_TREQ,Transmit Request" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 0. "SSR_RREQ,Receive Request" "0: CLEARED,1: SET"
|
|
line.long 0x4 "SRXDATA,I2C Slave RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SRXDATA_VALUE,Received Data."
|
|
group.long 0x1264++0xB
|
|
line.long 0x0 "STXDATA,I2C Slave TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STXDATA_VALUE,Transmit Data"
|
|
line.long 0x4 "SACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x4 4. "SACKCTL_ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte." "0: DISABLE,1: ENABLE"
|
|
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|
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bitfld.long 0x4 3. "SACKCTL_ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "SACKCTL_ACKOEN_ON_START,When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "SACKCTL_ACKOVAL,I2C Slave ACK Override Value" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "SACKCTL_ACKOEN,I2C Slave ACK Override Enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "SFIFOCTL,I2C Slave FIFO Control"
|
|
bitfld.long 0x8 15. "SFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "SFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
|
bitfld.long 0x8 7. "SFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
|
rgroup.long 0x1270++0x3
|
|
line.long 0x0 "SFIFOSR,I2C Slave FIFO Status Register"
|
|
bitfld.long 0x0 15. "SFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
|
bitfld.long 0x0 7. "SFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1274++0x3
|
|
line.long 0x0 "SLAVE_PECCTL,I2C Slave PEC control register"
|
|
bitfld.long 0x0 12. "SLAVE_PECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECCTL_PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from.."
|
|
rgroup.long 0x1278++0x3
|
|
line.long 0x0 "SLAVE_PECSR,I2C slave PEC status register"
|
|
bitfld.long 0x0 17. "SLAVE_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "SLAVE_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECSR_PECBYTECNT,This is the current PEC Byte Count of the Slave State Machine."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "I2C0"
|
|
base ad:0x400F0000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
newline
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
newline
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
newline
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
newline
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT0_IMASK_INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_IMASK_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_IMASK_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_IMASK_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_IMASK_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_IMASK_SDMA_DONE1_3,Slave DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_IMASK_SDMA_DONE1_2,Slave DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_IMASK_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_IMASK_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_IMASK_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_IMASK_STXEMPTY,Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_IMASK_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an Slave RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_MSTART,START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_RIS_INTR_OVFL,Interrupt overflow interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_RIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_RIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_RIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_RIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_RIS_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_RIS_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_RIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_RIS_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_RIS_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_RIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_RIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_MIS_INTR_OVFL,Interrupt overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_MIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_MIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_MIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_MIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_MIS_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_MIS_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_MIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_MIS_SSTOP,Slave STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_MIS_SSTART,Slave START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_MIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_MIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT0_MIS_MRXDONE,Master Receive Data Interrupt" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
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line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
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bitfld.long 0x0 31. "INT_EVENT0_ISET_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 30. "INT_EVENT0_ISET_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 29. "INT_EVENT0_ISET_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 28. "INT_EVENT0_ISET_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 27. "INT_EVENT0_ISET_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 26. "INT_EVENT0_ISET_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 25. "INT_EVENT0_ISET_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 24. "INT_EVENT0_ISET_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 23. "INT_EVENT0_ISET_SSTOP,Stop Condition Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 22. "INT_EVENT0_ISET_SSTART,Start Condition Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 21. "INT_EVENT0_ISET_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 20. "INT_EVENT0_ISET_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 19. "INT_EVENT0_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 18. "INT_EVENT0_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 17. "INT_EVENT0_ISET_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_ISET_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 14. "INT_EVENT0_ISET_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 12. "INT_EVENT0_ISET_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 11. "INT_EVENT0_ISET_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 10. "INT_EVENT0_ISET_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 9. "INT_EVENT0_ISET_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 8. "INT_EVENT0_ISET_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 7. "INT_EVENT0_ISET_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 5. "INT_EVENT0_ISET_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 4. "INT_EVENT0_ISET_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 3. "INT_EVENT0_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 1. "INT_EVENT0_ISET_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT0_ISET_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
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line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "INT_EVENT0_ICLR_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 30. "INT_EVENT0_ICLR_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 29. "INT_EVENT0_ICLR_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 28. "INT_EVENT0_ICLR_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 27. "INT_EVENT0_ICLR_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 26. "INT_EVENT0_ICLR_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 25. "INT_EVENT0_ICLR_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 24. "INT_EVENT0_ICLR_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 23. "INT_EVENT0_ICLR_SSTOP,Slave STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 22. "INT_EVENT0_ICLR_SSTART,Slave START Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 21. "INT_EVENT0_ICLR_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 20. "INT_EVENT0_ICLR_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 19. "INT_EVENT0_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 18. "INT_EVENT0_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 17. "INT_EVENT0_ICLR_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 16. "INT_EVENT0_ICLR_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 14. "INT_EVENT0_ICLR_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 12. "INT_EVENT0_ICLR_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 11. "INT_EVENT0_ICLR_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 10. "INT_EVENT0_ICLR_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 9. "INT_EVENT0_ICLR_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 8. "INT_EVENT0_ICLR_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 7. "INT_EVENT0_ICLR_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 4. "INT_EVENT0_ICLR_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 3. "INT_EVENT0_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT0_ICLR_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT0_ICLR_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
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line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT1_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT2_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT2_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1200++0x7
|
|
line.long 0x0 "GFCTL,I2C Glitch Filter Control"
|
|
bitfld.long 0x0 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
newline
|
|
bitfld.long 0x0 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "GFCTL_DGFSEL,Glitch Suppression Pulse Width" "0: DISABLED,1: CLK_1,2: CLK_2,3: CLK_3,4: CLK_4,5: CLK_8,6: CLK_16,7: CLK_31"
|
|
line.long 0x4 "TIMEOUT_CTL,I2C Timeout Count Control Register"
|
|
bitfld.long 0x4 31. "TIMEOUT_CTL_TCNTBEN,Timeout Counter B Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "TIMEOUT_CTL_TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h."
|
|
newline
|
|
bitfld.long 0x4 15. "TIMEOUT_CTL_TCNTAEN,Timeout Counter A Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TIMEOUT_CTL_TCNTLA,Timeout counter A load value"
|
|
rgroup.long 0x1208++0x3
|
|
line.long 0x0 "TIMEOUT_CNT,I2C Timeout Count Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TIMEOUT_CNT_TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TIMEOUT_CNT_TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"
|
|
group.long 0x1210++0x7
|
|
line.long 0x0 "MSA,I2C Master Slave Address Register"
|
|
bitfld.long 0x0 15. "MSA_MMODE,This bit selects the adressing mode to be used in master mode" "0: MODE7,1: MODE10"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "MSA_SADDR,I2C Slave Address This field specifies bits A9 through A0 of the slave address."
|
|
newline
|
|
bitfld.long 0x0 0. "MSA_DIR,Receive/Send" "0: TRANSMIT,1: RECEIVE"
|
|
line.long 0x4 "MCTR,I2C Master Control Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "MCTR_MBLEN,I2C transaction length"
|
|
newline
|
|
bitfld.long 0x4 5. "MCTR_RD_ON_TXEMPTY,Read on TX Empty" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4. "MCTR_MACKOEN,Master ACK overrride Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "MCTR_ACK,Data Acknowledge Enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "MCTR_STOP,Generate STOP" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "MCTR_START,Generate START" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "MCTR_BURSTRUN,I2C Master Enable" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1218++0x7
|
|
line.long 0x0 "MSR,I2C Master Status Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "MSR_MBCNT,I2C Master Transaction Count"
|
|
newline
|
|
bitfld.long 0x0 6. "MSR_BUSBSY,I2C Bus is Busy" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "MSR_IDLE,I2C Idle" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MSR_ARBLST,Arbitration Lost" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "MSR_DATACK,Acknowledge Data" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "MSR_ADRACK,Acknowledge Address" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MSR_ERR,Error" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MSR_BUSY,I2C Master FSM Busy" "0: CLEARED,1: SET"
|
|
line.long 0x4 "MRXDATA,I2C Master RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MRXDATA_VALUE,Received Data."
|
|
group.long 0x1220++0xB
|
|
line.long 0x0 "MTXDATA,I2C Master TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MTXDATA_VALUE,Transmit Data"
|
|
line.long 0x4 "MTPR,I2C Master Timer Period"
|
|
hexmask.long.byte 0x4 0.--6. 1. "MTPR_TPR,Timer Period"
|
|
line.long 0x8 "MCR,I2C Master Configuration"
|
|
bitfld.long 0x8 8. "MCR_LPBK,I2C Loopback" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 2. "MCR_CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 1. "MCR_MMST,Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 0. "MCR_ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1234++0x3
|
|
line.long 0x0 "MBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "MBMON_SDA,I2C SDA Status" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MBMON_SCL,I2C SCL Status" "0: CLEARED,1: SET"
|
|
group.long 0x1238++0x3
|
|
line.long 0x0 "MFIFOCTL,I2C Master FIFO Control"
|
|
bitfld.long 0x0 15. "MFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
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bitfld.long 0x0 8.--10. "MFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
|
bitfld.long 0x0 7. "MFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "MFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
|
rgroup.long 0x123C++0x3
|
|
line.long 0x0 "MFIFOSR,I2C Master FIFO Status Register"
|
|
bitfld.long 0x0 15. "MFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
|
bitfld.long 0x0 7. "MFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "MFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1240++0x3
|
|
line.long 0x0 "MASTER_I2CPECCTL,I2C master PEC control register"
|
|
bitfld.long 0x0 12. "MASTER_I2CPECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "MASTER_I2CPECCTL_PECCNT,PEC Count"
|
|
rgroup.long 0x1244++0x3
|
|
line.long 0x0 "MASTER_PECSR,I2C master PEC status register"
|
|
bitfld.long 0x0 17. "MASTER_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 16. "MASTER_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "MASTER_PECSR_PECBYTECNT,PEC Byte Count"
|
|
group.long 0x1250++0xB
|
|
line.long 0x0 "SOAR,I2C Slave Own Address"
|
|
bitfld.long 0x0 15. "SOAR_SMODE,This bit selects the adressing mode to be used in slave mode." "0: MODE7,1: MODE10"
|
|
newline
|
|
bitfld.long 0x0 14. "SOAR_OAREN,I2C Slave Own Address Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "SOAR_OAR,I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address."
|
|
line.long 0x4 "SOAR2,I2C Slave Own Address 2"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SOAR2_OAR2_MASK,I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address."
|
|
newline
|
|
bitfld.long 0x4 7. "SOAR2_OAR2EN,I2C Slave Own Address 2 Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "SOAR2_OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "SCTR,I2C Slave Control Register"
|
|
bitfld.long 0x8 10. "SCTR_SWUEN,Slave Wakeup Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 9. "SCTR_EN_DEFDEVADR,Enable Deault device address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 8. "SCTR_EN_ALRESPADR,Enable Alert Response Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 7. "SCTR_EN_DEFHOSTADR,Enable Default Host Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 6. "SCTR_RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 5. "SCTR_TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "SCTR_TXTRIG_TXMODE,Tx Trigger when slave FSM is in Tx Mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 3. "SCTR_TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 2. "SCTR_SCLKSTRETCH,Slave Clock Stretch Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "SCTR_GENCALL,General call response enable. This bit is only available in UCBxI2COA0." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 0. "SCTR_ACTIVE,Device Active. Setting this bit enables the slave functionality." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x125C++0x7
|
|
line.long 0x0 "SSR,I2C Slave Status Register"
|
|
hexmask.long.word 0x0 9.--18. 1. "SSR_ADDRMATCH,Indicates the address for which slave address match happened"
|
|
newline
|
|
bitfld.long 0x0 8. "SSR_STALE_TXFIFO,Stale Tx FIFO" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "SSR_TXMODE,Slave FSM is in TX MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "SSR_BUSBSY,I2C bus is busy" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 5. "SSR_QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read"
|
|
newline
|
|
rbitfld.long 0x0 4. "SSR_QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.."
|
|
newline
|
|
rbitfld.long 0x0 3. "SSR_OAR2SEL,OAR2 Address Matched" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "SSR_RXMODE,Slave FSM is in Rx MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 1. "SSR_TREQ,Transmit Request" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 0. "SSR_RREQ,Receive Request" "0: CLEARED,1: SET"
|
|
line.long 0x4 "SRXDATA,I2C Slave RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SRXDATA_VALUE,Received Data."
|
|
group.long 0x1264++0xB
|
|
line.long 0x0 "STXDATA,I2C Slave TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STXDATA_VALUE,Transmit Data"
|
|
line.long 0x4 "SACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x4 4. "SACKCTL_ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "SACKCTL_ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "SACKCTL_ACKOEN_ON_START,When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "SACKCTL_ACKOVAL,I2C Slave ACK Override Value" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "SACKCTL_ACKOEN,I2C Slave ACK Override Enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "SFIFOCTL,I2C Slave FIFO Control"
|
|
bitfld.long 0x8 15. "SFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "SFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
|
bitfld.long 0x8 7. "SFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
|
rgroup.long 0x1270++0x3
|
|
line.long 0x0 "SFIFOSR,I2C Slave FIFO Status Register"
|
|
bitfld.long 0x0 15. "SFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
|
bitfld.long 0x0 7. "SFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1274++0x3
|
|
line.long 0x0 "SLAVE_PECCTL,I2C Slave PEC control register"
|
|
bitfld.long 0x0 12. "SLAVE_PECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECCTL_PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from.."
|
|
rgroup.long 0x1278++0x3
|
|
line.long 0x0 "SLAVE_PECSR,I2C slave PEC status register"
|
|
bitfld.long 0x0 17. "SLAVE_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "SLAVE_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECSR_PECBYTECNT,This is the current PEC Byte Count of the Slave State Machine."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "I2C1"
|
|
base ad:0x400F2000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
newline
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
newline
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
newline
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
newline
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT0_IMASK_INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_IMASK_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_IMASK_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_IMASK_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_IMASK_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_IMASK_SDMA_DONE1_3,Slave DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 25. "INT_EVENT0_IMASK_SDMA_DONE1_2,Slave DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_IMASK_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_IMASK_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_IMASK_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_IMASK_STXEMPTY,Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_IMASK_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an Slave RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_IMASK_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_IMASK_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_IMASK_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_IMASK_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_IMASK_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_IMASK_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_IMASK_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_IMASK_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_IMASK_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_IMASK_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_IMASK_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_IMASK_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_IMASK_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_IMASK_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_IMASK_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
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rgroup.long 0x1030++0x3
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line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
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bitfld.long 0x0 31. "INT_EVENT0_RIS_INTR_OVFL,Interrupt overflow interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_RIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_RIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 28. "INT_EVENT0_RIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_RIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_RIS_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_RIS_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_RIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_RIS_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_RIS_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_RIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_RIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_RIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_RIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_RIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_RIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_RIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_RIS_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_RIS_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_RIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_RIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_RIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_RIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_RIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_RIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_RIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_RIS_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
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rgroup.long 0x1038++0x3
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line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
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bitfld.long 0x0 31. "INT_EVENT0_MIS_INTR_OVFL,Interrupt overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_MIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_MIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 28. "INT_EVENT0_MIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_MIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_MIS_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_MIS_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_MIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_MIS_SSTOP,Slave STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_MIS_SSTART,Slave START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_MIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_MIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_MIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_MIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_MIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_MIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_MIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_MIS_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_MIS_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_MIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_MIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_MIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_MIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_MIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_MIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_MIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_MIS_MRXDONE,Master Receive Data Interrupt" "0: CLR,1: SET"
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wgroup.long 0x1040++0x3
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line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
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bitfld.long 0x0 31. "INT_EVENT0_ISET_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_ISET_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_ISET_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 28. "INT_EVENT0_ISET_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_ISET_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_ISET_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_ISET_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_ISET_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_ISET_SSTOP,Stop Condition Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_ISET_SSTART,Start Condition Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_ISET_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_ISET_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_ISET_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_ISET_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_ISET_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_ISET_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_ISET_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_ISET_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_ISET_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_ISET_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_ISET_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_ISET_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_ISET_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 5. "INT_EVENT0_ISET_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_ISET_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 3. "INT_EVENT0_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_ISET_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 0. "INT_EVENT0_ISET_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: SET"
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wgroup.long 0x1048++0x3
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line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
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bitfld.long 0x0 31. "INT_EVENT0_ICLR_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_ICLR_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 29. "INT_EVENT0_ICLR_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 28. "INT_EVENT0_ICLR_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 27. "INT_EVENT0_ICLR_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_ICLR_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_ICLR_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 24. "INT_EVENT0_ICLR_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 23. "INT_EVENT0_ICLR_SSTOP,Slave STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 22. "INT_EVENT0_ICLR_SSTART,Slave START Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_ICLR_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 20. "INT_EVENT0_ICLR_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 19. "INT_EVENT0_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 18. "INT_EVENT0_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_ICLR_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_ICLR_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "INT_EVENT0_ICLR_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "INT_EVENT0_ICLR_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "INT_EVENT0_ICLR_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "INT_EVENT0_ICLR_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_ICLR_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_ICLR_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_ICLR_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "INT_EVENT0_ICLR_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_ICLR_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_ICLR_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_ICLR_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_ICLR_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1050++0x3
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line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
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group.long 0x1058++0x3
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line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
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bitfld.long 0x0 3. "INT_EVENT1_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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bitfld.long 0x0 2. "INT_EVENT1_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT1_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT1_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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rgroup.long 0x1060++0x3
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line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
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bitfld.long 0x0 3. "INT_EVENT1_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT1_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT1_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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rgroup.long 0x1068++0x3
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line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
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bitfld.long 0x0 3. "INT_EVENT1_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT1_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT1_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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wgroup.long 0x1070++0x3
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line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
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bitfld.long 0x0 3. "INT_EVENT1_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT1_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT1_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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wgroup.long 0x1078++0x3
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line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
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bitfld.long 0x0 3. "INT_EVENT1_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 1. "INT_EVENT1_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 0. "INT_EVENT1_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1080++0x3
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line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
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group.long 0x1088++0x3
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line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
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bitfld.long 0x0 3. "INT_EVENT2_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT2_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT2_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT2_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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rgroup.long 0x1090++0x3
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line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
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bitfld.long 0x0 3. "INT_EVENT2_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT2_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT2_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT2_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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rgroup.long 0x1098++0x3
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line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
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bitfld.long 0x0 3. "INT_EVENT2_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT2_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT2_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT2_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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wgroup.long 0x10A0++0x3
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line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
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bitfld.long 0x0 3. "INT_EVENT2_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT2_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT2_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT2_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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wgroup.long 0x10A8++0x3
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line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
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bitfld.long 0x0 3. "INT_EVENT2_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 2. "INT_EVENT2_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 1. "INT_EVENT2_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 0. "INT_EVENT2_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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rgroup.long 0x10E0++0x3
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line.long 0x0 "EVT_MODE,Event Mode"
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bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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newline
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bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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newline
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bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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wgroup.long 0x10E4++0x3
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line.long 0x0 "INTCTL,Interrupt control register"
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bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
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rgroup.long 0x10FC++0x3
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line.long 0x0 "DESC,Module Description"
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hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
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newline
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hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
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newline
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hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
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newline
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hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
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group.long 0x1200++0x7
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line.long 0x0 "GFCTL,I2C Glitch Filter Control"
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bitfld.long 0x0 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
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newline
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bitfld.long 0x0 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x0 0.--2. "GFCTL_DGFSEL,Glitch Suppression Pulse Width" "0: DISABLED,1: CLK_1,2: CLK_2,3: CLK_3,4: CLK_4,5: CLK_8,6: CLK_16,7: CLK_31"
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line.long 0x4 "TIMEOUT_CTL,I2C Timeout Count Control Register"
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bitfld.long 0x4 31. "TIMEOUT_CTL_TCNTBEN,Timeout Counter B Enable" "0: DISABLE,1: ENABLE"
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newline
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hexmask.long.byte 0x4 16.--23. 1. "TIMEOUT_CTL_TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h."
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newline
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bitfld.long 0x4 15. "TIMEOUT_CTL_TCNTAEN,Timeout Counter A Enable" "0: DISABLE,1: ENABLE"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "TIMEOUT_CTL_TCNTLA,Timeout counter A load value"
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rgroup.long 0x1208++0x3
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line.long 0x0 "TIMEOUT_CNT,I2C Timeout Count Register"
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hexmask.long.byte 0x0 16.--23. 1. "TIMEOUT_CNT_TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TIMEOUT_CNT_TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"
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group.long 0x1210++0x7
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line.long 0x0 "MSA,I2C Master Slave Address Register"
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bitfld.long 0x0 15. "MSA_MMODE,This bit selects the adressing mode to be used in master mode" "0: MODE7,1: MODE10"
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newline
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hexmask.long.word 0x0 1.--10. 1. "MSA_SADDR,I2C Slave Address This field specifies bits A9 through A0 of the slave address."
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newline
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bitfld.long 0x0 0. "MSA_DIR,Receive/Send" "0: TRANSMIT,1: RECEIVE"
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line.long 0x4 "MCTR,I2C Master Control Register"
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hexmask.long.word 0x4 16.--27. 1. "MCTR_MBLEN,I2C transaction length"
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newline
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bitfld.long 0x4 5. "MCTR_RD_ON_TXEMPTY,Read on TX Empty" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x4 4. "MCTR_MACKOEN,Master ACK overrride Enable" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x4 3. "MCTR_ACK,Data Acknowledge Enable." "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x4 2. "MCTR_STOP,Generate STOP" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x4 1. "MCTR_START,Generate START" "0: DISABLE,1: ENABLE"
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newline
|
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bitfld.long 0x4 0. "MCTR_BURSTRUN,I2C Master Enable" "0: DISABLE,1: ENABLE"
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rgroup.long 0x1218++0x7
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line.long 0x0 "MSR,I2C Master Status Register"
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hexmask.long.word 0x0 16.--27. 1. "MSR_MBCNT,I2C Master Transaction Count"
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newline
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bitfld.long 0x0 6. "MSR_BUSBSY,I2C Bus is Busy" "0: CLEARED,1: SET"
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newline
|
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bitfld.long 0x0 5. "MSR_IDLE,I2C Idle" "0: CLEARED,1: SET"
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newline
|
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bitfld.long 0x0 4. "MSR_ARBLST,Arbitration Lost" "0: CLEARED,1: SET"
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newline
|
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bitfld.long 0x0 3. "MSR_DATACK,Acknowledge Data" "0: CLEARED,1: SET"
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newline
|
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bitfld.long 0x0 2. "MSR_ADRACK,Acknowledge Address" "0: CLEARED,1: SET"
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newline
|
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bitfld.long 0x0 1. "MSR_ERR,Error" "0: CLEARED,1: SET"
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newline
|
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bitfld.long 0x0 0. "MSR_BUSY,I2C Master FSM Busy" "0: CLEARED,1: SET"
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line.long 0x4 "MRXDATA,I2C Master RXData"
|
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hexmask.long.byte 0x4 0.--7. 1. "MRXDATA_VALUE,Received Data."
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group.long 0x1220++0xB
|
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line.long 0x0 "MTXDATA,I2C Master TXData"
|
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hexmask.long.byte 0x0 0.--7. 1. "MTXDATA_VALUE,Transmit Data"
|
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line.long 0x4 "MTPR,I2C Master Timer Period"
|
|
hexmask.long.byte 0x4 0.--6. 1. "MTPR_TPR,Timer Period"
|
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line.long 0x8 "MCR,I2C Master Configuration"
|
|
bitfld.long 0x8 8. "MCR_LPBK,I2C Loopback" "0: DISABLE,1: ENABLE"
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newline
|
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bitfld.long 0x8 2. "MCR_CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x8 1. "MCR_MMST,Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: DISABLE,1: ENABLE"
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bitfld.long 0x8 0. "MCR_ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: DISABLE,1: ENABLE"
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rgroup.long 0x1234++0x3
|
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line.long 0x0 "MBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "MBMON_SDA,I2C SDA Status" "0: CLEARED,1: SET"
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newline
|
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bitfld.long 0x0 0. "MBMON_SCL,I2C SCL Status" "0: CLEARED,1: SET"
|
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group.long 0x1238++0x3
|
|
line.long 0x0 "MFIFOCTL,I2C Master FIFO Control"
|
|
bitfld.long 0x0 15. "MFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
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newline
|
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bitfld.long 0x0 8.--10. "MFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
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newline
|
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bitfld.long 0x0 7. "MFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
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newline
|
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bitfld.long 0x0 0.--2. "MFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
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rgroup.long 0x123C++0x3
|
|
line.long 0x0 "MFIFOSR,I2C Master FIFO Status Register"
|
|
bitfld.long 0x0 15. "MFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
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|
newline
|
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hexmask.long.byte 0x0 8.--11. 1. "MFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
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bitfld.long 0x0 7. "MFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "MFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1240++0x3
|
|
line.long 0x0 "MASTER_I2CPECCTL,I2C master PEC control register"
|
|
bitfld.long 0x0 12. "MASTER_I2CPECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "MASTER_I2CPECCTL_PECCNT,PEC Count"
|
|
rgroup.long 0x1244++0x3
|
|
line.long 0x0 "MASTER_PECSR,I2C master PEC status register"
|
|
bitfld.long 0x0 17. "MASTER_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
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bitfld.long 0x0 16. "MASTER_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
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|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "MASTER_PECSR_PECBYTECNT,PEC Byte Count"
|
|
group.long 0x1250++0xB
|
|
line.long 0x0 "SOAR,I2C Slave Own Address"
|
|
bitfld.long 0x0 15. "SOAR_SMODE,This bit selects the adressing mode to be used in slave mode." "0: MODE7,1: MODE10"
|
|
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|
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bitfld.long 0x0 14. "SOAR_OAREN,I2C Slave Own Address Enable" "0: DISABLE,1: ENABLE"
|
|
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|
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hexmask.long.word 0x0 0.--9. 1. "SOAR_OAR,I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address."
|
|
line.long 0x4 "SOAR2,I2C Slave Own Address 2"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SOAR2_OAR2_MASK,I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address."
|
|
newline
|
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bitfld.long 0x4 7. "SOAR2_OAR2EN,I2C Slave Own Address 2 Enable" "0: DISABLE,1: ENABLE"
|
|
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|
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hexmask.long.byte 0x4 0.--6. 1. "SOAR2_OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "SCTR,I2C Slave Control Register"
|
|
bitfld.long 0x8 10. "SCTR_SWUEN,Slave Wakeup Enable" "0: DISABLE,1: ENABLE"
|
|
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|
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bitfld.long 0x8 9. "SCTR_EN_DEFDEVADR,Enable Deault device address" "0: DISABLE,1: ENABLE"
|
|
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|
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bitfld.long 0x8 8. "SCTR_EN_ALRESPADR,Enable Alert Response Address" "0: DISABLE,1: ENABLE"
|
|
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|
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bitfld.long 0x8 7. "SCTR_EN_DEFHOSTADR,Enable Default Host Address" "0: DISABLE,1: ENABLE"
|
|
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|
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bitfld.long 0x8 6. "SCTR_RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: DISABLE,1: ENABLE"
|
|
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|
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bitfld.long 0x8 5. "SCTR_TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: DISABLE,1: ENABLE"
|
|
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|
|
bitfld.long 0x8 4. "SCTR_TXTRIG_TXMODE,Tx Trigger when slave FSM is in Tx Mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 3. "SCTR_TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: DISABLE,1: ENABLE"
|
|
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|
|
bitfld.long 0x8 2. "SCTR_SCLKSTRETCH,Slave Clock Stretch Enable" "0: DISABLE,1: ENABLE"
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|
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|
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bitfld.long 0x8 1. "SCTR_GENCALL,General call response enable. This bit is only available in UCBxI2COA0." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 0. "SCTR_ACTIVE,Device Active. Setting this bit enables the slave functionality." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x125C++0x7
|
|
line.long 0x0 "SSR,I2C Slave Status Register"
|
|
hexmask.long.word 0x0 9.--18. 1. "SSR_ADDRMATCH,Indicates the address for which slave address match happened"
|
|
newline
|
|
bitfld.long 0x0 8. "SSR_STALE_TXFIFO,Stale Tx FIFO" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 7. "SSR_TXMODE,Slave FSM is in TX MODE" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 6. "SSR_BUSBSY,I2C bus is busy" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 5. "SSR_QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read"
|
|
newline
|
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rbitfld.long 0x0 4. "SSR_QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.."
|
|
newline
|
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rbitfld.long 0x0 3. "SSR_OAR2SEL,OAR2 Address Matched" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "SSR_RXMODE,Slave FSM is in Rx MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 1. "SSR_TREQ,Transmit Request" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 0. "SSR_RREQ,Receive Request" "0: CLEARED,1: SET"
|
|
line.long 0x4 "SRXDATA,I2C Slave RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SRXDATA_VALUE,Received Data."
|
|
group.long 0x1264++0xB
|
|
line.long 0x0 "STXDATA,I2C Slave TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STXDATA_VALUE,Transmit Data"
|
|
line.long 0x4 "SACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x4 4. "SACKCTL_ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte." "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 3. "SACKCTL_ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 2. "SACKCTL_ACKOEN_ON_START,When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 1. "SACKCTL_ACKOVAL,I2C Slave ACK Override Value" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "SACKCTL_ACKOEN,I2C Slave ACK Override Enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "SFIFOCTL,I2C Slave FIFO Control"
|
|
bitfld.long 0x8 15. "SFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "SFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
|
bitfld.long 0x8 7. "SFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
|
rgroup.long 0x1270++0x3
|
|
line.long 0x0 "SFIFOSR,I2C Slave FIFO Status Register"
|
|
bitfld.long 0x0 15. "SFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
|
bitfld.long 0x0 7. "SFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1274++0x3
|
|
line.long 0x0 "SLAVE_PECCTL,I2C Slave PEC control register"
|
|
bitfld.long 0x0 12. "SLAVE_PECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECCTL_PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from.."
|
|
rgroup.long 0x1278++0x3
|
|
line.long 0x0 "SLAVE_PECSR,I2C slave PEC status register"
|
|
bitfld.long 0x0 17. "SLAVE_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "SLAVE_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECSR_PECBYTECNT,This is the current PEC Byte Count of the Slave State Machine."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "I2C0"
|
|
base ad:0x400F0000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
newline
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
newline
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
newline
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
newline
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT0_IMASK_INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_IMASK_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_IMASK_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_IMASK_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_IMASK_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_IMASK_SDMA_DONE1_3,Slave DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_IMASK_SDMA_DONE1_2,Slave DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_IMASK_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_IMASK_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_IMASK_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_IMASK_STXEMPTY,Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_IMASK_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an Slave RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_MSTART,START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_RIS_INTR_OVFL,Interrupt overflow interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_RIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_RIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_RIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_RIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_RIS_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_RIS_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_RIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_RIS_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_RIS_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_RIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_RIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 10. "INT_EVENT0_RIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_RIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_RIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_RIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_RIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_RIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_RIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_RIS_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
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rgroup.long 0x1038++0x3
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line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
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bitfld.long 0x0 31. "INT_EVENT0_MIS_INTR_OVFL,Interrupt overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_MIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_MIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 28. "INT_EVENT0_MIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_MIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_MIS_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_MIS_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_MIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_MIS_SSTOP,Slave STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_MIS_SSTART,Slave START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_MIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_MIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_MIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_MIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_MIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_MIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_MIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_MIS_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_MIS_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_MIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_MIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_MIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_MIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_MIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_MIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_MIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_MIS_MRXDONE,Master Receive Data Interrupt" "0: CLR,1: SET"
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wgroup.long 0x1040++0x3
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line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
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bitfld.long 0x0 31. "INT_EVENT0_ISET_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_ISET_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_ISET_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 28. "INT_EVENT0_ISET_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_ISET_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_ISET_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_ISET_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_ISET_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_ISET_SSTOP,Stop Condition Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_ISET_SSTART,Start Condition Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_ISET_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_ISET_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_ISET_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_ISET_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_ISET_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_ISET_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_ISET_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_ISET_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_ISET_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_ISET_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_ISET_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_ISET_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_ISET_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_ISET_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_ISET_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_ISET_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_ISET_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: SET"
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wgroup.long 0x1048++0x3
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line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
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bitfld.long 0x0 31. "INT_EVENT0_ICLR_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_ICLR_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 29. "INT_EVENT0_ICLR_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 28. "INT_EVENT0_ICLR_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 27. "INT_EVENT0_ICLR_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_ICLR_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_ICLR_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_ICLR_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_ICLR_SSTOP,Slave STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_ICLR_SSTART,Slave START Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_ICLR_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_ICLR_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_ICLR_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_ICLR_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_ICLR_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_ICLR_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_ICLR_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_ICLR_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_ICLR_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_ICLR_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_ICLR_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_ICLR_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_ICLR_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_ICLR_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_ICLR_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_ICLR_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1050++0x3
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line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
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group.long 0x1058++0x3
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line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
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bitfld.long 0x0 3. "INT_EVENT1_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT1_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT1_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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rgroup.long 0x1060++0x3
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line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
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bitfld.long 0x0 3. "INT_EVENT1_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT1_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT1_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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rgroup.long 0x1068++0x3
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line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
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bitfld.long 0x0 3. "INT_EVENT1_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT1_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT1_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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wgroup.long 0x1070++0x3
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line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
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bitfld.long 0x0 3. "INT_EVENT1_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT1_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT1_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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wgroup.long 0x1078++0x3
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line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
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bitfld.long 0x0 3. "INT_EVENT1_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 2. "INT_EVENT1_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT1_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 0. "INT_EVENT1_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT2_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
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bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
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hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
newline
|
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hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
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|
newline
|
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hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1200++0x7
|
|
line.long 0x0 "GFCTL,I2C Glitch Filter Control"
|
|
bitfld.long 0x0 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLE,1: ENABLE"
|
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newline
|
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bitfld.long 0x0 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
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newline
|
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bitfld.long 0x0 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x0 0.--2. "GFCTL_DGFSEL,Glitch Suppression Pulse Width" "0: DISABLED,1: CLK_1,2: CLK_2,3: CLK_3,4: CLK_4,5: CLK_8,6: CLK_16,7: CLK_31"
|
|
line.long 0x4 "TIMEOUT_CTL,I2C Timeout Count Control Register"
|
|
bitfld.long 0x4 31. "TIMEOUT_CTL_TCNTBEN,Timeout Counter B Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.byte 0x4 16.--23. 1. "TIMEOUT_CTL_TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h."
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newline
|
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bitfld.long 0x4 15. "TIMEOUT_CTL_TCNTAEN,Timeout Counter A Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TIMEOUT_CTL_TCNTLA,Timeout counter A load value"
|
|
rgroup.long 0x1208++0x3
|
|
line.long 0x0 "TIMEOUT_CNT,I2C Timeout Count Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TIMEOUT_CNT_TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TIMEOUT_CNT_TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"
|
|
group.long 0x1210++0x7
|
|
line.long 0x0 "MSA,I2C Master Slave Address Register"
|
|
bitfld.long 0x0 15. "MSA_MMODE,This bit selects the adressing mode to be used in master mode" "0: MODE7,1: MODE10"
|
|
newline
|
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hexmask.long.word 0x0 1.--10. 1. "MSA_SADDR,I2C Slave Address This field specifies bits A9 through A0 of the slave address."
|
|
newline
|
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bitfld.long 0x0 0. "MSA_DIR,Receive/Send" "0: TRANSMIT,1: RECEIVE"
|
|
line.long 0x4 "MCTR,I2C Master Control Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "MCTR_MBLEN,I2C transaction length"
|
|
newline
|
|
bitfld.long 0x4 5. "MCTR_RD_ON_TXEMPTY,Read on TX Empty" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 4. "MCTR_MACKOEN,Master ACK overrride Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "MCTR_ACK,Data Acknowledge Enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 2. "MCTR_STOP,Generate STOP" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 1. "MCTR_START,Generate START" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 0. "MCTR_BURSTRUN,I2C Master Enable" "0: DISABLE,1: ENABLE"
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rgroup.long 0x1218++0x7
|
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line.long 0x0 "MSR,I2C Master Status Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "MSR_MBCNT,I2C Master Transaction Count"
|
|
newline
|
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bitfld.long 0x0 6. "MSR_BUSBSY,I2C Bus is Busy" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 5. "MSR_IDLE,I2C Idle" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 4. "MSR_ARBLST,Arbitration Lost" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 3. "MSR_DATACK,Acknowledge Data" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "MSR_ADRACK,Acknowledge Address" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "MSR_ERR,Error" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "MSR_BUSY,I2C Master FSM Busy" "0: CLEARED,1: SET"
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line.long 0x4 "MRXDATA,I2C Master RXData"
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hexmask.long.byte 0x4 0.--7. 1. "MRXDATA_VALUE,Received Data."
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group.long 0x1220++0xB
|
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line.long 0x0 "MTXDATA,I2C Master TXData"
|
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hexmask.long.byte 0x0 0.--7. 1. "MTXDATA_VALUE,Transmit Data"
|
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line.long 0x4 "MTPR,I2C Master Timer Period"
|
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hexmask.long.byte 0x4 0.--6. 1. "MTPR_TPR,Timer Period"
|
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line.long 0x8 "MCR,I2C Master Configuration"
|
|
bitfld.long 0x8 8. "MCR_LPBK,I2C Loopback" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 2. "MCR_CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: DISABLE,1: ENABLE"
|
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newline
|
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bitfld.long 0x8 1. "MCR_MMST,Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: DISABLE,1: ENABLE"
|
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newline
|
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bitfld.long 0x8 0. "MCR_ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: DISABLE,1: ENABLE"
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rgroup.long 0x1234++0x3
|
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line.long 0x0 "MBMON,I2C Master Bus Monitor"
|
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bitfld.long 0x0 1. "MBMON_SDA,I2C SDA Status" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "MBMON_SCL,I2C SCL Status" "0: CLEARED,1: SET"
|
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group.long 0x1238++0x3
|
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line.long 0x0 "MFIFOCTL,I2C Master FIFO Control"
|
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bitfld.long 0x0 15. "MFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
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bitfld.long 0x0 8.--10. "MFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
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bitfld.long 0x0 7. "MFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
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bitfld.long 0x0 0.--2. "MFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
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rgroup.long 0x123C++0x3
|
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line.long 0x0 "MFIFOSR,I2C Master FIFO Status Register"
|
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bitfld.long 0x0 15. "MFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
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hexmask.long.byte 0x0 8.--11. 1. "MFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
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bitfld.long 0x0 7. "MFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "MFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
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group.long 0x1240++0x3
|
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line.long 0x0 "MASTER_I2CPECCTL,I2C master PEC control register"
|
|
bitfld.long 0x0 12. "MASTER_I2CPECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "MASTER_I2CPECCTL_PECCNT,PEC Count"
|
|
rgroup.long 0x1244++0x3
|
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line.long 0x0 "MASTER_PECSR,I2C master PEC status register"
|
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bitfld.long 0x0 17. "MASTER_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "MASTER_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "MASTER_PECSR_PECBYTECNT,PEC Byte Count"
|
|
group.long 0x1250++0xB
|
|
line.long 0x0 "SOAR,I2C Slave Own Address"
|
|
bitfld.long 0x0 15. "SOAR_SMODE,This bit selects the adressing mode to be used in slave mode." "0: MODE7,1: MODE10"
|
|
newline
|
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bitfld.long 0x0 14. "SOAR_OAREN,I2C Slave Own Address Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "SOAR_OAR,I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address."
|
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line.long 0x4 "SOAR2,I2C Slave Own Address 2"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SOAR2_OAR2_MASK,I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address."
|
|
newline
|
|
bitfld.long 0x4 7. "SOAR2_OAR2EN,I2C Slave Own Address 2 Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "SOAR2_OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "SCTR,I2C Slave Control Register"
|
|
bitfld.long 0x8 10. "SCTR_SWUEN,Slave Wakeup Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 9. "SCTR_EN_DEFDEVADR,Enable Deault device address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 8. "SCTR_EN_ALRESPADR,Enable Alert Response Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 7. "SCTR_EN_DEFHOSTADR,Enable Default Host Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 6. "SCTR_RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 5. "SCTR_TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "SCTR_TXTRIG_TXMODE,Tx Trigger when slave FSM is in Tx Mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 3. "SCTR_TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 2. "SCTR_SCLKSTRETCH,Slave Clock Stretch Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "SCTR_GENCALL,General call response enable. This bit is only available in UCBxI2COA0." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 0. "SCTR_ACTIVE,Device Active. Setting this bit enables the slave functionality." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x125C++0x7
|
|
line.long 0x0 "SSR,I2C Slave Status Register"
|
|
hexmask.long.word 0x0 9.--18. 1. "SSR_ADDRMATCH,Indicates the address for which slave address match happened"
|
|
newline
|
|
bitfld.long 0x0 8. "SSR_STALE_TXFIFO,Stale Tx FIFO" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "SSR_TXMODE,Slave FSM is in TX MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "SSR_BUSBSY,I2C bus is busy" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 5. "SSR_QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read"
|
|
newline
|
|
rbitfld.long 0x0 4. "SSR_QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.."
|
|
newline
|
|
rbitfld.long 0x0 3. "SSR_OAR2SEL,OAR2 Address Matched" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "SSR_RXMODE,Slave FSM is in Rx MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 1. "SSR_TREQ,Transmit Request" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 0. "SSR_RREQ,Receive Request" "0: CLEARED,1: SET"
|
|
line.long 0x4 "SRXDATA,I2C Slave RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SRXDATA_VALUE,Received Data."
|
|
group.long 0x1264++0xB
|
|
line.long 0x0 "STXDATA,I2C Slave TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STXDATA_VALUE,Transmit Data"
|
|
line.long 0x4 "SACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x4 4. "SACKCTL_ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "SACKCTL_ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "SACKCTL_ACKOEN_ON_START,When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "SACKCTL_ACKOVAL,I2C Slave ACK Override Value" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "SACKCTL_ACKOEN,I2C Slave ACK Override Enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "SFIFOCTL,I2C Slave FIFO Control"
|
|
bitfld.long 0x8 15. "SFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "SFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
|
bitfld.long 0x8 7. "SFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
|
rgroup.long 0x1270++0x3
|
|
line.long 0x0 "SFIFOSR,I2C Slave FIFO Status Register"
|
|
bitfld.long 0x0 15. "SFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
|
bitfld.long 0x0 7. "SFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1274++0x3
|
|
line.long 0x0 "SLAVE_PECCTL,I2C Slave PEC control register"
|
|
bitfld.long 0x0 12. "SLAVE_PECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECCTL_PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from.."
|
|
rgroup.long 0x1278++0x3
|
|
line.long 0x0 "SLAVE_PECSR,I2C slave PEC status register"
|
|
bitfld.long 0x0 17. "SLAVE_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "SLAVE_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECSR_PECBYTECNT,This is the current PEC Byte Count of the Slave State Machine."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "I2C1"
|
|
base ad:0x400F2000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
newline
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
newline
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
newline
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
newline
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT0_IMASK_INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_IMASK_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_IMASK_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_IMASK_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_IMASK_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_IMASK_SDMA_DONE1_3,Slave DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_IMASK_SDMA_DONE1_2,Slave DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_IMASK_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_IMASK_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_IMASK_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_IMASK_STXEMPTY,Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_IMASK_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an Slave RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_MSTART,START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_RIS_INTR_OVFL,Interrupt overflow interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_RIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_RIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_RIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_RIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_RIS_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_RIS_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_RIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_RIS_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_RIS_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_RIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_RIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_MIS_INTR_OVFL,Interrupt overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_MIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_MIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_MIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_MIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_MIS_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_MIS_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_MIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_MIS_SSTOP,Slave STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_MIS_SSTART,Slave START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_MIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_MIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_MRXDONE,Master Receive Data Interrupt" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 31. "INT_EVENT0_ISET_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_ISET_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_ISET_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_ISET_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_ISET_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_ISET_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_ISET_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_ISET_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 23. "INT_EVENT0_ISET_SSTOP,Stop Condition Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_ISET_SSTART,Start Condition Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_ISET_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_ISET_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ISET_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 31. "INT_EVENT0_ICLR_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_ICLR_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_ICLR_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_ICLR_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 27. "INT_EVENT0_ICLR_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 26. "INT_EVENT0_ICLR_SDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 25. "INT_EVENT0_ICLR_SDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 24. "INT_EVENT0_ICLR_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 23. "INT_EVENT0_ICLR_SSTOP,Slave STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_ICLR_SSTART,Slave START Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 21. "INT_EVENT0_ICLR_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 20. "INT_EVENT0_ICLR_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 19. "INT_EVENT0_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 16. "INT_EVENT0_ICLR_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_MDMA_DONE1_3,DMA Done 1 on Event Channel 3" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_MDMA_DONE1_2,DMA Done 1 on Event Channel 2" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 8. "INT_EVENT0_ICLR_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 7. "INT_EVENT0_ICLR_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 3. "INT_EVENT0_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT0_ICLR_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT0_ICLR_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
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line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1058++0x3
|
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line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
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line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT1_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT1_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT2_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
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rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1200++0x7
|
|
line.long 0x0 "GFCTL,I2C Glitch Filter Control"
|
|
bitfld.long 0x0 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
newline
|
|
bitfld.long 0x0 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "GFCTL_DGFSEL,Glitch Suppression Pulse Width" "0: DISABLED,1: CLK_1,2: CLK_2,3: CLK_3,4: CLK_4,5: CLK_8,6: CLK_16,7: CLK_31"
|
|
line.long 0x4 "TIMEOUT_CTL,I2C Timeout Count Control Register"
|
|
bitfld.long 0x4 31. "TIMEOUT_CTL_TCNTBEN,Timeout Counter B Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "TIMEOUT_CTL_TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h."
|
|
newline
|
|
bitfld.long 0x4 15. "TIMEOUT_CTL_TCNTAEN,Timeout Counter A Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TIMEOUT_CTL_TCNTLA,Timeout counter A load value"
|
|
rgroup.long 0x1208++0x3
|
|
line.long 0x0 "TIMEOUT_CNT,I2C Timeout Count Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TIMEOUT_CNT_TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TIMEOUT_CNT_TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"
|
|
group.long 0x1210++0x7
|
|
line.long 0x0 "MSA,I2C Master Slave Address Register"
|
|
bitfld.long 0x0 15. "MSA_MMODE,This bit selects the adressing mode to be used in master mode" "0: MODE7,1: MODE10"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "MSA_SADDR,I2C Slave Address This field specifies bits A9 through A0 of the slave address."
|
|
newline
|
|
bitfld.long 0x0 0. "MSA_DIR,Receive/Send" "0: TRANSMIT,1: RECEIVE"
|
|
line.long 0x4 "MCTR,I2C Master Control Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "MCTR_MBLEN,I2C transaction length"
|
|
newline
|
|
bitfld.long 0x4 5. "MCTR_RD_ON_TXEMPTY,Read on TX Empty" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4. "MCTR_MACKOEN,Master ACK overrride Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "MCTR_ACK,Data Acknowledge Enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "MCTR_STOP,Generate STOP" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "MCTR_START,Generate START" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "MCTR_BURSTRUN,I2C Master Enable" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1218++0x7
|
|
line.long 0x0 "MSR,I2C Master Status Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "MSR_MBCNT,I2C Master Transaction Count"
|
|
newline
|
|
bitfld.long 0x0 6. "MSR_BUSBSY,I2C Bus is Busy" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "MSR_IDLE,I2C Idle" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MSR_ARBLST,Arbitration Lost" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "MSR_DATACK,Acknowledge Data" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "MSR_ADRACK,Acknowledge Address" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MSR_ERR,Error" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MSR_BUSY,I2C Master FSM Busy" "0: CLEARED,1: SET"
|
|
line.long 0x4 "MRXDATA,I2C Master RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MRXDATA_VALUE,Received Data."
|
|
group.long 0x1220++0xB
|
|
line.long 0x0 "MTXDATA,I2C Master TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MTXDATA_VALUE,Transmit Data"
|
|
line.long 0x4 "MTPR,I2C Master Timer Period"
|
|
hexmask.long.byte 0x4 0.--6. 1. "MTPR_TPR,Timer Period"
|
|
line.long 0x8 "MCR,I2C Master Configuration"
|
|
bitfld.long 0x8 8. "MCR_LPBK,I2C Loopback" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 2. "MCR_CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 1. "MCR_MMST,Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 0. "MCR_ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1234++0x3
|
|
line.long 0x0 "MBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "MBMON_SDA,I2C SDA Status" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MBMON_SCL,I2C SCL Status" "0: CLEARED,1: SET"
|
|
group.long 0x1238++0x3
|
|
line.long 0x0 "MFIFOCTL,I2C Master FIFO Control"
|
|
bitfld.long 0x0 15. "MFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
|
bitfld.long 0x0 7. "MFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "MFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
|
rgroup.long 0x123C++0x3
|
|
line.long 0x0 "MFIFOSR,I2C Master FIFO Status Register"
|
|
bitfld.long 0x0 15. "MFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
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hexmask.long.byte 0x0 8.--11. 1. "MFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
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bitfld.long 0x0 7. "MFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "MFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1240++0x3
|
|
line.long 0x0 "MASTER_I2CPECCTL,I2C master PEC control register"
|
|
bitfld.long 0x0 12. "MASTER_I2CPECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "MASTER_I2CPECCTL_PECCNT,PEC Count"
|
|
rgroup.long 0x1244++0x3
|
|
line.long 0x0 "MASTER_PECSR,I2C master PEC status register"
|
|
bitfld.long 0x0 17. "MASTER_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 16. "MASTER_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "MASTER_PECSR_PECBYTECNT,PEC Byte Count"
|
|
group.long 0x1250++0xB
|
|
line.long 0x0 "SOAR,I2C Slave Own Address"
|
|
bitfld.long 0x0 15. "SOAR_SMODE,This bit selects the adressing mode to be used in slave mode." "0: MODE7,1: MODE10"
|
|
newline
|
|
bitfld.long 0x0 14. "SOAR_OAREN,I2C Slave Own Address Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "SOAR_OAR,I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address."
|
|
line.long 0x4 "SOAR2,I2C Slave Own Address 2"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SOAR2_OAR2_MASK,I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address."
|
|
newline
|
|
bitfld.long 0x4 7. "SOAR2_OAR2EN,I2C Slave Own Address 2 Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "SOAR2_OAR2,I2C Slave Own Address 2"
|
|
line.long 0x8 "SCTR,I2C Slave Control Register"
|
|
bitfld.long 0x8 10. "SCTR_SWUEN,Slave Wakeup Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 9. "SCTR_EN_DEFDEVADR,Enable Deault device address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 8. "SCTR_EN_ALRESPADR,Enable Alert Response Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 7. "SCTR_EN_DEFHOSTADR,Enable Default Host Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 6. "SCTR_RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 5. "SCTR_TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "SCTR_TXTRIG_TXMODE,Tx Trigger when slave FSM is in Tx Mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 3. "SCTR_TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 2. "SCTR_SCLKSTRETCH,Slave Clock Stretch Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "SCTR_GENCALL,General call response enable. This bit is only available in UCBxI2COA0." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 0. "SCTR_ACTIVE,Device Active. Setting this bit enables the slave functionality." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x125C++0x7
|
|
line.long 0x0 "SSR,I2C Slave Status Register"
|
|
hexmask.long.word 0x0 9.--18. 1. "SSR_ADDRMATCH,Indicates the address for which slave address match happened"
|
|
newline
|
|
bitfld.long 0x0 8. "SSR_STALE_TXFIFO,Stale Tx FIFO" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "SSR_TXMODE,Slave FSM is in TX MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "SSR_BUSBSY,I2C bus is busy" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 5. "SSR_QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read"
|
|
newline
|
|
rbitfld.long 0x0 4. "SSR_QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.."
|
|
newline
|
|
rbitfld.long 0x0 3. "SSR_OAR2SEL,OAR2 Address Matched" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "SSR_RXMODE,Slave FSM is in Rx MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 1. "SSR_TREQ,Transmit Request" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 0. "SSR_RREQ,Receive Request" "0: CLEARED,1: SET"
|
|
line.long 0x4 "SRXDATA,I2C Slave RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SRXDATA_VALUE,Received Data."
|
|
group.long 0x1264++0xB
|
|
line.long 0x0 "STXDATA,I2C Slave TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STXDATA_VALUE,Transmit Data"
|
|
line.long 0x4 "SACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x4 4. "SACKCTL_ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "SACKCTL_ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "SACKCTL_ACKOEN_ON_START,When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "SACKCTL_ACKOVAL,I2C Slave ACK Override Value" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "SACKCTL_ACKOEN,I2C Slave ACK Override Enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "SFIFOCTL,I2C Slave FIFO Control"
|
|
bitfld.long 0x8 15. "SFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "SFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
|
bitfld.long 0x8 7. "SFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
|
rgroup.long 0x1270++0x3
|
|
line.long 0x0 "SFIFOSR,I2C Slave FIFO Status Register"
|
|
bitfld.long 0x0 15. "SFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
|
bitfld.long 0x0 7. "SFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1274++0x3
|
|
line.long 0x0 "SLAVE_PECCTL,I2C Slave PEC control register"
|
|
bitfld.long 0x0 12. "SLAVE_PECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECCTL_PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from.."
|
|
rgroup.long 0x1278++0x3
|
|
line.long 0x0 "SLAVE_PECSR,I2C slave PEC status register"
|
|
bitfld.long 0x0 17. "SLAVE_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "SLAVE_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECSR_PECBYTECNT,This is the current PEC Byte Count of the Slave State Machine."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "I2C1"
|
|
base ad:0x400F2000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
newline
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
newline
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
newline
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
newline
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT0_IMASK_INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_IMASK_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_IMASK_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_IMASK_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_IMASK_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_IMASK_SDMA_DONE_RX,Slave DMA Done on Event Channel RX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_IMASK_SDMA_DONE_TX,Slave DMA Done on Event Channel TX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_IMASK_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_IMASK_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_IMASK_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_IMASK_STXEMPTY,Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_IMASK_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an Slave RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 14. "INT_EVENT0_IMASK_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_IMASK_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_IMASK_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_IMASK_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_IMASK_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_IMASK_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_IMASK_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_IMASK_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_IMASK_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_IMASK_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_IMASK_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_IMASK_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
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rgroup.long 0x1030++0x3
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line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
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bitfld.long 0x0 31. "INT_EVENT0_RIS_INTR_OVFL,Interrupt overflow interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_RIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_RIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 28. "INT_EVENT0_RIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_RIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_RIS_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_RIS_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_RIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_RIS_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_RIS_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_RIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_RIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_RIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_RIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_RIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_RIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_RIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_RIS_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_RIS_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_RIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_RIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_RIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_RIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_RIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_RIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_RIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_RIS_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
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rgroup.long 0x1038++0x3
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line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
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bitfld.long 0x0 31. "INT_EVENT0_MIS_INTR_OVFL,Interrupt overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_MIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_MIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 28. "INT_EVENT0_MIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_MIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_MIS_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_MIS_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_MIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_MIS_SSTOP,Slave STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_MIS_SSTART,Slave START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_MIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_MIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_MIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_MIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_MIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_MIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_MIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_MIS_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_MIS_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 10. "INT_EVENT0_MIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_MIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_MIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_MIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_MIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_MIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_MIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_MIS_MRXDONE,Master Receive Data Interrupt" "0: CLR,1: SET"
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wgroup.long 0x1040++0x3
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line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
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bitfld.long 0x0 31. "INT_EVENT0_ISET_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_ISET_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_ISET_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 28. "INT_EVENT0_ISET_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 27. "INT_EVENT0_ISET_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_ISET_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 25. "INT_EVENT0_ISET_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_ISET_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_ISET_SSTOP,Stop Condition Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_ISET_SSTART,Start Condition Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 21. "INT_EVENT0_ISET_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_ISET_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_ISET_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 16. "INT_EVENT0_ISET_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_ISET_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 14. "INT_EVENT0_ISET_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 13. "INT_EVENT0_ISET_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 12. "INT_EVENT0_ISET_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 11. "INT_EVENT0_ISET_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 10. "INT_EVENT0_ISET_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 9. "INT_EVENT0_ISET_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_ISET_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_ISET_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 5. "INT_EVENT0_ISET_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_ISET_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 3. "INT_EVENT0_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT0_ISET_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 0. "INT_EVENT0_ISET_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: SET"
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wgroup.long 0x1048++0x3
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line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
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bitfld.long 0x0 31. "INT_EVENT0_ICLR_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 30. "INT_EVENT0_ICLR_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 29. "INT_EVENT0_ICLR_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 28. "INT_EVENT0_ICLR_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 27. "INT_EVENT0_ICLR_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 26. "INT_EVENT0_ICLR_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 25. "INT_EVENT0_ICLR_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 24. "INT_EVENT0_ICLR_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 23. "INT_EVENT0_ICLR_SSTOP,Slave STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 22. "INT_EVENT0_ICLR_SSTART,Slave START Detection Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 21. "INT_EVENT0_ICLR_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 20. "INT_EVENT0_ICLR_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 19. "INT_EVENT0_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 18. "INT_EVENT0_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 17. "INT_EVENT0_ICLR_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 16. "INT_EVENT0_ICLR_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 14. "INT_EVENT0_ICLR_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 13. "INT_EVENT0_ICLR_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 12. "INT_EVENT0_ICLR_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 11. "INT_EVENT0_ICLR_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 10. "INT_EVENT0_ICLR_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 9. "INT_EVENT0_ICLR_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 8. "INT_EVENT0_ICLR_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ICLR_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 3. "INT_EVENT0_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
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line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
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bitfld.long 0x0 3. "INT_EVENT1_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT1_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT1_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT1_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
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group.long 0x1088++0x3
|
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line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT2_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT2_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
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rgroup.long 0x1090++0x3
|
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line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1200++0x7
|
|
line.long 0x0 "GFCTL,I2C Glitch Filter Control"
|
|
bitfld.long 0x0 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
newline
|
|
bitfld.long 0x0 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "GFCTL_DGFSEL,Glitch Suppression Pulse Width" "0: DISABLED,1: CLK_1,2: CLK_2,3: CLK_3,4: CLK_4,5: CLK_8,6: CLK_16,7: CLK_31"
|
|
line.long 0x4 "TIMEOUT_CTL,I2C Timeout Count Control Register"
|
|
bitfld.long 0x4 31. "TIMEOUT_CTL_TCNTBEN,Timeout Counter B Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--23. 1. "TIMEOUT_CTL_TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h."
|
|
newline
|
|
bitfld.long 0x4 15. "TIMEOUT_CTL_TCNTAEN,Timeout Counter A Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "TIMEOUT_CTL_TCNTLA,Timeout counter A load value"
|
|
rgroup.long 0x1208++0x3
|
|
line.long 0x0 "TIMEOUT_CNT,I2C Timeout Count Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TIMEOUT_CNT_TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TIMEOUT_CNT_TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"
|
|
group.long 0x1210++0x7
|
|
line.long 0x0 "MSA,I2C Master Slave Address Register"
|
|
bitfld.long 0x0 15. "MSA_MMODE,This bit selects the adressing mode to be used in master mode" "0: MODE7,1: MODE10"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "MSA_SADDR,I2C Slave Address This field specifies bits A9 through A0 of the slave address."
|
|
newline
|
|
bitfld.long 0x0 0. "MSA_DIR,Receive/Send" "0: TRANSMIT,1: RECEIVE"
|
|
line.long 0x4 "MCTR,I2C Master Control Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "MCTR_MBLEN,I2C transaction length"
|
|
newline
|
|
bitfld.long 0x4 5. "MCTR_RD_ON_TXEMPTY,Read on TX Empty" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4. "MCTR_MACKOEN,Master ACK overrride Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "MCTR_ACK,Data Acknowledge Enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "MCTR_STOP,Generate STOP" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "MCTR_START,Generate START" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "MCTR_BURSTRUN,I2C Master Enable and start transaction" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1218++0x7
|
|
line.long 0x0 "MSR,I2C Master Status Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "MSR_MBCNT,I2C Master Transaction Count"
|
|
newline
|
|
bitfld.long 0x0 6. "MSR_BUSBSY,I2C Bus is Busy" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "MSR_IDLE,I2C Idle" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MSR_ARBLST,Arbitration Lost" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "MSR_DATACK,Acknowledge Data" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "MSR_ADRACK,Acknowledge Address" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MSR_ERR,Error" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MSR_BUSY,I2C Master FSM Busy" "0: CLEARED,1: SET"
|
|
line.long 0x4 "MRXDATA,I2C Master RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MRXDATA_VALUE,Received Data."
|
|
group.long 0x1220++0xB
|
|
line.long 0x0 "MTXDATA,I2C Master TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MTXDATA_VALUE,Transmit Data"
|
|
line.long 0x4 "MTPR,I2C Master Timer Period"
|
|
hexmask.long.byte 0x4 0.--6. 1. "MTPR_TPR,Timer Period"
|
|
line.long 0x8 "MCR,I2C Master Configuration"
|
|
bitfld.long 0x8 8. "MCR_LPBK,I2C Loopback" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 2. "MCR_CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "MCR_MMST,Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 0. "MCR_ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1234++0x3
|
|
line.long 0x0 "MBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "MBMON_SDA,I2C SDA Status" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MBMON_SCL,I2C SCL Status" "0: CLEARED,1: SET"
|
|
group.long 0x1238++0x3
|
|
line.long 0x0 "MFIFOCTL,I2C Master FIFO Control"
|
|
bitfld.long 0x0 15. "MFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "MFIFOCTL_RXTRIG,RX FIFO Trigger" "0: LEVEL_1,1: LEVEL_2,2: LEVEL_3,3: LEVEL_4,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
|
bitfld.long 0x0 7. "MFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "MFIFOCTL_TXTRIG,TX FIFO Trigger" "0: EMPTY,1: LEVEL_1,2: LEVEL_2,3: LEVEL_3,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
|
rgroup.long 0x123C++0x3
|
|
line.long 0x0 "MFIFOSR,I2C Master FIFO Status Register"
|
|
bitfld.long 0x0 15. "MFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
|
bitfld.long 0x0 7. "MFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "MFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1240++0x3
|
|
line.long 0x0 "MASTER_I2CPECCTL,I2C master PEC control register"
|
|
bitfld.long 0x0 12. "MASTER_I2CPECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "MASTER_I2CPECCTL_PECCNT,PEC Count"
|
|
rgroup.long 0x1244++0x3
|
|
line.long 0x0 "MASTER_PECSR,I2C master PEC status register"
|
|
bitfld.long 0x0 17. "MASTER_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "MASTER_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "MASTER_PECSR_PECBYTECNT,PEC Byte Count"
|
|
group.long 0x1250++0xB
|
|
line.long 0x0 "SOAR,I2C Slave Own Address"
|
|
bitfld.long 0x0 15. "SOAR_SMODE,This bit selects the adressing mode to be used in slave mode." "0: MODE7,1: MODE10"
|
|
newline
|
|
bitfld.long 0x0 14. "SOAR_OAREN,I2C Slave Own Address Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "SOAR_OAR,I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address."
|
|
line.long 0x4 "SOAR2,I2C Slave Own Address 2"
|
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hexmask.long.byte 0x4 16.--22. 1. "SOAR2_OAR2_MASK,I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address."
|
|
newline
|
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bitfld.long 0x4 7. "SOAR2_OAR2EN,I2C Slave Own Address 2 Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.byte 0x4 0.--6. 1. "SOAR2_OAR2,I2C Slave Own Address 2 This field specifies the alternate OAR2 address."
|
|
line.long 0x8 "SCTR,I2C Slave Control Register"
|
|
bitfld.long 0x8 10. "SCTR_SWUEN,Slave Wakeup Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 9. "SCTR_EN_DEFDEVADR,Enable Deault device address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 8. "SCTR_EN_ALRESPADR,Enable Alert Response Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 7. "SCTR_EN_DEFHOSTADR,Enable Default Host Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 6. "SCTR_RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 5. "SCTR_TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "SCTR_TXTRIG_TXMODE,Tx Trigger when slave FSM is in Tx Mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 3. "SCTR_TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 2. "SCTR_SCLKSTRETCH,Slave Clock Stretch Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 1. "SCTR_GENCALL,General call response enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 0. "SCTR_ACTIVE,Device Active. Setting this bit enables the slave functionality." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x125C++0x7
|
|
line.long 0x0 "SSR,I2C Slave Status Register"
|
|
hexmask.long.word 0x0 9.--18. 1. "SSR_ADDRMATCH,Indicates the address for which slave address match happened"
|
|
newline
|
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bitfld.long 0x0 8. "SSR_STALE_TXFIFO,Stale Tx FIFO" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 7. "SSR_TXMODE,Slave FSM is in TX MODE" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 6. "SSR_BUSBSY,I2C bus is busy" "0: CLEARED,1: SET"
|
|
newline
|
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rbitfld.long 0x0 5. "SSR_QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read"
|
|
newline
|
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rbitfld.long 0x0 4. "SSR_QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.."
|
|
newline
|
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rbitfld.long 0x0 3. "SSR_OAR2SEL,OAR2 Address Matched This bit gets reevaluated after every address comparison." "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "SSR_RXMODE,Slave FSM is in Rx MODE" "0: CLEARED,1: SET"
|
|
newline
|
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rbitfld.long 0x0 1. "SSR_TREQ,Transmit Request" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 0. "SSR_RREQ,Receive Request" "0: CLEARED,1: SET"
|
|
line.long 0x4 "SRXDATA,I2C Slave RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SRXDATA_VALUE,Received Data."
|
|
group.long 0x1264++0xB
|
|
line.long 0x0 "STXDATA,I2C Slave TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STXDATA_VALUE,Transmit Data"
|
|
line.long 0x4 "SACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x4 4. "SACKCTL_ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte." "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 3. "SACKCTL_ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 2. "SACKCTL_ACKOEN_ON_START,When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 1. "SACKCTL_ACKOVAL,I2C Slave ACK Override Value" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 0. "SACKCTL_ACKOEN,I2C Slave ACK Override Enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "SFIFOCTL,I2C Slave FIFO Control"
|
|
bitfld.long 0x8 15. "SFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "SFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
|
bitfld.long 0x8 7. "SFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
|
rgroup.long 0x1270++0x3
|
|
line.long 0x0 "SFIFOSR,I2C Slave FIFO Status Register"
|
|
bitfld.long 0x0 15. "SFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
|
bitfld.long 0x0 7. "SFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1274++0x3
|
|
line.long 0x0 "SLAVE_PECCTL,I2C Slave PEC control register"
|
|
bitfld.long 0x0 12. "SLAVE_PECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECCTL_PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from.."
|
|
rgroup.long 0x1278++0x3
|
|
line.long 0x0 "SLAVE_PECSR,I2C slave PEC status register"
|
|
bitfld.long 0x0 17. "SLAVE_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
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|
newline
|
|
bitfld.long 0x0 16. "SLAVE_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECSR_PECBYTECNT,This is the current PEC Byte Count of the Slave State Machine."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "I2C2"
|
|
base ad:0x400F4000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
newline
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
newline
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
newline
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
newline
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
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|
newline
|
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bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
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|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 31. "INT_EVENT0_IMASK_INTR_OVFL,Interrupt Overflow Interrupt Mask" "0: CLR,1: SET"
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|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_IMASK_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_IMASK_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_IMASK_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_IMASK_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_IMASK_SDMA_DONE_RX,Slave DMA Done on Event Channel RX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_IMASK_SDMA_DONE_TX,Slave DMA Done on Event Channel TX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_IMASK_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_IMASK_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_IMASK_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_IMASK_STXEMPTY,Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_IMASK_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an Slave RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_MSTART,START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_RIS_INTR_OVFL,Interrupt overflow interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 30. "INT_EVENT0_RIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 29. "INT_EVENT0_RIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 28. "INT_EVENT0_RIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 27. "INT_EVENT0_RIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 26. "INT_EVENT0_RIS_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "INT_EVENT0_RIS_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "INT_EVENT0_RIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 23. "INT_EVENT0_RIS_SSTOP,Stop Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 22. "INT_EVENT0_RIS_SSTART,Start Condition Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 21. "INT_EVENT0_RIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "INT_EVENT0_RIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 19. "INT_EVENT0_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 18. "INT_EVENT0_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_MRXDONE,Master Receive Transaction completed Interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 31. "INT_EVENT0_MIS_INTR_OVFL,Interrupt overflow" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 30. "INT_EVENT0_MIS_SARBLOST,Slave Arbitration Lost" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 29. "INT_EVENT0_MIS_SRX_OVFL,Slave RX FIFO overflow" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 28. "INT_EVENT0_MIS_STX_UNFL,Slave TX FIFO underflow" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 27. "INT_EVENT0_MIS_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 26. "INT_EVENT0_MIS_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 25. "INT_EVENT0_MIS_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 24. "INT_EVENT0_MIS_SGENCALL,General Call Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_MIS_SSTOP,Slave STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 22. "INT_EVENT0_MIS_SSTART,Slave START Detection Interrupt" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 21. "INT_EVENT0_MIS_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 20. "INT_EVENT0_MIS_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 17. "INT_EVENT0_MIS_STXDONE,Slave Transmit Transaction completed Interrupt" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 16. "INT_EVENT0_MIS_SRXDONE,Slave Receive Data Interrupt" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 15. "INT_EVENT0_MIS_TIMEOUTB,Timeout B Interrupt" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 14. "INT_EVENT0_MIS_TIMEOUTA,Timeout A Interrupt" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 13. "INT_EVENT0_MIS_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 12. "INT_EVENT0_MIS_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_MIS_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 10. "INT_EVENT0_MIS_MARBLOST,Arbitration Lost Interrupt" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 9. "INT_EVENT0_MIS_MSTOP,STOP Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 8. "INT_EVENT0_MIS_MSTART,START Detection Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 7. "INT_EVENT0_MIS_MNACK,Address/Data NACK Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 5. "INT_EVENT0_MIS_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_MIS_MRXFIFOFULL,RXFIFO full event. This interrupt is set if the RX FIFO is full." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT0_MIS_MTXDONE,Master Transmit Transaction completed Interrupt" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 0. "INT_EVENT0_MIS_MRXDONE,Master Receive Data Interrupt" "0: CLR,1: SET"
|
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wgroup.long 0x1040++0x3
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line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
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bitfld.long 0x0 31. "INT_EVENT0_ISET_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: SET"
|
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newline
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bitfld.long 0x0 30. "INT_EVENT0_ISET_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 29. "INT_EVENT0_ISET_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 28. "INT_EVENT0_ISET_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 27. "INT_EVENT0_ISET_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 26. "INT_EVENT0_ISET_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 25. "INT_EVENT0_ISET_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 24. "INT_EVENT0_ISET_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 23. "INT_EVENT0_ISET_SSTOP,Stop Condition Interrupt" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 22. "INT_EVENT0_ISET_SSTART,Start Condition Interrupt" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 21. "INT_EVENT0_ISET_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 20. "INT_EVENT0_ISET_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 19. "INT_EVENT0_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 18. "INT_EVENT0_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 17. "INT_EVENT0_ISET_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 16. "INT_EVENT0_ISET_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 15. "INT_EVENT0_ISET_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 14. "INT_EVENT0_ISET_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 13. "INT_EVENT0_ISET_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 12. "INT_EVENT0_ISET_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 11. "INT_EVENT0_ISET_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 10. "INT_EVENT0_ISET_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 9. "INT_EVENT0_ISET_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 8. "INT_EVENT0_ISET_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 7. "INT_EVENT0_ISET_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 5. "INT_EVENT0_ISET_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 4. "INT_EVENT0_ISET_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 3. "INT_EVENT0_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT0_ISET_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 0. "INT_EVENT0_ISET_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: SET"
|
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wgroup.long 0x1048++0x3
|
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line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
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bitfld.long 0x0 31. "INT_EVENT0_ICLR_INTR_OVFL,Interrupt overflow" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 30. "INT_EVENT0_ICLR_SARBLOST,Slave Arbitration Lost" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 29. "INT_EVENT0_ICLR_SRX_OVFL,Slave RX FIFO overflow" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 28. "INT_EVENT0_ICLR_STX_UNFL,Slave TX FIFO underflow" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 27. "INT_EVENT0_ICLR_SPEC_RX_ERR,Slave RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 26. "INT_EVENT0_ICLR_SDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 25. "INT_EVENT0_ICLR_SDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 24. "INT_EVENT0_ICLR_SGENCALL,General Call Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 23. "INT_EVENT0_ICLR_SSTOP,Slave STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 22. "INT_EVENT0_ICLR_SSTART,Slave START Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 21. "INT_EVENT0_ICLR_STXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 20. "INT_EVENT0_ICLR_SRXFIFOFULL,RXFIFO full event. This interrupt is set if an RX FIFO is full." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 19. "INT_EVENT0_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 18. "INT_EVENT0_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 17. "INT_EVENT0_ICLR_STXDONE,Slave Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 16. "INT_EVENT0_ICLR_SRXDONE,Slave Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_TIMEOUTB,Timeout B Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 14. "INT_EVENT0_ICLR_TIMEOUTA,Timeout A interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 13. "INT_EVENT0_ICLR_MPEC_RX_ERR,Master RX Pec Error Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 12. "INT_EVENT0_ICLR_MDMA_DONE_RX,DMA Done on Event Channel RX" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 11. "INT_EVENT0_ICLR_MDMA_DONE_TX,DMA Done on Event Channel TX" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 10. "INT_EVENT0_ICLR_MARBLOST,Arbitration Lost Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 9. "INT_EVENT0_ICLR_MSTOP,STOP Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 8. "INT_EVENT0_ICLR_MSTART,START Detection Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 7. "INT_EVENT0_ICLR_MNACK,Address/Data NACK Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 5. "INT_EVENT0_ICLR_MTXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode." "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 4. "INT_EVENT0_ICLR_MRXFIFOFULL,RXFIFO full event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 3. "INT_EVENT0_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT0_ICLR_MTXDONE,Master Transmit Transaction completed Interrupt" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 0. "INT_EVENT0_ICLR_MRXDONE,Master Receive Data Interrupt" "0: NO_EFFECT,1: CLR"
|
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rgroup.long 0x1050++0x3
|
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line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
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group.long 0x1058++0x3
|
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line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
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bitfld.long 0x0 3. "INT_EVENT1_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 2. "INT_EVENT1_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 1. "INT_EVENT1_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 0. "INT_EVENT1_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
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rgroup.long 0x1060++0x3
|
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line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
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bitfld.long 0x0 3. "INT_EVENT1_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 2. "INT_EVENT1_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT1_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 0. "INT_EVENT1_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
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rgroup.long 0x1068++0x3
|
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line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
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bitfld.long 0x0 3. "INT_EVENT1_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 2. "INT_EVENT1_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 1. "INT_EVENT1_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 0. "INT_EVENT1_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
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wgroup.long 0x1070++0x3
|
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line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
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bitfld.long 0x0 3. "INT_EVENT1_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 2. "INT_EVENT1_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 1. "INT_EVENT1_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 0. "INT_EVENT1_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
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bitfld.long 0x0 3. "INT_EVENT1_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 2. "INT_EVENT1_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 1. "INT_EVENT1_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
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newline
|
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bitfld.long 0x0 0. "INT_EVENT1_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
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|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
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bitfld.long 0x0 3. "INT_EVENT2_IMASK_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 2. "INT_EVENT2_IMASK_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 1. "INT_EVENT2_IMASK_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 0. "INT_EVENT2_IMASK_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_RIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT2_RIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_RIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 0. "INT_EVENT2_RIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT2_MIS_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_MIS_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_MIS_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_MIS_MRXFIFOTRG,Master Receive FIFO Trigger" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ISET_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_ISET_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT2_ISET_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT2_ISET_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT2_ICLR_STXFIFOTRG,Slave Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT2_ICLR_SRXFIFOTRG,Slave Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT2_ICLR_MTXFIFOTRG,Master Transmit FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT2_ICLR_MRXFIFOTRG,Master Receive FIFO Trigger" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
newline
|
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hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
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|
newline
|
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hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1200++0x7
|
|
line.long 0x0 "GFCTL,I2C Glitch Filter Control"
|
|
bitfld.long 0x0 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
newline
|
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bitfld.long 0x0 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 0.--2. "GFCTL_DGFSEL,Glitch Suppression Pulse Width" "0: DISABLED,1: CLK_1,2: CLK_2,3: CLK_3,4: CLK_4,5: CLK_8,6: CLK_16,7: CLK_31"
|
|
line.long 0x4 "TIMEOUT_CTL,I2C Timeout Count Control Register"
|
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bitfld.long 0x4 31. "TIMEOUT_CTL_TCNTBEN,Timeout Counter B Enable" "0: DISABLE,1: ENABLE"
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newline
|
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hexmask.long.byte 0x4 16.--23. 1. "TIMEOUT_CTL_TCNTLB,Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h."
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|
newline
|
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bitfld.long 0x4 15. "TIMEOUT_CTL_TCNTAEN,Timeout Counter A Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.byte 0x4 0.--7. 1. "TIMEOUT_CTL_TCNTLA,Timeout counter A load value"
|
|
rgroup.long 0x1208++0x3
|
|
line.long 0x0 "TIMEOUT_CNT,I2C Timeout Count Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "TIMEOUT_CNT_TCNTB,Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TIMEOUT_CNT_TCNTA,Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"
|
|
group.long 0x1210++0x7
|
|
line.long 0x0 "MSA,I2C Master Slave Address Register"
|
|
bitfld.long 0x0 15. "MSA_MMODE,This bit selects the adressing mode to be used in master mode" "0: MODE7,1: MODE10"
|
|
newline
|
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hexmask.long.word 0x0 1.--10. 1. "MSA_SADDR,I2C Slave Address This field specifies bits A9 through A0 of the slave address."
|
|
newline
|
|
bitfld.long 0x0 0. "MSA_DIR,Receive/Send" "0: TRANSMIT,1: RECEIVE"
|
|
line.long 0x4 "MCTR,I2C Master Control Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "MCTR_MBLEN,I2C transaction length"
|
|
newline
|
|
bitfld.long 0x4 5. "MCTR_RD_ON_TXEMPTY,Read on TX Empty" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4. "MCTR_MACKOEN,Master ACK overrride Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 3. "MCTR_ACK,Data Acknowledge Enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "MCTR_STOP,Generate STOP" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "MCTR_START,Generate START" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "MCTR_BURSTRUN,I2C Master Enable and start transaction" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1218++0x7
|
|
line.long 0x0 "MSR,I2C Master Status Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "MSR_MBCNT,I2C Master Transaction Count"
|
|
newline
|
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bitfld.long 0x0 6. "MSR_BUSBSY,I2C Bus is Busy" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 5. "MSR_IDLE,I2C Idle" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 4. "MSR_ARBLST,Arbitration Lost" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 3. "MSR_DATACK,Acknowledge Data" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "MSR_ADRACK,Acknowledge Address" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MSR_ERR,Error" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "MSR_BUSY,I2C Master FSM Busy" "0: CLEARED,1: SET"
|
|
line.long 0x4 "MRXDATA,I2C Master RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MRXDATA_VALUE,Received Data."
|
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group.long 0x1220++0xB
|
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line.long 0x0 "MTXDATA,I2C Master TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MTXDATA_VALUE,Transmit Data"
|
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line.long 0x4 "MTPR,I2C Master Timer Period"
|
|
hexmask.long.byte 0x4 0.--6. 1. "MTPR_TPR,Timer Period"
|
|
line.long 0x8 "MCR,I2C Master Configuration"
|
|
bitfld.long 0x8 8. "MCR_LPBK,I2C Loopback" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 2. "MCR_CLKSTRETCH,Clock Stretching. This bit controls the support for clock stretching of the I2C bus." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 1. "MCR_MMST,Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x8 0. "MCR_ACTIVE,Device Active After this bit has been set it should not be set again unless it has been cleared by writing a 0 or by a reset otherwise transfer failures may occur." "0: DISABLE,1: ENABLE"
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rgroup.long 0x1234++0x3
|
|
line.long 0x0 "MBMON,I2C Master Bus Monitor"
|
|
bitfld.long 0x0 1. "MBMON_SDA,I2C SDA Status" "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "MBMON_SCL,I2C SCL Status" "0: CLEARED,1: SET"
|
|
group.long 0x1238++0x3
|
|
line.long 0x0 "MFIFOCTL,I2C Master FIFO Control"
|
|
bitfld.long 0x0 15. "MFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
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bitfld.long 0x0 8.--10. "MFIFOCTL_RXTRIG,RX FIFO Trigger" "0: LEVEL_1,1: LEVEL_2,2: LEVEL_3,3: LEVEL_4,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
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bitfld.long 0x0 7. "MFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
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bitfld.long 0x0 0.--2. "MFIFOCTL_TXTRIG,TX FIFO Trigger" "0: EMPTY,1: LEVEL_1,2: LEVEL_2,3: LEVEL_3,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
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rgroup.long 0x123C++0x3
|
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line.long 0x0 "MFIFOSR,I2C Master FIFO Status Register"
|
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bitfld.long 0x0 15. "MFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
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newline
|
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hexmask.long.byte 0x0 8.--11. 1. "MFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
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bitfld.long 0x0 7. "MFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "MFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
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group.long 0x1240++0x3
|
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line.long 0x0 "MASTER_I2CPECCTL,I2C master PEC control register"
|
|
bitfld.long 0x0 12. "MASTER_I2CPECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "MASTER_I2CPECCTL_PECCNT,PEC Count"
|
|
rgroup.long 0x1244++0x3
|
|
line.long 0x0 "MASTER_PECSR,I2C master PEC status register"
|
|
bitfld.long 0x0 17. "MASTER_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 16. "MASTER_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "MASTER_PECSR_PECBYTECNT,PEC Byte Count"
|
|
group.long 0x1250++0xB
|
|
line.long 0x0 "SOAR,I2C Slave Own Address"
|
|
bitfld.long 0x0 15. "SOAR_SMODE,This bit selects the adressing mode to be used in slave mode." "0: MODE7,1: MODE10"
|
|
newline
|
|
bitfld.long 0x0 14. "SOAR_OAREN,I2C Slave Own Address Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--9. 1. "SOAR_OAR,I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address."
|
|
line.long 0x4 "SOAR2,I2C Slave Own Address 2"
|
|
hexmask.long.byte 0x4 16.--22. 1. "SOAR2_OAR2_MASK,I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address."
|
|
newline
|
|
bitfld.long 0x4 7. "SOAR2_OAR2EN,I2C Slave Own Address 2 Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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hexmask.long.byte 0x4 0.--6. 1. "SOAR2_OAR2,I2C Slave Own Address 2 This field specifies the alternate OAR2 address."
|
|
line.long 0x8 "SCTR,I2C Slave Control Register"
|
|
bitfld.long 0x8 10. "SCTR_SWUEN,Slave Wakeup Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 9. "SCTR_EN_DEFDEVADR,Enable Deault device address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 8. "SCTR_EN_ALRESPADR,Enable Alert Response Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 7. "SCTR_EN_DEFHOSTADR,Enable Default Host Address" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 6. "SCTR_RXFULL_ON_RREQ,Rx full interrupt generated on RREQ condition as indicated in SSR" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 5. "SCTR_TXWAIT_STALE_TXFIFO,Tx transfer waits when stale data in Tx FIFO." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "SCTR_TXTRIG_TXMODE,Tx Trigger when slave FSM is in Tx Mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 3. "SCTR_TXEMPTY_ON_TREQ,Tx Empty Interrupt on TREQ" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 2. "SCTR_SCLKSTRETCH,Slave Clock Stretch Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "SCTR_GENCALL,General call response enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 0. "SCTR_ACTIVE,Device Active. Setting this bit enables the slave functionality." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x125C++0x7
|
|
line.long 0x0 "SSR,I2C Slave Status Register"
|
|
hexmask.long.word 0x0 9.--18. 1. "SSR_ADDRMATCH,Indicates the address for which slave address match happened"
|
|
newline
|
|
bitfld.long 0x0 8. "SSR_STALE_TXFIFO,Stale Tx FIFO" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "SSR_TXMODE,Slave FSM is in TX MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "SSR_BUSBSY,I2C bus is busy" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 5. "SSR_QCMDRW,Quick Command Read / Write" "0: Quick command was a write,1: Quick command was a read"
|
|
newline
|
|
rbitfld.long 0x0 4. "SSR_QCMDST,Quick Command Status" "0: The last transaction was a normal transaction or..,1: The last transaction was a Quick Command.."
|
|
newline
|
|
rbitfld.long 0x0 3. "SSR_OAR2SEL,OAR2 Address Matched This bit gets reevaluated after every address comparison." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "SSR_RXMODE,Slave FSM is in Rx MODE" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 1. "SSR_TREQ,Transmit Request" "0: CLEARED,1: SET"
|
|
newline
|
|
rbitfld.long 0x0 0. "SSR_RREQ,Receive Request" "0: CLEARED,1: SET"
|
|
line.long 0x4 "SRXDATA,I2C Slave RXData"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SRXDATA_VALUE,Received Data."
|
|
group.long 0x1264++0xB
|
|
line.long 0x0 "STXDATA,I2C Slave TXData"
|
|
hexmask.long.byte 0x0 0.--7. 1. "STXDATA_VALUE,Transmit Data"
|
|
line.long 0x4 "SACKCTL,I2C Slave ACK Control"
|
|
bitfld.long 0x4 4. "SACKCTL_ACKOEN_ON_PECDONE,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "SACKCTL_ACKOEN_ON_PECNEXT,When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "SACKCTL_ACKOEN_ON_START,When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "SACKCTL_ACKOVAL,I2C Slave ACK Override Value" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "SACKCTL_ACKOEN,I2C Slave ACK Override Enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "SFIFOCTL,I2C Slave FIFO Control"
|
|
bitfld.long 0x8 15. "SFIFOCTL_RXFLUSH,RX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "SFIFOCTL_RXTRIG,RX FIFO Trigger" "?,?,?,?,4: LEVEL_5,5: LEVEL_6,6: LEVEL_7,7: LEVEL_8"
|
|
newline
|
|
bitfld.long 0x8 7. "SFIFOCTL_TXFLUSH,TX FIFO Flush" "0: NOFLUSH,1: FLUSH"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SFIFOCTL_TXTRIG,TX FIFO Trigger" "?,?,?,?,4: LEVEL_4,5: LEVEL_5,6: LEVEL_6,7: LEVEL_7"
|
|
rgroup.long 0x1270++0x3
|
|
line.long 0x0 "SFIFOSR,I2C Slave FIFO Status Register"
|
|
bitfld.long 0x0 15. "SFIFOSR_TXFLUSH,TX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SFIFOSR_TXFIFOCNT,Number of Bytes which could be put into the TX FIFO"
|
|
newline
|
|
bitfld.long 0x0 7. "SFIFOSR_RXFLUSH,RX FIFO Flush" "0: INACTIVE,1: ACTIVE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SFIFOSR_RXFIFOCNT,Number of Bytes which could be read from the RX FIFO"
|
|
group.long 0x1274++0x3
|
|
line.long 0x0 "SLAVE_PECCTL,I2C Slave PEC control register"
|
|
bitfld.long 0x0 12. "SLAVE_PECCTL_PECEN,PEC Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECCTL_PECCNT,When this field is non zero the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting the contents of the LSFR is loaded into the shift register instead of the byte received from.."
|
|
rgroup.long 0x1278++0x3
|
|
line.long 0x0 "SLAVE_PECSR,I2C slave PEC status register"
|
|
bitfld.long 0x0 17. "SLAVE_PECSR_PECSTS_ERROR,This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "SLAVE_PECSR_PECSTS_CHECK,This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop." "0: CLEARED,1: SET"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLAVE_PECSR_PECBYTECNT,This is the current PEC Byte Count of the Slave State Machine."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "IOMUX (I/O Multiplexer)"
|
|
base ad:0x40428000
|
|
repeat 61. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "PINCM[$1],Pin Control Management Register in SECCFG region"
|
|
bitfld.long 0x0 28. "PINCM_WCOMP,Wakeup Compare Value bit" "0: MATCH0,1: MATCH1"
|
|
bitfld.long 0x0 27. "PINCM_WUEN,Wakeup Enable bit" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 26. "PINCM_INV,Data inversion selection" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 25. "PINCM_HIZ1,High output value will tri-state the output when this bit is enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 20. "PINCM_DRV,Drive strength control selection for HS IOCELL only" "0: DRVVAL0,1: DRVVAL1"
|
|
newline
|
|
bitfld.long 0x0 19. "PINCM_HYSTEN,Hysteresis Enable Control Selection" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 18. "PINCM_INENA,Input Enable Control Selection" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 17. "PINCM_PIPU,Pull Up control selection" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 16. "PINCM_PIPD,Pull Down control selection" "0: DISABLE,1: ENABLE"
|
|
rbitfld.long 0x0 13. "PINCM_WAKESTAT,This has the IOPAD WAKEUP signal as status bit." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 7. "PINCM_PC,Peripheral is Connected" "0: UNCONNECTED,1: CONNECTED"
|
|
hexmask.long.byte 0x0 0.--5. 1. "PINCM_PF,Peripheral Function selection bits"
|
|
repeat.end
|
|
tree.end
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "KEYSTORECTL"
|
|
base ad:0x400AC000
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CFG,Keystore configuration"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG_NK256,Number of 256 bit keys to be held in the key-store."
|
|
line.long 0x4 "KEYWR,Key write configuration"
|
|
hexmask.long.byte 0x4 4.--7. 1. "KEYWR_KEYSLOTSEL,Select the key slot to write the key into."
|
|
bitfld.long 0x4 0.--2. "KEYWR_KEYSZSEL,Key size selection. Selection of 128 or 256 bit keys" "0: K256,1: K128,?,?,?,?,?,?"
|
|
line.long 0x8 "KEYRD,Key read configuration"
|
|
bitfld.long 0x8 8.--9. "KEYRD_CRYPTOSEL,Crypto engine selector" "0: AES,?,?,?"
|
|
hexmask.long.byte 0x8 4.--7. 1. "KEYRD_KEYSLOTSEL,Select the key slot to read the key from."
|
|
bitfld.long 0x8 0.--2. "KEYRD_KEYSZSEL,Key size selection. Selection of 128 or 256 bit keys" "0: K256,1: K128,?,?,?,?,?,?"
|
|
rgroup.long 0x110C++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
rbitfld.long 0x0 16.--17. "STATUS_NKEYSLOTS,Size of keystorage: Number of 128-bit key slots" "0: TWO,1: THREE,2: FOUR,?"
|
|
hexmask.long.byte 0x0 4.--11. 1. "STATUS_VALID,Bitvector of valid bits to indicate which slots have been configured"
|
|
hexmask.long.byte 0x0 0.--3. 1. "STATUS_STAT,Status information"
|
|
wgroup.long 0x1110++0x3
|
|
line.long 0x0 "KEYIN,Input key"
|
|
hexmask.long 0x0 0.--31. 1. "KEYIN_DATA,32-bit key data"
|
|
tree.end
|
|
tree "LCD"
|
|
base ad:0x40070000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,LCD Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 2. "IMASK_BLKON,Blinkking segments on." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_BLKOFF,Blinking segments off." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "IMASK_FRMSTART,Start of new LCD frame." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 2. "RIS_BLKON,Blinking segments turned on." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_BLKOFF,Blinking segments turned off interrupt flag." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "RIS_FRMSTART,Set in start of a new frame." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 2. "MIS_BLKON,Masked BLKON interrupt flag" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_BLKOFF,Masked BLKOFF interrupt flag" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "MIS_FRMSTART,Master FRMSTART interrupt flag" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 2. "ISET_BLKON,Set BLKON RIS flag" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_BLKOFF,Set BLKOFF RIS flag" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "ISET_FRMSTART,Set FRMSTART RIS flag." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 2. "ICLR_BLKON,Clear BLKON RIS flag" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_BLKOFF,Clear BLKOFF RIS flag" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "ICLR_FRMSTART,Clear FRMSTART RIS flag" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "LCDCTL0,LCD control register 0"
|
|
bitfld.long 0x0 24. "LCDCTL0_LCDSYNCEXT,LCDSYNCEXT" "0: LCD_EXT_SYNC_OFF,1: LCD_EXT_SYNC_ON"
|
|
hexmask.long.byte 0x0 11.--15. 1. "LCDCTL0_LCDDIVX,LCD frequency divider. Together with LCDMXx the LCD frequency fLCD is calculated as fLCD = fSOURCE / ((LCDDIVx + 1) * Value[LCDMXx]). Change only while LCDON = 0. 00000b = Divide by 1 00001b = Divide by 2 . 11110b = Divide by 31 11111b.."
|
|
bitfld.long 0x0 3.--5. "LCDCTL0_LCDMXX,LCD mux rate. These bits select the LCD mode. Change only while LCDON = 0. 000b = Static 001b = 2-mux 010b = 3-mux 011b = 4-mux 100b = 5-mux 101b = 6-mux 110b = 7-mux 111b = 8-mux" "0: MX_STATIC,1: MX_2,2: MX_3,3: MX_4,4: MX_5,5: MX_6,6: MX_7,7: MX_8"
|
|
newline
|
|
bitfld.long 0x0 2. "LCDCTL0_LCDSON,LCD segments on. This bit supports flashing LCD applications by turning off all segment lines while leaving the LCD timing generator and R33 enabled. 0b = All LCD segments are off. 1b = All LCD segments are enabled and on or off.." "0: LCD_SEG_OFF,1: LCD_SEG_ON"
|
|
bitfld.long 0x0 1. "LCDCTL0_LCDLP,LCD low-power waveform. This bit is only applicable for 1/3 bias mode that is for LCDBIASSEL = 0. 0b = Standard LCD waveforms on segment and common lines selected. 1b = Low-power LCD waveforms on segment and common lines selected." "0: STD_LCD,1: LP_LCD"
|
|
bitfld.long 0x0 0. "LCDCTL0_LCDON,LCD on. This bit turns the LCD module on or off. 0b = LCD module off 1b = LCD module on" "0: LCD_MOD_DISABLE,1: LCD_MOD_ENABLE"
|
|
group.long 0x1108++0x1B
|
|
line.long 0x0 "LCDBLKCTL,LCD blicking control register"
|
|
bitfld.long 0x0 2.--4. "LCDBLKCTL_LCDBLKPREX,Clock prescaler for blinking frequency." "0: DIV_BY_2,1: DIV_BY_4,2: DIV_BY_8,3: DIV_BY_16,4: DIV_BY_32,5: DIV_BY_64,6: DIV_BY_128,7: DIV_BY_256"
|
|
bitfld.long 0x0 0.--1. "LCDBLKCTL_LCDBLKMODX,Blinking mode 00b = Blinking disabled. 01b = Blinking of individual segments as enabled in blinking memory register LCDBMx. In mux mode >5 blinking is disabled. 10b = Blinking of all segments 11b = Switching between display.." "0: BLINK_DISABLE,1: BLINK_SELECED,2: BLINK_ALL,3: BKINK_TOGGLE"
|
|
line.long 0x4 "LCDMEMCTL,LCD memory control LCD memory control register"
|
|
bitfld.long 0x4 2. "LCDMEMCTL_LCDCLRBM,Clear LCD blinking memory Clears all blinking memory registers LCDBMx. The bit is automatically reset when the blinking memory is cleared. Setting this bit in 5-mux mode and above has no effect. It is immediately reset again. 0b =.." "0: NO_CLR_BLNK_MEM_REGS,1: CLR_BLNK_MEM_REGS"
|
|
bitfld.long 0x4 1. "LCDMEMCTL_LCDCLRM,Clear LCD memory Clears all LCD memory registers LCDMx. The bit is automatically reset when the LCD memory is cleared. 0b = Contents of LCD memory registers LCDMx remain unchanged 1b = Clear content of all LCD memory registers LCDMx" "0: NO_CLR_LCD_MEM_REGS,1: CLR_LCD_MEM_REGS"
|
|
bitfld.long 0x4 0. "LCDMEMCTL_LCDDISP,Select LCD memory registers for display When LCDBLKMODx = 00 LCDDISP can be set by software. The bit is cleared in LCDBLKMODx = 01 and LCDBLKMODx = 10 or if a mux mode =5 is selected and cannot be changed by software. When LCDBLKMODx.." "0: SEL_LCD_MEM_REGS,1: SEL_BLNK_MEM_REGS"
|
|
line.long 0x8 "LCDVCTL,LCD voltage control register"
|
|
bitfld.long 0x8 24. "LCDVCTL_LCDVBSTEN,Enables the voltage boost circuitry which provides a boosted VDDA voltage. This boosted voltage is to be used in the switch controls when the VDDA supply is less than 1.6V." "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0x8 12.--15. 1. "LCDVCTL_LCDCPFSELX,Charge pump frequency selection. 0000b = 32.768 kHz / 1 / 8 = 4.096 kHz 0001b = 32.768 kHz / 2 / 8 = 2.048 kHz 0010b = 32.768 kHz / 3 / 8 = 1.365 kHz 0011b = 32.768 kHz / 4 / 8 = 1.024 kHz 0100b = 32.768 kHz / 5 / 8 = 819 Hz 0101b =.."
|
|
hexmask.long.byte 0x8 8.--11. 1. "LCDVCTL_VLCDX,Internal reference voltage select on R13."
|
|
newline
|
|
bitfld.long 0x8 7. "LCDVCTL_LCDCPEN,Charge pump enable 0b = Charge pump disabled(1) 1b = Charge pump enabled when VLCD is generated internally (VLCDEXT = 0) and VLCDx > 0 or VLCDREFx > 0." "0: CP_DISABLE,1: CP_ENABLE"
|
|
bitfld.long 0x8 6. "LCDVCTL_LCDREFEN,Internal reference voltage enable on R13 0b = Internal reference voltage disabled 1b = Internal reference voltage enabled" "0: INT_REF_DISABLE,1: INT_REF_ENABLE"
|
|
bitfld.long 0x8 5. "LCDVCTL_LCDSELVDD,Selects if R33 is supplied either from AVDD internally or from charge pump 0b = R33 connected to external supply 1b = R33 internally connected to AVDD" "0: SEL_EXT_SUPPLY,1: SEL_AVDD"
|
|
newline
|
|
bitfld.long 0x8 4. "LCDVCTL_LCD_HP_LP,High-power or Low-power LCD. This bit is only effective when the internal bias voltage resistor divider is used that is when LCDINTBIASEN = 1. It selects the resistor ladder that is used to generate the bias voltages for the LCD. 0b.." "0: LP_MODE,1: HP_MODE"
|
|
bitfld.long 0x8 3. "LCDVCTL_VLCDSEL_VDD_R33,Selects if the LCD bias voltage V1 is sourced from the R33 pin or from the internal supply voltage AVDD This bit is only effective when the internal bias voltage resistor divider is used that is when LCDINTBIASEN = 1 0b = V1 is.." "0: SEL_R33,1: SEL_AVDD"
|
|
bitfld.long 0x8 2. "LCDVCTL_LCDINTBIASEN,Enables the internal bias voltage resistor divider. The actual voltage source used for the resistor divider is selected by the VLCDSEL_VDD_R33 bit configuration. 0b = Internal bias voltage resistor divider is disabled 1b = Internal.." "0: INT_BIAS_DISABLE,1: INT_BIAS_ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "LCDVCTL_LCDBIASSEL,Bias select. LCDBIASSEL is ignored in static mode as well as for 2-mux 3-mux and 4-mux LCD modes. For 5-mux to 8-mux modes: 0b = 1/3 bias 1b = 1/4 bias" "0: ONE_BY_3_BIAS,1: ONE_BY_4_BIAS"
|
|
bitfld.long 0x8 0. "LCDVCTL_LCDREFMODE,Selects whether R13 voltage is switched or in static mode 0b = Static mode 1b = Switched mode" "0: STATIC_MODE,1: SWITCHED_MODE"
|
|
line.long 0xC "LCDPCTL0,LCD port control register 0"
|
|
bitfld.long 0xC 15. "LCDPCTL0_LCDS15,LCD pin 15 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0xC 14. "LCDPCTL0_LCDS14,LCD pin 14 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0xC 13. "LCDPCTL0_LCDS13,LCD pin 13 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
newline
|
|
bitfld.long 0xC 12. "LCDPCTL0_LCDS12,LCD pin 12 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0xC 11. "LCDPCTL0_LCDS11,LCD pin 11 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0xC 10. "LCDPCTL0_LCDS10,LCD pin 10 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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|
newline
|
|
bitfld.long 0xC 9. "LCDPCTL0_LCDS9,LCD pin 9 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0xC 8. "LCDPCTL0_LCDS8,LCD pin 8 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0xC 7. "LCDPCTL0_LCDS7,LCD pin 7 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
newline
|
|
bitfld.long 0xC 6. "LCDPCTL0_LCDS6,LCD pin 6 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0xC 5. "LCDPCTL0_LCDS5,LCD pin 5 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0xC 4. "LCDPCTL0_LCDS4,LCD pin 4 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
newline
|
|
bitfld.long 0xC 3. "LCDPCTL0_LCDS3,LCD pin 3 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0xC 2. "LCDPCTL0_LCDS2,LCD pin 2 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0xC 1. "LCDPCTL0_LCDS1,LCD pin 1 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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|
newline
|
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bitfld.long 0xC 0. "LCDPCTL0_LCDS0,LCD pin 0 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
line.long 0x10 "LCDPCTL1,LCD port control register 1"
|
|
bitfld.long 0x10 15. "LCDPCTL1_LCDS31,LCD pin 31 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0x10 14. "LCDPCTL1_LCDS30,LCD pin 30 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0x10 13. "LCDPCTL1_LCDS29,LCD pin 29 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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|
newline
|
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bitfld.long 0x10 12. "LCDPCTL1_LCDS28,LCD pin 28 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0x10 11. "LCDPCTL1_LCDS27,LCD pin 27 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0x10 10. "LCDPCTL1_LCDS26,LCD pin 26 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x10 9. "LCDPCTL1_LCDS25,LCD pin 25 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0x10 8. "LCDPCTL1_LCDS24,LCD pin 24 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0x10 7. "LCDPCTL1_LCDS23,LCD segment line 23 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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|
newline
|
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bitfld.long 0x10 6. "LCDPCTL1_LCDS22,LCD segment line 22 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0x10 5. "LCDPCTL1_LCDS21,LCD segment line 21 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
|
|
bitfld.long 0x10 4. "LCDPCTL1_LCDS20,LCD segment line 20 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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|
newline
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bitfld.long 0x10 3. "LCDPCTL1_LCDS19,LCD segment line 19 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x10 2. "LCDPCTL1_LCDS18,LCD segment line 18 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x10 1. "LCDPCTL1_LCDS17,LCD segment line 17 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x10 0. "LCDPCTL1_LCDS16,LCD segment line 16 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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line.long 0x14 "LCDPCTL2,LCD port control register 2"
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bitfld.long 0x14 15. "LCDPCTL2_LCDS47,LCD pin 47 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x14 14. "LCDPCTL2_LCDS46,LCD pin 46 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x14 13. "LCDPCTL2_LCDS45,LCD pin 45 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x14 12. "LCDPCTL2_LCDS44,LCD pin 44 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x14 11. "LCDPCTL2_LCDS43,LCD pin 43 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x14 10. "LCDPCTL2_LCDS42,LCD pin 42 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x14 9. "LCDPCTL2_LCDS41,LCD pin 41 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x14 8. "LCDPCTL2_LCDS40,LCD pin 40 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x14 7. "LCDPCTL2_LCDS39,LCD pin 39 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x14 6. "LCDPCTL2_LCDS38,LCD pin 38 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x14 5. "LCDPCTL2_LCDS37,LCD pin 37 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x14 4. "LCDPCTL2_LCDS36,LCD pin 36 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x14 3. "LCDPCTL2_LCDS35,LCD pin 35 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x14 2. "LCDPCTL2_LCDS34,LCD pin 34 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x14 1. "LCDPCTL2_LCDS33,LCD pin 33 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x14 0. "LCDPCTL2_LCDS32,LCD pin 32 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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line.long 0x18 "LCDPCTL3,LCD port control register 3"
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bitfld.long 0x18 15. "LCDPCTL3_LCDS63,LCD pin 63 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x18 14. "LCDPCTL3_LCDS62,LCD pin 62 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x18 13. "LCDPCTL3_LCDS61,LCD pin 61 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x18 12. "LCDPCTL3_LCDS60,LCD pin 60 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x18 11. "LCDPCTL3_LCDS59,LCD pin 59 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x18 10. "LCDPCTL3_LCDS58,LCD pin 58 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x18 9. "LCDPCTL3_LCDS57,LCD pin 57 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x18 8. "LCDPCTL3_LCDS56,LCD pin 56 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x18 7. "LCDPCTL3_LCDS55,LCD pin 55 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x18 6. "LCDPCTL3_LCDS54,LCD pin 54 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x18 5. "LCDPCTL3_LCDS53,LCD pin 53 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x18 4. "LCDPCTL3_LCDS52,LCD pin 52 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x18 3. "LCDPCTL3_LCDS51,LCD pin 51 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x18 2. "LCDPCTL3_LCDS50,LCD pin 50 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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bitfld.long 0x18 1. "LCDPCTL3_LCDS49,LCD pin 49 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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newline
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bitfld.long 0x18 0. "LCDPCTL3_LCDS48,LCD pin 48 enable. This bit affects only pins with multiplexed functions. Dedicated LCD pins are always LCD function. 0b = Multiplexed pins are port functions. 1b = Pins are LCD functions." "0: SEL_PORT,1: SEL_LCD"
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group.long 0x1128++0xF
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line.long 0x0 "LCDCSSEL0,LCD common segment select register 0"
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bitfld.long 0x0 15. "LCDCSSEL0_LCDCSS15,Selects pin L15 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x0 14. "LCDCSSEL0_LCDCSS14,Selects pin L14 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x0 13. "LCDCSSEL0_LCDCSS13,Selects pin L13 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x0 12. "LCDCSSEL0_LCDCSS12,Selects pin L12 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x0 11. "LCDCSSEL0_LCDCSS11,Selects pin L11 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x0 10. "LCDCSSEL0_LCDCSS10,Selects pin L10 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x0 9. "LCDCSSEL0_LCDCSS9,Selects pin L9 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x0 8. "LCDCSSEL0_LCDCSS8,Selects pin L8 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x0 7. "LCDCSSEL0_LCDCSS7,Selects pin L7 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x0 6. "LCDCSSEL0_LCDCSS6,Selects pin L6 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x0 5. "LCDCSSEL0_LCDCSS5,Selects pin L5 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x0 4. "LCDCSSEL0_LCDCSS4,Selects pin L4 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x0 3. "LCDCSSEL0_LCDCSS3,Selects pin L3 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x0 2. "LCDCSSEL0_LCDCSS2,Selects pin L2 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x0 1. "LCDCSSEL0_LCDCSS1,Selects pin L1 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x0 0. "LCDCSSEL0_LCDCSS0,Selects pin L0 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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line.long 0x4 "LCDCSSEL1,LCD common segment select register 1"
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bitfld.long 0x4 15. "LCDCSSEL1_LCDCSS31,Selects pin L31 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x4 14. "LCDCSSEL1_LCDCSS30,Selects pin L30 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x4 13. "LCDCSSEL1_LCDCSS29,Selects pin L29 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x4 12. "LCDCSSEL1_LCDCSS28,Selects pin L28 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x4 11. "LCDCSSEL1_LCDCSS27,Selects pin L27 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x4 10. "LCDCSSEL1_LCDCSS26,Selects pin L26 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x4 9. "LCDCSSEL1_LCDCSS25,Selects pin L25 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x4 8. "LCDCSSEL1_LCDCSS24,Selects pin L24 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x4 7. "LCDCSSEL1_LCDCSS23,Selects pin L23 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x4 6. "LCDCSSEL1_LCDCSS22,Selects pin L22 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x4 5. "LCDCSSEL1_LCDCSS21,Selects pin L21 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x4 4. "LCDCSSEL1_LCDCSS20,Selects pin L20 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x4 3. "LCDCSSEL1_LCDCSS19,Selects pin L19 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x4 2. "LCDCSSEL1_LCDCSS18,Selects pin L18 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x4 1. "LCDCSSEL1_LCDCSS17,Selects pin L17 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x4 0. "LCDCSSEL1_LCDCSS16,Selects pin L16 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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line.long 0x8 "LCDCSSEL2,LCD common segment select register 2"
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bitfld.long 0x8 15. "LCDCSSEL2_LCDCSS47,Selects pin L47 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x8 14. "LCDCSSEL2_LCDCSS46,Selects pin L46 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x8 13. "LCDCSSEL2_LCDCSS45,Selects pin L45 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x8 12. "LCDCSSEL2_LCDCSS44,Selects pin L44 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x8 11. "LCDCSSEL2_LCDCSS43,Selects pin L43 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x8 10. "LCDCSSEL2_LCDCSS42,Selects pin L42 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x8 9. "LCDCSSEL2_LCDCSS41,Selects pin L41 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x8 8. "LCDCSSEL2_LCDCSS40,Selects pin L40 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x8 7. "LCDCSSEL2_LCDCSS39,Selects pin L39 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x8 6. "LCDCSSEL2_LCDCSS38,Selects pin L38 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x8 5. "LCDCSSEL2_LCDCSS37,Selects pin L37 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x8 4. "LCDCSSEL2_LCDCSS36,Selects pin L36 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x8 3. "LCDCSSEL2_LCDCSS35,Selects pin L35 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x8 2. "LCDCSSEL2_LCDCSS34,Selects pin L34 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0x8 1. "LCDCSSEL2_LCDCSS33,Selects pin L33 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0x8 0. "LCDCSSEL2_LCDCSS32,Selects pin L32 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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line.long 0xC "LCDCSSEL3,LCD common segment select register 3"
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bitfld.long 0xC 15. "LCDCSSEL3_LCDCSS63,Selects pin L63 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0xC 14. "LCDCSSEL3_LCDCSS62,Selects pin L62 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0xC 13. "LCDCSSEL3_LCDCSS61,Selects pin L61 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0xC 12. "LCDCSSEL3_LCDCSS60,Selects pin L60 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0xC 11. "LCDCSSEL3_LCDCSS59,Selects pin L59 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0xC 10. "LCDCSSEL3_LCDCSS58,Selects pin L58 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0xC 9. "LCDCSSEL3_LCDCSS57,Selects pin L57 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0xC 8. "LCDCSSEL3_LCDCSS56,Selects pin L56 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0xC 7. "LCDCSSEL3_LCDCSS55,Selects pin L55 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0xC 6. "LCDCSSEL3_LCDCSS54,Selects pin L54 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0xC 5. "LCDCSSEL3_LCDCSS53,Selects pin L53 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0xC 4. "LCDCSSEL3_LCDCSS52,Selects pin L52 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
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bitfld.long 0xC 3. "LCDCSSEL3_LCDCSS51,Selects pin L51 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0xC 2. "LCDCSSEL3_LCDCSS50,Selects pin L50 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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bitfld.long 0xC 1. "LCDCSSEL3_LCDCSS49,Selects pin L49 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
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newline
|
|
bitfld.long 0xC 0. "LCDCSSEL3_LCDCSS48,Selects pin L48 as either common or segment line. 0b = Segment line 1b = Common line" "0: SEL_SEG,1: SEL_COM"
|
|
repeat 64. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x1140)++0x0
|
|
line.byte 0x0 "LCDM[$1],LCD memory index register"
|
|
bitfld.byte 0x0 7. "LCDM_MBIT7,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 4-mux (LCDMXx=011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line (LCDCSS[2*index+1] = 1b): 0b =.." "0: OFF,1: ON"
|
|
bitfld.byte 0x0 6. "LCDM_MBIT6,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 3- or 4-mux (010b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line.." "0,1"
|
|
bitfld.byte 0x0 5. "LCDM_MBIT5,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 2- 3- or 4-mux (001b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line.." "0: OFF,1: ON"
|
|
newline
|
|
bitfld.byte 0x0 4. "LCDM_MBIT4,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is static 2- 3- or 4-mux (000 <= LCDMXx <= 011b) 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line.." "0: OFF,1: ON"
|
|
bitfld.byte 0x0 3. "LCDM_MBIT3,If LCD pin L(index) is selected as segment line (LCDCSS(index) = 0b) and LCD mux rate is 4-mux (LCDMXx=011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index] = 1b): 0b = Pin L[2*index].." "0: OFF,1: ON"
|
|
bitfld.byte 0x0 2. "LCDM_MBIT2,If LCD pin L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is 3- or 4-mux (010b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index].." "0: OFF,1: ON"
|
|
newline
|
|
bitfld.byte 0x0 1. "LCDM_MBIT1,If LCD pin L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is 2- 3- or 4-mux (001b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line.." "0: OFF,1: ON"
|
|
bitfld.byte 0x0 0. "LCDM_MBIT0,If LCD L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is static 2- 3- or 4-mux (000b <= LCDMXx <= 011b) 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line.." "0: OFF,1: ON"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x1180)++0x0
|
|
line.byte 0x0 "LCDBM[$1],LCD blinking memory index register"
|
|
bitfld.byte 0x0 7. "LCDBM_MBIT7,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 4-mux (LCDMXx=011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line (LCDCSS[2*index+1] = 1b): 0b =.." "0: OFF,1: ON"
|
|
bitfld.byte 0x0 6. "LCDBM_MBIT6,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 3- or 4-mux (010b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line.." "0: OFF,1: ON"
|
|
bitfld.byte 0x0 5. "LCDBM_MBIT5,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is 2- 3- or 4-mux (001b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common line.." "0: OFF,1: ON"
|
|
newline
|
|
bitfld.byte 0x0 4. "LCDBM_MBIT4,If LCD pin L[2*index+1] is selected as segment line (LCDCSS[2*index+1] = 0b) and LCD mux rate is static 2- 3- or 4-mux (000b <= LCDMXx <= 011b) 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index+1] is selected as common.." "0: OFF,1: ON"
|
|
bitfld.byte 0x0 3. "LCDBM_MBIT3,If LCD pin L(index) is selected as segment line (LCDCSS(index) = 0b) and LCD mux rate is 4-mux (LCDMXx=011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line (LCDCSS[2*index] = 1b): 0b = Pin.." "0: OFF,1: ON"
|
|
bitfld.byte 0x0 2. "LCDBM_MBIT2,If LCD pin L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is 3- or 4-mux (010b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line.." "0: OFF,1: ON"
|
|
newline
|
|
bitfld.byte 0x0 1. "LCDBM_MBIT1,If LCD pin L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is 2- 3- or 4-mux (001b <= LCDMXx <= 011b): 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line.." "0: OFF,1: ON"
|
|
bitfld.byte 0x0 0. "LCDBM_MBIT0,If LCD L[2*index] is selected as segment line (LCDCSS[2*index] = 0b) and LCD mux rate is static 2- 3- or 4-mux (000b <= LCDMXx <= 011b) 0b = LCD segment off 1b = LCD segment on If LCD pin L[2*index] is selected as common line.." "0: OFF,1: ON"
|
|
repeat.end
|
|
tree.end
|
|
tree "LFSS"
|
|
base ad:0x40094000
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "CPU_INT_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPU_INT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "CPU_INT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 23. "CPU_INT_IMASK_TIO15,Tamper I/O 15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 22. "CPU_INT_IMASK_TIO14,Tamper I/O 14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_IMASK_TIO13,Tamper I/O 13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "CPU_INT_IMASK_TIO12,Tamper I/O 12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 19. "CPU_INT_IMASK_TIO11,Tamper I/O 11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_IMASK_TIO10,Tamper I/O 10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "CPU_INT_IMASK_TIO9,Tamper I/O 9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "CPU_INT_IMASK_TIO8,Tamper I/O 8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_IMASK_TIO7,Tamper I/O 7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "CPU_INT_IMASK_TIO6,Tamper I/O 6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "CPU_INT_IMASK_TIO5,Tamper I/O 5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_IMASK_TIO4,Tamper I/O 4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "CPU_INT_IMASK_TIO3,Tamper I/O 3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "CPU_INT_IMASK_TIO2,Tamper I/O 2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_IMASK_TIO1,Tamper I/O 1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "CPU_INT_IMASK_TIO0,Tamper I/O 0 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "CPU_INT_IMASK_TSEVT,Time stamp event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_IMASK_RT2PS,RTC prescale timer 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_IMASK_RT1PS,RTC prescale timer 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_IMASK_RT0PS,RTC prescale timer 0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_IMASK_RTCA2,RTC alarm 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "CPU_INT_IMASK_RTCA1,RTC alarm 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "CPU_INT_IMASK_RTCTEV,RTC time event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_IMASK_RTCRDY,RTC ready" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "CPU_INT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 23. "CPU_INT_RIS_TIO15,Tamper I/O 15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 22. "CPU_INT_RIS_TIO14,Tamper I/O 14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_RIS_TIO13,Tamper I/O 13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "CPU_INT_RIS_TIO12,Tamper I/O 12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 19. "CPU_INT_RIS_TIO11,Tamper I/O 11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_RIS_TIO10,Tamper I/O 10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "CPU_INT_RIS_TIO9,Tamper I/O 9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "CPU_INT_RIS_TIO8,Tamper I/O 8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_RIS_TIO7,Tamper I/O 7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "CPU_INT_RIS_TIO6,Tamper I/O 6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "CPU_INT_RIS_TIO5,Tamper I/O 5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_RIS_TIO4,Tamper I/O 4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "CPU_INT_RIS_TIO3,Tamper I/O 3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "CPU_INT_RIS_TIO2,Tamper I/O 2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_RIS_TIO1,Tamper I/O 1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "CPU_INT_RIS_TIO0,Tamper I/O 0 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "CPU_INT_RIS_TSEVT,Time stamp event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_RIS_RT2PS,RTC prescale timer 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_RIS_RT1PS,RTC prescale timer 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_RIS_RT0PS,RTC prescale timer 0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_RIS_RTCA2,RTC alarm 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "CPU_INT_RIS_RTCA1,RTC alarm 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "CPU_INT_RIS_RTCTEV,RTC time event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_RIS_RTCRDY,RTC ready" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "CPU_INT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 23. "CPU_INT_MIS_TIO15,Tamper I/O 15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 22. "CPU_INT_MIS_TIO14,Tamper I/O 14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_MIS_TIO13,Tamper I/O 13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "CPU_INT_MIS_TIO12,Tamper I/O 12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 19. "CPU_INT_MIS_TIO11,Tamper I/O 11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_MIS_TIO10,Tamper I/O 10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "CPU_INT_MIS_TIO9,Tamper I/O 9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "CPU_INT_MIS_TIO8,Tamper I/O 8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_MIS_TIO7,Tamper I/O 7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "CPU_INT_MIS_TIO6,Tamper I/O 6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "CPU_INT_MIS_TIO5,Tamper I/O 5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_MIS_TIO4,Tamper I/O 4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "CPU_INT_MIS_TIO3,Tamper I/O 3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "CPU_INT_MIS_TIO2,Tamper I/O 2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_MIS_TIO1,Tamper I/O 1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "CPU_INT_MIS_TIO0,Tamper I/O 0 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "CPU_INT_MIS_TSEVT,Time stamp event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_MIS_RT2PS,RTC prescale timer 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_MIS_RT1PS,RTC prescale timer 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_MIS_RT0PS,RTC prescale timer 0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_MIS_RTCA2,RTC alarm 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "CPU_INT_MIS_RTCA1,RTC alarm 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "CPU_INT_MIS_RTCTEV,RTC time event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_MIS_RTCRDY,RTC ready" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "CPU_INT_ISET,Interrupt set"
|
|
bitfld.long 0x0 23. "CPU_INT_ISET_TIO15,Tamper I/O 15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 22. "CPU_INT_ISET_TIO14,Tamper I/O 14 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "CPU_INT_ISET_TIO13,Tamper I/O 13 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "CPU_INT_ISET_TIO12,Tamper I/O 12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 19. "CPU_INT_ISET_TIO11,Tamper I/O 11 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "CPU_INT_ISET_TIO10,Tamper I/O 10 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "CPU_INT_ISET_TIO9,Tamper I/O 9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "CPU_INT_ISET_TIO8,Tamper I/O 8 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "CPU_INT_ISET_TIO7,Tamper I/O 7 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "CPU_INT_ISET_TIO6,Tamper I/O 6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "CPU_INT_ISET_TIO5,Tamper I/O 5 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "CPU_INT_ISET_TIO4,Tamper I/O 4 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "CPU_INT_ISET_TIO3,Tamper I/O 3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "CPU_INT_ISET_TIO2,Tamper I/O 2 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_ISET_TIO1,Tamper I/O 1 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "CPU_INT_ISET_TIO0,Tamper I/O 0 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "CPU_INT_ISET_TSEVT,Time stamp event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_ISET_RT2PS,RTC prescale timer 2" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_ISET_RT1PS,RTC prescale timer 1" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "CPU_INT_ISET_RT0PS,RTC prescale timer 0" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_ISET_RTCA2,RTC alarm 2" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "CPU_INT_ISET_RTCA1,RTC alarm 1" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "CPU_INT_ISET_RTCTEV,RTC time event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_ISET_RTCRDY,RTC ready" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "CPU_INT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 23. "CPU_INT_ICLR_TIO15,Tamper I/O 15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 22. "CPU_INT_ICLR_TIO14,Tamper I/O 14 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "CPU_INT_ICLR_TIO13,Tamper I/O 13 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 20. "CPU_INT_ICLR_TIO12,Tamper I/O 12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 19. "CPU_INT_ICLR_TIO11,Tamper I/O 11 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "CPU_INT_ICLR_TIO10,Tamper I/O 10 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 17. "CPU_INT_ICLR_TIO9,Tamper I/O 9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 16. "CPU_INT_ICLR_TIO8,Tamper I/O 8 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "CPU_INT_ICLR_TIO7,Tamper I/O 7 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 14. "CPU_INT_ICLR_TIO6,Tamper I/O 6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "CPU_INT_ICLR_TIO5,Tamper I/O 5 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "CPU_INT_ICLR_TIO4,Tamper I/O 4 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "CPU_INT_ICLR_TIO3,Tamper I/O 3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "CPU_INT_ICLR_TIO2,Tamper I/O 2 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "CPU_INT_ICLR_TIO1,Tamper I/O 1 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "CPU_INT_ICLR_TIO0,Tamper I/O 0 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "CPU_INT_ICLR_TSEVT,Time stamp event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "CPU_INT_ICLR_RT2PS,RTC prescale timer 2" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "CPU_INT_ICLR_RT1PS,RTC prescale timer 1" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "CPU_INT_ICLR_RT0PS,RTC prescale timer 0" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "CPU_INT_ICLR_RTCA2,RTC alarm 2" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "CPU_INT_ICLR_RTCA1,RTC alarm 1" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "CPU_INT_ICLR_RTCTEV,RTC time event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "CPU_INT_ICLR_RTCRDY,RTC ready" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "GEN_EVENT_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "GEN_EVENT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "GEN_EVENT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 23. "GEN_EVENT_IMASK_TIO15,Tamper I/O 15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 22. "GEN_EVENT_IMASK_TIO14,Tamper I/O 14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT_IMASK_TIO13,Tamper I/O 13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "GEN_EVENT_IMASK_TIO12,Tamper I/O 12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 19. "GEN_EVENT_IMASK_TIO11,Tamper I/O 11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT_IMASK_TIO10,Tamper I/O 10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "GEN_EVENT_IMASK_TIO9,Tamper I/O 9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "GEN_EVENT_IMASK_TIO8,Tamper I/O 8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "GEN_EVENT_IMASK_TIO7,Tamper I/O 7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "GEN_EVENT_IMASK_TIO6,Tamper I/O 6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT_IMASK_TIO5,Tamper I/O 5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "GEN_EVENT_IMASK_TIO4,Tamper I/O 4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "GEN_EVENT_IMASK_TIO3,Tamper I/O 3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT_IMASK_TIO2,Tamper I/O 2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "GEN_EVENT_IMASK_TIO1,Tamper I/O 1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "GEN_EVENT_IMASK_TIO0,Tamper I/O 0 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT_IMASK_TSEVT,Time stamp event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_IMASK_RT2PS,RTC prescale timer 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_IMASK_RT1PS,RTC prescale timer 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_IMASK_RT0PS,RTC prescale timer 0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "GEN_EVENT_IMASK_RTCA2,RTC alarm 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "GEN_EVENT_IMASK_RTCA1,RTC alarm 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT_IMASK_RTCTEV,RTC time event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_IMASK_RTCRDY,RTC ready" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "GEN_EVENT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 23. "GEN_EVENT_RIS_TIO15,Tamper I/O 15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 22. "GEN_EVENT_RIS_TIO14,Tamper I/O 14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT_RIS_TIO13,Tamper I/O 13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "GEN_EVENT_RIS_TIO12,Tamper I/O 12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 19. "GEN_EVENT_RIS_TIO11,Tamper I/O 11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT_RIS_TIO10,Tamper I/O 10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "GEN_EVENT_RIS_TIO9,Tamper I/O 9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "GEN_EVENT_RIS_TIO8,Tamper I/O 8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "GEN_EVENT_RIS_TIO7,Tamper I/O 7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "GEN_EVENT_RIS_TIO6,Tamper I/O 6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT_RIS_TIO5,Tamper I/O 5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "GEN_EVENT_RIS_TIO4,Tamper I/O 4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "GEN_EVENT_RIS_TIO3,Tamper I/O 3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT_RIS_TIO2,Tamper I/O 2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "GEN_EVENT_RIS_TIO1,Tamper I/O 1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "GEN_EVENT_RIS_TIO0,Tamper I/O 0 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT_RIS_TSEVT,Time stamp event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_RIS_RT2PS,RTC prescale timer 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_RIS_RT1PS,RTC prescale timer 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_RIS_RT0PS,RTC prescale timer 0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "GEN_EVENT_RIS_RTCA2,RTC alarm 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "GEN_EVENT_RIS_RTCA1,RTC alarm 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT_RIS_RTCTEV,RTC time event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_RIS_RTCRDY,RTC ready" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "GEN_EVENT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 23. "GEN_EVENT_MIS_TIO15,Tamper I/O 15 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 22. "GEN_EVENT_MIS_TIO14,Tamper I/O 14 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT_MIS_TIO13,Tamper I/O 13 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "GEN_EVENT_MIS_TIO12,Tamper I/O 12 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 19. "GEN_EVENT_MIS_TIO11,Tamper I/O 11 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT_MIS_TIO10,Tamper I/O 10 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "GEN_EVENT_MIS_TIO9,Tamper I/O 9 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "GEN_EVENT_MIS_TIO8,Tamper I/O 8 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "GEN_EVENT_MIS_TIO7,Tamper I/O 7 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "GEN_EVENT_MIS_TIO6,Tamper I/O 6 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT_MIS_TIO5,Tamper I/O 5 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "GEN_EVENT_MIS_TIO4,Tamper I/O 4 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "GEN_EVENT_MIS_TIO3,Tamper I/O 3 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT_MIS_TIO2,Tamper I/O 2 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "GEN_EVENT_MIS_TIO1,Tamper I/O 1 event" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "GEN_EVENT_MIS_TIO0,Tamper I/O 0 event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT_MIS_TSEVT,Time stamp event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_MIS_RT2PS,RTC prescale timer 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_MIS_RT1PS,RTC prescale timer 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_MIS_RT0PS,RTC prescale timer 0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "GEN_EVENT_MIS_RTCA2,RTC alarm 2" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "GEN_EVENT_MIS_RTCA1,RTC alarm 1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT_MIS_RTCTEV,RTC time event" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_MIS_RTCRDY,RTC ready" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "GEN_EVENT_ISET,Interrupt set"
|
|
bitfld.long 0x0 23. "GEN_EVENT_ISET_TIO15,Tamper I/O 15 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 22. "GEN_EVENT_ISET_TIO14,Tamper I/O 14 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 21. "GEN_EVENT_ISET_TIO13,Tamper I/O 13 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 20. "GEN_EVENT_ISET_TIO12,Tamper I/O 12 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 19. "GEN_EVENT_ISET_TIO11,Tamper I/O 11 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 18. "GEN_EVENT_ISET_TIO10,Tamper I/O 10 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 17. "GEN_EVENT_ISET_TIO9,Tamper I/O 9 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "GEN_EVENT_ISET_TIO8,Tamper I/O 8 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "GEN_EVENT_ISET_TIO7,Tamper I/O 7 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "GEN_EVENT_ISET_TIO6,Tamper I/O 6 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "GEN_EVENT_ISET_TIO5,Tamper I/O 5 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "GEN_EVENT_ISET_TIO4,Tamper I/O 4 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "GEN_EVENT_ISET_TIO3,Tamper I/O 3 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "GEN_EVENT_ISET_TIO2,Tamper I/O 2 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "GEN_EVENT_ISET_TIO1,Tamper I/O 1 event" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "GEN_EVENT_ISET_TIO0,Tamper I/O 0 event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "GEN_EVENT_ISET_TSEVT,Time stamp event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "GEN_EVENT_ISET_RT2PS,RTC prescale timer 2" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_ISET_RT1PS,RTC prescale timer 1" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "GEN_EVENT_ISET_RT0PS,RTC prescale timer 0" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "GEN_EVENT_ISET_RTCA2,RTC alarm 2" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "GEN_EVENT_ISET_RTCA1,RTC alarm 1" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "GEN_EVENT_ISET_RTCTEV,RTC time event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "GEN_EVENT_ISET_RTCRDY,RTC ready" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "GEN_EVENT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 23. "GEN_EVENT_ICLR_TIO15,Tamper I/O 15 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 22. "GEN_EVENT_ICLR_TIO14,Tamper I/O 14 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 21. "GEN_EVENT_ICLR_TIO13,Tamper I/O 13 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 20. "GEN_EVENT_ICLR_TIO12,Tamper I/O 12 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 19. "GEN_EVENT_ICLR_TIO11,Tamper I/O 11 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 18. "GEN_EVENT_ICLR_TIO10,Tamper I/O 10 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 17. "GEN_EVENT_ICLR_TIO9,Tamper I/O 9 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 16. "GEN_EVENT_ICLR_TIO8,Tamper I/O 8 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "GEN_EVENT_ICLR_TIO7,Tamper I/O 7 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 14. "GEN_EVENT_ICLR_TIO6,Tamper I/O 6 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "GEN_EVENT_ICLR_TIO5,Tamper I/O 5 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "GEN_EVENT_ICLR_TIO4,Tamper I/O 4 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "GEN_EVENT_ICLR_TIO3,Tamper I/O 3 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "GEN_EVENT_ICLR_TIO2,Tamper I/O 2 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "GEN_EVENT_ICLR_TIO1,Tamper I/O 1 event" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "GEN_EVENT_ICLR_TIO0,Tamper I/O 0 event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "GEN_EVENT_ICLR_TSEVT,Time stamp event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "GEN_EVENT_ICLR_RT2PS,RTC prescale timer 2" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "GEN_EVENT_ICLR_RT1PS,RTC prescale timer 1" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "GEN_EVENT_ICLR_RT0PS,RTC prescale timer 0" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "GEN_EVENT_ICLR_RTCA2,RTC alarm 2" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "GEN_EVENT_ICLR_RTCA1,RTC alarm 1" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "GEN_EVENT_ICLR_RTCTEV,RTC time event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "GEN_EVENT_ICLR_RTCRDY,RTC ready" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode 1 select" "?,?,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode 0 select" "?,1: SOFTWARE,?,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,LFSS Descriptor Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identifier. This ID is unique for each module. 0x2911 = Module ID of the LFSS Module"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature set of this module. Differentiates the complexity of the actually instantiated module if there are differences."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instantiated version. Describes which instance of the module accessed."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major revision. This number holds the module revision and is incremented by the module developers. n = Major version (see device-specific data sheet)"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor revision. This number holds the module revision and is incremented by the module developers. n = Minor module revision (see device-specific data sheet)"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CLKCTL,RTC Clock Control Register"
|
|
bitfld.long 0x0 31. "CLKCTL_MODCLKEN,This bit enables the supply of the 32kHz clock to the RTC. It will not power-up the 32kHz crystal oscillator this needs to be done in the Clock System Module." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "DBGCTL,RTC Module Debug Control Register"
|
|
bitfld.long 0x4 1. "DBGCTL_DBGINT,Debug Interrupt Enable." "0: OFF,1: ON"
|
|
bitfld.long 0x4 0. "DBGCTL_DBGRUN,Debug Run." "0: HALT,1: RUN"
|
|
line.long 0x8 "CTL,RTC Control Register"
|
|
bitfld.long 0x8 7. "CTL_RTCBCD,Real-time clock BCD select. Selects BCD counting for real-time clock." "0: BINARY,1: BCD"
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bitfld.long 0x8 0.--1. "CTL_RTCTEVTX,Real-time clock time event 0x0 = Minute changed 0x1 = Hour changed 0x2 = Every day at midnight (00:00) 0x3 = Every day at noon (12:00)" "0: 00,1: Hour changed,2: Every day at midnight,3: Every day at noon"
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rgroup.long 0x110C++0x3
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line.long 0x0 "STA,RTC Status Register"
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bitfld.long 0x0 2. "STA_RTCTCOK,Real-time clock temperature compensation write OK. This is a read-only bit that indicates if the write to RTCTCMP is successful or not." "0: NOT_OK,1: OK"
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bitfld.long 0x0 1. "STA_RTCTCRDY,Real-time clock temperature compensation ready. This is a read only bit that indicates when the RTCTCMPx can be written. Write to RTCTCMPx should be avoided when RTCTCRDY is reset." "0: NOT_READY,1: READY"
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bitfld.long 0x0 0. "STA_RTCRDY,Real-time clock ready. This bit indicates when the real-time clock time values are safe for reading." "0: NOT_READY,1: READY"
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group.long 0x1110++0x3F
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line.long 0x0 "CAL,RTC Clock Offset Calibration Register"
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bitfld.long 0x0 16.--17. "CAL_RTCCALFX,Real-time clock calibration frequency. Selects frequency output to RTCCLK pin for calibration measurement. The corresponding port must be configured for the peripheral module function." "0: F32KHZ,1: F512HZ,2: F256HZ,3: F1HZ"
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bitfld.long 0x0 15. "CAL_RTCOCALS,Real-time clock offset error calibration sign. This bit decides the sign of offset error calibration." "0: DOWN,1: UP"
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hexmask.long.byte 0x0 0.--7. 1. "CAL_RTCOCALX,Real-time clock offset error calibration. Each LSB represents approximately +1ppm (RTCOCALXS = 1) or -1ppm (RTCOCALXS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm will.."
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line.long 0x4 "TCMP,RTC Temperature Compensation Register"
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bitfld.long 0x4 15. "TCMP_RTCTCMPS,Real-time clock temperature compensation sign. This bit decides the sign of temperature compensation." "0: DOWN,1: UP"
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hexmask.long.byte 0x4 0.--7. 1. "TCMP_RTCTCMPX,Real-time clock temperature compensation. Value written into this register is used for temperature compensation of RTC. Each LSB represents approximately +1ppm (RTCTCMPS = 1) or -1ppm (RTCTCMPS = 0) adjustment in frequency. Maximum.."
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line.long 0x8 "SEC,RTC Seconds Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x8 12.--14. "SEC_SECHIGHBCD,Seconds BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 8.--11. 1. "SEC_SECLOWBCD,Seconds BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x8 0.--5. 1. "SEC_SECBIN,Seconds Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0xC "MIN,RTC Minutes Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0xC 12.--14. "MIN_MINHIGHBCD,Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0xC 8.--11. 1. "MIN_MINLOWBCD,Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0xC 0.--5. 1. "MIN_MINBIN,Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x10 "HOUR,RTC Hours Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x10 12.--13. "HOUR_HOURHIGHBCD,Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3"
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hexmask.long.byte 0x10 8.--11. 1. "HOUR_HOURLOWBCD,Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x10 0.--4. 1. "HOUR_HOURBIN,Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x14 "DAY,RTC Day Of Week / Month Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x14 20.--21. "DAY_DOMHIGHBCD,Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3"
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hexmask.long.byte 0x14 16.--19. 1. "DAY_DOMLOWBCD,Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x14 8.--12. 1. "DAY_DOMBIN,Day of month Binary (1 to 28 29 30 31). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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bitfld.long 0x14 0.--2. "DAY_DOW,Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7"
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line.long 0x18 "MON,RTC Month Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x18 12. "MON_MONHIGHBCD,Month BCD high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1"
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hexmask.long.byte 0x18 8.--11. 1. "MON_MONLOWBCD,Month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x18 0.--3. 1. "MON_MONBIN,Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x1C "YEAR,RTC Year Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x1C 28.--30. "YEAR_CENTHIGHBCD,Century BCD high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x1C 24.--27. 1. "YEAR_CENTLOWBCD,Century BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x1C 20.--23. 1. "YEAR_DECADEBCD,Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x1C 16.--19. 1. "YEAR_YEARLOWESTBCD,Year BCD lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x1C 8.--11. 1. "YEAR_YEARHIGHBIN,Year Binary high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x1C 0.--7. 1. "YEAR_YEARLOWBIN,Year Binary low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x20 "A1MIN,RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x20 15. "A1MIN_AMINAEBCD,Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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bitfld.long 0x20 12.--14. "A1MIN_AMINHIGHBCD,Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 8.--11. 1. "A1MIN_AMINLOWBCD,Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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bitfld.long 0x20 7. "A1MIN_AMINAEBIN,Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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hexmask.long.byte 0x20 0.--5. 1. "A1MIN_AMINBIN,Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x24 "A1HOUR,RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x24 15. "A1HOUR_AHOURAEBCD,Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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bitfld.long 0x24 12.--13. "A1HOUR_AHOURHIGHBCD,Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.." "0,1,2,3"
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hexmask.long.byte 0x24 8.--11. 1. "A1HOUR_AHOURLOWBCD,Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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bitfld.long 0x24 7. "A1HOUR_AHOURAEBIN,Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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hexmask.long.byte 0x24 0.--4. 1. "A1HOUR_AHOURBIN,Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x28 "A1DAY,RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x28 23. "A1DAY_ADOMAEBCD,Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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bitfld.long 0x28 20.--21. "A1DAY_ADOMHIGHBCD,Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3"
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hexmask.long.byte 0x28 16.--19. 1. "A1DAY_ADOMLOWBCD,Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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bitfld.long 0x28 15. "A1DAY_ADOMAEBIN,Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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hexmask.long.byte 0x28 8.--12. 1. "A1DAY_ADOMBIN,Alarm Day of month Binary (1 to 28 29 30 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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bitfld.long 0x28 7. "A1DAY_ADOWAE,Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0." "0: DISABLE,1: ENABLE"
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bitfld.long 0x28 0.--2. "A1DAY_ADOW,Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7"
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line.long 0x2C "A2MIN,RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x2C 15. "A2MIN_AMINAEBCD,Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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bitfld.long 0x2C 12.--14. "A2MIN_AMINHIGHBCD,Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x2C 8.--11. 1. "A2MIN_AMINLOWBCD,Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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bitfld.long 0x2C 7. "A2MIN_AMINAEBIN,Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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hexmask.long.byte 0x2C 0.--5. 1. "A2MIN_AMINBIN,Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x30 "A2HOUR,RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x30 15. "A2HOUR_AHOURAEBCD,Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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bitfld.long 0x30 12.--13. "A2HOUR_AHOURHIGHBCD,Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.." "0,1,2,3"
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hexmask.long.byte 0x30 8.--11. 1. "A2HOUR_AHOURLOWBCD,Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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bitfld.long 0x30 7. "A2HOUR_AHOURAEBIN,Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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hexmask.long.byte 0x30 0.--4. 1. "A2HOUR_AHOURBIN,Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x34 "A2DAY,RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x34 23. "A2DAY_ADOMAEBCD,Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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bitfld.long 0x34 20.--21. "A2DAY_ADOMHIGHBCD,Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3"
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hexmask.long.byte 0x34 16.--19. 1. "A2DAY_ADOMLOWBCD,Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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bitfld.long 0x34 15. "A2DAY_ADOMAEBIN,Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled." "0: Alarm disabled,1: Alarm enabled"
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hexmask.long.byte 0x34 8.--12. 1. "A2DAY_ADOMBIN,Alarm Day of month Binary (1 to 28 29 30 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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bitfld.long 0x34 7. "A2DAY_ADOWAE,Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0." "0: DISABLE,1: ENABLE"
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bitfld.long 0x34 0.--2. "A2DAY_ADOW,Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7"
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line.long 0x38 "PSCTL,RTC Prescale Timer 0/1 Control Register"
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bitfld.long 0x38 18.--20. "PSCTL_RT1IP,Prescale timer 1 interrupt interval" "0: INT15P6MS,1: INT31P3MS,2: INT62P5MS,3: INT125MS,4: INT250MS,5: INT500MS,6: INT1S,7: INT2S"
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bitfld.long 0x38 2.--4. "PSCTL_RT0IP,Prescale timer 0 interrupt interval" "?,?,2: INT244US,3: INT488US,4: INT0P98MS,5: INT1P95MS,6: INT3P91MS,7: INT7P81MS"
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line.long 0x3C "EXTPSCTL,RTC Prescale Timer 2 Control Register"
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bitfld.long 0x3C 2.--3. "EXTPSCTL_RT2PS,Prescale timer 2 interrupt interval" "0: INT4S,1: INT8S,2: INT16S,?"
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rgroup.long 0x1150++0x1B
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line.long 0x0 "TSSEC,Time Stamp Seconds Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x0 12.--14. "TSSEC_SECHIGHBCD,Time Stamp Seconds BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 8.--11. 1. "TSSEC_SECLOWBCD,Time Stamp Seconds BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x0 0.--5. 1. "TSSEC_SECBIN,Time Stamp Second Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x4 "TSMIN,Time Stamp Minutes Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x4 12.--14. "TSMIN_MINHIGHBCD,Time Stamp Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 8.--11. 1. "TSMIN_MINLOWBCD,Time Stamp Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x4 0.--5. 1. "TSMIN_MINBIN,Time Stamp Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x8 "TSHOUR,Time Stamp Hours Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x8 12.--13. "TSHOUR_HOURHIGHBCD,Time Stamp Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3"
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hexmask.long.byte 0x8 8.--11. 1. "TSHOUR_HOURLOWBCD,Time Stamp Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x8 0.--4. 1. "TSHOUR_HOURBIN,Time Stamp Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0xC "TSDAY,Time Stamp Day Of Week / MonthRegister - Calendar Mode With Binary / BCD Format"
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bitfld.long 0xC 20.--21. "TSDAY_DOMHIGHBCD,Time Stamp Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3"
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hexmask.long.byte 0xC 16.--19. 1. "TSDAY_DOMLOWBCD,Time Stamp Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0xC 8.--12. 1. "TSDAY_DOMBIN,Time Stamp Day of month Binary (1 to 28 29 30 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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bitfld.long 0xC 0.--2. "TSDAY_DOW,Time Stamp Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7"
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line.long 0x10 "TSMON,Time Stamp Month Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x10 12. "TSMON_MONHIGHBCD,Time Stamp Month BCD high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1"
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hexmask.long.byte 0x10 8.--11. 1. "TSMON_MONLOWBCD,Time Stamp Month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x10 0.--3. 1. "TSMON_MONBIN,Time Stamp Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x14 "TSYEAR,Time Stamp Years Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x14 28.--30. "TSYEAR_CENTHIGHBCD,Time Stamp Century BCD high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x14 24.--27. 1. "TSYEAR_CENTLOWBCD,Time Stamp Century BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x14 20.--23. 1. "TSYEAR_DECADEBCD,Time Stamp Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x14 16.--19. 1. "TSYEAR_YERARLOWESTBCD,Time Stamp Year BCD lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x14 8.--11. 1. "TSYEAR_YEARHIGHBIN,Time Stamp Year Binary high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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hexmask.long.byte 0x14 0.--7. 1. "TSYEAR_YEARLOWBIN,Time Stamp Year Binary low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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line.long 0x18 "TSSTAT,Time Stamp Status Register"
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bitfld.long 0x18 16. "TSSTAT_TSVDDEVT,Loss of VDD caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 15. "TSSTAT_TSTIOEVT15,Tamper I/O 15 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 14. "TSSTAT_TSTIOEVT14,Tamper I/O 14 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 13. "TSSTAT_TSTIOEVT13,Tamper I/O 13 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 12. "TSSTAT_TSTIOEVT12,Tamper I/O 12 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 11. "TSSTAT_TSTIOEVT11,Tamper I/O 11 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 10. "TSSTAT_TSTIOEVT10,Tamper I/O 10 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 9. "TSSTAT_TSTIOEVT9,Tamper I/O 9 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 8. "TSSTAT_TSTIOEVT8,Tamper I/O 8 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 7. "TSSTAT_TSTIOEVT7,Tamper I/O 7 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 6. "TSSTAT_TSTIOEVT6,Tamper I/O 6 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 5. "TSSTAT_TSTIOEVT5,Tamper I/O 5 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 4. "TSSTAT_TSTIOEVT4,Tamper I/O 4 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 3. "TSSTAT_TSTIOEVT3,Tamper I/O 3 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 2. "TSSTAT_TSTIOEVT2,Tamper I/O 2 caused time stamp event" "0: CLR,1: SET"
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bitfld.long 0x18 1. "TSSTAT_TSTIOEVT1,Tamper I/O 1 caused time stamp event" "0: CLR,1: SET"
|
|
bitfld.long 0x18 0. "TSSTAT_TSTIOEVT0,Tamper I/O 0 caused time stamp event" "0: CLR,1: SET"
|
|
group.long 0x116C++0x3
|
|
line.long 0x0 "TSCTL,Time Stamp Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TSCTL_KEY,need to write (KEY=0xC5) to update this register"
|
|
bitfld.long 0x0 20. "TSCTL_TSCAPTURE,Defines the capture method of the RTC timestamp when a time stamp event occurens." "0: FIRST,1: LAST"
|
|
bitfld.long 0x0 16. "TSCTL_TSVDDEN,Time Stamp by VDD Loss detection enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 15. "TSCTL_TSTIOEN15,Time Stamp by Tamper I/O 15 enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 14. "TSCTL_TSTIOEN14,Time Stamp by Tamper I/O 14 enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 13. "TSCTL_TSTIOEN13,Time Stamp by Tamper I/O 13 enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 12. "TSCTL_TSTIOEN12,Time Stamp by Tamper I/O 12 enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 11. "TSCTL_TSTIOEN11,Time Stamp by Tamper I/O 11 enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 10. "TSCTL_TSTIOEN10,Time Stamp by Tamper I/O 10 enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 9. "TSCTL_TSTIOEN9,Time Stamp by Tamper I/O 9 enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 8. "TSCTL_TSTIOEN8,Time Stamp by Tamper I/O 8 enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 7. "TSCTL_TSTIOEN7,Time Stamp by Tamper I/O 7 enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 6. "TSCTL_TSTIOEN6,Time Stamp by Tamper I/O 6 enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "TSCTL_TSTIOEN5,Time Stamp by Tamper I/O 5 enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "TSCTL_TSTIOEN4,Time Stamp by Tamper I/O 4 enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 3. "TSCTL_TSTIOEN3,Time Stamp by Tamper I/O 3 enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "TSCTL_TSTIOEN2,Time Stamp by Tamper I/O 2 enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 1. "TSCTL_TSTIOEN1,Time Stamp by Tamper I/O 1 enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "TSCTL_TSTIOEN0,Time Stamp by Tamper I/O 0 enable" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x1170++0x3
|
|
line.long 0x0 "TSCLR,Time Stamp Clear Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TSCLR_KEY,need to write (KEY=0xE2) to update this register"
|
|
bitfld.long 0x0 0. "TSCLR_CLR,Clear time stamp and status register." "0: NO_EFFECT,1: CLR"
|
|
group.long 0x11F0++0x3
|
|
line.long 0x0 "LFSSRST,Low frequency sub-system reset request"
|
|
hexmask.long.byte 0x0 24.--31. 1. "LFSSRST_KEY,need to write (KEY=0x12) to update this register"
|
|
bitfld.long 0x0 0. "LFSSRST_VBATPOR,If set the register bit will request a power on reset to the PMU of the LFSS." "0: NO_EFFECT,1: SET"
|
|
group.long 0x11FC++0x3
|
|
line.long 0x0 "RTCLOCK,Real time clock lock register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RTCLOCK_KEY,need to write (KEY=0x22) to update this register"
|
|
bitfld.long 0x0 0. "RTCLOCK_PROTECT,If set the register bit will protect the CLKCTL SEC MIN HOUR DAY MON YEAR and LFSSRST from accidental writes." "0: CLR,1: SET"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1200)++0x3
|
|
line.long 0x0 "TIOCTL[$1],Tamper I/O Control Register"
|
|
bitfld.long 0x0 19. "TIOCTL_OUTINV,Output inversion enable" "0: DISBALE,1: ENABLE"
|
|
bitfld.long 0x0 18. "TIOCTL_INENA,input enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 17. "TIOCTL_PIPU,pull up enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 16. "TIOCTL_PIPD,pull down enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12.--13. "TIOCTL_FILTEREN,Programmable counter length of digital glitch filter for TIO0" "0: NO_FLT,1: FLT_1,2: FLT_2,3: FLT_3"
|
|
bitfld.long 0x0 8.--9. "TIOCTL_POLARITY,Enables and configures edge detection polarity for TIO" "0: DISABLE,1: RISE,2: FALL,3: BOTH"
|
|
newline
|
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bitfld.long 0x0 4.--5. "TIOCTL_TOUTSEL,Selects the source for TOUT control" "0: TOUT,1: LFCLKEXT,2: HEARTBEAT,3: TSEVTSTAT"
|
|
bitfld.long 0x0 0. "TIOCTL_IOMUX,tamper I/O is controlled by SoC IOMUX module" "0: IOMUX,1: TAMPER"
|
|
repeat.end
|
|
group.long 0x1280++0x1F
|
|
line.long 0x0 "TOUT3_0,Tamper Output 3 to 0"
|
|
bitfld.long 0x0 24. "TOUT3_0_TIO3,This bit sets the value of the pin tamper I/O 3 (TIO3) when the output is enabled through TOE3 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 16. "TOUT3_0_TIO2,This bit sets the value of the pin tamper I/O 2 (TIO0) when the output is enabled through TOE2 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "TOUT3_0_TIO1,This bit sets the value of the pin tamper I/O 1 (TIO1) when the output is enabled through TOE1 register." "0: ZERO,1: ONE"
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|
newline
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bitfld.long 0x0 0. "TOUT3_0_TIO0,This bit sets the value of the pin tamper I/O 0 (TIO0) when the output is enabled through TOE0 register." "0: ZERO,1: ONE"
|
|
line.long 0x4 "TOUT7_4,Tamper Output 7 to 4"
|
|
bitfld.long 0x4 24. "TOUT7_4_TIO7,This bit sets the value of the pin tamper I/O 7 (TIO7) when the output is enabled through TOE7 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 16. "TOUT7_4_TIO6,This bit sets the value of the pin tamper I/O 2 (TIO6) when the output is enabled through TOE6 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 8. "TOUT7_4_TIO5,This bit sets the value of the pin tamper I/O 5 (TIO5) when the output is enabled through TOE5 register." "0: ZERO,1: ONE"
|
|
newline
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bitfld.long 0x4 0. "TOUT7_4_TIO4,This bit sets the value of the pin tamper I/O 4 (TIO4) when the output is enabled through TOE4 register." "0: ZERO,1: ONE"
|
|
line.long 0x8 "TOUT11_8,Tamper Output 11 to 8"
|
|
bitfld.long 0x8 24. "TOUT11_8_TIO11,This bit sets the value of the pin tamper I/O 11 (TIO11) when the output is enabled through TOE11 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 16. "TOUT11_8_TIO10,This bit sets the value of the pin tamper I/O 10 (TIO10) when the output is enabled through TOE10 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 8. "TOUT11_8_TIO9,This bit sets the value of the pin tamper I/O 9 (TIO9) when the output is enabled through TOE9 register." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x8 0. "TOUT11_8_TIO8,This bit sets the value of the pin tamper I/O 8 (TIO8) when the output is enabled through TOE8 register." "0: ZERO,1: ONE"
|
|
line.long 0xC "TOUT15_12,Tamper Output 15 to 12"
|
|
bitfld.long 0xC 24. "TOUT15_12_TIO15,This bit sets the value of the pin tamper I/O 15 (TIO15) when the output is enabled through TOE15 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "TOUT15_12_TIO14,This bit sets the value of the pin tamper I/O 14 (TIO14) when the output is enabled through TOE14 register." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "TOUT15_12_TIO13,This bit sets the value of the pin tamper I/O 13 (TIO13) when the output is enabled through TOE13 register." "0: ZERO,1: ONE"
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|
newline
|
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bitfld.long 0xC 0. "TOUT15_12_TIO12,This bit sets the value of the pin tamper I/O 12 (TIO12) when the output is enabled through TOE12 register." "0: ZERO,1: ONE"
|
|
line.long 0x10 "TOE3_0,Tamper Output Enable 3 to 0"
|
|
bitfld.long 0x10 24. "TOE3_0_TIO3,Enables data output for tamper I/O 3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 16. "TOE3_0_TIO2,Enables data output for tamper I/O 2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 8. "TOE3_0_TIO1,Enables data output for tamper I/O 1" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x10 0. "TOE3_0_TIO0,Enables data output for tamper I/O 0" "0: DISABLE,1: ENABLE"
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|
line.long 0x14 "TOE7_4,Tamper Output Enable 7 to 4"
|
|
bitfld.long 0x14 24. "TOE7_4_TIO7,Enables data output for tamper I/O 7" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 16. "TOE7_4_TIO6,Enables data output for tamper I/O 6" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 8. "TOE7_4_TIO5,Enables data output for tamper I/O 5" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x14 0. "TOE7_4_TIO4,Enables data output for tamper I/O 4" "0: DISABLE,1: ENABLE"
|
|
line.long 0x18 "TOE11_8,Tamper Output Enable 7 to 4"
|
|
bitfld.long 0x18 24. "TOE11_8_TIO11,Enables data output for tamper I/O 11" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 16. "TOE11_8_TIO10,Enables data output for tamper I/O 10" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 8. "TOE11_8_TIO9,Enables data output for tamper I/O 9" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x18 0. "TOE11_8_TIO8,Enables data output for tamper I/O 8" "0: DISABLE,1: ENABLE"
|
|
line.long 0x1C "TOE15_12,Tamper Output Enable 7 to 4"
|
|
bitfld.long 0x1C 24. "TOE15_12_TIO15,Enables data output for tamper I/O 15" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 16. "TOE15_12_TIO14,Enables data output for tamper I/O 14" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 8. "TOE15_12_TIO13,Enables data output for tamper I/O 13" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x1C 0. "TOE15_12_TIO12,Enables data output for tamper I/O 12" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x12A0++0xF
|
|
line.long 0x0 "TIN3_0,Tamper Input Register"
|
|
bitfld.long 0x0 24. "TIN3_0_TIO3,This bit reads the data input value of tamper I/O 3." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 16. "TIN3_0_TIO2,This bit reads the data input value of tamper I/O 2." "0: ZERO,1: ONE"
|
|
bitfld.long 0x0 8. "TIN3_0_TIO1,This bit reads the data input value of tamper I/O 1." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x0 0. "TIN3_0_TIO0,This bit reads the data input value of tamper I/O 0." "0: ZERO,1: ONE"
|
|
line.long 0x4 "TIN7_4,Tamper Input Register"
|
|
bitfld.long 0x4 24. "TIN7_4_TIO7,This bit reads the data input value of tamper I/O 7." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 16. "TIN7_4_TIO6,This bit reads the data input value of tamper I/O 6." "0: ZERO,1: ONE"
|
|
bitfld.long 0x4 8. "TIN7_4_TIO5,This bit reads the data input value of tamper I/O 5." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x4 0. "TIN7_4_TIO4,This bit reads the data input value of tamper I/O 4." "0: ZERO,1: ONE"
|
|
line.long 0x8 "TIN11_8,Tamper Input Register"
|
|
bitfld.long 0x8 24. "TIN11_8_TIO11,This bit reads the data input value of tamper I/O 11." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 16. "TIN11_8_TIO10,This bit reads the data input value of tamper I/O 10." "0: ZERO,1: ONE"
|
|
bitfld.long 0x8 8. "TIN11_8_TIO9,This bit reads the data input value of tamper I/O 9." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0x8 0. "TIN11_8_TIO8,This bit reads the data input value of tamper I/O 8." "0: ZERO,1: ONE"
|
|
line.long 0xC "TIN15_12,Tamper Input Register"
|
|
bitfld.long 0xC 24. "TIN15_12_TIO15,This bit reads the data input value of tamper I/O 15." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 16. "TIN15_12_TIO14,This bit reads the data input value of tamper I/O 14." "0: ZERO,1: ONE"
|
|
bitfld.long 0xC 8. "TIN15_12_TIO13,This bit reads the data input value of tamper I/O 13." "0: ZERO,1: ONE"
|
|
newline
|
|
bitfld.long 0xC 0. "TIN15_12_TIO12,This bit reads the data input value of tamper I/O 12." "0: ZERO,1: ONE"
|
|
group.long 0x12C0++0x3
|
|
line.long 0x0 "HEARTBEAT,Heartbeat Register"
|
|
bitfld.long 0x0 16.--17. "HEARTBEAT_HBMODE,Heart beat mode" "0: HB_DIS,1: HB_ALLWAYS,2: HB_TS,3: HB_VDDFAIL"
|
|
bitfld.long 0x0 8.--10. "HEARTBEAT_HBWIDTH,Heart beat interval width" "0: HBPWDTH1,1: HBPWDTH2,2: HBPWDTH4,3: HBPWDTH8,4: HBPWDTH16,5: HBPWDTH32,6: HBPWDTH64,7: HBPWDTH128"
|
|
bitfld.long 0x0 0.--2. "HEARTBEAT_HBINTERVAL,Heart beat interval" "0: HBINT0P125,1: HBINT0P25,2: HBINT0P5,3: HBINT1,4: HBINT2,5: HBINT4,6: HBINT8,7: HBINT16"
|
|
group.long 0x12FC++0xF
|
|
line.long 0x0 "TIOLOCK,Tamper I/O lock register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TIOLOCK_KEY,need to write (KEY=0x18) to update this register"
|
|
bitfld.long 0x0 0. "TIOLOCK_PROTECT,If set the register bit will protect the TIOCTL and HEARTBEAT from accidental writes." "0: CLR,1: SET"
|
|
line.long 0x4 "WDTEN,Watchdog Timer Enable Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "WDTEN_KEY,KEY to allow write access to this register. Writing to this register with an incorrect key causes a POR level reset. Read as 0."
|
|
bitfld.long 0x4 0. "WDTEN_ENABLE,Enable bit for the WDT." "0: CLR,1: SET"
|
|
line.long 0x8 "WDTDBGCTL,Watchdog Timer Debug Control Register"
|
|
bitfld.long 0x8 0. "WDTDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
line.long 0xC "WDTCTL,Watchdog Timer Control Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. "WDTCTL_KEY,KEY to allow write access to this register. Writing to this register with an incorrect key causes a POR level reset. Read as 0."
|
|
bitfld.long 0xC 4.--6. "WDTCTL_PER,Timer Period of the WDT. These bits select the total watchdog timer count." "0: PER_EN_25,1: PER_EN_21,2: PER_EN_18,3: PER_EN_15,4: PER_EN_12,5: PER_EN_10,6: PER_EN_8,7: PER_EN_6"
|
|
bitfld.long 0xC 0.--2. "WDTCTL_CLKDIV,Module Clock Divider Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible." "0: MIN,?,?,?,?,?,?,7: MAX"
|
|
wgroup.long 0x130C++0x3
|
|
line.long 0x0 "WDTCNTRST,Watchdog Timer Counter Reset Register"
|
|
hexmask.long 0x0 0.--31. 1. "WDTCNTRST_RESTART,Writing 03A7h to this register restarts the WDT Counter. Writing any other value causes a POR level reset. Read as 0x0h."
|
|
rgroup.long 0x1310++0x3
|
|
line.long 0x0 "WDTSTAT,Watchdog Timer Status Register"
|
|
bitfld.long 0x0 0. "WDTSTAT_RUN,Watchdog running status flag." "0: STOP,1: RUN"
|
|
group.long 0x13FC++0x3
|
|
line.long 0x0 "WDTLOCK,Watchdog timer lock register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WDTLOCK_KEY,need to write (KEY=0xBD) to update this register"
|
|
bitfld.long 0x0 0. "WDTLOCK_PROTECT,If set the register bit will protect the WDTEN and WDTCTL from accidental writes." "0: CLR,1: SET"
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1400)++0x3
|
|
line.long 0x0 "SPMEM[$1],Scratch Pad Memory Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SPMEM_DATA3,memory data byte 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "SPMEM_DATA2,memory data byte 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. "SPMEM_DATA1,memory data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "SPMEM_DATA0,memory data byte 0"
|
|
repeat.end
|
|
group.long 0x1500++0x1F
|
|
line.long 0x0 "SPMWPROT0,Scratch Pad Memory Write Protect Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SPMWPROT0_KEY,need to write (KEY=0xE8) to update this register"
|
|
bitfld.long 0x0 15. "SPMWPROT0_WP_3_3,write protect SPMEM3 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x0 14. "SPMWPROT0_WP_3_2,write protect SPMEM3 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x0 13. "SPMWPROT0_WP_3_1,write protect SPMEM3 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x0 12. "SPMWPROT0_WP_3_0,write protect SPMEM3 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x0 11. "SPMWPROT0_WP_2_3,write protect SPMEM2 - DATA3" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x0 10. "SPMWPROT0_WP_2_2,write protect SPMEM2 - DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x0 9. "SPMWPROT0_WP_2_1,write protect SPMEM2 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x0 8. "SPMWPROT0_WP_2_0,write protect SPMEM2 - DATA0" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x0 7. "SPMWPROT0_WP_1_3,write protect SPMEM1 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x0 6. "SPMWPROT0_WP_1_2,write protect SPMEM1 - DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x0 5. "SPMWPROT0_WP_1_1,write protect SPMEM1 - DATA1" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x0 4. "SPMWPROT0_WP_1_0,write protect SPMEM1 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x0 3. "SPMWPROT0_WP_0_3,write protect SPMEM0 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x0 2. "SPMWPROT0_WP_0_2,write protect SPMEM0 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x0 1. "SPMWPROT0_WP_0_1,write protect SPMEM0 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x0 0. "SPMWPROT0_WP_0_0,write protect SPMEM0 - DATA0" "0: READWRITE,1: READONLY"
|
|
line.long 0x4 "SPMWPROT1,Scratch Pad Memory Write Protect Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "SPMWPROT1_KEY,need to write (KEY=0xE8) to update this register"
|
|
bitfld.long 0x4 15. "SPMWPROT1_WP_7_3,write protect SPMEM7 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x4 14. "SPMWPROT1_WP_7_2,write protect SPMEM7 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x4 13. "SPMWPROT1_WP_7_1,write protect SPMEM7 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x4 12. "SPMWPROT1_WP_7_0,write protect SPMEM7 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x4 11. "SPMWPROT1_WP_6_3,write protect SPMEM6 - DATA3" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x4 10. "SPMWPROT1_WP_6_2,write protect SPMEM6 - DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x4 9. "SPMWPROT1_WP_6_1,write protect SPMEM6 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x4 8. "SPMWPROT1_WP_6_0,write protect SPMEM6 - DATA0" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x4 7. "SPMWPROT1_WP_5_3,write protect SPMEM5 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x4 6. "SPMWPROT1_WP_5_2,write protect SPMEM5 - DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x4 5. "SPMWPROT1_WP_5_1,write protect SPMEM5 - DATA1" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x4 4. "SPMWPROT1_WP_5_0,write protect SPMEM5 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x4 3. "SPMWPROT1_WP_4_3,write protect SPMEM4 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x4 2. "SPMWPROT1_WP_4_2,write protect SPMEM4 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x4 1. "SPMWPROT1_WP_4_1,write protect SPMEM4 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x4 0. "SPMWPROT1_WP_4_0,write protect SPMEM4 - DATA0" "0: READWRITE,1: READONLY"
|
|
line.long 0x8 "SPMWPROT2,Scratch Pad Memory Write Protect Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "SPMWPROT2_KEY,need to write (KEY=0xE8) to update this register"
|
|
bitfld.long 0x8 15. "SPMWPROT2_WP_11_3,write protect SPMEM11 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x8 14. "SPMWPROT2_WP_11_2,write protect SPMEM11 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x8 13. "SPMWPROT2_WP_11_1,write protect SPMEM11 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x8 12. "SPMWPROT2_WP_11_0,write protect SPMEM11 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x8 11. "SPMWPROT2_WP_10_3,write protect SPMEM10 - DATA3" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x8 10. "SPMWPROT2_WP_10_2,write protect SPMEM610- DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x8 9. "SPMWPROT2_WP_10_1,write protect SPMEM10 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x8 8. "SPMWPROT2_WP_10_0,write protect SPMEM10 - DATA0" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x8 7. "SPMWPROT2_WP_9_3,write protect SPMEM9 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x8 6. "SPMWPROT2_WP_9_2,write protect SPMEM9 - DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x8 5. "SPMWPROT2_WP_9_1,write protect SPMEM9 - DATA1" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x8 4. "SPMWPROT2_WP_9_0,write protect SPMEM9 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x8 3. "SPMWPROT2_WP_8_3,write protect SPMEM8 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x8 2. "SPMWPROT2_WP_8_2,write protect SPMEM8 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x8 1. "SPMWPROT2_WP_8_1,write protect SPMEM8 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x8 0. "SPMWPROT2_WP_8_0,write protect SPMEM8 - DATA0" "0: READWRITE,1: READONLY"
|
|
line.long 0xC "SPMWPROT3,Scratch Pad Memory Write Protect Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. "SPMWPROT3_KEY,need to write (KEY=0xE8) to update this register"
|
|
bitfld.long 0xC 15. "SPMWPROT3_WP_15_3,write protect SPMEM15 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0xC 14. "SPMWPROT3_WP_15_2,write protect SPMEM15 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0xC 13. "SPMWPROT3_WP_15_1,write protect SPMEM15 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0xC 12. "SPMWPROT3_WP_15_0,write protect SPMEM15 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0xC 11. "SPMWPROT3_WP_14_3,write protect SPMEM14 - DATA3" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0xC 10. "SPMWPROT3_WP_14_2,write protect SPMEM14- DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0xC 9. "SPMWPROT3_WP_14_1,write protect SPMEM14 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0xC 8. "SPMWPROT3_WP_14_0,write protect SPMEM14 - DATA0" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0xC 7. "SPMWPROT3_WP_13_3,write protect SPMEM13 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0xC 6. "SPMWPROT3_WP_13_2,write protect SPMEM13 - DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0xC 5. "SPMWPROT3_WP_13_1,write protect SPMEM13 - DATA1" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0xC 4. "SPMWPROT3_WP_13_0,write protect SPMEM13 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0xC 3. "SPMWPROT3_WP_12_3,write protect SPMEM12 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0xC 2. "SPMWPROT3_WP_12_2,write protect SPMEM12 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0xC 1. "SPMWPROT3_WP_12_1,write protect SPMEM12 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0xC 0. "SPMWPROT3_WP_12_0,write protect SPMEM12 - DATA0" "0: READWRITE,1: READONLY"
|
|
line.long 0x10 "SPMWPROT4,Scratch Pad Memory Write Protect Register 4"
|
|
hexmask.long.byte 0x10 24.--31. 1. "SPMWPROT4_KEY,need to write (KEY=0xE8) to update this register"
|
|
bitfld.long 0x10 15. "SPMWPROT4_WP_19_3,write protect SPMEM19 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x10 14. "SPMWPROT4_WP_19_2,write protect SPMEM19 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x10 13. "SPMWPROT4_WP_19_1,write protect SPMEM19 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x10 12. "SPMWPROT4_WP_19_0,write protect SPMEM19 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x10 11. "SPMWPROT4_WP_18_3,write protect SPMEM18 - DATA3" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x10 10. "SPMWPROT4_WP_18_2,write protect SPMEM18- DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x10 9. "SPMWPROT4_WP_18_1,write protect SPMEM18 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x10 8. "SPMWPROT4_WP_18_0,write protect SPMEM18 - DATA0" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x10 7. "SPMWPROT4_WP_17_3,write protect SPMEM17 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x10 6. "SPMWPROT4_WP_17_2,write protect SPMEM17 - DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x10 5. "SPMWPROT4_WP_17_1,write protect SPMEM17 - DATA1" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x10 4. "SPMWPROT4_WP_17_0,write protect SPMEM17 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x10 3. "SPMWPROT4_WP_16_3,write protect SPMEM16 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x10 2. "SPMWPROT4_WP_16_2,write protect SPMEM16 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x10 1. "SPMWPROT4_WP_16_1,write protect SPMEM16 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x10 0. "SPMWPROT4_WP_16_0,write protect SPMEM16 - DATA0" "0: READWRITE,1: READONLY"
|
|
line.long 0x14 "SPMWPROT5,Scratch Pad Memory Write Protect Register 5"
|
|
hexmask.long.byte 0x14 24.--31. 1. "SPMWPROT5_KEY,need to write (KEY=0xE8) to update this register"
|
|
bitfld.long 0x14 15. "SPMWPROT5_WP_23_3,write protect SPMEM23 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x14 14. "SPMWPROT5_WP_23_2,write protect SPMEM23 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x14 13. "SPMWPROT5_WP_23_1,write protect SPMEM23 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x14 12. "SPMWPROT5_WP_23_0,write protect SPMEM23 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x14 11. "SPMWPROT5_WP_22_3,write protect SPMEM22 - DATA3" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x14 10. "SPMWPROT5_WP_22_2,write protect SPMEM22- DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x14 9. "SPMWPROT5_WP_22_1,write protect SPMEM22 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x14 8. "SPMWPROT5_WP_22_0,write protect SPMEM22 - DATA0" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x14 7. "SPMWPROT5_WP_21_3,write protect SPMEM21 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x14 6. "SPMWPROT5_WP_21_2,write protect SPMEM21 - DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x14 5. "SPMWPROT5_WP_21_1,write protect SPMEM21 - DATA1" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x14 4. "SPMWPROT5_WP_21_0,write protect SPMEM21 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x14 3. "SPMWPROT5_WP_20_3,write protect SPMEM20 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x14 2. "SPMWPROT5_WP_20_2,write protect SPMEM20 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x14 1. "SPMWPROT5_WP_20_1,write protect SPMEM20 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x14 0. "SPMWPROT5_WP_20_0,write protect SPMEM20 - DATA0" "0: READWRITE,1: READONLY"
|
|
line.long 0x18 "SPMWPROT6,Scratch Pad Memory Write Protect Register 6"
|
|
hexmask.long.byte 0x18 24.--31. 1. "SPMWPROT6_KEY,need to write (KEY=0xE8) to update this register"
|
|
bitfld.long 0x18 15. "SPMWPROT6_WP_27_3,write protect SPMEM27 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x18 14. "SPMWPROT6_WP_27_2,write protect SPMEM27 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x18 13. "SPMWPROT6_WP_27_1,write protect SPMEM27 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x18 12. "SPMWPROT6_WP_27_0,write protect SPMEM27 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x18 11. "SPMWPROT6_WP_26_3,write protect SPMEM26 - DATA3" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x18 10. "SPMWPROT6_WP_26_2,write protect SPMEM26- DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x18 9. "SPMWPROT6_WP_26_1,write protect SPMEM26 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x18 8. "SPMWPROT6_WP_26_0,write protect SPMEM26 - DATA0" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x18 7. "SPMWPROT6_WP_25_3,write protect SPMEM25 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x18 6. "SPMWPROT6_WP_25_2,write protect SPMEM25 - DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x18 5. "SPMWPROT6_WP_25_1,write protect SPMEM25 - DATA1" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x18 4. "SPMWPROT6_WP_25_0,write protect SPMEM25 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x18 3. "SPMWPROT6_WP_24_3,write protect SPMEM24 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x18 2. "SPMWPROT6_WP_24_2,write protect SPMEM24 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x18 1. "SPMWPROT6_WP_24_1,write protect SPMEM24 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x18 0. "SPMWPROT6_WP_24_0,write protect SPMEM24 - DATA0" "0: READWRITE,1: READONLY"
|
|
line.long 0x1C "SPMWPROT7,Scratch Pad Memory Write Protect Register 7"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "SPMWPROT7_KEY,need to write (KEY=0xE8) to update this register"
|
|
bitfld.long 0x1C 15. "SPMWPROT7_WP_31_3,write protect SPMEM31 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x1C 14. "SPMWPROT7_WP_31_2,write protect SPMEM31 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x1C 13. "SPMWPROT7_WP_31_1,write protect SPMEM31 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x1C 12. "SPMWPROT7_WP_31_0,write protect SPMEM31 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x1C 11. "SPMWPROT7_WP_30_3,write protect SPMEM30 - DATA3" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x1C 10. "SPMWPROT7_WP_30_2,write protect SPMEM30- DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x1C 9. "SPMWPROT7_WP_30_1,write protect SPMEM30 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x1C 8. "SPMWPROT7_WP_30_0,write protect SPMEM30 - DATA0" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x1C 7. "SPMWPROT7_WP_29_3,write protect SPMEM29 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x1C 6. "SPMWPROT7_WP_29_2,write protect SPMEM29 - DATA2" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x1C 5. "SPMWPROT7_WP_29_1,write protect SPMEM29 - DATA1" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x1C 4. "SPMWPROT7_WP_29_0,write protect SPMEM29 - DATA0" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x1C 3. "SPMWPROT7_WP_28_3,write protect SPMEM28 - DATA3" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x1C 2. "SPMWPROT7_WP_28_2,write protect SPMEM28 - DATA2" "0: READWRITE,1: READONLY"
|
|
newline
|
|
bitfld.long 0x1C 1. "SPMWPROT7_WP_28_1,write protect SPMEM28 - DATA1" "0: READWRITE,1: READONLY"
|
|
bitfld.long 0x1C 0. "SPMWPROT7_WP_28_0,write protect SPMEM28 - DATA0" "0: READWRITE,1: READONLY"
|
|
group.long 0x1540++0x1F
|
|
line.long 0x0 "SPMTERASE0,Scratch Pad Memory Tamper Erase Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SPMTERASE0_KEY,need to write (KEY=0xA3) to update this register"
|
|
bitfld.long 0x0 15. "SPMTERASE0_TE_3_3,tamper erase enable SPMEM3 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 14. "SPMTERASE0_TE_3_2,tamper erase enable SPMEM3 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 13. "SPMTERASE0_TE_3_1,tamper erase enable SPMEM3 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12. "SPMTERASE0_TE_3_0,tamper erase enable SPMEM3 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 11. "SPMTERASE0_TE_2_3,tamper erase enable SPMEM2 - DATA3" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 10. "SPMTERASE0_TE_2_2,tamper erase enable SPMEM2 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 9. "SPMTERASE0_TE_2_1,tamper erase enable SPMEM2 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 8. "SPMTERASE0_TE_2_0,tamper erase enable SPMEM2 - DATA0" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 7. "SPMTERASE0_TE_1_3,tamper erase enable SPMEM1 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 6. "SPMTERASE0_TE_1_2,tamper erase enable SPMEM1 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "SPMTERASE0_TE_1_1,tamper erase enable SPMEM1 - DATA1" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 4. "SPMTERASE0_TE_1_0,tamper erase enable SPMEM1 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "SPMTERASE0_TE_0_3,tamper erase enable SPMEM0 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "SPMTERASE0_TE_0_2,tamper erase enable SPMEM0 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "SPMTERASE0_TE_0_1,tamper erase enable SPMEM0 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "SPMTERASE0_TE_0_0,tamper erase enable SPMEM0 - DATA0" "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "SPMTERASE1,Scratch Pad Memory Tamper Erase Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "SPMTERASE1_KEY,need to write (KEY=0xA3) to update this register"
|
|
bitfld.long 0x4 15. "SPMTERASE1_TE_7_3,tamper erase enable SPMEM7 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 14. "SPMTERASE1_TE_7_2,tamper erase enable SPMEM7 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 13. "SPMTERASE1_TE_7_1,tamper erase enable SPMEM7 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 12. "SPMTERASE1_TE_7_0,tamper erase enable SPMEM7 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 11. "SPMTERASE1_TE_6_3,tamper erase enable SPMEM6 - DATA3" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 10. "SPMTERASE1_TE_6_2,tamper erase enable SPMEM6 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 9. "SPMTERASE1_TE_6_1,tamper erase enable SPMEM6 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "SPMTERASE1_TE_6_0,tamper erase enable SPMEM6 - DATA0" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 7. "SPMTERASE1_TE_5_3,tamper erase enable SPMEM5 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "SPMTERASE1_TE_5_2,tamper erase enable SPMEM5 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "SPMTERASE1_TE_5_1,tamper erase enable SPMEM5 - DATA1" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4. "SPMTERASE1_TE_5_0,tamper erase enable SPMEM5 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 3. "SPMTERASE1_TE_4_3,tamper erase enable SPMEM4 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "SPMTERASE1_TE_4_2,tamper erase enable SPMEM4 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "SPMTERASE1_TE_4_1,tamper erase enable SPMEM4 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "SPMTERASE1_TE_4_0,tamper erase enable SPMEM4 - DATA0" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "SPMTERASE2,Scratch Pad Memory Tamper Erase Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. "SPMTERASE2_KEY,need to write (KEY=0xA3) to update this register"
|
|
bitfld.long 0x8 15. "SPMTERASE2_TE_11_3,tamper erase enable SPMEM11 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 14. "SPMTERASE2_TE_11_2,tamper erase enable SPMEM11 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 13. "SPMTERASE2_TE_11_1,tamper erase enable SPMEM11 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 12. "SPMTERASE2_TE_11_0,tamper erase enable SPMEM11 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 11. "SPMTERASE2_TE_10_3,tamper erase enable SPMEM10 - DATA3" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 10. "SPMTERASE2_TE_10_2,tamper erase enable SPMEM10 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 9. "SPMTERASE2_TE_10_1,tamper erase enable SPMEM10 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 8. "SPMTERASE2_TE_10_0,tamper erase enable SPMEM10 - DATA0" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 7. "SPMTERASE2_TE_9_3,tamper erase enable SPMEM9 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 6. "SPMTERASE2_TE_9_2,tamper erase enable SPMEM9 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 5. "SPMTERASE2_TE_9_1,tamper erase enable SPMEM9 - DATA1" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 4. "SPMTERASE2_TE_9_0,tamper erase enable SPMEM9 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 3. "SPMTERASE2_TE_8_3,tamper erase enable SPMEM8 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 2. "SPMTERASE2_TE_8_2,tamper erase enable SPMEM8 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x8 1. "SPMTERASE2_TE_8_1,tamper erase enable SPMEM8 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x8 0. "SPMTERASE2_TE_8_0,tamper erase enable SPMEM8 - DATA0" "0: DISABLE,1: ENABLE"
|
|
line.long 0xC "SPMTERASE3,Scratch Pad Memory Tamper Erase Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. "SPMTERASE3_KEY,need to write (KEY=0xA3) to update this register"
|
|
bitfld.long 0xC 15. "SPMTERASE3_TE_15_3,tamper erase enable SPMEM15 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0xC 14. "SPMTERASE3_TE_15_2,tamper erase enable SPMEM15 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0xC 13. "SPMTERASE3_TE_15_1,tamper erase enable SPMEM15 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0xC 12. "SPMTERASE3_TE_15_0,tamper erase enable SPMEM15 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0xC 11. "SPMTERASE3_TE_14_3,tamper erase enable SPMEM14 - DATA3" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0xC 10. "SPMTERASE3_TE_14_2,tamper erase enable SPMEM14 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0xC 9. "SPMTERASE3_TE_14_1,tamper erase enable SPMEM14 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0xC 8. "SPMTERASE3_TE_14_0,tamper erase enable SPMEM14 - DATA0" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0xC 7. "SPMTERASE3_TE_13_3,tamper erase enable SPMEM13 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0xC 6. "SPMTERASE3_TE_13_2,tamper erase enable SPMEM13 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0xC 5. "SPMTERASE3_TE_13_1,tamper erase enable SPMEM13 - DATA1" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0xC 4. "SPMTERASE3_TE_13_0,tamper erase enable SPMEM13 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0xC 3. "SPMTERASE3_TE_12_3,tamper erase enable SPMEM12 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0xC 2. "SPMTERASE3_TE_12_2,tamper erase enable SPMEM12 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0xC 1. "SPMTERASE3_TE_12_1,tamper erase enable SPMEM12 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0xC 0. "SPMTERASE3_TE_12_0,tamper erase enable SPMEM12 - DATA0" "0: DISABLE,1: ENABLE"
|
|
line.long 0x10 "SPMTERASE4,Scratch Pad Memory Tamper Erase Register 4"
|
|
hexmask.long.byte 0x10 24.--31. 1. "SPMTERASE4_KEY,need to write (KEY=0xA3) to update this register"
|
|
bitfld.long 0x10 15. "SPMTERASE4_TE_19_3,tamper erase enable SPMEM19 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 14. "SPMTERASE4_TE_19_2,tamper erase enable SPMEM19 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x10 13. "SPMTERASE4_TE_19_1,tamper erase enable SPMEM19 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 12. "SPMTERASE4_TE_19_0,tamper erase enable SPMEM19 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 11. "SPMTERASE4_TE_18_3,tamper erase enable SPMEM18 - DATA3" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x10 10. "SPMTERASE4_TE_18_2,tamper erase enable SPMEM18 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 9. "SPMTERASE4_TE_18_1,tamper erase enable SPMEM18 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 8. "SPMTERASE4_TE_18_0,tamper erase enable SPMEM18 - DATA0" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x10 7. "SPMTERASE4_TE_17_3,tamper erase enable SPMEM17 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 6. "SPMTERASE4_TE_17_2,tamper erase enable SPMEM17 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 5. "SPMTERASE4_TE_17_1,tamper erase enable SPMEM17 - DATA1" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x10 4. "SPMTERASE4_TE_17_0,tamper erase enable SPMEM17 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 3. "SPMTERASE4_TE_16_3,tamper erase enable SPMEM16 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 2. "SPMTERASE4_TE_16_2,tamper erase enable SPMEM16 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x10 1. "SPMTERASE4_TE_16_1,tamper erase enable SPMEM16 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x10 0. "SPMTERASE4_TE_16_0,tamper erase enable SPMEM16 - DATA0" "0: DISABLE,1: ENABLE"
|
|
line.long 0x14 "SPMTERASE5,Scratch Pad Memory Tamper Erase Register 5"
|
|
hexmask.long.byte 0x14 24.--31. 1. "SPMTERASE5_KEY,need to write (KEY=0xA3) to update this register"
|
|
bitfld.long 0x14 15. "SPMTERASE5_TE_23_3,tamper erase enable SPMEM23 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 14. "SPMTERASE5_TE_23_2,tamper erase enable SPMEM23 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x14 13. "SPMTERASE5_TE_23_1,tamper erase enable SPMEM23 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 12. "SPMTERASE5_TE_23_0,tamper erase enable SPMEM23 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 11. "SPMTERASE5_TE_22_3,tamper erase enable SPMEM22 - DATA3" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x14 10. "SPMTERASE5_TE_22_2,tamper erase enable SPMEM22 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 9. "SPMTERASE5_TE_22_1,tamper erase enable SPMEM22 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 8. "SPMTERASE5_TE_22_0,tamper erase enable SPMEM22 - DATA0" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x14 7. "SPMTERASE5_TE_21_3,tamper erase enable SPMEM21 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 6. "SPMTERASE5_TE_21_2,tamper erase enable SPMEM21 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 5. "SPMTERASE5_TE_21_1,tamper erase enable SPMEM21 - DATA1" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x14 4. "SPMTERASE5_TE_21_0,tamper erase enable SPMEM21 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 3. "SPMTERASE5_TE_20_3,tamper erase enable SPMEM20 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 2. "SPMTERASE5_TE_20_2,tamper erase enable SPMEM20 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x14 1. "SPMTERASE5_TE_20_1,tamper erase enable SPMEM20 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x14 0. "SPMTERASE5_TE_20_0,tamper erase enable SPMEM20 - DATA0" "0: DISABLE,1: ENABLE"
|
|
line.long 0x18 "SPMTERASE6,Scratch Pad Memory Tamper Erase Register 6"
|
|
hexmask.long.byte 0x18 24.--31. 1. "SPMTERASE6_KEY,need to write (KEY=0xA3) to update this register"
|
|
bitfld.long 0x18 15. "SPMTERASE6_TE_27_3,tamper erase enable SPMEM27 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 14. "SPMTERASE6_TE_27_2,tamper erase enable SPMEM27 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x18 13. "SPMTERASE6_TE_27_1,tamper erase enable SPMEM27 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 12. "SPMTERASE6_TE_27_0,tamper erase enable SPMEM27 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 11. "SPMTERASE6_TE_26_3,tamper erase enable SPMEM26 - DATA3" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x18 10. "SPMTERASE6_TE_26_2,tamper erase enable SPMEM26 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 9. "SPMTERASE6_TE_26_1,tamper erase enable SPMEM26 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 8. "SPMTERASE6_TE_26_0,tamper erase enable SPMEM26 - DATA0" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x18 7. "SPMTERASE6_TE_25_3,tamper erase enable SPMEM25 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 6. "SPMTERASE6_TE_25_2,tamper erase enable SPMEM25 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 5. "SPMTERASE6_TE_25_1,tamper erase enable SPMEM25 - DATA1" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x18 4. "SPMTERASE6_TE_25_0,tamper erase enable SPMEM25 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 3. "SPMTERASE6_TE_24_3,tamper erase enable SPMEM24 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 2. "SPMTERASE6_TE_24_2,tamper erase enable SPMEM24 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x18 1. "SPMTERASE6_TE_24_1,tamper erase enable SPMEM24 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x18 0. "SPMTERASE6_TE_24_0,tamper erase enable SPMEM24 - DATA0" "0: DISABLE,1: ENABLE"
|
|
line.long 0x1C "SPMTERASE7,Scratch Pad Memory Tamper Erase Register 7"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "SPMTERASE7_KEY,need to write (KEY=0xA3) to update this register"
|
|
bitfld.long 0x1C 15. "SPMTERASE7_TE_31_3,tamper erase enable SPMEM31 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 14. "SPMTERASE7_TE_31_2,tamper erase enable SPMEM31 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x1C 13. "SPMTERASE7_TE_31_1,tamper erase enable SPMEM31 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 12. "SPMTERASE7_TE_31_0,tamper erase enable SPMEM31 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 11. "SPMTERASE7_TE_30_3,tamper erase enable SPMEM30 - DATA3" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x1C 10. "SPMTERASE7_TE_30_2,tamper erase enable SPMEM30 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 9. "SPMTERASE7_TE_30_1,tamper erase enable SPMEM30 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 8. "SPMTERASE7_TE_30_0,tamper erase enable SPMEM30 - DATA0" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x1C 7. "SPMTERASE7_TE_29_3,tamper erase enable SPMEM29 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 6. "SPMTERASE7_TE_29_2,tamper erase enable SPMEM29 - DATA2" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 5. "SPMTERASE7_TE_29_1,tamper erase enable SPMEM29 - DATA1" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x1C 4. "SPMTERASE7_TE_29_0,tamper erase enable SPMEM29 - DATA0" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 3. "SPMTERASE7_TE_28_3,tamper erase enable SPMEM28 - DATA3" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 2. "SPMTERASE7_TE_28_2,tamper erase enable SPMEM28 - DATA2" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x1C 1. "SPMTERASE7_TE_28_1,tamper erase enable SPMEM28 - DATA1" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x1C 0. "SPMTERASE7_TE_28_0,tamper erase enable SPMEM28 - DATA0" "0: DISABLE,1: ENABLE"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*"))
|
|
tree "MATHACL"
|
|
base ad:0x40410000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "CTL,Control Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "CTL_NUMITER,Number of iterations applicable if the function does the computations iteratively for example sine/cosine/atan2/sqrt."
|
|
bitfld.long 0x0 22. "CTL_SATEN,Saturation enable" "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0x0 16.--21. 1. "CTL_SFACTOR,Scaling factor. In case of SQRT function the input operand needs to be in a range. If not it has to be scaled to 2^(+/-n). This field should be written with the value 'n'."
|
|
hexmask.long.byte 0x0 8.--12. 1. "CTL_QVAL,Indicates the fractional bits in the operands ranges from 0 to 31. Applicable to DIV function."
|
|
newline
|
|
bitfld.long 0x0 5. "CTL_OPTYPE,Operand type could signed or unsigned. applicable to DIV function." "0: UNSIGNED,1: SIGNED"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CTL_FUNC,ULP_ADCHP Enable Conversions."
|
|
group.long 0x1118++0xF
|
|
line.long 0x0 "OP2,Operand 2 register."
|
|
hexmask.long 0x0 0.--31. 1. "OP2_DATA,Operand 2 Register"
|
|
line.long 0x4 "OP1,Operand 1 register."
|
|
hexmask.long 0x4 0.--31. 1. "OP1_DATA,Operand 1 register."
|
|
line.long 0x8 "RES1,Result 1 register."
|
|
hexmask.long 0x8 0.--31. 1. "RES1_DATA,Result 1 register"
|
|
line.long 0xC "RES2,Result 2 register."
|
|
hexmask.long 0xC 0.--31. 1. "RES2_DATA,Result 2 register"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "STATUS,Status Register"
|
|
bitfld.long 0x0 8. "STATUS_BUSY,MATHACL busy bit." "0: DONE,1: NOTDONE"
|
|
bitfld.long 0x0 2.--3. "STATUS_ERR,Incorrect inputs/outputs." "0: NOERROR,1: DIVBY0,?,?"
|
|
bitfld.long 0x0 1. "STATUS_OVF,Overflow bit for MPY32 SQUARE32 DIV MAC and SAC functions" "0,1"
|
|
bitfld.long 0x0 0. "STATUS_UF,Underflow Flag" "0: NO_UNDERFLOW,1: UNDERFLOW"
|
|
wgroup.long 0x1140++0x3
|
|
line.long 0x0 "STATUSCLR,Status flag clear register"
|
|
bitfld.long 0x0 2. "STATUSCLR_CLR_ERR,Write 1 to this bit to clear STATUS.ERR field" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "STATUSCLR_CLR_OVF,Write 1 to this bit to clear STATUS.OVF bit" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "STATUSCLR_CLR_UF,Write 1 to this bit to clear STATUS.UF bit" "0: NO_EFFECT,1: CLR"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G150*")||cpuis("MSPM0G350*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "OPA (Operational Amplifier)"
|
|
base ad:0x0
|
|
tree "OPA0"
|
|
base ad:0x40020000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1010++0x3
|
|
line.long 0x0 "CLKOVR,Clock Override"
|
|
bitfld.long 0x0 1. "CLKOVR_RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: RUN,1: STOP"
|
|
bitfld.long 0x0 0. "CLKOVR_OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: DISABLED,1: ENABLED"
|
|
group.long 0x101C++0x3
|
|
line.long 0x0 "PWRCTL,Power Control"
|
|
bitfld.long 0x0 0. "PWRCTL_AUTO_OFF,When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CTL,Control Register"
|
|
bitfld.long 0x0 0. "CTL_ENABLE,OAxn Enable." "0: OFF,1: ON"
|
|
line.long 0x4 "CFGBASE,Configuration Base Register"
|
|
bitfld.long 0x4 2. "CFGBASE_RRI,Rail-to-rail input enable. Can only be modified when STAT.BUSY=0" "0: OFF,1: ON"
|
|
bitfld.long 0x4 0. "CFGBASE_GBW,Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0." "0: LOWGAIN,1: HIGHGAIN"
|
|
line.long 0x8 "CFG,Configuration Register"
|
|
bitfld.long 0x8 13.--15. "CFG_GAIN,Gain setting. Refer to TRM for enumeration information." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 10.--12. "CFG_MSEL,MSEL Mux selection." "0: NC,1: EXTNPIN1,2: VSS,3: DAC12OUT,4: OANM1RTOP,?,?,?"
|
|
bitfld.long 0x8 7.--9. "CFG_NSEL,Negative OA input selection." "0: NC,1: EXTPIN0,2: EXTPIN1,3: OANP1RBOT,4: OANRTAP,5: OANRTOP,6: SPARE,?"
|
|
hexmask.long.byte 0x8 3.--6. 1. "CFG_PSEL,Positive OA input selection."
|
|
newline
|
|
bitfld.long 0x8 2. "CFG_OUTPIN,Enable output pin" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x8 0.--1. "CFG_CHOP,Chopping enable." "0: OFF,1: ON,2: AVGON,?"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 0. "STAT_RDY,OA ready status." "0: FALSE,1: TRUE"
|
|
tree.end
|
|
tree "OPA1"
|
|
base ad:0x40022000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1010++0x3
|
|
line.long 0x0 "CLKOVR,Clock Override"
|
|
bitfld.long 0x0 1. "CLKOVR_RUN_STOP,If [OVERRIDE] is enabled this register is used to manually control the peripheral's clock request to the system" "0: RUN,1: STOP"
|
|
bitfld.long 0x0 0. "CLKOVR_OVERRIDE,Unlocks the functionality of [RUN_STOP] to override the automatic peripheral clock request" "0: DISABLED,1: ENABLED"
|
|
group.long 0x101C++0x3
|
|
line.long 0x0 "PWRCTL,Power Control"
|
|
bitfld.long 0x0 0. "PWRCTL_AUTO_OFF,When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CTL,Control Register"
|
|
bitfld.long 0x0 0. "CTL_ENABLE,OAxn Enable." "0: OFF,1: ON"
|
|
line.long 0x4 "CFGBASE,Configuration Base Register"
|
|
bitfld.long 0x4 2. "CFGBASE_RRI,Rail-to-rail input enable. Can only be modified when STAT.BUSY=0" "0: OFF,1: ON"
|
|
bitfld.long 0x4 0. "CFGBASE_GBW,Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0." "0: LOWGAIN,1: HIGHGAIN"
|
|
line.long 0x8 "CFG,Configuration Register"
|
|
bitfld.long 0x8 13.--15. "CFG_GAIN,Gain setting. Refer to TRM for enumeration information." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 10.--12. "CFG_MSEL,MSEL Mux selection." "0: NC,1: EXTNPIN1,2: VSS,3: DAC12OUT,4: OANM1RTOP,?,?,?"
|
|
bitfld.long 0x8 7.--9. "CFG_NSEL,Negative OA input selection." "0: NC,1: EXTPIN0,2: EXTPIN1,3: OANP1RBOT,4: OANRTAP,5: OANRTOP,6: SPARE,?"
|
|
hexmask.long.byte 0x8 3.--6. 1. "CFG_PSEL,Positive OA input selection."
|
|
newline
|
|
bitfld.long 0x8 2. "CFG_OUTPIN,Enable output pin" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x8 0.--1. "CFG_CHOP,Chopping enable." "0: OFF,1: ON,2: AVGON,?"
|
|
rgroup.long 0x1118++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 0. "STAT_RDY,OA ready status." "0: FALSE,1: TRUE"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0x40094000
|
|
group.long 0x444++0x3
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1004++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_RT1PS,Enable Prescaler-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_RT0PS,Enable Prescaler-0 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_RTCA2,Enable Alarm-2 interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_RTCA1,Enable Alarm-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_RTCTEV,Enable Time-Event interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTCRDY,Enable RTC-Ready interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_RT1PS,Raw Prescaler-1 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_RT0PS,Raw Prescaler-0 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_RTCA2,Raw Alarm-2 interrupts status" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_RTCA1,Raw Alarm-1 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_RTCTEV,Raw Time-Event interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RTCRDY,Raw RTC-Ready interrupts status" "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_RT1PS,Masked Prescaler-1 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_RT0PS,Masked Prescaler-0 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_RTCA2,Masked Alarm-2 interrupt status" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_RTCA1,Masked Alarm-1 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_RTCTEV,Masked Time-Event interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RTCRDY,Masked RTC-Ready interrupt status" "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_RT1PS,Set Prescaler-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_RT0PS,Set Prescaler-0 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_RTCA2,Set Alarm-2 interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_RTCA1,Set Alarm-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_RTCTEV,Set Time-Event interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RTCRDY,Set RTC-Ready interrupt" "0: CLR,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_RT1PS,Clear Prescaler-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_RT0PS,Clear Prescaler-0 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_RTCA2,Clear Alarm-2 interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_RTCA1,Clear Alarm-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_RTCTEV,Clear Time-Event interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTCRDY,Clear RTC-Ready interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 5. "INT_EVENT1_IMASK_RT1PS,Enable Prescaler-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_IMASK_RT0PS,Enable Prescaler-0 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_RTCA2,Enable Alarm-2 interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_RTCA1,Enable Alarm-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_IMASK_RTCTEV,Enable Time-Event interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTCRDY,Enable RTC-Ready interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 5. "INT_EVENT1_RIS_RT1PS,Raw Prescaler-1 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_RIS_RT0PS,Raw Prescaler-0 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_RTCA2,Raw Alarm-2 interrupts status" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_RTCA1,Raw Alarm-1 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_RIS_RTCTEV,Raw Time-Event interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_RTCRDY,Raw RTC-Ready interrupts status" "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 5. "INT_EVENT1_MIS_RT1PS,Masked Prescaler-1 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_MIS_RT0PS,Masked Prescaler-0 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_RTCA2,Masked Alarm-2 interrupt status" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_RTCA1,Masked Alarm-1 interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_MIS_RTCTEV,Masked Time-Event interrupt status" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_RTCRDY,Masked RTC-Ready interrupt status" "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 5. "INT_EVENT1_ISET_RT1PS,Set Prescaler-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ISET_RT0PS,Set Prescaler-0 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_RTCA2,Set Alarm-2 interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_RTCA1,Set Alarm-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_ISET_RTCTEV,Set Time-Event interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_RTCRDY,Set RTC-Ready interrupt" "0: CLR,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 5. "INT_EVENT1_ICLR_RT1PS,Clear Prescaler-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT1_ICLR_RT0PS,Clear Prescaler-0 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_RTCA2,Clear Alarm-2 interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_RTCA1,Clear Alarm-1 interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT1_ICLR_RTCTEV,Clear Time-Event interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTCRDY,Clear RTC-Ready interrupt" "0: CLR,1: SET"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode 1 select" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode 0 select" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,RTC Descriptor Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identifier. This ID is unique for each module. 0x0911 = Module ID of the RTC Module"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature set of this module. Differentiates the complexity of the actually instantiated module if there are differences."
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instantiated version. Describes which instance of the module accessed."
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major revision. This number holds the module revision and is incremented by the module developers. n = Major version (see device-specific data sheet)"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor revision. This number holds the module revision and is incremented by the module developers. n = Minor module revision (see device-specific data sheet)"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CLKCTL,RTC Clock Control Register"
|
|
bitfld.long 0x0 31. "CLKCTL_MODCLKEN,This bit enables the supply of the 32kHz clock to the RTC. It will not power-up the 32kHz crystal oscillator this needs to be done in the Clock System Module." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "DBGCTL,RTC Module Debug Control Register"
|
|
bitfld.long 0x4 1. "DBGCTL_DBGINT,Debug Interrupt Enable." "0: OFF,1: ON"
|
|
bitfld.long 0x4 0. "DBGCTL_DBGRUN,Debug Run." "0: HALT,1: RUN"
|
|
line.long 0x8 "CTL,RTC Control Register"
|
|
bitfld.long 0x8 7. "CTL_RTCBCD,Real-time clock BCD select. Selects BCD counting for real-time clock." "0: BINARY,1: BCD"
|
|
bitfld.long 0x8 0.--1. "CTL_RTCTEVTX,Real-time clock time event." "0: MINUTE,1: HOUR,2: MIDNIGHT,3: NOON"
|
|
rgroup.long 0x110C++0x3
|
|
line.long 0x0 "STA,RTC Status Register"
|
|
bitfld.long 0x0 2. "STA_RTCTCOK,Real-time clock temperature compensation write OK. This is a read-only bit that indicates if the write to RTCTCMP is successful or not." "0: NOT_OK,1: OK"
|
|
bitfld.long 0x0 1. "STA_RTCTCRDY,Real-time clock temperature compensation ready. This is a read only bit that indicates when the RTCTCMPx can be written. Write to RTCTCMPx should be avoided when RTCTCRDY is reset." "0: NOT_READY,1: READY"
|
|
bitfld.long 0x0 0. "STA_RTCRDY,Real-time clock ready. This bit indicates when the real-time clock time values are safe for reading." "0: NOT_READY,1: READY"
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|
group.long 0x1110++0x3B
|
|
line.long 0x0 "CAL,RTC Clock Offset Calibration Register"
|
|
bitfld.long 0x0 16.--17. "CAL_RTCCALFX,Real-time clock calibration frequency. Selects frequency output to RTC_OUT pin for calibration measurement. The corresponding port must be configured for the peripheral module function." "0: OFF,1: F512HZ,2: F256HZ,3: F1HZ"
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|
bitfld.long 0x0 15. "CAL_RTCOCALS,Real-time clock offset error calibration sign. This bit decides the sign of offset error calibration." "0: DOWN,1: UP"
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|
hexmask.long.byte 0x0 0.--7. 1. "CAL_RTCOCALX,Real-time clock offset error calibration. Each LSB represents approximately +1ppm (RTCOCALXS = 1) or -1ppm (RTCOCALXS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm will.."
|
|
line.long 0x4 "TCMP,RTC Temperature Compensation Register"
|
|
bitfld.long 0x4 15. "TCMP_RTCTCMPS,Real-time clock temperature compensation sign. This bit decides the sign of temperature compensation." "0: DOWN,1: UP"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TCMP_RTCTCMPX,Real-time clock temperature compensation. Value written into this register is used for temperature compensation of RTC. Each LSB represents approximately +1ppm (RTCTCMPS = 1) or -1ppm (RTCTCMPS = 0) adjustment in frequency. Maximum.."
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|
line.long 0x8 "SEC,RTC Seconds Register - Calendar Mode With Binary / BCD Format"
|
|
bitfld.long 0x8 12.--14. "SEC_SECHIGHBCD,Seconds BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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|
hexmask.long.byte 0x8 8.--11. 1. "SEC_SECLOWBCD,Seconds BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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|
hexmask.long.byte 0x8 0.--5. 1. "SEC_SECBIN,Seconds Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
|
|
line.long 0xC "MIN,RTC Minutes Register - Calendar Mode With Binary / BCD Format"
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|
bitfld.long 0xC 12.--14. "MIN_MINHIGHBCD,Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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|
hexmask.long.byte 0xC 8.--11. 1. "MIN_MINLOWBCD,Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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|
hexmask.long.byte 0xC 0.--5. 1. "MIN_MINBIN,Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
|
|
line.long 0x10 "HOUR,RTC Hours Register - Calendar Mode With Binary / BCD Format"
|
|
bitfld.long 0x10 12.--13. "HOUR_HOURHIGHBCD,Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3"
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|
hexmask.long.byte 0x10 8.--11. 1. "HOUR_HOURLOWBCD,Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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|
hexmask.long.byte 0x10 0.--4. 1. "HOUR_HOURBIN,Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
|
|
line.long 0x14 "DAY,RTC Day Of Week / Month Register - Calendar Mode With Binary / BCD Format"
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bitfld.long 0x14 20.--21. "DAY_DOMHIGHBCD,Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3"
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|
hexmask.long.byte 0x14 16.--19. 1. "DAY_DOMLOWBCD,Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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|
hexmask.long.byte 0x14 8.--12. 1. "DAY_DOMBIN,Day of month Binary (1 to 28 29 30 31). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
|
|
newline
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bitfld.long 0x14 0.--2. "DAY_DOW,Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7"
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|
line.long 0x18 "MON,RTC Month Register - Calendar Mode With Binary / BCD Format"
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|
bitfld.long 0x18 12. "MON_MONHIGHBCD,Month BCD high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1"
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|
hexmask.long.byte 0x18 8.--11. 1. "MON_MONLOWBCD,Month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
|
|
hexmask.long.byte 0x18 0.--3. 1. "MON_MONBIN,Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
|
|
line.long 0x1C "YEAR,RTC Year Register - Calendar Mode With Binary / BCD Format"
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|
bitfld.long 0x1C 28.--30. "YEAR_CENTHIGHBCD,Century BCD high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x1C 24.--27. 1. "YEAR_CENTLOWBCD,Century BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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|
hexmask.long.byte 0x1C 20.--23. 1. "YEAR_DECADEBCD,Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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|
newline
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hexmask.long.byte 0x1C 16.--19. 1. "YEAR_YEARLOWESTBCD,Year BCD lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
|
|
hexmask.long.byte 0x1C 8.--11. 1. "YEAR_YEARHIGHBIN,Year Binary high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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|
hexmask.long.byte 0x1C 0.--7. 1. "YEAR_YEARLOWBIN,Year Binary low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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|
line.long 0x20 "A1MIN,RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format"
|
|
bitfld.long 0x20 15. "A1MIN_AMINAEBCD,Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x20 12.--14. "A1MIN_AMINHIGHBCD,Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
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|
hexmask.long.byte 0x20 8.--11. 1. "A1MIN_AMINLOWBCD,Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
|
|
newline
|
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bitfld.long 0x20 7. "A1MIN_AMINAEBIN,Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0x20 0.--5. 1. "A1MIN_AMINBIN,Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
|
|
line.long 0x24 "A1HOUR,RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format"
|
|
bitfld.long 0x24 15. "A1HOUR_AHOURAEBCD,Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x24 12.--13. "A1HOUR_AHOURHIGHBCD,Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.." "0,1,2,3"
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|
hexmask.long.byte 0x24 8.--11. 1. "A1HOUR_AHOURLOWBCD,Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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|
newline
|
|
bitfld.long 0x24 7. "A1HOUR_AHOURAEBIN,Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0x24 0.--4. 1. "A1HOUR_AHOURBIN,Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
|
|
line.long 0x28 "A1DAY,RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format"
|
|
bitfld.long 0x28 23. "A1DAY_ADOMAEBCD,Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x28 20.--21. "A1DAY_ADOMHIGHBCD,Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3"
|
|
hexmask.long.byte 0x28 16.--19. 1. "A1DAY_ADOMLOWBCD,Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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|
newline
|
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bitfld.long 0x28 15. "A1DAY_ADOMAEBIN,Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
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|
hexmask.long.byte 0x28 8.--12. 1. "A1DAY_ADOMBIN,Alarm Day of month Binary (1 to 28 29 30 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0."
|
|
bitfld.long 0x28 7. "A1DAY_ADOWAE,Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x28 0.--2. "A1DAY_ADOW,Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7"
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|
line.long 0x2C "A2MIN,RTC Minute Alarm Register - Calendar Mode With Binary / BCD Format"
|
|
bitfld.long 0x2C 15. "A2MIN_AMINAEBCD,Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x2C 12.--14. "A2MIN_AMINHIGHBCD,Alarm Minutes BCD high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x2C 8.--11. 1. "A2MIN_AMINLOWBCD,Alarm Minutes BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
|
|
newline
|
|
bitfld.long 0x2C 7. "A2MIN_AMINAEBIN,Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0x2C 0.--5. 1. "A2MIN_AMINBIN,Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
|
|
line.long 0x30 "A2HOUR,RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format"
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|
bitfld.long 0x30 15. "A2HOUR_AHOURAEBCD,Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x30 12.--13. "A2HOUR_AHOURHIGHBCD,Alarm Hours BCD high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.." "0,1,2,3"
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|
hexmask.long.byte 0x30 8.--11. 1. "A2HOUR_AHOURLOWBCD,Alarm Hours BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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|
newline
|
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bitfld.long 0x30 7. "A2HOUR_AHOURAEBIN,Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
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hexmask.long.byte 0x30 0.--4. 1. "A2HOUR_AHOURBIN,Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0."
|
|
line.long 0x34 "A2DAY,RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format"
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|
bitfld.long 0x34 23. "A2DAY_ADOMAEBCD,Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
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bitfld.long 0x34 20.--21. "A2DAY_ADOMHIGHBCD,Alarm Day of month BCD high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0." "0,1,2,3"
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|
hexmask.long.byte 0x34 16.--19. 1. "A2DAY_ADOMLOWBCD,Alarm Day of month BCD low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0."
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|
newline
|
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bitfld.long 0x34 15. "A2DAY_ADOMAEBIN,Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored." "0: DISABLE,1: ENABLE"
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hexmask.long.byte 0x34 8.--12. 1. "A2DAY_ADOMBIN,Alarm Day of month Binary (1 to 28 29 30 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0."
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bitfld.long 0x34 7. "A2DAY_ADOWAE,Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x34 0.--2. "A2DAY_ADOW,Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0." "0,1,2,3,4,5,6,7"
|
|
line.long 0x38 "PSCTL,RTC Prescale Timer 0/1 Control Register"
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bitfld.long 0x38 18.--20. "PSCTL_RT1IP,Prescale timer 1 interrupt interval" "0: DIV2,1: DIV4,2: DIV8,3: DIV16,4: DIV32,5: DIV64,6: DIV128,7: DIV256"
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|
bitfld.long 0x38 2.--4. "PSCTL_RT0IP,Prescale timer 0 interrupt interval" "?,?,2: DIV8,3: DIV16,4: DIV32,5: DIV64,6: DIV128,7: DIV256"
|
|
tree.end
|
|
endif
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
tree "SPI0"
|
|
base ad:0x40468000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "IMASK_RXFULL,RX FIFO Full Interrupt Mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "IMASK_DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "IMASK_DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "IMASK_IDLE,SPI Idle event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_TXEMPTY,Transmit FIFO Empty event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "IMASK_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "IMASK_RTOUT,Enable SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "IMASK_PER,Parity error event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "IMASK_RXFIFO_OVF,RXFIFO overflow event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "RIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "RIS_DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "RIS_DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "RIS_IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_RTOUT,SPI Receive Time-Out event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "RIS_PER,Parity error event: this bit is set if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "RIS_RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "MIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_TXFIFO_UNF,TX FIFO underflow interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "MIS_DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "MIS_DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "MIS_IDLE,Masked SPI IDLE mode event." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_TXEMPTY,Masked Transmit FIFO Empty event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "MIS_RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_RTOUT,Masked SPI Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS_PER,Masked Parity error event: this bit if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "MIS_RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "ISET_RXFULL,Set RX FIFO Full Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_TXFIFO_UNF,Set TX FIFO Underflow Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "ISET_DMA_DONE_TX,Set DMA Done 1 event for TX." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "ISET_DMA_DONE_RX,Set DMA Done 1 event for RX." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "ISET_IDLE,Set SPI IDLE mode event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_TXEMPTY,Set Transmit FIFO Empty event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_RTOUT,Set SPI Receive Time-Out Event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_PER,Set Parity error event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "ISET_RXFIFO_OVF,Set RXFIFO overflow event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "ICLR_RXFULL,Clear RX FIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_TXFIFO_UNF,Clear TXFIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "ICLR_DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "ICLR_DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "ICLR_IDLE,Clear SPI IDLE mode event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_TXEMPTY,Clear Transmit FIFO Empty event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_RTOUT,Clear SPI Receive Time-Out Event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_PER,Clear Parity error event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "ICLR_RXFIFO_OVF,Clear RXFIFO overflow event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,SPI control register 0"
|
|
bitfld.long 0x0 14. "CTL0_CSCLR,Clear shift register counter on CS inactive" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12.--13. "CTL0_CSSEL,Select the CS line to control on data transfer" "0: CSSEL_0,1: CSSEL_1,2: CSSEL_2,3: CSSEL_3"
|
|
bitfld.long 0x0 9. "CTL0_SPH,CLKOUT phase (Motorola SPI frame format only)" "0: FIRST,1: SECOND"
|
|
newline
|
|
bitfld.long 0x0 8. "CTL0_SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 7. "CTL0_PACKEN,Packing Enable." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 5.--6. "CTL0_FRF,Frame format Select" "0: MOTOROLA_3WIRE,1: MOTOROLA_4WIRE,2: TI_SYNC,3: MIRCOWIRE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "CTL0_DSS,Data Size Select."
|
|
line.long 0x4 "CTL1,SPI control register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "CTL1_RXTIMEOUT,Receive Timeout (only for Peripheral mode)"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CTL1_REPEATTX,Counter to repeat last transfer"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CTL1_CDMODE,Command/Data Mode Value"
|
|
newline
|
|
bitfld.long 0x4 11. "CTL1_CDENABLE,Command/Data Mode enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "CTL1_PTEN,Parity transmit enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "CTL1_PES,Even Parity Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 5. "CTL1_PREN,Parity receive enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 4. "CTL1_MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 3. "CTL1_POD,Peripheral-mode: Data output disabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "CTL1_CP,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CTL1_LBM,Loop back mode" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,SPI enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "CLKCTL,Clock prescaler and divider register."
|
|
hexmask.long.byte 0x8 28.--31. 1. "CLKCTL_DSAMPLE,Delayed sampling value."
|
|
hexmask.long.word 0x8 0.--9. 1. "CLKCTL_SCR,Serial clock divider:"
|
|
line.long 0xC "IFLS,Interrupt FIFO Level Select Register"
|
|
bitfld.long 0xC 3.--5. "IFLS_RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_OFF,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_RES4,5: LVL_FULL,6: LVL_RES6,7: LEVEL_1"
|
|
bitfld.long 0xC 0.--2. "IFLS_TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: LVL_OFF,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,4: LVL_RES4,5: LVL_EMPTY,6: LVL_RES6,7: LEVEL_1"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 4. "STAT_BUSY,Busy" "0: IDLE,1: ACTIVE"
|
|
bitfld.long 0x0 3. "STAT_RNF,Receive FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 2. "STAT_RFE,Receive FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
newline
|
|
bitfld.long 0x0 1. "STAT_TNF,Transmit FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 0. "STAT_TFE,Transmit FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "RXDATA,RXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA_DATA,Received Data"
|
|
group.long 0x1140++0x3
|
|
line.long 0x0 "TXDATA,TXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA_DATA,Transmit Data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "SPI0"
|
|
base ad:0x40468000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXFULL,RX FIFO Full Interrupt Mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_IDLE,SPI Idle event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_TXEMPTY,Transmit FIFO Empty event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_RTOUT,Enable SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_PER,Parity error event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RXFIFO_OVF,RXFIFO overflow event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_RTOUT,SPI Receive Time-Out event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_PER,Parity error event: this bit is set if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_TXFIFO_UNF,TX FIFO underflow interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_IDLE,Masked SPI IDLE mode event." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_TXEMPTY,Masked Transmit FIFO Empty event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_RTOUT,Masked SPI Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_PER,Masked Parity error event: this bit if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXFULL,Set RX FIFO Full Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_TXFIFO_UNF,Set TX FIFO Underflow Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done 1 event for TX." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done 1 event for RX." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_IDLE,Set SPI IDLE mode event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_TXEMPTY,Set Transmit FIFO Empty event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_RTOUT,Set SPI Receive Time-Out Event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_PER,Set Parity error event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RXFIFO_OVF,Set RXFIFO overflow event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXFULL,Clear RX FIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_TXFIFO_UNF,Clear TXFIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_IDLE,Clear SPI IDLE mode event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_TXEMPTY,Clear Transmit FIFO Empty event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_RTOUT,Clear SPI Receive Time-Out Event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_PER,Clear Parity error event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RXFIFO_OVF,Clear RXFIFO overflow event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_RX,Receive FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_RTOUT,SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_RTOUT,SPI Receive Time-Out Event." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_RX,Receive FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_RTOUT,SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_RTOUT,Set SPI Receive Time-Out event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_RTOUT,Clear SPI Receive Time-Out event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 4. "INT_EVENT2_IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 4. "INT_EVENT2_RIS_TX,Transmit FIFO event:" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 4. "INT_EVENT2_MIS_TX,Masked Transmit FIFO event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 4. "INT_EVENT2_ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 4. "INT_EVENT2_ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,SPI control register 0"
|
|
bitfld.long 0x0 14. "CTL0_CSCLR,Clear shift register counter on CS inactive" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12.--13. "CTL0_CSSEL,Select the CS line to control on data transfer" "0: CSSEL_0,1: CSSEL_1,2: CSSEL_2,3: CSSEL_3"
|
|
bitfld.long 0x0 9. "CTL0_SPH,CLKOUT phase (Motorola SPI frame format only)" "0: FIRST,1: SECOND"
|
|
newline
|
|
bitfld.long 0x0 8. "CTL0_SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 7. "CTL0_PACKEN,Packing Enable." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 5.--6. "CTL0_FRF,Frame format Select" "0: MOTOROLA_3WIRE,1: MOTOROLA_4WIRE,2: TI_SYNC,3: MIRCOWIRE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "CTL0_DSS,Data Size Select."
|
|
line.long 0x4 "CTL1,SPI control register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "CTL1_RXTIMEOUT,Receive Timeout (only for Peripheral mode)"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CTL1_REPEATTX,Counter to repeat last transfer"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CTL1_CDMODE,Command/Data Mode Value"
|
|
newline
|
|
bitfld.long 0x4 11. "CTL1_CDENABLE,Command/Data Mode enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "CTL1_PTEN,Parity transmit enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 7. "CTL1_PBS,Parity Bit Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 6. "CTL1_PES,Even Parity Select" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "CTL1_PREN,Parity receive enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 4. "CTL1_MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "CTL1_SOD,Peripheral-mode: Data output disabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "CTL1_MS,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CTL1_LBM,Loop back mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,SPI enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "CLKCTL,Clock prescaler and divider register."
|
|
hexmask.long.byte 0x8 28.--31. 1. "CLKCTL_DSAMPLE,Delayed sampling value."
|
|
hexmask.long.word 0x8 0.--9. 1. "CLKCTL_SCR,Serial clock divider:"
|
|
line.long 0xC "IFLS,UART Interrupt FIFO Level Select Register"
|
|
bitfld.long 0xC 3.--5. "IFLS_RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_OFF,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_RES4,5: LVL_FULL,6: LVL_RES6,7: LEVEL_1"
|
|
bitfld.long 0xC 0.--2. "IFLS_TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: LVL_OFF,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,4: LVL_RES4,5: LVL_EMPTY,6: LVL_RES6,7: LEVEL_1"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 4. "STAT_BUSY,Busy" "0: IDLE,1: ACTIVE"
|
|
bitfld.long 0x0 3. "STAT_RNF,Receive FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 2. "STAT_RFE,Receive FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
newline
|
|
bitfld.long 0x0 1. "STAT_TNF,Transmit FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 0. "STAT_TFE,Transmit FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "RXDATA,RXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA_DATA,Received Data"
|
|
group.long 0x1140++0x3
|
|
line.long 0x0 "TXDATA,TXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA_DATA,Transmit Data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "SPI0"
|
|
base ad:0x40468000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXFULL,RX FIFO Full Interrupt Mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_IDLE,SPI Idle event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_TXEMPTY,Transmit FIFO Empty event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_RTOUT,Enable SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_PER,Parity error event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RXFIFO_OVF,RXFIFO overflow event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_RTOUT,SPI Receive Time-Out event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_PER,Parity error event: this bit is set if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_TXFIFO_UNF,TX FIFO underflow interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_IDLE,Masked SPI IDLE mode event." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_TXEMPTY,Masked Transmit FIFO Empty event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_RTOUT,Masked SPI Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_PER,Masked Parity error event: this bit if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXFULL,Set RX FIFO Full Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_TXFIFO_UNF,Set TX FIFO Underflow Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done 1 event for TX." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done 1 event for RX." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_IDLE,Set SPI IDLE mode event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_TXEMPTY,Set Transmit FIFO Empty event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_RTOUT,Set SPI Receive Time-Out Event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_PER,Set Parity error event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RXFIFO_OVF,Set RXFIFO overflow event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXFULL,Clear RX FIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_TXFIFO_UNF,Clear TXFIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_IDLE,Clear SPI IDLE mode event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_TXEMPTY,Clear Transmit FIFO Empty event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_RTOUT,Clear SPI Receive Time-Out Event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_PER,Clear Parity error event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RXFIFO_OVF,Clear RXFIFO overflow event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_RX,Receive FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_RTOUT,SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_RTOUT,SPI Receive Time-Out Event." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_RX,Receive FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_RTOUT,SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_RTOUT,Set SPI Receive Time-Out event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_RTOUT,Clear SPI Receive Time-Out event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 4. "INT_EVENT2_IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 4. "INT_EVENT2_RIS_TX,Transmit FIFO event:" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 4. "INT_EVENT2_MIS_TX,Masked Transmit FIFO event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 4. "INT_EVENT2_ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 4. "INT_EVENT2_ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,SPI control register 0"
|
|
bitfld.long 0x0 14. "CTL0_CSCLR,Clear shift register counter on CS inactive" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12.--13. "CTL0_CSSEL,Select the CS line to control on data transfer" "0: CSSEL_0,1: CSSEL_1,2: CSSEL_2,3: CSSEL_3"
|
|
bitfld.long 0x0 9. "CTL0_SPH,CLKOUT phase (Motorola SPI frame format only)" "0: FIRST,1: SECOND"
|
|
newline
|
|
bitfld.long 0x0 8. "CTL0_SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 7. "CTL0_PACKEN,Packing Enable." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 5.--6. "CTL0_FRF,Frame format Select" "0: MOTOROLA_3WIRE,1: MOTOROLA_4WIRE,2: TI_SYNC,3: MIRCOWIRE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "CTL0_DSS,Data Size Select."
|
|
line.long 0x4 "CTL1,SPI control register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "CTL1_RXTIMEOUT,Receive Timeout (only for Peripheral mode)"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CTL1_REPEATTX,Counter to repeat last transfer"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CTL1_CDMODE,Command/Data Mode Value"
|
|
newline
|
|
bitfld.long 0x4 11. "CTL1_CDENABLE,Command/Data Mode enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "CTL1_PTEN,Parity transmit enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 7. "CTL1_PBS,Parity Bit Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 6. "CTL1_PES,Even Parity Select" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "CTL1_PREN,Parity receive enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 4. "CTL1_MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "CTL1_SOD,Peripheral-mode: Data output disabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "CTL1_MS,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CTL1_LBM,Loop back mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,SPI enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "CLKCTL,Clock prescaler and divider register."
|
|
hexmask.long.byte 0x8 28.--31. 1. "CLKCTL_DSAMPLE,Delayed sampling value."
|
|
hexmask.long.word 0x8 0.--9. 1. "CLKCTL_SCR,Serial clock divider:"
|
|
line.long 0xC "IFLS,UART Interrupt FIFO Level Select Register"
|
|
bitfld.long 0xC 3.--5. "IFLS_RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_OFF,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_RES4,5: LVL_FULL,6: LVL_RES6,7: LEVEL_1"
|
|
bitfld.long 0xC 0.--2. "IFLS_TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: LVL_OFF,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,4: LVL_RES4,5: LVL_EMPTY,6: LVL_RES6,7: LEVEL_1"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 4. "STAT_BUSY,Busy" "0: IDLE,1: ACTIVE"
|
|
bitfld.long 0x0 3. "STAT_RNF,Receive FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 2. "STAT_RFE,Receive FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
newline
|
|
bitfld.long 0x0 1. "STAT_TNF,Transmit FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 0. "STAT_TFE,Transmit FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "RXDATA,RXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA_DATA,Received Data"
|
|
group.long 0x1140++0x3
|
|
line.long 0x0 "TXDATA,TXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA_DATA,Transmit Data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "SPI0"
|
|
base ad:0x40468000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "CPU_INT_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPU_INT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "CPU_INT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "CPU_INT_IMASK_RXFULL,RX FIFO Full Interrupt Mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_IMASK_TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_IMASK_DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_IMASK_DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_IMASK_IDLE,SPI Idle event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_IMASK_TXEMPTY,Transmit FIFO Empty event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_IMASK_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_IMASK_RTOUT,Enable SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_IMASK_PER,Parity error event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_IMASK_RXFIFO_OVF,RXFIFO overflow event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "CPU_INT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "CPU_INT_RIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_RIS_TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_RIS_DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_RIS_DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_RIS_IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_RIS_TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_RIS_TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_RIS_RTOUT,SPI Receive Time-Out event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_RIS_PER,Parity error event: this bit is set if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_RIS_RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "CPU_INT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "CPU_INT_MIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_MIS_TXFIFO_UNF,TX FIFO underflow interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_MIS_DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_MIS_DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_MIS_IDLE,Masked SPI IDLE mode event." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_MIS_TXEMPTY,Masked Transmit FIFO Empty event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_MIS_TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_MIS_RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_MIS_RTOUT,Masked SPI Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_MIS_PER,Masked Parity error event: this bit if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_MIS_RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "CPU_INT_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "CPU_INT_ISET_RXFULL,Set RX FIFO Full Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_ISET_TXFIFO_UNF,Set TX FIFO Underflow Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_ISET_DMA_DONE_TX,Set DMA Done 1 event for TX." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_ISET_DMA_DONE_RX,Set DMA Done 1 event for RX." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_ISET_IDLE,Set SPI IDLE mode event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_ISET_TXEMPTY,Set Transmit FIFO Empty event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_ISET_RTOUT,Set SPI Receive Time-Out Event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ISET_PER,Set Parity error event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_ISET_RXFIFO_OVF,Set RXFIFO overflow event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "CPU_INT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "CPU_INT_ICLR_RXFULL,Clear RX FIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "CPU_INT_ICLR_TXFIFO_UNF,Clear TXFIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "CPU_INT_ICLR_DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_ICLR_DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "CPU_INT_ICLR_IDLE,Clear SPI IDLE mode event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "CPU_INT_ICLR_TXEMPTY,Clear Transmit FIFO Empty event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "CPU_INT_ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "CPU_INT_ICLR_RTOUT,Clear SPI Receive Time-Out Event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ICLR_PER,Clear Parity error event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "CPU_INT_ICLR_RXFIFO_OVF,Clear RXFIFO overflow event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMA_TRIG_RX_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "DMA_TRIG_RX_IMASK_RX,Receive FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "DMA_TRIG_RX_IMASK_RTOUT,SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "DMA_TRIG_RX_RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "DMA_TRIG_RX_RIS_RTOUT,SPI Receive Time-Out Event." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "DMA_TRIG_RX_MIS_RX,Receive FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "DMA_TRIG_RX_MIS_RTOUT,SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "DMA_TRIG_RX_ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "DMA_TRIG_RX_ISET_RTOUT,Set SPI Receive Time-Out event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "DMA_TRIG_RX_ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "DMA_TRIG_RX_ICLR_RTOUT,Clear SPI Receive Time-Out event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMA_TRIG_TX_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 4. "DMA_TRIG_TX_IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 4. "DMA_TRIG_TX_RIS_TX,Transmit FIFO event:" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 4. "DMA_TRIG_TX_MIS_TX,Masked Transmit FIFO event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_ISET,Interrupt set"
|
|
bitfld.long 0x0 4. "DMA_TRIG_TX_ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 4. "DMA_TRIG_TX_ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,SPI control register 0"
|
|
bitfld.long 0x0 14. "CTL0_CSCLR,Clear shift register counter on CS inactive" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12.--13. "CTL0_CSSEL,Select the CS line to control on data transfer" "0: CSSEL_0,1: CSSEL_1,2: CSSEL_2,3: CSSEL_3"
|
|
bitfld.long 0x0 9. "CTL0_SPH,CLKOUT phase (Motorola SPI frame format only)" "0: FIRST,1: SECOND"
|
|
newline
|
|
bitfld.long 0x0 8. "CTL0_SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 7. "CTL0_PACKEN,Packing Enable." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 5.--6. "CTL0_FRF,Frame format Select" "0: MOTOROLA_3WIRE,1: MOTOROLA_4WIRE,2: TI_SYNC,3: MIRCOWIRE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "CTL0_DSS,Data Size Select."
|
|
line.long 0x4 "CTL1,SPI control register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "CTL1_RXTIMEOUT,Receive Timeout (only for Peripheral mode)"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CTL1_REPEATTX,Counter to repeat last transfer"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CTL1_CDMODE,Command/Data Mode Value"
|
|
newline
|
|
bitfld.long 0x4 11. "CTL1_CDENABLE,Command/Data Mode enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "CTL1_PTEN,Parity transmit enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "CTL1_PES,Even Parity Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 5. "CTL1_PREN,Parity receive enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 4. "CTL1_MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 3. "CTL1_POD,Peripheral-mode: Data output disabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "CTL1_CP,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CTL1_LBM,Loop back mode" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,SPI enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "CLKCTL,Clock prescaler and divider register."
|
|
hexmask.long.byte 0x8 28.--31. 1. "CLKCTL_DSAMPLE,Delayed sampling value."
|
|
hexmask.long.word 0x8 0.--9. 1. "CLKCTL_SCR,Serial clock divider:"
|
|
line.long 0xC "IFLS,Interrupt FIFO Level Select Register"
|
|
bitfld.long 0xC 3.--5. "IFLS_RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_OFF,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_RES4,5: LVL_FULL,6: LVL_RES6,7: LEVEL_1"
|
|
bitfld.long 0xC 0.--2. "IFLS_TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: LVL_OFF,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,4: LVL_RES4,5: LVL_EMPTY,6: LVL_RES6,7: LEVEL_1"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 4. "STAT_BUSY,Busy" "0: IDLE,1: ACTIVE"
|
|
bitfld.long 0x0 3. "STAT_RNF,Receive FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 2. "STAT_RFE,Receive FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
newline
|
|
bitfld.long 0x0 1. "STAT_TNF,Transmit FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 0. "STAT_TFE,Transmit FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "RXDATA,RXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA_DATA,Received Data"
|
|
group.long 0x1140++0x3
|
|
line.long 0x0 "TXDATA,TXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA_DATA,Transmit Data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "SPI1"
|
|
base ad:0x4046A000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "CPU_INT_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPU_INT_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "CPU_INT_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "CPU_INT_IMASK_RXFULL,RX FIFO Full Interrupt Mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_IMASK_TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_IMASK_DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_IMASK_DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_IMASK_IDLE,SPI Idle event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_IMASK_TXEMPTY,Transmit FIFO Empty event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_IMASK_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_IMASK_RTOUT,Enable SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_IMASK_PER,Parity error event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_IMASK_RXFIFO_OVF,RXFIFO overflow event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "CPU_INT_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "CPU_INT_RIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_RIS_TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_RIS_DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_RIS_DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_RIS_IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_RIS_TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_RIS_TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_RIS_RTOUT,SPI Receive Time-Out event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_RIS_PER,Parity error event: this bit is set if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_RIS_RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "CPU_INT_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "CPU_INT_MIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_MIS_TXFIFO_UNF,TX FIFO underflow interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_MIS_DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_MIS_DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_MIS_IDLE,Masked SPI IDLE mode event." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_MIS_TXEMPTY,Masked Transmit FIFO Empty event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_MIS_TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_MIS_RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_MIS_RTOUT,Masked SPI Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_MIS_PER,Masked Parity error event: this bit if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_MIS_RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "CPU_INT_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "CPU_INT_ISET_RXFULL,Set RX FIFO Full Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "CPU_INT_ISET_TXFIFO_UNF,Set TX FIFO Underflow Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "CPU_INT_ISET_DMA_DONE_TX,Set DMA Done 1 event for TX." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_ISET_DMA_DONE_RX,Set DMA Done 1 event for RX." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "CPU_INT_ISET_IDLE,Set SPI IDLE mode event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "CPU_INT_ISET_TXEMPTY,Set Transmit FIFO Empty event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "CPU_INT_ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "CPU_INT_ISET_RTOUT,Set SPI Receive Time-Out Event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ISET_PER,Set Parity error event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "CPU_INT_ISET_RXFIFO_OVF,Set RXFIFO overflow event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "CPU_INT_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "CPU_INT_ICLR_RXFULL,Clear RX FIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "CPU_INT_ICLR_TXFIFO_UNF,Clear TXFIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "CPU_INT_ICLR_DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "CPU_INT_ICLR_DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "CPU_INT_ICLR_IDLE,Clear SPI IDLE mode event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "CPU_INT_ICLR_TXEMPTY,Clear Transmit FIFO Empty event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "CPU_INT_ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "CPU_INT_ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "CPU_INT_ICLR_RTOUT,Clear SPI Receive Time-Out Event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_INT_ICLR_PER,Clear Parity error event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "CPU_INT_ICLR_RXFIFO_OVF,Clear RXFIFO overflow event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMA_TRIG_RX_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "DMA_TRIG_RX_IMASK_RX,Receive FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "DMA_TRIG_RX_IMASK_RTOUT,SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "DMA_TRIG_RX_RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "DMA_TRIG_RX_RIS_RTOUT,SPI Receive Time-Out Event." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "DMA_TRIG_RX_MIS_RX,Receive FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "DMA_TRIG_RX_MIS_RTOUT,SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "DMA_TRIG_RX_ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "DMA_TRIG_RX_ISET_RTOUT,Set SPI Receive Time-Out event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "DMA_TRIG_RX_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "DMA_TRIG_RX_ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "DMA_TRIG_RX_ICLR_RTOUT,Clear SPI Receive Time-Out event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMA_TRIG_TX_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 4. "DMA_TRIG_TX_IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 4. "DMA_TRIG_TX_RIS_TX,Transmit FIFO event:" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 4. "DMA_TRIG_TX_MIS_TX,Masked Transmit FIFO event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_ISET,Interrupt set"
|
|
bitfld.long 0x0 4. "DMA_TRIG_TX_ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "DMA_TRIG_TX_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 4. "DMA_TRIG_TX_ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,SPI control register 0"
|
|
bitfld.long 0x0 14. "CTL0_CSCLR,Clear shift register counter on CS inactive" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12.--13. "CTL0_CSSEL,Select the CS line to control on data transfer" "0: CSSEL_0,1: CSSEL_1,2: CSSEL_2,3: CSSEL_3"
|
|
bitfld.long 0x0 9. "CTL0_SPH,CLKOUT phase (Motorola SPI frame format only)" "0: FIRST,1: SECOND"
|
|
newline
|
|
bitfld.long 0x0 8. "CTL0_SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 7. "CTL0_PACKEN,Packing Enable." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 5.--6. "CTL0_FRF,Frame format Select" "0: MOTOROLA_3WIRE,1: MOTOROLA_4WIRE,2: TI_SYNC,3: MIRCOWIRE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "CTL0_DSS,Data Size Select."
|
|
line.long 0x4 "CTL1,SPI control register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "CTL1_RXTIMEOUT,Receive Timeout (only for Peripheral mode)"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CTL1_REPEATTX,Counter to repeat last transfer"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CTL1_CDMODE,Command/Data Mode Value"
|
|
newline
|
|
bitfld.long 0x4 11. "CTL1_CDENABLE,Command/Data Mode enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "CTL1_PTEN,Parity transmit enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "CTL1_PES,Even Parity Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 5. "CTL1_PREN,Parity receive enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 4. "CTL1_MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 3. "CTL1_POD,Peripheral-mode: Data output disabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "CTL1_CP,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CTL1_LBM,Loop back mode" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,SPI enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "CLKCTL,Clock prescaler and divider register."
|
|
hexmask.long.byte 0x8 28.--31. 1. "CLKCTL_DSAMPLE,Delayed sampling value."
|
|
hexmask.long.word 0x8 0.--9. 1. "CLKCTL_SCR,Serial clock divider:"
|
|
line.long 0xC "IFLS,Interrupt FIFO Level Select Register"
|
|
bitfld.long 0xC 3.--5. "IFLS_RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_OFF,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_RES4,5: LVL_FULL,6: LVL_RES6,7: LEVEL_1"
|
|
bitfld.long 0xC 0.--2. "IFLS_TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: LVL_OFF,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,4: LVL_RES4,5: LVL_EMPTY,6: LVL_RES6,7: LEVEL_1"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 4. "STAT_BUSY,Busy" "0: IDLE,1: ACTIVE"
|
|
bitfld.long 0x0 3. "STAT_RNF,Receive FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 2. "STAT_RFE,Receive FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
newline
|
|
bitfld.long 0x0 1. "STAT_TNF,Transmit FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 0. "STAT_TFE,Transmit FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "RXDATA,RXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA_DATA,Received Data"
|
|
group.long 0x1140++0x3
|
|
line.long 0x0 "TXDATA,TXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA_DATA,Transmit Data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "SPI1"
|
|
base ad:0x4046A000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
line.long 0x4 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x4 3. "CLKSEL_SYSCLK_SEL,Selects SYSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXFULL,RX FIFO Full Interrupt Mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_TXFIFO_UNF,TX FIFO underflow interrupt mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_DMA_DONE_TX,DMA Done 1 event for TX event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_DMA_DONE_RX,DMA Done 1 event for RX event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_IDLE,SPI Idle event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_TXEMPTY,Transmit FIFO Empty event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_RTOUT,Enable SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_PER,Parity error event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RXFIFO_OVF,RXFIFO overflow event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_TXFIFO_UNF,TX FIFO Underflow Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_IDLE,SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_TXEMPTY,Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_TX,Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_RTOUT,SPI Receive Time-Out event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_PER,Parity error event: this bit is set if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RXFIFO_OVF,RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXFULL,RX FIFO Full Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_TXFIFO_UNF,TX FIFO underflow interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done 1 event for TX." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done 1 event for RX." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_IDLE,Masked SPI IDLE mode event." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_TXEMPTY,Masked Transmit FIFO Empty event." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_TX,Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_RX,Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_RTOUT,Masked SPI Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_PER,Masked Parity error event: this bit if a Parity error has been detected" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RXFIFO_OVF,Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXFULL,Set RX FIFO Full Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_TXFIFO_UNF,Set TX FIFO Underflow Event" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done 1 event for TX." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done 1 event for RX." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_IDLE,Set SPI IDLE mode event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_TXEMPTY,Set Transmit FIFO Empty event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_RTOUT,Set SPI Receive Time-Out Event." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_PER,Set Parity error event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RXFIFO_OVF,Set RXFIFO overflow event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXFULL,Clear RX FIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_TXFIFO_UNF,Clear TXFIFO underflow event" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done 1 event for TX." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done 1 event for RX." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_IDLE,Clear SPI IDLE mode event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_TXEMPTY,Clear Transmit FIFO Empty event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_RTOUT,Clear SPI Receive Time-Out Event." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_PER,Clear Parity error event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RXFIFO_OVF,Clear RXFIFO overflow event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "INT_EVENT1_IMASK_RX,Receive FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_IMASK_RTOUT,SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_RIS_RX,Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached" "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_RIS_RTOUT,SPI Receive Time-Out Event." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "INT_EVENT1_MIS_RX,Receive FIFO event mask." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_MIS_RTOUT,SPI Receive Time-Out event mask." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ISET_RX,Set Receive FIFO event." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ISET_RTOUT,Set SPI Receive Time-Out event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "INT_EVENT1_ICLR_RX,Clear Receive FIFO event." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT1_ICLR_RTOUT,Clear SPI Receive Time-Out event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt Index Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,Interrupt index status"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 4. "INT_EVENT2_IMASK_TX,Transmit FIFO event mask." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 4. "INT_EVENT2_RIS_TX,Transmit FIFO event:" "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 4. "INT_EVENT2_MIS_TX,Masked Transmit FIFO event" "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 4. "INT_EVENT2_ISET_TX,Set Transmit FIFO event." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 4. "INT_EVENT2_ICLR_TX,Clear Transmit FIFO event." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CTL0,SPI control register 0"
|
|
bitfld.long 0x0 14. "CTL0_CSCLR,Clear shift register counter on CS inactive" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 12.--13. "CTL0_CSSEL,Select the CS line to control on data transfer" "0: CSSEL_0,1: CSSEL_1,2: CSSEL_2,3: CSSEL_3"
|
|
bitfld.long 0x0 9. "CTL0_SPH,CLKOUT phase (Motorola SPI frame format only)" "0: FIRST,1: SECOND"
|
|
newline
|
|
bitfld.long 0x0 8. "CTL0_SPO,CLKOUT polarity (Motorola SPI frame format only)" "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 7. "CTL0_PACKEN,Packing Enable." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 5.--6. "CTL0_FRF,Frame format Select" "0: MOTOROLA_3WIRE,1: MOTOROLA_4WIRE,2: TI_SYNC,3: MIRCOWIRE"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "CTL0_DSS,Data Size Select."
|
|
line.long 0x4 "CTL1,SPI control register 1"
|
|
hexmask.long.byte 0x4 24.--29. 1. "CTL1_RXTIMEOUT,Receive Timeout (only for Peripheral mode)"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CTL1_REPEATTX,Counter to repeat last transfer"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CTL1_CDMODE,Command/Data Mode Value"
|
|
newline
|
|
bitfld.long 0x4 11. "CTL1_CDENABLE,Command/Data Mode enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 8. "CTL1_PTEN,Parity transmit enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 7. "CTL1_PBS,Parity Bit Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 6. "CTL1_PES,Even Parity Select" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "CTL1_PREN,Parity receive enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 4. "CTL1_MSB,MSB first select. Controls the direction of the receive and transmit shift register." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 3. "CTL1_SOD,Peripheral-mode: Data output disabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "CTL1_MS,Controller or peripheral mode select. This bit can be modified only when SPI is disabled CTL1.ENABLE=0." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "CTL1_LBM,Loop back mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "CTL1_ENABLE,SPI enable" "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "CLKCTL,Clock prescaler and divider register."
|
|
hexmask.long.byte 0x8 28.--31. 1. "CLKCTL_DSAMPLE,Delayed sampling value."
|
|
hexmask.long.word 0x8 0.--9. 1. "CLKCTL_SCR,Serial clock divider:"
|
|
line.long 0xC "IFLS,UART Interrupt FIFO Level Select Register"
|
|
bitfld.long 0xC 3.--5. "IFLS_RXIFLSEL,SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_OFF,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_RES4,5: LVL_FULL,6: LVL_RES6,7: LEVEL_1"
|
|
bitfld.long 0xC 0.--2. "IFLS_TXIFLSEL,SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0: LVL_OFF,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,4: LVL_RES4,5: LVL_EMPTY,6: LVL_RES6,7: LEVEL_1"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 4. "STAT_BUSY,Busy" "0: IDLE,1: ACTIVE"
|
|
bitfld.long 0x0 3. "STAT_RNF,Receive FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 2. "STAT_RFE,Receive FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
newline
|
|
bitfld.long 0x0 1. "STAT_TNF,Transmit FIFO not full" "0: FULL,1: NOT_FULL"
|
|
bitfld.long 0x0 0. "STAT_TFE,Transmit FIFO empty." "0: NOT_EMPTY,1: EMPTY"
|
|
rgroup.long 0x1130++0x3
|
|
line.long 0x0 "RXDATA,RXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA_DATA,Received Data"
|
|
group.long 0x1140++0x3
|
|
line.long 0x0 "TXDATA,TXDATA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA_DATA,Transmit Data"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "SYSCTL (System Controller)"
|
|
base ad:0x400AF000
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,SYSCTL interrupt index"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
bitfld.long 0x0 0.--1. "IIDX_STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read.." "0: NO_INTR,1: LFOSCGOOD,2: ANACLKERR,?"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "IIDX_STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read.."
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "IIDX_STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read.."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "IIDX_STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read.."
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "IIDX_STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read.."
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 0.--1. "IIDX_STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read.." "0: NO_INTR,1: LFOSCGOOD,2: ANACLKERR,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 0.--1. "IIDX_STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read.." "0: NO_INTR,1: LFOSCGOOD,2: ANACLKERR,?"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 0.--1. "IIDX_STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read.." "0: NO_INTR,1: LFOSCGOOD,2: ANACLKERR,?"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 0.--2. "IIDX_STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read.." "0: NO_INTR,1: LFOSCGOOD,2: ANACLKERR,3: FLASHSEC,4: SRAMSEC,5: LFXTGOOD,6: HFCLKGOOD,7: HSCLKGOOD"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 0.--2. "IIDX_STAT,The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast deterministic handling in the interrupt service routine. A read.." "0: NO_INTR,1: LFOSCGOOD,2: ANACLKERR,3: FLASHSEC,4: SRAMSEC,5: LFXTGOOD,6: HFCLKGOOD,7: HSCLKGOOD"
|
|
endif
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,SYSCTL interrupt mask"
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 7. "IMASK_HSCLKGOOD,HSCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 7. "IMASK_HSCLKGOOD,HSCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 7. "IMASK_HSCLKGOOD,HSCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 7. "IMASK_HSCLKGOOD,HSCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 6. "IMASK_SYSPLLGOOD,SYSPLL GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "IMASK_HFCLKGOOD,HFCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 6. "IMASK_SYSPLLGOOD,SYSPLL GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "IMASK_HFCLKGOOD,HFCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 6. "IMASK_SYSPLLGOOD,SYSPLL GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "IMASK_HFCLKGOOD,HFCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 6. "IMASK_SYSPLLGOOD,SYSPLL GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "IMASK_HFCLKGOOD,HFCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 6. "IMASK_HSCLKGOOD,HSCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "IMASK_HFCLKGOOD,HFCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 6. "IMASK_HSCLKGOOD,HSCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "IMASK_HFCLKGOOD,HFCLK GOOD" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 4. "IMASK_LFXTGOOD,LFXT GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "IMASK_SRAMSEC,SRAM Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 4. "IMASK_LFXTGOOD,LFXT GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "IMASK_SRAMSEC,SRAM Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 4. "IMASK_LFXTGOOD,LFXT GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "IMASK_SRAMSEC,SRAM Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 4. "IMASK_LFXTGOOD,LFXT GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "IMASK_SRAMSEC,SRAM Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 4. "IMASK_LFXTGOOD,LFXT GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "IMASK_SRAMSEC,SRAM Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 4. "IMASK_LFXTGOOD,LFXT GOOD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "IMASK_SRAMSEC,SRAM Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 2. "IMASK_FLASHSEC,Flash Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 2. "IMASK_FLASHSEC,Flash Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 2. "IMASK_FLASHSEC,Flash Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 2. "IMASK_FLASHSEC,Flash Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 2. "IMASK_FLASHSEC,Flash Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 2. "IMASK_FLASHSEC,Flash Single Error Correct" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
bitfld.long 0x0 1. "IMASK_ANACLKERR,Analog Clocking Consistency Error" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_LFOSCGOOD,Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,SYSCTL raw interrupt status"
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 7. "RIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 7. "RIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 7. "RIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 7. "RIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 6. "RIS_SYSPLLGOOD,SYSPLL GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "RIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 6. "RIS_SYSPLLGOOD,SYSPLL GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "RIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 6. "RIS_SYSPLLGOOD,SYSPLL GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "RIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 6. "RIS_SYSPLLGOOD,SYSPLL GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "RIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 6. "RIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "RIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 6. "RIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "RIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 4. "RIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "RIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 4. "RIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "RIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 4. "RIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "RIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 4. "RIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "RIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 4. "RIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "RIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 4. "RIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "RIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 2. "RIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 2. "RIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 2. "RIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 2. "RIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 2. "RIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 2. "RIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x0 1. "RIS_ANACLKERR,Analog Clocking Consistency Error" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 0. "RIS_LFOSCGOOD,Raw status of the LFOSCGOOD interrupt." "0: FALSE,1: TRUE"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,SYSCTL masked interrupt status"
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 7. "MIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 7. "MIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 7. "MIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 7. "MIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 6. "MIS_SYSPLLGOOD,SYSPLL GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "MIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 6. "MIS_SYSPLLGOOD,SYSPLL GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "MIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 6. "MIS_SYSPLLGOOD,SYSPLL GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "MIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 6. "MIS_SYSPLLGOOD,SYSPLL GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "MIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 6. "MIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "MIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 6. "MIS_HSCLKGOOD,HSCLK GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "MIS_HFCLKGOOD,HFCLK GOOD" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 4. "MIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "MIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 4. "MIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "MIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 4. "MIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "MIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 4. "MIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "MIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 4. "MIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "MIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 4. "MIS_LFXTGOOD,LFXT GOOD" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 3. "MIS_SRAMSEC,SRAM Single Error Correct" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 2. "MIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 2. "MIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 2. "MIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 2. "MIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 2. "MIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 2. "MIS_FLASHSEC,Flash Single Error Correct" "0: FALSE,1: TRUE"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x0 1. "MIS_ANACLKERR,Analog Clocking Consistency Error" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 0. "MIS_LFOSCGOOD,Masked status of the LFOSCGOOD interrupt." "0: FALSE,1: TRUE"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,SYSCTL interrupt set"
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 7. "ISET_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 7. "ISET_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 7. "ISET_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 7. "ISET_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 6. "ISET_SYSPLLGOOD,SYSPLL GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 6. "ISET_SYSPLLGOOD,SYSPLL GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 6. "ISET_SYSPLLGOOD,SYSPLL GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 6. "ISET_SYSPLLGOOD,SYSPLL GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 6. "ISET_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 6. "ISET_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 4. "ISET_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "ISET_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 4. "ISET_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "ISET_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 4. "ISET_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "ISET_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 4. "ISET_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "ISET_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 4. "ISET_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "ISET_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 4. "ISET_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "ISET_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 2. "ISET_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 2. "ISET_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 2. "ISET_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 2. "ISET_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 2. "ISET_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 2. "ISET_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_ANACLKERR,Analog Clocking Consistency Error" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "ISET_LFOSCGOOD,Set the LFOSCGOOD interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,SYSCTL interrupt clear"
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 7. "ICLR_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 7. "ICLR_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 7. "ICLR_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 7. "ICLR_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 6. "ICLR_SYSPLLGOOD,SYSPLL GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 6. "ICLR_SYSPLLGOOD,SYSPLL GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 6. "ICLR_SYSPLLGOOD,SYSPLL GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 6. "ICLR_SYSPLLGOOD,SYSPLL GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 6. "ICLR_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 6. "ICLR_HSCLKGOOD,HSCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_HFCLKGOOD,HFCLK GOOD" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 4. "ICLR_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "ICLR_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 4. "ICLR_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "ICLR_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 4. "ICLR_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "ICLR_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 4. "ICLR_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "ICLR_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 4. "ICLR_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "ICLR_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 4. "ICLR_LFXTGOOD,LFXT GOOD" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "ICLR_SRAMSEC,SRAM Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 2. "ICLR_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 2. "ICLR_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 2. "ICLR_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 2. "ICLR_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 2. "ICLR_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 2. "ICLR_FLASHSEC,Flash Single Error Correct" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_ANACLKERR,Analog Clocking Consistency Error" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "ICLR_LFOSCGOOD,Clear the LFOSCGOOD interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "NMIIIDX,NMI interrupt index"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
bitfld.long 0x0 0.--1. "NMIIIDX_STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the.." "0: NO_INTR,1: BORLVL,2: WWDT0,?"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "NMIIIDX_STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the.."
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "NMIIIDX_STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the.."
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "NMIIIDX_STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the.."
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "NMIIIDX_STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the.."
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 0.--1. "NMIIIDX_STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the.." "0: NO_INTR,1: BORLVL,2: WWDT0,?"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 0.--1. "NMIIIDX_STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the.." "0: NO_INTR,1: BORLVL,2: WWDT0,?"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 0.--1. "NMIIIDX_STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the.." "0: NO_INTR,1: BORLVL,2: WWDT0,?"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 0.--2. "NMIIIDX_STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the.." "0: NO_INTR,1: BORLVL,2: WWDT0,3: LFCLKFAIL,4: FLASHDED,5: SRAMDED,6: VBATDN,7: VBATUP"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 0.--2. "NMIIIDX_STAT,The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast deterministic handling in the NMI service routine. A read of the.." "0: NO_INTR,1: BORLVL,2: WWDT0,3: LFCLKFAIL,4: FLASHDED,5: SRAMDED,6: VBATDN,7: VBATUP"
|
|
endif
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "NMIRIS,NMI raw interrupt status"
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 6. "NMIRIS_VBATUP,VBAT Power On" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "NMIRIS_VBATDN,VBAT Power Off" "0: FALSE,1: TRUE"
|
|
newline
|
|
rbitfld.long 0x0 4. "NMIRIS_SRAMDED,SRAM Double Error Detect" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 6. "NMIRIS_VBATUP,VBAT Power On" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 5. "NMIRIS_VBATDN,VBAT Power Off" "0: FALSE,1: TRUE"
|
|
newline
|
|
rbitfld.long 0x0 4. "NMIRIS_SRAMDED,SRAM Double Error Detect" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 5. "NMIRIS_SRAMDED,SRAM Double Error Detect" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 5. "NMIRIS_SRAMDED,SRAM Double Error Detect" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 5. "NMIRIS_SRAMDED,SRAM Double Error Detect" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 5. "NMIRIS_SRAMDED,SRAM Double Error Detect" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 4. "NMIRIS_FLASHDED,Flash Double Error Detect" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 4. "NMIRIS_FLASHDED,Flash Double Error Detect" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 4. "NMIRIS_FLASHDED,Flash Double Error Detect" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 4. "NMIRIS_FLASHDED,Flash Double Error Detect" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
rbitfld.long 0x0 3. "NMIRIS_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 2. "NMIRIS_WWDT1,Watch Dog 0 Fault" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
rbitfld.long 0x0 3. "NMIRIS_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 2. "NMIRIS_WWDT1,Watch Dog 0 Fault" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
rbitfld.long 0x0 3. "NMIRIS_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 2. "NMIRIS_WWDT1,Watch Dog 0 Fault" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
rbitfld.long 0x0 3. "NMIRIS_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 2. "NMIRIS_WWDT1,Watch Dog 0 Fault" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 3. "NMIRIS_FLASHDED,Flash Double Error Detect" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 3. "NMIRIS_FLASHDED,Flash Double Error Detect" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
rbitfld.long 0x0 2. "NMIRIS_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
rbitfld.long 0x0 2. "NMIRIS_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: FALSE,1: TRUE"
|
|
endif
|
|
newline
|
|
rbitfld.long 0x0 1. "NMIRIS_WWDT0,Watch Dog 0 Fault" "0: FALSE,1: TRUE"
|
|
rbitfld.long 0x0 0. "NMIRIS_BORLVL,Raw status of the BORLVL NMI" "0: FALSE,1: TRUE"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "NMIISET,NMI interrupt set"
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 6. "NMIISET_VBATUP,VBAT Power On" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "NMIISET_VBATDN,VBAT Power Off" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "NMIISET_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 6. "NMIISET_VBATUP,VBAT Power On" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "NMIISET_VBATDN,VBAT Power Off" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "NMIISET_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 5. "NMIISET_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 5. "NMIISET_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 5. "NMIISET_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 5. "NMIISET_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 4. "NMIISET_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 4. "NMIISET_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 4. "NMIISET_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 4. "NMIISET_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 3. "NMIISET_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "NMIISET_WWDT1,Watch Dog 0 Fault" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 3. "NMIISET_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "NMIISET_WWDT1,Watch Dog 0 Fault" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 3. "NMIISET_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "NMIISET_WWDT1,Watch Dog 0 Fault" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 3. "NMIISET_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "NMIISET_WWDT1,Watch Dog 0 Fault" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 3. "NMIISET_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 3. "NMIISET_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 2. "NMIISET_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 2. "NMIISET_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: SET"
|
|
endif
|
|
newline
|
|
bitfld.long 0x0 1. "NMIISET_WWDT0,Watch Dog 0 Fault" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "NMIISET_BORLVL,Set the BORLVL NMI" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "NMIICLR,NMI interrupt clear"
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 6. "NMIICLR_VBATUP,VBAT Power On" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "NMIICLR_VBATDN,VBAT Power Off" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "NMIICLR_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 6. "NMIICLR_VBATUP,VBAT Power On" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "NMIICLR_VBATDN,VBAT Power Off" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "NMIICLR_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 5. "NMIICLR_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 5. "NMIICLR_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 5. "NMIICLR_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 5. "NMIICLR_SRAMDED,SRAM Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 4. "NMIICLR_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 4. "NMIICLR_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 4. "NMIICLR_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 4. "NMIICLR_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 3. "NMIICLR_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "NMIICLR_WWDT1,Watch Dog 0 Fault" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 3. "NMIICLR_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "NMIICLR_WWDT1,Watch Dog 0 Fault" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 3. "NMIICLR_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "NMIICLR_WWDT1,Watch Dog 0 Fault" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 3. "NMIICLR_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "NMIICLR_WWDT1,Watch Dog 0 Fault" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 3. "NMIICLR_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 3. "NMIICLR_FLASHDED,Flash Double Error Detect" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 2. "NMIICLR_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 2. "NMIICLR_LFCLKFAIL,LFXT-EXLF Monitor Fail" "0: NO_EFFECT,1: CLR"
|
|
endif
|
|
newline
|
|
bitfld.long 0x0 1. "NMIICLR_WWDT0,Watch Dog 0 Fault" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "NMIICLR_BORLVL,Clr the BORLVL NMI" "0: NO_EFFECT,1: CLR"
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "SYSOSCCFG,SYSOSC configuration"
|
|
bitfld.long 0x0 17. "SYSOSCCFG_FASTCPUEVENT,FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU reducing interrupt latency." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 16. "SYSOSCCFG_BLOCKASYNCALL,BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests preventing hardware from dynamically changing the active clock configuration when operating in a given mode." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 10. "SYSOSCCFG_DISABLE,DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN SLEEP and STOP modes to reduce power consumption. When SYSOSC is disabled MCLK and ULPCLK are sourced from LFCLK." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 9. "SYSOSCCFG_DISABLESTOP,DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode the SYSOSC may be automatically disabled. When set ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power.." "0: DISABLE,1: ENABLE"
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 8. "SYSOSCCFG_USE4MHZSTOP,USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 8. "SYSOSCCFG_USE4MHZSTOP,USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 8. "SYSOSCCFG_USE4MHZSTOP,USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 8. "SYSOSCCFG_USE4MHZSTOP,USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 8. "SYSOSCCFG_USE4MHZSTOP,USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 8. "SYSOSCCFG_USE4MHZSTOP,USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 8. "SYSOSCCFG_USE4MHZSTOP,USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 8. "SYSOSCCFG_USE4MHZSTOP,USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 8. "SYSOSCCFG_USE4MHZSTOP,USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 0.--1. "SYSOSCCFG_FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: SYSOSCBASE,1: SYSOSC4M,2: SYSOSCUSER,3: SYSOSCTURBO"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 0.--1. "SYSOSCCFG_FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: SYSOSCBASE,1: SYSOSC4M,2: SYSOSCUSER,3: SYSOSCTURBO"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 0.--1. "SYSOSCCFG_FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: SYSOSCBASE,1: SYSOSC4M,2: SYSOSCUSER,3: SYSOSCTURBO"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 0.--1. "SYSOSCCFG_FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: SYSOSCBASE,1: SYSOSC4M,2: SYSOSCUSER,?"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 0.--1. "SYSOSCCFG_FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: SYSOSCBASE,1: SYSOSC4M,2: SYSOSCUSER,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 0.--1. "SYSOSCCFG_FREQ,Target operating frequency for the system oscillator (SYSOSC)" "0: SYSOSCBASE,1: SYSOSC4M,2: SYSOSCUSER,?"
|
|
endif
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
group.long 0x1108++0x3
|
|
line.long 0x0 "HSCLKEN,High-speed clock (HSCLK) source enable/disable"
|
|
bitfld.long 0x0 16. "HSCLKEN_USEEXTHFCLK,USEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously." "0: DISABLE,1: ENABLE"
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 8. "HSCLKEN_SYSPLLEN,SYSPLLEN enables or disables the system phase-lock loop (SYSPLL)." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 8. "HSCLKEN_SYSPLLEN,SYSPLLEN enables or disables the system phase-lock loop (SYSPLL)." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 8. "HSCLKEN_SYSPLLEN,SYSPLLEN enables or disables the system phase-lock loop (SYSPLL)." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 8. "HSCLKEN_SYSPLLEN,SYSPLLEN enables or disables the system phase-lock loop (SYSPLL)." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 0. "HSCLKEN_HFXTEN,HFXTEN enables or disables the high frequency crystal oscillator (HFXT)." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 0. "HSCLKEN_HFXTEN,HFXTEN enables or disables the high frequency crystal oscillator (HFXT)." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 0. "HSCLKEN_HFXTEN,HFXTEN enables or disables the high frequency crystal oscillator (HFXT)." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 0. "HSCLKEN_HFXTEN,HFXTEN enables or disables the high frequency crystal oscillator (HFXT)." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
wgroup.long 0x1318++0x3
|
|
line.long 0x0 "EXLFCTL,LFCLK_IN and LFCLK control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "EXLFCTL_KEY,The key value of 36h (54) must be written to KEY together with SETUSEEXLF to set SETUSEEXLF."
|
|
bitfld.long 0x0 0. "EXLFCTL_SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
group.long 0x1120++0xF
|
|
line.long 0x0 "SYSPLLCFG0,SYSPLL reference and output configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSPLLCFG0_RDIVCLK2X,RDIVCLK2X sets the final divider for the SYSPLLCLK2X output."
|
|
hexmask.long.byte 0x0 12.--15. 1. "SYSPLLCFG0_RDIVCLK1,RDIVCLK1 sets the final divider for the SYSPLLCLK1 output."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SYSPLLCFG0_RDIVCLK0,RDIVCLK0 sets the final divider for the SYSPLLCLK0 output."
|
|
bitfld.long 0x0 6. "SYSPLLCFG0_ENABLECLK2X,ENABLECLK2X enables or disables the SYSPLLCLK2X output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 5. "SYSPLLCFG0_ENABLECLK1,ENABLECLK1 enables or disables the SYSPLLCLK1 output." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "SYSPLLCFG0_ENABLECLK0,ENABLECLK0 enables or disables the SYSPLLCLK0 output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "SYSPLLCFG0_MCLK2XVCO,MCLK2XVCO selects the SYSPLL output which is sent to the HSCLK mux for use by MCLK." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "SYSPLLCFG0_SYSPLLREF,SYSPLLREF selects the system PLL (SYSPLL) reference clock source." "0: SYSOSC,1: HFCLK"
|
|
line.long 0x4 "SYSPLLCFG1,SYSPLL reference and feedback divider"
|
|
hexmask.long.byte 0x4 8.--14. 1. "SYSPLLCFG1_QDIV,QDIV selects the SYSPLL feedback path divider."
|
|
bitfld.long 0x4 0.--1. "SYSPLLCFG1_PDIV,PDIV selects the SYSPLL reference clock prescale divider." "0: REFDIV1,1: REFDIV2,2: REFDIV4,3: REFDIV8"
|
|
line.long 0x8 "SYSPLLPARAM0,SYSPLL PARAM0 (load from FACTORY region)"
|
|
bitfld.long 0x8 31. "SYSPLLPARAM0_CAPBOVERRIDE,CAPBOVERRIDE controls the override for Cap B" "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYSPLLPARAM0_CAPBVAL,Override value for Cap B"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "SYSPLLPARAM0_CPCURRENT,Charge pump current"
|
|
hexmask.long.byte 0x8 8.--13. 1. "SYSPLLPARAM0_STARTTIMELP,Startup time from low power mode exit to locked clock in 1us resolution"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "SYSPLLPARAM0_STARTTIME,Startup time from enable to locked clock in 1us resolution"
|
|
line.long 0xC "SYSPLLPARAM1,SYSPLL PARAM1 (load from FACTORY region)"
|
|
hexmask.long.byte 0xC 24.--31. 1. "SYSPLLPARAM1_LPFRESC,Loop filter Res C"
|
|
hexmask.long.word 0xC 8.--17. 1. "SYSPLLPARAM1_LPFRESA,Loop filter Res A"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SYSPLLPARAM1_LPFCAPA,Loop filter Cap A"
|
|
group.long 0x1170++0x3
|
|
line.long 0x0 "SYSOSCTRIMUSER,SYSOSC user-specified trim"
|
|
hexmask.long.word 0x0 20.--28. 1. "SYSOSCTRIMUSER_RDIV,RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSOSCTRIMUSER_RESFINE,RESFINE specifies the resister fine trim. This value changes with the target frequency."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "SYSOSCTRIMUSER_RESCOARSE,RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."
|
|
bitfld.long 0x0 4.--6. "SYSOSCTRIMUSER_CAP,CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SYSOSCTRIMUSER_FREQ,FREQ specifies the target user-trimmed frequency for SYSOSC." "?,1: SYSOSC16M,2: SYSOSC24M,?"
|
|
rgroup.long 0x120C++0x3
|
|
line.long 0x0 "DEDERRADDR,Memory DED Address"
|
|
hexmask.long 0x0 0.--31. 1. "DEDERRADDR_ADDR,Address of MEMORY DED Error."
|
|
wgroup.long 0x1314++0x3
|
|
line.long 0x0 "LFXTCTL,LFXT and LFCLK control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "LFXTCTL_KEY,The key value of 91h (145) must be written to KEY together with either STARTLFXT or SETUSELFXT to set the corresponding bit."
|
|
bitfld.long 0x0 1. "LFXTCTL_SETUSELFXT,Set SETUSELFXT to switch LFCLK to LFXT. Once set SETUSELFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "LFXTCTL_STARTLFXT,Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set STARTLFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "PMUOPAMP,GPAMP control"
|
|
bitfld.long 0x0 10.--11. "PMUOPAMP_CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: CHOPDISABLED,1: REGCHOP,2: ADCASSIST,?"
|
|
bitfld.long 0x0 8.--9. "PMUOPAMP_CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: CLK16KHZ,1: CLK8KHZ,2: CLK4KHZ,3: CLK2KHZ"
|
|
newline
|
|
bitfld.long 0x0 6. "PMUOPAMP_OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: FALSE,1: TRUE"
|
|
bitfld.long 0x0 4.--5. "PMUOPAMP_RRI,RRI selects the rail-to-rail input mode." "0: MODE0,1: MODE1,2: MODE2,3: MODE3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PMUOPAMP_NSEL,NSEL selects the GPAMP negative channel input." "0: SEL0,1: SEL1,2: SEL2,3: SEL3"
|
|
bitfld.long 0x0 1. "PMUOPAMP_PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "PMUOPAMP_ENABLE,Set ENABLE to turn on the GPAMP." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
group.long 0x1120++0xF
|
|
line.long 0x0 "SYSPLLCFG0,SYSPLL reference and output configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSPLLCFG0_RDIVCLK2X,RDIVCLK2X sets the final divider for the SYSPLLCLK2X output."
|
|
hexmask.long.byte 0x0 12.--15. 1. "SYSPLLCFG0_RDIVCLK1,RDIVCLK1 sets the final divider for the SYSPLLCLK1 output."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SYSPLLCFG0_RDIVCLK0,RDIVCLK0 sets the final divider for the SYSPLLCLK0 output."
|
|
bitfld.long 0x0 6. "SYSPLLCFG0_ENABLECLK2X,ENABLECLK2X enables or disables the SYSPLLCLK2X output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 5. "SYSPLLCFG0_ENABLECLK1,ENABLECLK1 enables or disables the SYSPLLCLK1 output." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "SYSPLLCFG0_ENABLECLK0,ENABLECLK0 enables or disables the SYSPLLCLK0 output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "SYSPLLCFG0_MCLK2XVCO,MCLK2XVCO selects the SYSPLL output which is sent to the HSCLK mux for use by MCLK." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "SYSPLLCFG0_SYSPLLREF,SYSPLLREF selects the system PLL (SYSPLL) reference clock source." "0: SYSOSC,1: HFCLK"
|
|
line.long 0x4 "SYSPLLCFG1,SYSPLL reference and feedback divider"
|
|
hexmask.long.byte 0x4 8.--14. 1. "SYSPLLCFG1_QDIV,QDIV selects the SYSPLL feedback path divider."
|
|
bitfld.long 0x4 0.--1. "SYSPLLCFG1_PDIV,PDIV selects the SYSPLL reference clock prescale divider." "0: REFDIV1,1: REFDIV2,2: REFDIV4,3: REFDIV8"
|
|
line.long 0x8 "SYSPLLPARAM0,SYSPLL PARAM0 (load from FACTORY region)"
|
|
bitfld.long 0x8 31. "SYSPLLPARAM0_CAPBOVERRIDE,CAPBOVERRIDE controls the override for Cap B" "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYSPLLPARAM0_CAPBVAL,Override value for Cap B"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "SYSPLLPARAM0_CPCURRENT,Charge pump current"
|
|
hexmask.long.byte 0x8 8.--13. 1. "SYSPLLPARAM0_STARTTIMELP,Startup time from low power mode exit to locked clock in 1us resolution"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "SYSPLLPARAM0_STARTTIME,Startup time from enable to locked clock in 1us resolution"
|
|
line.long 0xC "SYSPLLPARAM1,SYSPLL PARAM1 (load from FACTORY region)"
|
|
hexmask.long.byte 0xC 24.--31. 1. "SYSPLLPARAM1_LPFRESC,Loop filter Res C"
|
|
hexmask.long.word 0xC 8.--17. 1. "SYSPLLPARAM1_LPFRESA,Loop filter Res A"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SYSPLLPARAM1_LPFCAPA,Loop filter Cap A"
|
|
group.long 0x1170++0x3
|
|
line.long 0x0 "SYSOSCTRIMUSER,SYSOSC user-specified trim"
|
|
hexmask.long.word 0x0 20.--28. 1. "SYSOSCTRIMUSER_RDIV,RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSOSCTRIMUSER_RESFINE,RESFINE specifies the resister fine trim. This value changes with the target frequency."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "SYSOSCTRIMUSER_RESCOARSE,RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."
|
|
bitfld.long 0x0 4.--6. "SYSOSCTRIMUSER_CAP,CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SYSOSCTRIMUSER_FREQ,FREQ specifies the target user-trimmed frequency for SYSOSC." "?,1: SYSOSC16M,2: SYSOSC24M,?"
|
|
rgroup.long 0x120C++0x3
|
|
line.long 0x0 "DEDERRADDR,Memory DED Address"
|
|
hexmask.long 0x0 0.--31. 1. "DEDERRADDR_ADDR,Address of MEMORY DED Error."
|
|
wgroup.long 0x1314++0x3
|
|
line.long 0x0 "LFXTCTL,LFXT and LFCLK control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "LFXTCTL_KEY,The key value of 91h (145) must be written to KEY together with either STARTLFXT or SETUSELFXT to set the corresponding bit."
|
|
bitfld.long 0x0 1. "LFXTCTL_SETUSELFXT,Set SETUSELFXT to switch LFCLK to LFXT. Once set SETUSELFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "LFXTCTL_STARTLFXT,Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set STARTLFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "PMUOPAMP,GPAMP control"
|
|
bitfld.long 0x0 10.--11. "PMUOPAMP_CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: CHOPDISABLED,1: REGCHOP,2: ADCASSIST,?"
|
|
bitfld.long 0x0 8.--9. "PMUOPAMP_CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: CLK16KHZ,1: CLK8KHZ,2: CLK4KHZ,3: CLK2KHZ"
|
|
newline
|
|
bitfld.long 0x0 6. "PMUOPAMP_OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: FALSE,1: TRUE"
|
|
bitfld.long 0x0 4.--5. "PMUOPAMP_RRI,RRI selects the rail-to-rail input mode." "0: MODE0,1: MODE1,2: MODE2,3: MODE3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PMUOPAMP_NSEL,NSEL selects the GPAMP negative channel input." "0: SEL0,1: SEL1,2: SEL2,3: SEL3"
|
|
bitfld.long 0x0 1. "PMUOPAMP_PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "PMUOPAMP_ENABLE,Set ENABLE to turn on the GPAMP." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
group.long 0x1120++0xF
|
|
line.long 0x0 "SYSPLLCFG0,SYSPLL reference and output configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSPLLCFG0_RDIVCLK2X,RDIVCLK2X sets the final divider for the SYSPLLCLK2X output."
|
|
hexmask.long.byte 0x0 12.--15. 1. "SYSPLLCFG0_RDIVCLK1,RDIVCLK1 sets the final divider for the SYSPLLCLK1 output."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SYSPLLCFG0_RDIVCLK0,RDIVCLK0 sets the final divider for the SYSPLLCLK0 output."
|
|
bitfld.long 0x0 6. "SYSPLLCFG0_ENABLECLK2X,ENABLECLK2X enables or disables the SYSPLLCLK2X output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 5. "SYSPLLCFG0_ENABLECLK1,ENABLECLK1 enables or disables the SYSPLLCLK1 output." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "SYSPLLCFG0_ENABLECLK0,ENABLECLK0 enables or disables the SYSPLLCLK0 output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "SYSPLLCFG0_MCLK2XVCO,MCLK2XVCO selects the SYSPLL output which is sent to the HSCLK mux for use by MCLK." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "SYSPLLCFG0_SYSPLLREF,SYSPLLREF selects the system PLL (SYSPLL) reference clock source." "0: SYSOSC,1: HFCLK"
|
|
line.long 0x4 "SYSPLLCFG1,SYSPLL reference and feedback divider"
|
|
hexmask.long.byte 0x4 8.--14. 1. "SYSPLLCFG1_QDIV,QDIV selects the SYSPLL feedback path divider."
|
|
bitfld.long 0x4 0.--1. "SYSPLLCFG1_PDIV,PDIV selects the SYSPLL reference clock prescale divider." "0: REFDIV1,1: REFDIV2,2: REFDIV4,3: REFDIV8"
|
|
line.long 0x8 "SYSPLLPARAM0,SYSPLL PARAM0 (load from FACTORY region)"
|
|
bitfld.long 0x8 31. "SYSPLLPARAM0_CAPBOVERRIDE,CAPBOVERRIDE controls the override for Cap B" "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYSPLLPARAM0_CAPBVAL,Override value for Cap B"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "SYSPLLPARAM0_CPCURRENT,Charge pump current"
|
|
hexmask.long.byte 0x8 8.--13. 1. "SYSPLLPARAM0_STARTTIMELP,Startup time from low power mode exit to locked clock in 1us resolution"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "SYSPLLPARAM0_STARTTIME,Startup time from enable to locked clock in 1us resolution"
|
|
line.long 0xC "SYSPLLPARAM1,SYSPLL PARAM1 (load from FACTORY region)"
|
|
hexmask.long.byte 0xC 24.--31. 1. "SYSPLLPARAM1_LPFRESC,Loop filter Res C"
|
|
hexmask.long.word 0xC 8.--17. 1. "SYSPLLPARAM1_LPFRESA,Loop filter Res A"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SYSPLLPARAM1_LPFCAPA,Loop filter Cap A"
|
|
group.long 0x1170++0x3
|
|
line.long 0x0 "SYSOSCTRIMUSER,SYSOSC user-specified trim"
|
|
hexmask.long.word 0x0 20.--28. 1. "SYSOSCTRIMUSER_RDIV,RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSOSCTRIMUSER_RESFINE,RESFINE specifies the resister fine trim. This value changes with the target frequency."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "SYSOSCTRIMUSER_RESCOARSE,RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."
|
|
bitfld.long 0x0 4.--6. "SYSOSCTRIMUSER_CAP,CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SYSOSCTRIMUSER_FREQ,FREQ specifies the target user-trimmed frequency for SYSOSC." "?,1: SYSOSC16M,2: SYSOSC24M,?"
|
|
rgroup.long 0x120C++0x3
|
|
line.long 0x0 "DEDERRADDR,Memory DED Address"
|
|
hexmask.long 0x0 0.--31. 1. "DEDERRADDR_ADDR,Address of MEMORY DED Error."
|
|
wgroup.long 0x1314++0x3
|
|
line.long 0x0 "LFXTCTL,LFXT and LFCLK control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "LFXTCTL_KEY,The key value of 91h (145) must be written to KEY together with either STARTLFXT or SETUSELFXT to set the corresponding bit."
|
|
bitfld.long 0x0 1. "LFXTCTL_SETUSELFXT,Set SETUSELFXT to switch LFCLK to LFXT. Once set SETUSELFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "LFXTCTL_STARTLFXT,Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set STARTLFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "PMUOPAMP,GPAMP control"
|
|
bitfld.long 0x0 10.--11. "PMUOPAMP_CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: CHOPDISABLED,1: REGCHOP,2: ADCASSIST,?"
|
|
bitfld.long 0x0 8.--9. "PMUOPAMP_CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: CLK16KHZ,1: CLK8KHZ,2: CLK4KHZ,3: CLK2KHZ"
|
|
newline
|
|
bitfld.long 0x0 6. "PMUOPAMP_OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: FALSE,1: TRUE"
|
|
bitfld.long 0x0 4.--5. "PMUOPAMP_RRI,RRI selects the rail-to-rail input mode." "0: MODE0,1: MODE1,2: MODE2,3: MODE3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PMUOPAMP_NSEL,NSEL selects the GPAMP negative channel input." "0: SEL0,1: SEL1,2: SEL2,3: SEL3"
|
|
bitfld.long 0x0 1. "PMUOPAMP_PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "PMUOPAMP_ENABLE,Set ENABLE to turn on the GPAMP." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
group.long 0x1120++0xF
|
|
line.long 0x0 "SYSPLLCFG0,SYSPLL reference and output configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSPLLCFG0_RDIVCLK2X,RDIVCLK2X sets the final divider for the SYSPLLCLK2X output."
|
|
hexmask.long.byte 0x0 12.--15. 1. "SYSPLLCFG0_RDIVCLK1,RDIVCLK1 sets the final divider for the SYSPLLCLK1 output."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "SYSPLLCFG0_RDIVCLK0,RDIVCLK0 sets the final divider for the SYSPLLCLK0 output."
|
|
bitfld.long 0x0 6. "SYSPLLCFG0_ENABLECLK2X,ENABLECLK2X enables or disables the SYSPLLCLK2X output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 5. "SYSPLLCFG0_ENABLECLK1,ENABLECLK1 enables or disables the SYSPLLCLK1 output." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "SYSPLLCFG0_ENABLECLK0,ENABLECLK0 enables or disables the SYSPLLCLK0 output." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "SYSPLLCFG0_MCLK2XVCO,MCLK2XVCO selects the SYSPLL output which is sent to the HSCLK mux for use by MCLK." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "SYSPLLCFG0_SYSPLLREF,SYSPLLREF selects the system PLL (SYSPLL) reference clock source." "0: SYSOSC,1: HFCLK"
|
|
line.long 0x4 "SYSPLLCFG1,SYSPLL reference and feedback divider"
|
|
hexmask.long.byte 0x4 8.--14. 1. "SYSPLLCFG1_QDIV,QDIV selects the SYSPLL feedback path divider."
|
|
bitfld.long 0x4 0.--1. "SYSPLLCFG1_PDIV,PDIV selects the SYSPLL reference clock prescale divider." "0: REFDIV1,1: REFDIV2,2: REFDIV4,3: REFDIV8"
|
|
line.long 0x8 "SYSPLLPARAM0,SYSPLL PARAM0 (load from FACTORY region)"
|
|
bitfld.long 0x8 31. "SYSPLLPARAM0_CAPBOVERRIDE,CAPBOVERRIDE controls the override for Cap B" "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYSPLLPARAM0_CAPBVAL,Override value for Cap B"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "SYSPLLPARAM0_CPCURRENT,Charge pump current"
|
|
hexmask.long.byte 0x8 8.--13. 1. "SYSPLLPARAM0_STARTTIMELP,Startup time from low power mode exit to locked clock in 1us resolution"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "SYSPLLPARAM0_STARTTIME,Startup time from enable to locked clock in 1us resolution"
|
|
line.long 0xC "SYSPLLPARAM1,SYSPLL PARAM1 (load from FACTORY region)"
|
|
hexmask.long.byte 0xC 24.--31. 1. "SYSPLLPARAM1_LPFRESC,Loop filter Res C"
|
|
hexmask.long.word 0xC 8.--17. 1. "SYSPLLPARAM1_LPFRESA,Loop filter Res A"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SYSPLLPARAM1_LPFCAPA,Loop filter Cap A"
|
|
group.long 0x1170++0x3
|
|
line.long 0x0 "SYSOSCTRIMUSER,SYSOSC user-specified trim"
|
|
hexmask.long.word 0x0 20.--28. 1. "SYSOSCTRIMUSER_RDIV,RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSOSCTRIMUSER_RESFINE,RESFINE specifies the resister fine trim. This value changes with the target frequency."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "SYSOSCTRIMUSER_RESCOARSE,RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."
|
|
bitfld.long 0x0 4.--6. "SYSOSCTRIMUSER_CAP,CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SYSOSCTRIMUSER_FREQ,FREQ specifies the target user-trimmed frequency for SYSOSC." "?,1: SYSOSC16M,2: SYSOSC24M,?"
|
|
rgroup.long 0x120C++0x3
|
|
line.long 0x0 "DEDERRADDR,Memory DED Address"
|
|
hexmask.long 0x0 0.--31. 1. "DEDERRADDR_ADDR,Address of MEMORY DED Error."
|
|
wgroup.long 0x1314++0x3
|
|
line.long 0x0 "LFXTCTL,LFXT and LFCLK control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "LFXTCTL_KEY,The key value of 91h (145) must be written to KEY together with either STARTLFXT or SETUSELFXT to set the corresponding bit."
|
|
bitfld.long 0x0 1. "LFXTCTL_SETUSELFXT,Set SETUSELFXT to switch LFCLK to LFXT. Once set SETUSELFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "LFXTCTL_STARTLFXT,Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set STARTLFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "PMUOPAMP,GPAMP control"
|
|
bitfld.long 0x0 10.--11. "PMUOPAMP_CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: CHOPDISABLED,1: REGCHOP,2: ADCASSIST,?"
|
|
bitfld.long 0x0 8.--9. "PMUOPAMP_CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: CLK16KHZ,1: CLK8KHZ,2: CLK4KHZ,3: CLK2KHZ"
|
|
newline
|
|
bitfld.long 0x0 6. "PMUOPAMP_OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: FALSE,1: TRUE"
|
|
bitfld.long 0x0 4.--5. "PMUOPAMP_RRI,RRI selects the rail-to-rail input mode." "0: MODE0,1: MODE1,2: MODE2,3: MODE3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PMUOPAMP_NSEL,NSEL selects the GPAMP negative channel input." "0: SEL0,1: SEL1,2: SEL2,3: SEL3"
|
|
bitfld.long 0x0 1. "PMUOPAMP_PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "PMUOPAMP_ENABLE,Set ENABLE to turn on the GPAMP." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
group.long 0x1108++0x3
|
|
line.long 0x0 "HSCLKEN,High-speed clock (HSCLK) source enable/disable"
|
|
bitfld.long 0x0 16. "HSCLKEN_USEEXTHFCLK,USEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "HSCLKEN_HFXTEN,HFXTEN enables or disables the high frequency crystal oscillator (HFXT)." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1170++0x3
|
|
line.long 0x0 "SYSOSCTRIMUSER,SYSOSC user-specified trim"
|
|
hexmask.long.word 0x0 20.--28. 1. "SYSOSCTRIMUSER_RDIV,RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSOSCTRIMUSER_RESFINE,RESFINE specifies the resister fine trim. This value changes with the target frequency."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "SYSOSCTRIMUSER_RESCOARSE,RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."
|
|
bitfld.long 0x0 4.--6. "SYSOSCTRIMUSER_CAP,CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SYSOSCTRIMUSER_FREQ,FREQ specifies the target user-trimmed frequency for SYSOSC." "?,1: SYSOSC16M,2: SYSOSC24M,?"
|
|
rgroup.long 0x120C++0x3
|
|
line.long 0x0 "DEDERRADDR,Memory DED Address"
|
|
hexmask.long 0x0 0.--31. 1. "DEDERRADDR_ADDR,Address of MEMORY DED Error."
|
|
wgroup.long 0x1314++0x7
|
|
line.long 0x0 "LFXTCTL,LFXT and LFCLK control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "LFXTCTL_KEY,The key value of 91h (145) must be written to KEY together with either STARTLFXT or SETUSELFXT to set the corresponding bit."
|
|
bitfld.long 0x0 1. "LFXTCTL_SETUSELFXT,Set SETUSELFXT to switch LFCLK to LFXT. Once set SETUSELFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "LFXTCTL_STARTLFXT,Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set STARTLFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
line.long 0x4 "EXLFCTL,LFCLK_IN and LFCLK control"
|
|
hexmask.long.byte 0x4 24.--31. 1. "EXLFCTL_KEY,The key value of 36h (54) must be written to KEY together with SETUSEEXLF to set SETUSEEXLF."
|
|
bitfld.long 0x4 0. "EXLFCTL_SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
group.long 0x1108++0x3
|
|
line.long 0x0 "HSCLKEN,High-speed clock (HSCLK) source enable/disable"
|
|
bitfld.long 0x0 16. "HSCLKEN_USEEXTHFCLK,USEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "HSCLKEN_HFXTEN,HFXTEN enables or disables the high frequency crystal oscillator (HFXT)." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1170++0x3
|
|
line.long 0x0 "SYSOSCTRIMUSER,SYSOSC user-specified trim"
|
|
hexmask.long.word 0x0 20.--28. 1. "SYSOSCTRIMUSER_RDIV,RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSOSCTRIMUSER_RESFINE,RESFINE specifies the resister fine trim. This value changes with the target frequency."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "SYSOSCTRIMUSER_RESCOARSE,RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."
|
|
bitfld.long 0x0 4.--6. "SYSOSCTRIMUSER_CAP,CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SYSOSCTRIMUSER_FREQ,FREQ specifies the target user-trimmed frequency for SYSOSC." "?,1: SYSOSC16M,2: SYSOSC24M,?"
|
|
rgroup.long 0x120C++0x3
|
|
line.long 0x0 "DEDERRADDR,Memory DED Address"
|
|
hexmask.long 0x0 0.--31. 1. "DEDERRADDR_ADDR,Address of MEMORY DED Error."
|
|
wgroup.long 0x1314++0x7
|
|
line.long 0x0 "LFXTCTL,LFXT and LFCLK control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "LFXTCTL_KEY,The key value of 91h (145) must be written to KEY together with either STARTLFXT or SETUSELFXT to set the corresponding bit."
|
|
bitfld.long 0x0 1. "LFXTCTL_SETUSELFXT,Set SETUSELFXT to switch LFCLK to LFXT. Once set SETUSELFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "LFXTCTL_STARTLFXT,Set STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set STARTLFXT remains set until the next BOOTRST." "0: FALSE,1: TRUE"
|
|
line.long 0x4 "EXLFCTL,LFCLK_IN and LFCLK control"
|
|
hexmask.long.byte 0x4 24.--31. 1. "EXLFCTL_KEY,The key value of 36h (54) must be written to KEY together with SETUSEEXLF to set SETUSEEXLF."
|
|
bitfld.long 0x4 0. "EXLFCTL_SETUSEEXLF,Set SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set SETUSEEXLF remains set until the next BOOTRST." "?,1: TRUE"
|
|
group.long 0x3000++0x3
|
|
line.long 0x0 "FWEPROTMAIN,1 Sector Write-Erase per bit starting at address 0x0 of flash"
|
|
hexmask.long 0x0 0.--31. 1. "FWEPROTMAIN_DATA,1 Sector Write Erase protection 1: prohibits write-erase 0: allows"
|
|
group.long 0x3018++0xF
|
|
line.long 0x0 "FRXPROTMAINSTART,Flash RX Protection Start Address"
|
|
hexmask.long.word 0x0 6.--21. 1. "FRXPROTMAINSTART_ADDR,Flash RX Protection Start Address 64B granularity"
|
|
line.long 0x4 "FRXPROTMAINEND,Flash RX Protection End Address"
|
|
hexmask.long.word 0x4 6.--21. 1. "FRXPROTMAINEND_ADDR,Flash RX Protection End Address 64B granularity"
|
|
line.long 0x8 "FIPPROTMAINSTART,Flash IP Protection Start Address"
|
|
hexmask.long.word 0x8 6.--21. 1. "FIPPROTMAINSTART_ADDR,Flash IP Protection Start Address 64B granularity"
|
|
line.long 0xC "FIPPROTMAINEND,Flash IP Protection End Address"
|
|
hexmask.long.word 0xC 6.--21. 1. "FIPPROTMAINEND_ADDR,Flash IP Protection End Address 64B granularity"
|
|
wgroup.long 0x3038++0x7
|
|
line.long 0x0 "FLBANKSWPPOLICY,Flash Bank Swap Policy"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FLBANKSWPPOLICY_KEY,Must have KEY==0xCA(202) for write"
|
|
bitfld.long 0x0 0. "FLBANKSWPPOLICY_DISABLE,1: Disables Policy To Allow Flash Bank Swapping" "?,1: Disables Policy To Allow Flash Bank Swapping"
|
|
line.long 0x4 "FLBANKSWP,Flash MAIN bank address swap"
|
|
hexmask.long.byte 0x4 24.--31. 1. "FLBANKSWP_KEY,The key value of 58h (88) must be written with USEUPPER to change the bank swap configuration."
|
|
bitfld.long 0x4 0. "FLBANKSWP_USEUPPER,1: Use Upper Bank as Logical 0" "0: DISABLE,1: Use Upper Bank as Logical 0"
|
|
wgroup.long 0x3044++0x3
|
|
line.long 0x0 "FWENABLE,Security Firewall Enable Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FWENABLE_KEY,Must have KEY==0x76(118) for write"
|
|
bitfld.long 0x0 8. "FWENABLE_SRAMBOUNDARYLOCK,1: Blocks Writes from Changing SRAMBOUNDARY MMR" "?,1: Blocks Writes from Changing SRAMBOUNDARY MMR"
|
|
newline
|
|
bitfld.long 0x0 6. "FWENABLE_FLIPPROT,1: Flash Read IP ProtectionActive" "?,1: Flash Read IP ProtectionActive"
|
|
bitfld.long 0x0 4. "FWENABLE_FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active"
|
|
endif
|
|
group.long 0x113C++0x7
|
|
line.long 0x0 "GENCLKEN,General clock enable control"
|
|
bitfld.long 0x0 4. "GENCLKEN_MFPCLKEN,MFPCLKEN enables the middle frequency precision clock (MFPCLK)." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "GENCLKEN_EXCLKEN,EXCLKEN enables the CLK_OUT external clock output block." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "PMODECFG,Power mode configuration"
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x4 5. "PMODECFG_SYSSRAMONSTOP,SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x4 5. "PMODECFG_SYSSRAMONSTOP,SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x4 5. "PMODECFG_SYSSRAMONSTOP,SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 0.--1. "PMODECFG_DSLEEP,DSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU." "0: STOP,1: STANDBY,2: SHUTDOWN,?"
|
|
rgroup.long 0x1150++0x3
|
|
line.long 0x0 "FCC,Frequency clock counter (FCC) count"
|
|
hexmask.long.tbyte 0x0 0.--21. 1. "FCC_DATA,Frequency clock counter (FCC) count value."
|
|
sif (cpuis("MSPM0L110*"))
|
|
group.long 0x1170++0x3
|
|
line.long 0x0 "SYSOSCTRIMUSER,SYSOSC user-specified trim"
|
|
hexmask.long.word 0x0 20.--28. 1. "SYSOSCTRIMUSER_RDIV,RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSOSCTRIMUSER_RESFINE,RESFINE specifies the resister fine trim. This value changes with the target frequency."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "SYSOSCTRIMUSER_RESCOARSE,RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."
|
|
bitfld.long 0x0 4.--6. "SYSOSCTRIMUSER_CAP,CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SYSOSCTRIMUSER_FREQ,FREQ specifies the target user-trimmed frequency for SYSOSC." "?,1: SYSOSC16M,2: SYSOSC24M,?"
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "PMUOPAMP,GPAMP control"
|
|
bitfld.long 0x0 10.--11. "PMUOPAMP_CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: CHOPDISABLED,1: REGCHOP,2: ADCASSIST,?"
|
|
bitfld.long 0x0 8.--9. "PMUOPAMP_CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: CLK16KHZ,1: CLK8KHZ,2: CLK4KHZ,3: CLK2KHZ"
|
|
newline
|
|
bitfld.long 0x0 6. "PMUOPAMP_OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: FALSE,1: TRUE"
|
|
bitfld.long 0x0 4.--5. "PMUOPAMP_RRI,RRI selects the rail-to-rail input mode." "0: MODE0,1: MODE1,2: MODE2,3: MODE3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PMUOPAMP_NSEL,NSEL selects the GPAMP negative channel input." "0: SEL0,1: SEL1,2: SEL2,3: SEL3"
|
|
bitfld.long 0x0 1. "PMUOPAMP_PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "PMUOPAMP_ENABLE,Set ENABLE to turn on the GPAMP." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
group.long 0x1170++0x3
|
|
line.long 0x0 "SYSOSCTRIMUSER,SYSOSC user-specified trim"
|
|
hexmask.long.word 0x0 20.--28. 1. "SYSOSCTRIMUSER_RDIV,RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSOSCTRIMUSER_RESFINE,RESFINE specifies the resister fine trim. This value changes with the target frequency."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "SYSOSCTRIMUSER_RESCOARSE,RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."
|
|
bitfld.long 0x0 4.--6. "SYSOSCTRIMUSER_CAP,CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SYSOSCTRIMUSER_FREQ,FREQ specifies the target user-trimmed frequency for SYSOSC." "?,1: SYSOSC16M,2: SYSOSC24M,?"
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "PMUOPAMP,GPAMP control"
|
|
bitfld.long 0x0 10.--11. "PMUOPAMP_CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: CHOPDISABLED,1: REGCHOP,2: ADCASSIST,?"
|
|
bitfld.long 0x0 8.--9. "PMUOPAMP_CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: CLK16KHZ,1: CLK8KHZ,2: CLK4KHZ,3: CLK2KHZ"
|
|
newline
|
|
bitfld.long 0x0 6. "PMUOPAMP_OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: FALSE,1: TRUE"
|
|
bitfld.long 0x0 4.--5. "PMUOPAMP_RRI,RRI selects the rail-to-rail input mode." "0: MODE0,1: MODE1,2: MODE2,3: MODE3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PMUOPAMP_NSEL,NSEL selects the GPAMP negative channel input." "0: SEL0,1: SEL1,2: SEL2,3: SEL3"
|
|
bitfld.long 0x0 1. "PMUOPAMP_PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "PMUOPAMP_ENABLE,Set ENABLE to turn on the GPAMP." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
group.long 0x1170++0x3
|
|
line.long 0x0 "SYSOSCTRIMUSER,SYSOSC user-specified trim"
|
|
hexmask.long.word 0x0 20.--28. 1. "SYSOSCTRIMUSER_RDIV,RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."
|
|
hexmask.long.byte 0x0 16.--19. 1. "SYSOSCTRIMUSER_RESFINE,RESFINE specifies the resister fine trim. This value changes with the target frequency."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "SYSOSCTRIMUSER_RESCOARSE,RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."
|
|
bitfld.long 0x0 4.--6. "SYSOSCTRIMUSER_CAP,CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SYSOSCTRIMUSER_FREQ,FREQ specifies the target user-trimmed frequency for SYSOSC." "?,1: SYSOSC16M,2: SYSOSC24M,?"
|
|
group.long 0x1380++0x3
|
|
line.long 0x0 "PMUOPAMP,GPAMP control"
|
|
bitfld.long 0x0 10.--11. "PMUOPAMP_CHOPCLKMODE,CHOPCLKMODE selects the GPAMP chopping mode." "0: CHOPDISABLED,1: REGCHOP,2: ADCASSIST,?"
|
|
bitfld.long 0x0 8.--9. "PMUOPAMP_CHOPCLKFREQ,CHOPCLKFREQ selects the GPAMP chopping clock frequency" "0: CLK16KHZ,1: CLK8KHZ,2: CLK4KHZ,3: CLK2KHZ"
|
|
newline
|
|
bitfld.long 0x0 6. "PMUOPAMP_OUTENABLE,Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin" "0: FALSE,1: TRUE"
|
|
bitfld.long 0x0 4.--5. "PMUOPAMP_RRI,RRI selects the rail-to-rail input mode." "0: MODE0,1: MODE1,2: MODE2,3: MODE3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "PMUOPAMP_NSEL,NSEL selects the GPAMP negative channel input." "0: SEL0,1: SEL1,2: SEL2,3: SEL3"
|
|
bitfld.long 0x0 1. "PMUOPAMP_PCHENABLE,Set PCHENABLE to enable the positive channel input." "0: FALSE,1: TRUE"
|
|
newline
|
|
bitfld.long 0x0 0. "PMUOPAMP_ENABLE,Set ENABLE to turn on the GPAMP." "0: FALSE,1: TRUE"
|
|
endif
|
|
group.long 0x1178++0x3
|
|
line.long 0x0 "SRAMBOUNDARY,SRAM Write Boundary"
|
|
hexmask.long.word 0x0 5.--19. 1. "SRAMBOUNDARY_ADDR,SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid.."
|
|
group.long 0x1180++0x3
|
|
line.long 0x0 "SYSTEMCFG,System configuration"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SYSTEMCFG_KEY,The key value of 1Bh (27) must be written to KEY together with contents to be updated. Reads as 0"
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 8. "SYSTEMCFG_SUPERCAPEN,SUPERCAP specifies whether the battery backup system can be powered by a SUPERCAP" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 8. "SYSTEMCFG_SUPERCAPEN,SUPERCAP specifies whether the battery backup system can be powered by a SUPERCAP" "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 2. "SYSTEMCFG_FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 2. "SYSTEMCFG_FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 2. "SYSTEMCFG_FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 2. "SYSTEMCFG_FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 2. "SYSTEMCFG_FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 2. "SYSTEMCFG_FLASHECCRSTDIS,FLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI." "0: FALSE,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x0 1. "SYSTEMCFG_WWDTLP1RSTDIS,WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI." "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x0 1. "SYSTEMCFG_WWDTLP1RSTDIS,WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI." "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x0 1. "SYSTEMCFG_WWDTLP1RSTDIS,WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI." "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x0 1. "SYSTEMCFG_WWDTLP1RSTDIS,WWDTLP1RSTDIS specifies whether a WWDT Error Event will trigger a SYSRST or an NMI." "0: FALSE,1: TRUE"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 0. "SYSTEMCFG_WWDTLP0RSTDIS,WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI." "0: FALSE,1: TRUE"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
group.long 0x1190++0x3
|
|
line.long 0x0 "BEEPCFG,BEEPER Configuration"
|
|
bitfld.long 0x0 4.--5. "BEEPCFG_FREQ,Beeper Output Frequency Configuration" "0: 8KHZ,1: 4KHZ,2: 2KHZ,3: 1KHZ"
|
|
bitfld.long 0x0 0. "BEEPCFG_EN,Beeper Output Enable" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
group.long 0x1200++0x3
|
|
line.long 0x0 "WRITELOCK,SYSCTL register write lockout"
|
|
bitfld.long 0x0 0. "WRITELOCK_ACTIVE,ACTIVE controls whether critical SYSCTL registers are write protected or not." "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1220++0x3
|
|
line.long 0x0 "RSTCAUSE,Reset cause"
|
|
hexmask.long.byte 0x0 0.--4. 1. "RSTCAUSE_ID,ID is a read-to-clear field which indicates the lowest level reset cause since the last read."
|
|
group.long 0x1300++0x3
|
|
line.long 0x0 "RESETLEVEL,Reset level for application-triggered reset command"
|
|
bitfld.long 0x0 0.--2. "RESETLEVEL_LEVEL,LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset." "0: CPU,1: BOOT,2: BOOTLOADERENTRY,3: POR,4: BOOTLOADEREXIT,?,?,?"
|
|
wgroup.long 0x1304++0x3
|
|
line.long 0x0 "RESETCMD,Execute an application-triggered reset command"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RESETCMD_KEY,The key value of E4h (228) must be written to KEY together with GO to trigger the reset."
|
|
bitfld.long 0x0 0. "RESETCMD_GO,Execute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY." "?,1: TRUE"
|
|
group.long 0x1308++0x3
|
|
line.long 0x0 "BORTHRESHOLD,BOR threshold selection"
|
|
bitfld.long 0x0 0.--1. "BORTHRESHOLD_LEVEL,LEVEL specifies the desired BOR threshold and BOR mode." "0: BORMIN,1: BORLEVEL1,2: BORLEVEL2,3: BORLEVEL3"
|
|
wgroup.long 0x130C++0x7
|
|
line.long 0x0 "BORCLRCMD,Set the BOR threshold"
|
|
hexmask.long.byte 0x0 24.--31. 1. "BORCLRCMD_KEY,The key value of C7h (199) must be written to KEY together with GO to trigger the clear and BOR threshold change."
|
|
bitfld.long 0x0 0. "BORCLRCMD_GO,GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register." "?,1: TRUE"
|
|
line.long 0x4 "SYSOSCFCLCTL,SYSOSC frequency correction loop (FCL) ROSC enable"
|
|
hexmask.long.byte 0x4 24.--31. 1. "SYSOSCFCLCTL_KEY,The key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL."
|
|
sif (cpuis("MSPM0G110*"))
|
|
bitfld.long 0x4 1. "SYSOSCFCLCTL_SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
bitfld.long 0x4 1. "SYSOSCFCLCTL_SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
bitfld.long 0x4 1. "SYSOSCFCLCTL_SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
bitfld.long 0x4 1. "SYSOSCFCLCTL_SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x4 1. "SYSOSCFCLCTL_SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: TRUE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x4 1. "SYSOSCFCLCTL_SETUSEEXRES,Set SETUSEEXRES to specify that an external resistor will be used for the FCL. An appropriate resistor must be populated on the ROSC pin. This state is locked until the next BOOTRST." "?,1: TRUE"
|
|
endif
|
|
newline
|
|
bitfld.long 0x4 0. "SYSOSCFCLCTL_SETUSEFCL,Set SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled this state is locked until the next BOOTRST." "?,1: TRUE"
|
|
wgroup.long 0x131C++0x7
|
|
line.long 0x0 "SHDNIOREL,SHUTDOWN IO release control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SHDNIOREL_KEY,The key value 91h must be written to KEY together with RELEASE to set RELEASE."
|
|
bitfld.long 0x0 0. "SHDNIOREL_RELEASE,Set RELEASE to release the IO after a SHUTDOWN mode exit." "?,1: TRUE"
|
|
line.long 0x4 "EXRSTPIN,Disable the reset function of the NRST pin"
|
|
hexmask.long.byte 0x4 24.--31. 1. "EXRSTPIN_KEY,The key value 1Eh must be written together with DISABLE to disable the reset function."
|
|
bitfld.long 0x4 0. "EXRSTPIN_DISABLE,Set DISABLE to disable the reset function of the NRST pin. Once set this configuration is locked until the next POR." "0: FALSE,1: TRUE"
|
|
wgroup.long 0x1328++0x7
|
|
line.long 0x0 "SWDCFG,Disable the SWD function on the SWD pins"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SWDCFG_KEY,The key value 62h (98) must be written to KEY together with DISBALE to disable the SWD functions."
|
|
bitfld.long 0x0 0. "SWDCFG_DISABLE,Set DISABLE to disable the SWD function on SWD pins allowing the SWD pins to be used as GPIO." "?,1: TRUE"
|
|
line.long 0x4 "FCCCMD,Frequency clock counter start capture"
|
|
hexmask.long.byte 0x4 24.--31. 1. "FCCCMD_KEY,The key value 0Eh (14) must be written with GO to start a capture."
|
|
bitfld.long 0x4 0. "FCCCMD_GO,Set GO to start a capture with the frequency clock counter (FCC)." "?,1: TRUE"
|
|
group.long 0x1400++0xF
|
|
line.long 0x0 "SHUTDNSTORE0,Shutdown storage memory (byte 0)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SHUTDNSTORE0_DATA,Shutdown storage byte 0"
|
|
line.long 0x4 "SHUTDNSTORE1,Shutdown storage memory (byte 1)"
|
|
hexmask.long.byte 0x4 0.--7. 1. "SHUTDNSTORE1_DATA,Shutdown storage byte 1"
|
|
line.long 0x8 "SHUTDNSTORE2,Shutdown storage memory (byte 2)"
|
|
hexmask.long.byte 0x8 0.--7. 1. "SHUTDNSTORE2_DATA,Shutdown storage byte 2"
|
|
line.long 0xC "SHUTDNSTORE3,Shutdown storage memory (byte 3)"
|
|
hexmask.long.byte 0xC 0.--7. 1. "SHUTDNSTORE3_DATA,Shutdown storage byte 3"
|
|
sif (cpuis("MSPM0L122*"))
|
|
group.long 0x3000++0x3
|
|
line.long 0x0 "FWEPROTMAIN,1 Sector Write-Erase per bit starting at address 0x0 of flash"
|
|
hexmask.long 0x0 0.--31. 1. "FWEPROTMAIN_DATA,1 Sector Write Erase protection 1: prohibits write-erase 0: allows"
|
|
group.long 0x3018++0xF
|
|
line.long 0x0 "FRXPROTMAINSTART,Flash RX Protection Start Address"
|
|
hexmask.long.word 0x0 6.--21. 1. "FRXPROTMAINSTART_ADDR,Flash RX Protection Start Address 64B granularity"
|
|
line.long 0x4 "FRXPROTMAINEND,Flash RX Protection End Address"
|
|
hexmask.long.word 0x4 6.--21. 1. "FRXPROTMAINEND_ADDR,Flash RX Protection End Address 64B granularity"
|
|
line.long 0x8 "FIPPROTMAINSTART,Flash IP Protection Start Address"
|
|
hexmask.long.word 0x8 6.--21. 1. "FIPPROTMAINSTART_ADDR,Flash IP Protection Start Address 64B granularity"
|
|
line.long 0xC "FIPPROTMAINEND,Flash IP Protection End Address"
|
|
hexmask.long.word 0xC 6.--21. 1. "FIPPROTMAINEND_ADDR,Flash IP Protection End Address 64B granularity"
|
|
wgroup.long 0x3038++0x7
|
|
line.long 0x0 "FLBANKSWPPOLICY,Flash Bank Swap Policy"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FLBANKSWPPOLICY_KEY,Must have KEY==0xCA(202) for write"
|
|
bitfld.long 0x0 0. "FLBANKSWPPOLICY_DISABLE,1: Disables Policy To Allow Flash Bank Swapping" "?,1: Disables Policy To Allow Flash Bank Swapping"
|
|
line.long 0x4 "FLBANKSWP,Flash MAIN bank address swap"
|
|
hexmask.long.byte 0x4 24.--31. 1. "FLBANKSWP_KEY,The key value of 58h (88) must be written with USEUPPER to change the bank swap configuration."
|
|
bitfld.long 0x4 0. "FLBANKSWP_USEUPPER,1: Use Upper Bank as Logical 0" "0: DISABLE,1: Use Upper Bank as Logical 0"
|
|
wgroup.long 0x3044++0x3
|
|
line.long 0x0 "FWENABLE,Security Firewall Enable Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FWENABLE_KEY,Must have KEY==0x76(118) for write"
|
|
bitfld.long 0x0 8. "FWENABLE_SRAMBOUNDARYLOCK,1: Blocks Writes from Changing SRAMBOUNDARY MMR" "?,1: Blocks Writes from Changing SRAMBOUNDARY MMR"
|
|
newline
|
|
bitfld.long 0x0 6. "FWENABLE_FLIPPROT,1: Flash Read IP ProtectionActive" "?,1: Flash Read IP ProtectionActive"
|
|
bitfld.long 0x0 4. "FWENABLE_FLRXPROT,1: Flash Read Execute Protection Active" "?,1: Flash Read Execute Protection Active"
|
|
wgroup.long 0x3060++0x3
|
|
line.long 0x0 "INITDONE,INITCODE PASS"
|
|
hexmask.long.byte 0x0 24.--31. 1. "INITDONE_KEY,Must have KEY==0x9D(157) for write"
|
|
bitfld.long 0x0 0. "INITDONE_PASS,INITCODE writes 1 for PASS left unwritten a timeout will occur if not blocked" "?,1: TRUE"
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
wgroup.long 0x3060++0x3
|
|
line.long 0x0 "INITDONE,INITCODE PASS"
|
|
hexmask.long.byte 0x0 24.--31. 1. "INITDONE_KEY,Must have KEY==0x9D(157) for write"
|
|
bitfld.long 0x0 0. "INITDONE_PASS,INITCODE writes 1 for PASS left unwritten a timeout will occur if not blocked" "?,1: TRUE"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*")||cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "TIMA (Advanced Timer)"
|
|
base ad:0x0
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
tree "TIMA0"
|
|
base ad:0x40860000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
bitfld.long 0x0 0.--1. "FPUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
bitfld.long 0x4 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 26. "IMASK_REPC,Repeat Counter Zero Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "IMASK_F,Fault Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "IMASK_CCU5,Compare UP event mask CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "IMASK_CCU4,Compare UP event mask CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "IMASK_CCD5,Compare DN event mask CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "IMASK_CCD4,Compare DN event mask CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "IMASK_CCU3,Capture or Compare UP event mask CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "IMASK_CCU2,Capture or Compare UP event mask CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "IMASK_CCD3,Capture or Compare DN event mask CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "IMASK_CCD2,Capture or Compare DN event mask CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 26. "RIS_REPC,Repeat Counter Zero" "0: CLR,1: SET"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "RIS_F,Fault" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "RIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "RIS_CCU4,Compare up event generated an interrupt CCU4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "RIS_CCD5,Compare down event generated an interrupt CCD5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "RIS_CCD4,Compare down event generated an interrupt CCD4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RIS_CCU3,Capture or compare up event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "RIS_CCU2,Capture or compare up event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "RIS_CCD3,Capture or compare down event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "RIS_CCD2,Capture or compare down event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 26. "MIS_REPC,Repeat Counter Zero" "0: CLR,1: SET"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "MIS_F,Fault" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "MIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "MIS_CCU4,Compare up event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "MIS_CCD5,Compare down event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "MIS_CCD4,Compare down event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "MIS_CCU3,Capture or compare up event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "MIS_CCU2,Capture or compare up event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "MIS_CCD3,Capture or compare down event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "MIS_CCD2,Capture or compare down event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 26. "ISET_REPC,Repeat Counter Zero event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "ISET_F,Fault event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "ISET_CCU5,Compare up event 5 SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "ISET_CCU4,Compare up event 4 SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "ISET_CCD5,Compare down event 5 SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "ISET_CCD4,Compare down event 4 SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "ISET_CCU3,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "ISET_CCU2,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "ISET_CCD3,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "ISET_CCD2,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 26. "ICLR_REPC,Repeat Counter Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 24. "ICLR_F,Fault event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "ICLR_CCU5,Compare up event 5 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 14. "ICLR_CCU4,Compare up event 4 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "ICLR_CCD5,Compare down event 5 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "ICLR_CCD4,Compare down event 4 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "ICLR_CCU3,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "ICLR_CCU2,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "ICLR_CCD3,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "ICLR_CCD2,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 3. "CCPD_C0CCP3,Counter CCP3" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 2. "CCPD_C0CCP2,Counter CCP2" "0: INPUT,1: OUTPUT"
|
|
newline
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 3. "ODIS_C0CCP3,Counter CCP3 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 2. "ODIS_C0CCP2,Counter CCP2 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
newline
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1120++0x7
|
|
line.long 0x0 "FSCTL,Fault Source Control"
|
|
bitfld.long 0x0 6. "FSCTL_FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "FSCTL_FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 4. "FSCTL_FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "FSCTL_FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 2. "FSCTL_FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 1. "FSCTL_FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "FSCTL_FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "GCTL,Shadow to active load mask"
|
|
bitfld.long 0x4 0. "GCTL_SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 24. "CTRCTL_PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x4 23. "CTRCTL_SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x4 19. "CTRCTL_FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 18. "CTRCTL_FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: CONT_COUNT,1: SUSP_COUNT"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1818)++0x3
|
|
line.long 0x0 "CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_23_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1820)++0x3
|
|
line.long 0x0 "CC_45[$1],Compare Register 4 to Compare Register 5"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_45_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 25. "CCCTL_01_SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
newline
|
|
bitfld.long 0x0 18.--20. "CCCTL_01_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
|
|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1838)++0x3
|
|
line.long 0x0 "CCCTL_23[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_23_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_23_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 25. "CCCTL_23_SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 22.--24. "CCCTL_23_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
newline
|
|
bitfld.long 0x0 18.--20. "CCCTL_23_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
bitfld.long 0x0 17. "CCCTL_23_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_23_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
bitfld.long 0x0 8.--10. "CCCTL_23_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 4.--6. "CCCTL_23_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
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|
bitfld.long 0x0 0.--2. "CCCTL_23_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1840)++0x3
|
|
line.long 0x0 "CCCTL_45[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 25. "CCCTL_45_SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 18.--20. "CCCTL_45_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1858)++0x3
|
|
line.long 0x0 "OCTL_23[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_23_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_23_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_23_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 30.--31. "CCACT_01_SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Force Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
newline
|
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bitfld.long 0x0 25.--27. "CCACT_01_FEXACT,CCP Output Action on Fault Exit" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE,4: CCP_HIGHZ,?,?,?"
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|
bitfld.long 0x0 22.--24. "CCACT_01_FENACT,CCP Output Action on Fault Entry" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE,4: CCP_HIGHZ,?,?,?"
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|
newline
|
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bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
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bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
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bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1878)++0x3
|
|
line.long 0x0 "CCACT_23[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 30.--31. "CCACT_23_SWFRCACT_CMPL,CCP_CMPL Output Action on Software Force Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 28.--29. "CCACT_23_SWFRCACT,CCP Output Action on Software Force Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
newline
|
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bitfld.long 0x0 25.--27. "CCACT_23_FEXACT,CCP Output Action on Fault Exit" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE,4: CCP_HIGHZ,?,?,?"
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|
bitfld.long 0x0 22.--24. "CCACT_23_FENACT,CCP Output Action on Fault Entry" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE,4: CCP_HIGHZ,?,?,?"
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|
newline
|
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bitfld.long 0x0 15.--16. "CCACT_23_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 12.--13. "CCACT_23_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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newline
|
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bitfld.long 0x0 9.--10. "CCACT_23_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 6.--7. "CCACT_23_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
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bitfld.long 0x0 3.--4. "CCACT_23_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 0.--1. "CCACT_23_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1888)++0x3
|
|
line.long 0x0 "IFCTL_23[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_23_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_23_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_23_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_23_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_23_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18A0++0x7
|
|
line.long 0x0 "PL,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PL_PHASE,Phase Load value"
|
|
line.long 0x4 "DBCTL,Dead Band insertion control register"
|
|
hexmask.long.word 0x4 16.--27. 1. "DBCTL_FALLDELAY,Fall Delay"
|
|
bitfld.long 0x4 12. "DBCTL_M1_ENABLE,Dead Band Mode 1 Enable." "0: DISABLED,1: ENABLED"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "DBCTL_RISEDELAY,Rise Delay"
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
rgroup.long 0x18B4++0x3
|
|
line.long 0x0 "RC,Repeat counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RC_RC,Repeat Counter Value"
|
|
group.long 0x18B8++0x3
|
|
line.long 0x0 "RCLD,Repeat counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RCLD_RCLD,Repeat Counter Load Value"
|
|
group.long 0x18D0++0x7
|
|
line.long 0x0 "FCTL,Fault Control Register"
|
|
bitfld.long 0x0 13. "FCTL_FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
bitfld.long 0x0 12. "FCTL_FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
newline
|
|
bitfld.long 0x0 11. "FCTL_FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
bitfld.long 0x0 10. "FCTL_FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
newline
|
|
bitfld.long 0x0 9. "FCTL_FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
bitfld.long 0x0 8. "FCTL_FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
newline
|
|
bitfld.long 0x0 7. "FCTL_TFIM,Trigger Fault Input Mask" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 3.--4. "FCTL_FL,Fault Latch mode" "0: NO_LATCH,1: LATCH_SW_CLR,2: LATCH_Z_CLR,3: LATCH_LD_CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "FCTL_FI,Fault Input" "0: INDEPENDENT,1: DEPENDENT"
|
|
bitfld.long 0x0 0. "FCTL_FIEN,Fault Input Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0x4 "FIFCTL,Fault input Filter control register"
|
|
bitfld.long 0x4 4. "FIFCTL_FILTEN,Filter Enable" "0: BYPASS,1: FILTERED"
|
|
bitfld.long 0x4 3. "FIFCTL_CPV,Consecutive Period/Voting Select" "0: CONSEC_PER,1: VOTING"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "FIFCTL_FP,Filter Period" "0: PER_3,1: PER_5,2: PER_8,?"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "TIMA0"
|
|
base ad:0x40860000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 26. "IMASK_REPC,Repeat Counter Zero Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "IMASK_F,Fault Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "IMASK_CCU5,Compare UP event mask CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "IMASK_CCU4,Compare UP event mask CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "IMASK_CCD5,Compare DN event mask CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "IMASK_CCD4,Compare DN event mask CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "IMASK_CCU3,Capture or Compare UP event mask CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "IMASK_CCU2,Capture or Compare UP event mask CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "IMASK_CCD3,Capture or Compare DN event mask CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "IMASK_CCD2,Capture or Compare DN event mask CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 26. "RIS_REPC,Repeat Counter Zero" "0: CLR,1: SET"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "RIS_F,Fault" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "RIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "RIS_CCU4,Compare up event generated an interrupt CCU4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "RIS_CCD5,Compare down event generated an interrupt CCD5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "RIS_CCD4,Compare down event generated an interrupt CCD4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RIS_CCU3,Capture or compare up event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "RIS_CCU2,Capture or compare up event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "RIS_CCD3,Capture or compare down event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "RIS_CCD2,Capture or compare down event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 26. "MIS_REPC,Repeat Counter Zero" "0: CLR,1: SET"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "MIS_F,Fault" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "MIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "MIS_CCU4,Compare up event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "MIS_CCD5,Compare down event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "MIS_CCD4,Compare down event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "MIS_CCU3,Capture or compare up event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "MIS_CCU2,Capture or compare up event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "MIS_CCD3,Capture or compare down event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "MIS_CCD2,Capture or compare down event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 26. "ISET_REPC,Repeat Counter Zero event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 24. "ISET_F,Fault event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "ISET_CCU5,Compare up event 5 SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "ISET_CCU4,Compare up event 4 SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "ISET_CCD5,Compare down event 5 SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "ISET_CCD4,Compare down event 4 SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "ISET_CCU3,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "ISET_CCU2,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "ISET_CCD3,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "ISET_CCD2,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 26. "ICLR_REPC,Repeat Counter Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 24. "ICLR_F,Fault event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "ICLR_CCU5,Compare up event 5 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 14. "ICLR_CCU4,Compare up event 4 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "ICLR_CCD5,Compare down event 5 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "ICLR_CCD4,Compare down event 4 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "ICLR_CCU3,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "ICLR_CCU2,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "ICLR_CCD3,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "ICLR_CCD2,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 3. "CCPD_C0CCP3,Counter CCP3" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 2. "CCPD_C0CCP2,Counter CCP2" "0: INPUT,1: OUTPUT"
|
|
newline
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 3. "ODIS_C0CCP3,Counter CCP3 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 2. "ODIS_C0CCP2,Counter CCP2 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
newline
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1120++0x7
|
|
line.long 0x0 "FSCTL,Fault Source Control"
|
|
bitfld.long 0x0 6. "FSCTL_FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "FSCTL_FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 4. "FSCTL_FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "FSCTL_FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 2. "FSCTL_FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 1. "FSCTL_FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "FSCTL_FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "GCTL,Shadow to active load mask"
|
|
bitfld.long 0x4 0. "GCTL_SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 24. "CTRCTL_PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x4 23. "CTRCTL_SLZERCNEZ,Suppress Load and Zero Events if Repeat Counter is Not Equal to Zero." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x4 19. "CTRCTL_FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 18. "CTRCTL_FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: CONT_COUNT,1: SUSP_COUNT"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1818)++0x3
|
|
line.long 0x0 "CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_23_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1820)++0x3
|
|
line.long 0x0 "CC_45[$1],Compare Register 4 to Compare Register 5"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_45_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 25. "CCCTL_01_SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
newline
|
|
bitfld.long 0x0 18.--20. "CCCTL_01_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
|
|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1838)++0x3
|
|
line.long 0x0 "CCCTL_23[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_23_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_23_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 25. "CCCTL_23_SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 22.--24. "CCCTL_23_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
newline
|
|
bitfld.long 0x0 18.--20. "CCCTL_23_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
bitfld.long 0x0 17. "CCCTL_23_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_23_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "CCCTL_23_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CCCTL_23_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
|
|
bitfld.long 0x0 0.--2. "CCCTL_23_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1840)++0x3
|
|
line.long 0x0 "CCCTL_45[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 25. "CCCTL_45_SCERCNEZ,Suppress Compare Event if Repeat Counter is Not Equal to Zero" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 18.--20. "CCCTL_45_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1858)++0x3
|
|
line.long 0x0 "OCTL_23[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_23_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_23_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_23_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 30.--31. "CCACT_01_SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
newline
|
|
bitfld.long 0x0 25.--27. "CCACT_01_FEXACT,CCP Output Action on Fault Exit" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE,4: CCP_HIGHZ,?,?,?"
|
|
bitfld.long 0x0 22.--24. "CCACT_01_FENACT,CCP Output Action on Fault Entry" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE,4: CCP_HIGHZ,?,?,?"
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|
newline
|
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bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
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bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
|
bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1878)++0x3
|
|
line.long 0x0 "CCACT_23[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 30.--31. "CCACT_23_SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 28.--29. "CCACT_23_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
newline
|
|
bitfld.long 0x0 25.--27. "CCACT_23_FEXACT,CCP Output Action on Fault Exit" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE,4: CCP_HIGHZ,?,?,?"
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|
bitfld.long 0x0 22.--24. "CCACT_23_FENACT,CCP Output Action on Fault Entry" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE,4: CCP_HIGHZ,?,?,?"
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|
newline
|
|
bitfld.long 0x0 15.--16. "CCACT_23_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 12.--13. "CCACT_23_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
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newline
|
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bitfld.long 0x0 9.--10. "CCACT_23_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 6.--7. "CCACT_23_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
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bitfld.long 0x0 3.--4. "CCACT_23_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 0.--1. "CCACT_23_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1888)++0x3
|
|
line.long 0x0 "IFCTL_23[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_23_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_23_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_23_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_23_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_23_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18A0++0x7
|
|
line.long 0x0 "PL,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PL_PHASE,Phase Load value"
|
|
line.long 0x4 "DBCTL,Dead Band insertion control register"
|
|
hexmask.long.word 0x4 16.--27. 1. "DBCTL_FALLDELAY,Fall Delay"
|
|
bitfld.long 0x4 12. "DBCTL_M1_ENABLE,Dead Band Mode 1 Enable." "0: DISABLED,1: ENABLED"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "DBCTL_RISEDELAY,Rise Delay"
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
rgroup.long 0x18B4++0x3
|
|
line.long 0x0 "RC,Repeat counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RC_RC,Repeat Counter Value"
|
|
group.long 0x18B8++0x3
|
|
line.long 0x0 "RCLD,Repeat counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RCLD_RCLD,Repeat Counter Load Value"
|
|
group.long 0x18D0++0x7
|
|
line.long 0x0 "FCTL,Fault Control Register"
|
|
bitfld.long 0x0 13. "FCTL_FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
bitfld.long 0x0 12. "FCTL_FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
newline
|
|
bitfld.long 0x0 11. "FCTL_FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
bitfld.long 0x0 10. "FCTL_FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
newline
|
|
bitfld.long 0x0 9. "FCTL_FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
bitfld.long 0x0 8. "FCTL_FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
newline
|
|
bitfld.long 0x0 7. "FCTL_TFIM,Trigger Fault Input Mask" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 3.--4. "FCTL_FL,Fault Latch mode" "0: NO_LATCH,1: LATCH_SW_CLR,2: LATCH_Z_CLR,3: LATCH_LD_CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "FCTL_FI,Fault Input" "0: INDEPENDENT,1: DEPENDENT"
|
|
bitfld.long 0x0 0. "FCTL_FIEN,Fault Input Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0x4 "FIFCTL,Fault input Filter control register"
|
|
bitfld.long 0x4 4. "FIFCTL_FILTEN,Filter Enable" "0: BYPASS,1: FILTERED"
|
|
bitfld.long 0x4 3. "FIFCTL_CPV,Consecutive Period/Voting Select" "0: CONSEC_PER,1: VOTING"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "FIFCTL_FP,Filter Period" "0: PER_3,1: PER_5,2: PER_8,?"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "TIMA1"
|
|
base ad:0x40862000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "IMASK_F,Fault Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "IMASK_CCU5,Compare UP event mask CCP5" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "IMASK_CCU4,Compare UP event mask CCP4" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "IMASK_CCD5,Compare DN event mask CCP5" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "IMASK_CCD4,Compare DN event mask CCP4" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "RIS_F,Fault" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "RIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "RIS_CCU4,Compare up event generated an interrupt CCU4" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "RIS_CCD5,Compare down event generated an interrupt CCD5" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "RIS_CCD4,Compare down event generated an interrupt CCD4" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 24. "MIS_F,Fault" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "MIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "MIS_CCU4,Compare up event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "MIS_CCD5,Compare down event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "MIS_CCD4,Compare down event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 24. "ISET_F,Fault event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "ISET_CCU5,Compare up event 5 SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "ISET_CCU4,Compare up event 4 SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "ISET_CCD5,Compare down event 5 SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "ISET_CCD4,Compare down event 4 SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 24. "ICLR_F,Fault event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 15. "ICLR_CCU5,Compare up event 5 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "ICLR_CCU4,Compare up event 4 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "ICLR_CCD5,Compare down event 5 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "ICLR_CCD4,Compare down event 4 CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
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hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1120++0x7
|
|
line.long 0x0 "FSCTL,Fault Source Control"
|
|
bitfld.long 0x0 6. "FSCTL_FEX2EN,This field controls whether the fault caused by external fault pin2 is enable." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 5. "FSCTL_FEX1EN,This field controls whether the fault caused by external fault pin1 is enable." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 4. "FSCTL_FEX0EN,This field controls whether the fault caused by external fault pin0 is enable." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "FSCTL_FAC2EN,This field controls whether the fault signal detected by the analog comparator2 is enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 2. "FSCTL_FAC1EN,This field controls whether the fault signal detected by the analog comparator1 is enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 1. "FSCTL_FAC0EN,This field controls whether the fault signal detected by the analog comparator0 is enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "FSCTL_FCEN,This field controls whether the fault caused by the system clock fault is enable." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "GCTL,Shadow to active load mask"
|
|
bitfld.long 0x4 0. "GCTL_SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 24. "CTRCTL_PLEN,Phase Load Enable. This bit allows the timer to have phase load feature." "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x4 19. "CTRCTL_FRB,Fault Resume Behavior This bit specifies what the device does following the release/exit of fault condition." "0: RESUME,1: CVAE_ACTION"
|
|
bitfld.long 0x4 18. "CTRCTL_FB,Fault Behavior This bit specifies whether the counter continues running or suspends during a fault mode. There is a separate control under REPEAT to indicate whether counting is to suspend at next Counter==0" "0: CONT_COUNT,1: SUSP_COUNT"
|
|
newline
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1820)++0x3
|
|
line.long 0x0 "CC_45[$1],Compare Register 4 to Compare Register 5"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_45_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
bitfld.long 0x0 18.--20. "CCCTL_01_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1840)++0x3
|
|
line.long 0x0 "CCCTL_45[$1],Capture or Compare Control Registers"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 30.--31. "CCACT_01_SWFRCACT_CMPL,CCP_CMPL Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
newline
|
|
bitfld.long 0x0 25.--27. "CCACT_01_FEXACT,CCP Output Action on Fault Exit" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE,4: CCP_HIGHZ,?,?,?"
|
|
bitfld.long 0x0 22.--24. "CCACT_01_FENACT,CCP Output Action on Fault Entry" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE,4: CCP_HIGHZ,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18A0++0x7
|
|
line.long 0x0 "PL,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "PL_PHASE,Phase Load value"
|
|
line.long 0x4 "DBCTL,Dead Band insertion control register"
|
|
hexmask.long.word 0x4 16.--27. 1. "DBCTL_FALLDELAY,Fall Delay"
|
|
bitfld.long 0x4 12. "DBCTL_M1_ENABLE,Dead Band Mode 1 Enable." "0: DISABLED,1: ENABLED"
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "DBCTL_RISEDELAY,Rise Delay"
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
group.long 0x18D0++0x7
|
|
line.long 0x0 "FCTL,Fault Control Register"
|
|
bitfld.long 0x0 13. "FCTL_FSENEXT2,Specifies whether the external fault pin3 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
bitfld.long 0x0 12. "FCTL_FSENEXT1,Specifies whether the external fault pin1 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
newline
|
|
bitfld.long 0x0 11. "FCTL_FSENEXT0,Specifies whether the external fault pin0 sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
bitfld.long 0x0 10. "FCTL_FSENAC2,Specifies whether the analog comparator2 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
newline
|
|
bitfld.long 0x0 9. "FCTL_FSENAC1,Specifies whether the analog comparator1 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
bitfld.long 0x0 8. "FCTL_FSENAC0,Specifies whether the analog comparator0 fault sense is high or low active" "0: LOWCTIVE,1: HIGHACTIVE"
|
|
newline
|
|
bitfld.long 0x0 7. "FCTL_TFIM,Trigger Fault Input Mask" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 3.--4. "FCTL_FL,Fault Latch mode" "0: NO_LATCH,1: LATCH_SW_CLR,2: LATCH_Z_CLR,3: LATCH_LD_CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "FCTL_FI,Fault Input" "0: INDEPENDENT,1: DEPENDENT"
|
|
bitfld.long 0x0 0. "FCTL_FIEN,Fault Input Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0x4 "FIFCTL,Fault input Filter control register"
|
|
bitfld.long 0x4 4. "FIFCTL_FILTEN,Filter Enable" "0: BYPASS,1: FILTERED"
|
|
bitfld.long 0x4 3. "FIFCTL_CPV,Consecutive Period/Voting Select" "0: CONSEC_PER,1: VOTING"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "FIFCTL_FP,Filter Period" "0: PER_3,1: PER_5,2: PER_8,?"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "TIMG (General Purpose Timer)"
|
|
base ad:0x0
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "TIMG0"
|
|
base ad:0x40084000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
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|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
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|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
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|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
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|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
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|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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newline
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|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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newline
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bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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newline
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bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
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bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
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bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
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newline
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bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
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bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
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|
newline
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hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
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repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
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|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "TIMG0"
|
|
base ad:0x40084000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
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|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
bitfld.long 0x0 0.--1. "FPUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
bitfld.long 0x4 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
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hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
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bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
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|
newline
|
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bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
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|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
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|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
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|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
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|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
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|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
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|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
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|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
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|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
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|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
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|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
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|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
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|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
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bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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newline
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bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
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bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
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bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
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newline
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bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
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|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
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|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
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|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "TIMG1"
|
|
base ad:0x40086000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
bitfld.long 0x0 0.--1. "FPUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
bitfld.long 0x4 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
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|
newline
|
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bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
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|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
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|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
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|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
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|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
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|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
|
bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "TIMG2"
|
|
base ad:0x40088000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
bitfld.long 0x0 0.--1. "FPUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
bitfld.long 0x4 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
|
|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
|
bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "TIMG4"
|
|
base ad:0x4008C000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
bitfld.long 0x0 0.--1. "FPUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
bitfld.long 0x4 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "MIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "MIS_CCU4,Compare up event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "MIS_CCD5,Compare down event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "MIS_CCD4,Compare down event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1124++0x3
|
|
line.long 0x0 "GCTL,Shadow to active load mask"
|
|
bitfld.long 0x0 0. "GCTL_SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
bitfld.long 0x0 18.--20. "CCCTL_01_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
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bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
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|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "TIMG4"
|
|
base ad:0x4008C000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "MIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "MIS_CCU4,Compare up event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "MIS_CCD5,Compare down event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "MIS_CCD4,Compare down event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1124++0x3
|
|
line.long 0x0 "GCTL,Shadow to active load mask"
|
|
bitfld.long 0x0 0. "GCTL_SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
bitfld.long 0x0 18.--20. "CCCTL_01_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
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|
newline
|
|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Force Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
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|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
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bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
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|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
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|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
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|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "TIMG5"
|
|
base ad:0x4008E000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
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|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
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|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "MIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "MIS_CCU4,Compare up event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "MIS_CCD5,Compare down event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "MIS_CCD4,Compare down event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1124++0x3
|
|
line.long 0x0 "GCTL,Shadow to active load mask"
|
|
bitfld.long 0x0 0. "GCTL_SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
bitfld.long 0x0 18.--20. "CCCTL_01_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Force Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "TIMG6"
|
|
base ad:0x40868000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "MIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "MIS_CCU4,Compare up event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "MIS_CCD5,Compare down event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "MIS_CCD4,Compare down event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1124++0x3
|
|
line.long 0x0 "GCTL,Shadow to active load mask"
|
|
bitfld.long 0x0 0. "GCTL_SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
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|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
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|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
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|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
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|
bitfld.long 0x0 18.--20. "CCCTL_01_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
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|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
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|
newline
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|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
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bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
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|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
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|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
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bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
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bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
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bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
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|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
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|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
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|
newline
|
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bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
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|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
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|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "TIMG7"
|
|
base ad:0x4086A000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
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|
newline
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|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
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|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
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|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
group.long 0x1018++0x3
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|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
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|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
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|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
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|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
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|
newline
|
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bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "MIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "MIS_CCU4,Compare up event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "MIS_CCD5,Compare down event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "MIS_CCD4,Compare down event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1124++0x3
|
|
line.long 0x0 "GCTL,Shadow to active load mask"
|
|
bitfld.long 0x0 0. "GCTL_SHDWLDEN,Enables shadow to active load of bufferred registers and register fields." "0: DISABLE,1: ENABLE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
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|
newline
|
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bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
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|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
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|
bitfld.long 0x0 18.--20. "CCCTL_01_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
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|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
newline
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
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|
newline
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bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
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bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
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|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
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|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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newline
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bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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newline
|
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bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
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bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
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|
newline
|
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bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
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|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "TIMG8"
|
|
base ad:0x40090000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
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|
newline
|
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bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
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|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
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|
group.long 0x1000++0x3
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|
line.long 0x0 "CLKDIV,Clock Divider"
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|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
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|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
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|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 28. "IMASK_QEIERR,QEIERR Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "IMASK_DC,Direction Change Event mask" "0: CLR,1: SET"
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|
newline
|
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bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
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|
newline
|
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bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 28. "RIS_QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "RIS_DC,Direction Change" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 28. "MIS_QEIERR,QEIERR" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "MIS_DC,Direction Change" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 28. "ISET_QEIERR,QEIERR event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "ISET_DC,Direction Change event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 28. "ICLR_QEIERR,QEIERR event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "ICLR_DC,Direction Change event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
|
|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
rgroup.long 0x18BC++0x3
|
|
line.long 0x0 "QDIR,Count Direction Register"
|
|
bitfld.long 0x0 0. "QDIR_DIR,Direction of count" "0: DOWN,1: UP"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
tree "TIMG8"
|
|
base ad:0x40090000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
bitfld.long 0x0 0.--1. "FPUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
bitfld.long 0x4 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 28. "IMASK_QEIERR,QEIERR Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "IMASK_DC,Direction Change Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 28. "RIS_QEIERR,QEIERR set on an incorrect state transition on the encoder interface." "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "RIS_DC,Direction Change" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 28. "MIS_QEIERR,QEIERR" "0: CLR,1: SET"
|
|
bitfld.long 0x0 27. "MIS_DC,Direction Change" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 28. "ISET_QEIERR,QEIERR event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 27. "ISET_DC,Direction Change event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 28. "ICLR_QEIERR,QEIERR event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 27. "ICLR_DC,Direction Change event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
|
|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
newline
|
|
bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
|
|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
|
|
bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Force Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
rgroup.long 0x18BC++0x3
|
|
line.long 0x0 "QDIR,Count Direction Register"
|
|
bitfld.long 0x0 0. "QDIR_DIR,Direction of count" "0: DOWN,1: UP"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "TIMG12"
|
|
base ad:0x40870000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
hexmask.long.byte 0x0 0.--3. 1. "FPUB_0_CHANID,0 = disconnected."
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPUB_1_CHANID,0 = disconnected."
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "MIS_CCU5,Compare up event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "MIS_CCU4,Compare up event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "MIS_CCD5,Compare down event generated an interrupt CCP5" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "MIS_CCD4,Compare down event generated an interrupt CCP4" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
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|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
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|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
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|
newline
|
|
bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
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|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
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|
newline
|
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bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
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|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long 0x8 0.--31. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
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|
bitfld.long 0x0 18.--20. "CCCTL_01_CCUPD,Capture and Compare Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
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|
newline
|
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bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Froce Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
newline
|
|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
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|
bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
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|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
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|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
tree "TIMG14"
|
|
base ad:0x40084000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subsciber Port 0"
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x444++0x7
|
|
line.long 0x0 "FPUB_0,Publisher Port 0"
|
|
bitfld.long 0x0 0.--1. "FPUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
line.long 0x4 "FPUB_1,Publisher Port 1"
|
|
bitfld.long 0x4 0.--1. "FPUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 25. "IMASK_TOV,Trigger Overflow Event mask" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "IMASK_CCU3,Capture or Compare UP event mask CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "IMASK_CCU2,Capture or Compare UP event mask CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_CCU1,Capture or Compare UP event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_CCU0,Capture or Compare UP event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "IMASK_CCD3,Capture or Compare DN event mask CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "IMASK_CCD2,Capture or Compare DN event mask CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "IMASK_CCD1,Capture or Compare DN event mask CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "IMASK_CCD0,Capture or Compare DN event mask CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_L,Load Event mask" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_Z,Zero Event mask" "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 25. "RIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RIS_CCU3,Capture or compare up event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "RIS_CCU2,Capture or compare up event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "RIS_CCD3,Capture or compare down event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "RIS_CCD2,Capture or compare down event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "RIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "RIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 25. "MIS_TOV,Trigger overflow" "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "MIS_CCU3,Capture or compare up event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "MIS_CCU2,Capture or compare up event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_CCU1,Capture or compare up event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_CCU0,Capture or compare up event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "MIS_CCD3,Capture or compare down event generated an interrupt CCP3" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "MIS_CCD2,Capture or compare down event generated an interrupt CCP2" "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "MIS_CCD1,Capture or compare down event generated an interrupt CCP1" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "MIS_CCD0,Capture or compare down event generated an interrupt CCP0" "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_L,Load event generated an interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_Z,Zero event generated an interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 25. "ISET_TOV,Trigger Overflow event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 11. "ISET_CCU3,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "ISET_CCU2,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_CCU1,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_CCU0,Capture or compare up event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "ISET_CCD3,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "ISET_CCD2,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "ISET_CCD1,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "ISET_CCD0,Capture or compare down event SET" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_L,Load event SET" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_Z,Zero event SET" "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 25. "ICLR_TOV,Trigger Overflow event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 11. "ICLR_CCU3,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "ICLR_CCU2,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_CCU1,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_CCU0,Capture or compare up event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "ICLR_CCD3,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "ICLR_CCD2,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "ICLR_CCD1,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "ICLR_CCD0,Capture or compare down event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_L,Load event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_Z,Zero event CLEAR" "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_EVT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xF
|
|
line.long 0x0 "CCPD,CCP Direction"
|
|
bitfld.long 0x0 1. "CCPD_C0CCP1,Counter CCP1" "0: INPUT,1: OUTPUT"
|
|
bitfld.long 0x0 0. "CCPD_C0CCP0,Counter CCP0" "0: INPUT,1: OUTPUT"
|
|
line.long 0x4 "ODIS,Output Disable"
|
|
bitfld.long 0x4 1. "ODIS_C0CCP1,Counter CCP1 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
bitfld.long 0x4 0. "ODIS_C0CCP0,Counter CCP0 Disable Mask" "0: CCP_OUTPUT_OCTL,1: CCP_OUTPUT_LOW"
|
|
line.long 0x8 "CCLKCTL,Counter Clock Control Register"
|
|
bitfld.long 0x8 0. "CCLKCTL_CLKEN,Clock Enable" "0: DISABLED,1: ENABLED"
|
|
line.long 0xC "CPS,Clock Prescale Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "CPS_PCNT,Pre-Scale Count"
|
|
rgroup.long 0x1110++0x3
|
|
line.long 0x0 "CPSV,Clock prescale count status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CPSV_CPSVAL,Current Prescale Count Value"
|
|
group.long 0x1114++0x3
|
|
line.long 0x0 "CTTRIGCTL,Timer Cross Trigger Control Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CTTRIGCTL_EVTCTTRIGSEL,Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"
|
|
bitfld.long 0x0 1. "CTTRIGCTL_EVTCTEN,Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path" "0: DISABLED,1: ENABLE"
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|
newline
|
|
bitfld.long 0x0 0. "CTTRIGCTL_CTEN,Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system." "0: DISABLED,1: ENABLE"
|
|
wgroup.long 0x111C++0x3
|
|
line.long 0x0 "CTTRIG,Timer Cross Trigger Register"
|
|
bitfld.long 0x0 0. "CTTRIG_TRIG,Generate Cross Trigger" "0: DISABLED,1: GENERATE"
|
|
group.long 0x1800++0xB
|
|
line.long 0x0 "CTR,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CTR_CCTR,Current Counter value"
|
|
line.long 0x4 "CTRCTL,Counter Control Register"
|
|
bitfld.long 0x4 28.--29. "CTRCTL_CVAE,Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active." "0: LDVAL,1: NOCHANGE,2: ZEROVAL,?"
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|
bitfld.long 0x4 17. "CTRCTL_DRB,Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode." "0: RESUME,1: CVAE_ACTION"
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|
newline
|
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bitfld.long 0x4 13.--15. "CTRCTL_CZC,Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value." "0: CCCTL0_ZCOND,1: CCCTL1_ZCOND,2: CCCTL2_ZCOND,3: CCCTL3_ZCOND,4: QEI_2INP,5: QEI_3INP,?,?"
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|
bitfld.long 0x4 10.--12. "CTRCTL_CAC,Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value." "0: CCCTL0_ACOND,1: CCCTL1_ACOND,2: CCCTL2_ACOND,3: CCCTL3_ACOND,4: QEI_2INP,5: QEI_3INP,?,?"
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newline
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bitfld.long 0x4 7.--9. "CTRCTL_CLC,Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value." "0: CCCTL0_LCOND,1: CCCTL1_LCOND,2: CCCTL2_LCOND,3: CCCTL3_LCOND,4: QEI_2INP,5: QEI_3INP,?,?"
|
|
bitfld.long 0x4 4.--5. "CTRCTL_CM,Count Mode" "0: DOWN,1: UP_DOWN,2: UP,?"
|
|
newline
|
|
bitfld.long 0x4 1.--3. "CTRCTL_REPEAT,Repeat. The repeat bit controls whether the counter continues to advance following a zero event or the exiting of a debug or fault condition. If counting down a zero event is followed by a load at the next advance condition. If counting.." "0: REPEAT_0,1: REPEAT_1,2: REPEAT_2,3: REPEAT_3,4: REPEAT_4,?,?,?"
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|
bitfld.long 0x4 0. "CTRCTL_EN,Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit the counter value is set.." "0: DISABLED,1: ENABLED"
|
|
line.long 0x8 "LOAD,Load Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LOAD_LD,Load Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1810)++0x3
|
|
line.long 0x0 "CC_01[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_01_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1818)++0x3
|
|
line.long 0x0 "CC_23[$1],Capture or Compare Register 0 to Capture or Compare Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC_23_CCVAL,Capture or compare value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1830)++0x3
|
|
line.long 0x0 "CCCTL_01[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_01_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_01_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_01_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
|
|
bitfld.long 0x0 17. "CCCTL_01_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
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|
newline
|
|
bitfld.long 0x0 12.--14. "CCCTL_01_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
bitfld.long 0x0 8.--10. "CCCTL_01_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
newline
|
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bitfld.long 0x0 4.--6. "CCCTL_01_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
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bitfld.long 0x0 0.--2. "CCCTL_01_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1838)++0x3
|
|
line.long 0x0 "CCCTL_23[$1],Capture or Compare Control Registers"
|
|
bitfld.long 0x0 29.--31. "CCCTL_23_CC2SELD,Selects the source second CCD event." "0: SEL_CCD0,1: SEL_CCD1,2: SEL_CCD2,3: SEL_CCD3,4: SEL_CCD4,5: SEL_CCD5,?,?"
|
|
bitfld.long 0x0 26.--28. "CCCTL_23_CCACTUPD,CCACT shadow register Update Method" "0: IMMEDIATELY,1: ZERO_EVT,2: COMPARE_DOWN_EVT,3: COMPARE_UP_EVT,4: ZERO_LOAD_EVT,5: ZERO_RC_ZERO_EVT,6: TRIG,?"
|
|
newline
|
|
bitfld.long 0x0 22.--24. "CCCTL_23_CC2SELU,Selects the source second CCU event." "0: SEL_CCU0,1: SEL_CCU1,2: SEL_CCU2,3: SEL_CCU3,4: SEL_CCU4,5: SEL_CCU5,?,?"
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bitfld.long 0x0 17. "CCCTL_23_COC,Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)." "0: COMPARE,1: CAPTURE"
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newline
|
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bitfld.long 0x0 12.--14. "CCCTL_23_ZCOND,Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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bitfld.long 0x0 8.--10. "CCCTL_23_LCOND,Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved" "?,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
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|
newline
|
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bitfld.long 0x0 4.--6. "CCCTL_23_ACOND,Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved" "0: TIMCLK,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,5: CC_TRIG_HIGH,?,?"
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bitfld.long 0x0 0.--2. "CCCTL_23_CCOND,Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved" "0: NOCAPTURE,1: CC_TRIG_RISE,2: CC_TRIG_FALL,3: CC_TRIG_EDGE,?,?,?,?"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1850)++0x3
|
|
line.long 0x0 "OCTL_01[$1],CCP Output Control Registers"
|
|
bitfld.long 0x0 5. "OCTL_01_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
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bitfld.long 0x0 4. "OCTL_01_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "OCTL_01_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1858)++0x3
|
|
line.long 0x0 "OCTL_23[$1],CCP Output Control Registers"
|
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bitfld.long 0x0 5. "OCTL_23_CCPIV,CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)." "0: LOW,1: HIGH"
|
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bitfld.long 0x0 4. "OCTL_23_CCPOINV,CCP Output Invert The output as selected by CCPO is conditionally inverted." "0: NOINV,1: INV"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "OCTL_23_CCPO,CCP Output Source"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1870)++0x3
|
|
line.long 0x0 "CCACT_01[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_01_SWFRCACT,CCP Output Action on Software Force Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 15.--16. "CCACT_01_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_01_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 9.--10. "CCACT_01_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CCACT_01_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 3.--4. "CCACT_01_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CCACT_01_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1878)++0x3
|
|
line.long 0x0 "CCACT_23[$1],Capture or Compare Action Registers"
|
|
bitfld.long 0x0 28.--29. "CCACT_23_SWFRCACT,CCP Output Action on Software Force Output" "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,?"
|
|
bitfld.long 0x0 15.--16. "CCACT_23_CC2UACT,CCP Output Action on CC2U event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "CCACT_23_CC2DACT,CCP Output Action on CC2D event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 9.--10. "CCACT_23_CUACT,CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CCACT_23_CDACT,CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
bitfld.long 0x0 3.--4. "CCACT_23_LACT,CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CCACT_23_ZACT,CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event." "0: DISABLED,1: CCP_HIGH,2: CCP_LOW,3: CCP_TOGGLE"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1880)++0x3
|
|
line.long 0x0 "IFCTL_01[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_01_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_01_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_01_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_01_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_01_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1888)++0x3
|
|
line.long 0x0 "IFCTL_23[$1],Input Filter Control Register"
|
|
bitfld.long 0x0 12. "IFCTL_23_FE,Filter Enable" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 11. "IFCTL_23_CPV,Consecutive Period/Voting Select" "0: CONSECUTIVE,1: VOTING"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IFCTL_23_FP,Filter Period. This field specifies the sample period for the" "0: _3,1: _5,2: _8,?"
|
|
bitfld.long 0x0 7. "IFCTL_23_INV,Input Inversion This bit controls whether the selected input is inverted." "0: NOINVERT,1: INVERT"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "IFCTL_23_ISEL,Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"
|
|
repeat.end
|
|
group.long 0x18B0++0x3
|
|
line.long 0x0 "TSEL,Trigger Select"
|
|
bitfld.long 0x0 9. "TSEL_TE,Trigger Enable." "0: Triggers are not used,1: Triggers are used as selected by the ETSEL field"
|
|
hexmask.long.byte 0x0 0.--4. 1. "TSEL_ETSEL,External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*")||cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x40444000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,Interrupt index status"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 3. "IMASK_IRQ_CAPTURED_RDY,Mask for IRQ_CAPTURED_RDY. Indicates to the CPU that the Captured Word is ready to be read." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 2. "IMASK_IRQ_CMD_DONE,Mask for IRQ_CMD_DONE. Indicates that a command has finished" "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0x0 1. "IMASK_IRQ_CMD_FAIL,Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected." "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0x0 0. "IMASK_IRQ_HEALTH_FAIL,Mask for IRQ_HEALTH_FAIL. Indicates that a health test has failed." "0: DISABLED,1: ENABLED"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 3. "RIS_IRQ_CAPTURED_RDY,Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX will clear this interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "RIS_IRQ_CMD_DONE,Raw interrupt source for IRQ_CMD_DONE. Indicates that the issued command/mode has completed." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_IRQ_CMD_FAIL,Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "RIS_IRQ_HEALTH_FAIL,Indicates to the CPU that any of the health tests have failed. Reading the IIDX will clear this interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 3. "MIS_IRQ_CAPTURED_RDY,Masked interrupt result for CAPTURED_READY. Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX will clear this interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "MIS_IRQ_CMD_DONE,Masked interrupt source for IRQ_CMD_DONE. Indicates that the issued command/mode has completed." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_IRQ_CMD_FAIL,Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "MIS_IRQ_HEALTH_FAIL,Masked interrupt result for HEALTH_FAIL. Indicates to the CPU that any of the health tests have failed for the latest 1024-bit window." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 3. "ISET_IRQ_CAPTURED_RDY,Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "ISET_IRQ_CMD_DONE,Write to turn on CMD_DONE IRQ. Indicates that the last issued TRNG command has finished." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_IRQ_CMD_FAIL,Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "ISET_IRQ_HEALTH_FAIL,Indicates to the CPU that any of the health tests have failed. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 3. "ICLR_IRQ_CAPTURED_RDY,Indicates to the CPU that the Captured Word is ready to be read. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "ICLR_IRQ_CMD_DONE,Write to turn off CMD_DONE IRQ. Indicates that the last issued TRNG command has finished." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_IRQ_CMD_FAIL,Masked interrupt source for IRQ_CMD_FAIL. Indicates that the just issued command/mode has been rejected." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "ICLR_IRQ_HEALTH_FAIL,Indicates to the CPU that any of the health tests have failed. Reading the IIDX or DATA_CAPTURE registers will clear this interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module descriptions"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module Identifier - An internal TI page has been created to request unique module IDs"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0x3
|
|
line.long 0x0 "CTL,Controls the command and decimation rate"
|
|
bitfld.long 0x0 19.--20. "CTL_PWRUP_PSTART_CFG,Configure pusle startup sequence length" "0: Disabled,1: rise at 10us,2: rise at 10us,3: rise at 10us"
|
|
bitfld.long 0x0 17.--18. "CTL_PWRUP_PCHRG_CFG,Configure PCHARGE sequence length" "0: Disabled,1: 20 us PCHARGE,2: 30 us PCHARGE,3: 40 us PCHARGE"
|
|
bitfld.long 0x0 16. "CTL_PWRUP_CLKDIV,When '1' the powerup sequence will take twice as long (i.e. clock frequency halved)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "CTL_DECIM_RATE,Set decimation rate. Decimate by n" "0: Decimation by 1,1: Decimation by 2,?,?,?,?,?,7: Decimation by 8"
|
|
bitfld.long 0x0 0.--1. "CTL_CMD,Sets the TRNG mode through a command. The mode will not be updated until the previous command is done as indicated by IRQ_CMD_DONE." "0: PWR_OFF,1: PWRUP_DIG,2: PWRUP_ANA,3: NORM_FUNC"
|
|
rgroup.long 0x1104++0xB
|
|
line.long 0x0 "STAT,Status register that informs health test results and last issued command"
|
|
hexmask.long.byte 0x0 16.--19. 1. "STAT_FSM_STATE,Current state of the front end FSM (behind a clock domain crossing)."
|
|
rbitfld.long 0x0 8.--9. "STAT_ISSUED_CMD,Indicates the last accepted command that is issued to the TRNG interface." "0,1,2,3"
|
|
rbitfld.long 0x0 1. "STAT_REP_FAIL,Indicates that the repetition counter test caused the most recent failure. Thus the health count numbers are most likely not for a complete 1024-bit window." "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "STAT_ADAP_FAIL,Indicates that the Adaptive Proportion Test (1 2 3 or 4-bit counters) failed by having too many or too few counted samples in the last 1024 bit window." "0,1"
|
|
line.long 0x4 "DATA_CAPTURE,Captured word buffer of RNG data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA_CAPTURE_BUFFER,Captured Data from the Decimation Block"
|
|
line.long 0x8 "TEST_RESULTS,Test results from TEST_ANA and TEST_DIG"
|
|
bitfld.long 0x8 8. "TEST_RESULTS_ANA_TEST,Runs through 4096 samples from an enabled entropy source and verifies that none of the health tests failed indicating sufficient entropy was produced by the analog components" "0,1"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TEST_RESULTS_DIG_TEST,Bit 0 indicates if the first decimation rate test and health test(verifies conditioning decimation and captured buffer) fails and Bit 1 indicates if the second decimation test and health test fails"
|
|
group.long 0x1110++0x3
|
|
line.long 0x0 "CLKDIVIDE,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIVIDE_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,?,3: DIV_BY_4,?,5: DIV_BY_6,?,7: DIV_BY_8"
|
|
tree.end
|
|
endif
|
|
tree "UART (Universal Asynchronouns Receiver Transmitter)"
|
|
base ad:0x0
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
tree "UART0"
|
|
base ad:0x40108000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 17. "IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "IMASK_CTS,Enable UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "IMASK_LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "IMASK_LINC1,Enable LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "IMASK_LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 17. "RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "RIS_DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "RIS_DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "RIS_CTS,UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RIS_LINOVF,LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RIS_LINC1,LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "RIS_LINC0,LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 17. "MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 15. "MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "MIS_CTS,Masked UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 13. "MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "MIS_LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "MIS_LINC1,Masked LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 7. "MIS_LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 17. "ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 15. "ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "ISET_CTS,Set UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 13. "ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 9. "ISET_LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "ISET_LINC1,Set LIN Capture 1 Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 7. "ISET_LINC0,Set LIN Capture 0 / Match Interrupt ." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 17. "ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 16. "ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 15. "ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 14. "ICLR_CTS,Clear UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 13. "ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 9. "ICLR_LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "ICLR_LINC1,Clear LIN Capture 1 Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 7. "ICLR_LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0x7
|
|
line.long 0x0 "CTL0,UART Control Register 0"
|
|
bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 18. "CTL0_MAJVOTE,Majority Vote Enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
|
|
bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
|
|
bitfld.long 0x0 7. "CTL0_MENC,Manchester Encode enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "LCRH,UART Line Control Register"
|
|
hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
|
|
hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
|
|
bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
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|
bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
|
|
bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "STAT,UART Status Register"
|
|
bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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|
newline
|
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bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
|
|
group.long 0x110C++0xF
|
|
line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
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|
bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_FULL,5: LVL_FULL,?,7: LVL_1"
|
|
bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,?,5: LVL_EMPTY,?,7: LVL_1"
|
|
line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
|
|
line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
|
|
hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
|
|
line.long 0xC "GFCTL,Glitch Filter Control"
|
|
bitfld.long 0xC 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "GFCTL_DGFSEL,Glitch Suppression Pulse Width"
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "TXDATA,UART Transmit Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
|
|
rgroup.long 0x1124++0x3
|
|
line.long 0x0 "RXDATA,UART Receive Data Register"
|
|
bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
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|
bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
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|
bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Received Data. When read this field contains the data that was received by the UART."
|
|
group.long 0x1130++0x13
|
|
line.long 0x0 "LINCNT,UART LIN Mode Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCNT_VALUE,16 bit up counter clocked by the functional clock of the UART."
|
|
line.long 0x4 "LINCTL,UART LIN Mode Control Register"
|
|
bitfld.long 0x4 6. "LINCTL_LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "LINCTL_LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x4 4. "LINCTL_LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "LINCTL_CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 1. "LINCTL_ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "LINCTL_CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "LINC0,UART LIN Mode Capture 0 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LINC0_DATA,16 Bit Capture / Compare Register"
|
|
line.long 0xC "LINC1,UART LIN Mode Capture 1 Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "LINC1_DATA,16 Bit Capture / Compare Register"
|
|
line.long 0x10 "IRCTL,eUSCI_Ax IrDA Control Word Register"
|
|
bitfld.long 0x10 9. "IRCTL_IRRXPL,IrDA receive input UCAxRXD polarity" "0: HIGHPULSE,1: LOWPULSE"
|
|
hexmask.long.byte 0x10 2.--7. 1. "IRCTL_IRTXPL,Transmit pulse length."
|
|
bitfld.long 0x10 1. "IRCTL_IRTXCLK,IrDA transmit pulse clock select" "0: BITCLK,1: BRCLK"
|
|
newline
|
|
bitfld.long 0x10 0. "IRCTL_IREN,IrDA encoder/decoder enable" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1148++0x7
|
|
line.long 0x0 "AMASK,Self Address Mask Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register.."
|
|
line.long 0x4 "ADDR,Self Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh."
|
|
group.long 0x1160++0x3
|
|
line.long 0x0 "CLKDIV2,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV2_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "UART0"
|
|
base ad:0x40108000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_LINC1,Enable LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_LINOVF,LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_LINC1,LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_LINC0,LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
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bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1038++0x3
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line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
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bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
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bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
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bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
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bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
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bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 9. "INT_EVENT0_MIS_LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 8. "INT_EVENT0_MIS_LINC1,Masked LIN Capture 1 Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 7. "INT_EVENT0_MIS_LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
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bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
|
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bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
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wgroup.long 0x1040++0x3
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line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
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|
bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
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bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
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bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "INT_EVENT0_ISET_LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "INT_EVENT0_ISET_LINC1,Set LIN Capture 1 Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "INT_EVENT0_ISET_LINC0,Set LIN Capture 0 / Match Interrupt ." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
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wgroup.long 0x1048++0x3
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line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
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bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "INT_EVENT0_ICLR_LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: NO_EFFECT,1: CLR"
|
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bitfld.long 0x0 8. "INT_EVENT0_ICLR_LINC1,Clear LIN Capture 1 Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "INT_EVENT0_ICLR_LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: NO_EFFECT,1: CLR"
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|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1050++0x3
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line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
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group.long 0x1058++0x3
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line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
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bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1060++0x3
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line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
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bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1068++0x3
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line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
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bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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wgroup.long 0x1070++0x3
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line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
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bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
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wgroup.long 0x1078++0x3
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line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
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bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1080++0x3
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line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
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group.long 0x1088++0x3
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line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
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bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1090++0x3
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line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
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bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1098++0x3
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line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
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bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
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wgroup.long 0x10A0++0x3
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line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
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bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
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wgroup.long 0x10A8++0x3
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line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
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bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x10E0++0x3
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line.long 0x0 "EVT_MODE,Event Mode"
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bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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wgroup.long 0x10E4++0x3
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line.long 0x0 "INTCTL,Interrupt control register"
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bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
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group.long 0x1100++0x7
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line.long 0x0 "CTL0,UART Control Register 0"
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bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 18. "CTL0_MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not.." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
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bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
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bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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bitfld.long 0x0 7. "CTL0_MENC,Manchester Encode enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
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bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
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line.long 0x4 "LCRH,UART Line Control Register"
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hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
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hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
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bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
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bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
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bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
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rgroup.long 0x1108++0x3
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line.long 0x0 "STAT,UART Status Register"
|
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bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: CLEARED,1: SET"
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bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
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|
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bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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|
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bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
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group.long 0x110C++0xF
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line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
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hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
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bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?"
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bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7"
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line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
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hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
|
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line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
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hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
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line.long 0xC "GFCTL,Glitch Filter Control"
|
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bitfld.long 0xC 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
newline
|
|
bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0xC 0.--5. 1. "GFCTL_DGFSEL,Glitch Suppression Pulse Width"
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "TXDATA,UART Transmit Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
|
|
rgroup.long 0x1124++0x3
|
|
line.long 0x0 "RXDATA,UART Receive Data Register"
|
|
bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Received Data. When read this field contains the data that was received by the UART."
|
|
group.long 0x1130++0x13
|
|
line.long 0x0 "LINCNT,UART LIN Mode Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCNT_VALUE,16 bit up counter clocked by the functional clock of the UART."
|
|
line.long 0x4 "LINCTL,UART LIN Mode Control Register"
|
|
bitfld.long 0x4 6. "LINCTL_LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 5. "LINCTL_LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4. "LINCTL_LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "LINCTL_CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "LINCTL_ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "LINCTL_CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "LINC0,UART LIN Mode Capture 0 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LINC0_DATA,16 Bit Capture / Compare Register"
|
|
line.long 0xC "LINC1,UART LIN Mode Capture 1 Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "LINC1_DATA,16 Bit Capture / Compare Register"
|
|
line.long 0x10 "IRCTL,eUSCI_Ax IrDA Control Word Register"
|
|
bitfld.long 0x10 9. "IRCTL_IRRXPL,IrDA receive input UCAxRXD polarity" "0: HIGHPULSE,1: LOWPULSE"
|
|
hexmask.long.byte 0x10 2.--7. 1. "IRCTL_IRTXPL,Transmit pulse length."
|
|
newline
|
|
bitfld.long 0x10 1. "IRCTL_IRTXCLK,IrDA transmit pulse clock select" "0: BITCLK,1: BRCLK"
|
|
bitfld.long 0x10 0. "IRCTL_IREN,IrDA encoder/decoder enable" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1148++0x7
|
|
line.long 0x0 "AMASK,Self Address Mask Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register.."
|
|
line.long 0x4 "ADDR,Self Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh."
|
|
group.long 0x1160++0x3
|
|
line.long 0x0 "CLKDIV2,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV2_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "UART0"
|
|
base ad:0x40108000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
newline
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
newline
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
newline
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
newline
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_IMASK_LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_LINC1,Enable LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_IMASK_LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_RIS_LINOVF,LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_LINC1,LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_RIS_LINC0,LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_LINC1,Masked LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_LINC1,Set LIN Capture 1 Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ISET_LINC0,Set LIN Capture 0 / Match Interrupt ." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: CLR"
|
|
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|
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bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_LINC1,Clear LIN Capture 1 Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ICLR_LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
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|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
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|
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bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
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|
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bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
newline
|
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hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0x7
|
|
line.long 0x0 "CTL0,UART Control Register 0"
|
|
bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
|
|
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|
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bitfld.long 0x0 18. "CTL0_MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not.." "0: DISABLE,1: ENABLE"
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|
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|
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bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
|
|
newline
|
|
bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
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|
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|
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bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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|
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bitfld.long 0x0 7. "CTL0_MENC,Manchester Encode enable" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
|
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bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: UARTxTXD pin can be controlled by TXD_OUT"
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bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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|
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bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "LCRH,UART Line Control Register"
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hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
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|
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hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
|
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|
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bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
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newline
|
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bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
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|
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bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
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|
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bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
|
|
newline
|
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bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "STAT,UART Status Register"
|
|
bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
|
|
group.long 0x110C++0xF
|
|
line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
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|
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|
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bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?"
|
|
newline
|
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bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
|
|
line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
|
|
hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
|
|
line.long 0xC "GFCTL,Glitch Filter Control"
|
|
bitfld.long 0xC 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLED,1: ENABLED"
|
|
newline
|
|
bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
newline
|
|
bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "GFCTL_DGFSEL,Glitch Suppression Pulse Width"
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "TXDATA,UART Transmit Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
|
|
rgroup.long 0x1124++0x3
|
|
line.long 0x0 "RXDATA,UART Receive Data Register"
|
|
bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
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|
newline
|
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bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
|
|
group.long 0x1130++0x13
|
|
line.long 0x0 "LINCNT,UART LIN Mode Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCNT_VALUE,16 bit up counter clocked by the module clock of the UART."
|
|
line.long 0x4 "LINCTL,UART LIN Mode Control Register"
|
|
bitfld.long 0x4 6. "LINCTL_LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 5. "LINCTL_LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4. "LINCTL_LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 2. "LINCTL_CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "LINCTL_ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "LINCTL_CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "LINC0,UART LIN Mode Capture 0 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LINC0_DATA,16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge when enabled. It can generate a DATA interrupt on capture. If compare mode is enabled (DATA_MATCH = 1) a counter match can generate a LINC0 interrupt."
|
|
line.long 0xC "LINC1,UART LIN Mode Capture 1 Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "LINC1_DATA,16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge when enabled. It can generate a LINC1 interrupt on capture."
|
|
line.long 0x10 "IRCTL,eUSCI_Ax IrDA Control Word Register"
|
|
bitfld.long 0x10 9. "IRCTL_IRRXPL,IrDA receive input UCAxRXD polarity" "0: HIGHPULSE,1: LOWPULSE"
|
|
newline
|
|
hexmask.long.byte 0x10 2.--7. 1. "IRCTL_IRTXPL,Transmit pulse length."
|
|
newline
|
|
bitfld.long 0x10 1. "IRCTL_IRTXCLK,IrDA transmit pulse clock select" "0: BITCLK,1: BRCLK"
|
|
newline
|
|
bitfld.long 0x10 0. "IRCTL_IREN,IrDA encoder/decoder enable" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1148++0x7
|
|
line.long 0x0 "AMASK,Self Address Mask Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UART9BITADDR.."
|
|
line.long 0x4 "ADDR,Self Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh."
|
|
group.long 0x1160++0x3
|
|
line.long 0x0 "CLKDIV2,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV2_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "UART0"
|
|
base ad:0x40108000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
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line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
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bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
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bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
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line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
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bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
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rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
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group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
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bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
newline
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bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
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rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
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bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 9. "INT_EVENT0_IMASK_LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_IMASK_LINC1,Enable LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 7. "INT_EVENT0_IMASK_LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
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bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 9. "INT_EVENT0_RIS_LINOVF,LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_LINC1,LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 7. "INT_EVENT0_RIS_LINC0,LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_LINC1,Masked LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_ISET_LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ISET_LINC1,Set LIN Capture 1 Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ISET_LINC0,Set LIN Capture 0 / Match Interrupt ." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_ICLR_LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 8. "INT_EVENT0_ICLR_LINC1,Clear LIN Capture 1 Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_ICLR_LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
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bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0x7
|
|
line.long 0x0 "CTL0,UART Control Register 0"
|
|
bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 18. "CTL0_MAJVOTE,Majority Vote Enable" "0: DISABLE,1: ENABLE"
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|
newline
|
|
bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
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|
newline
|
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bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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newline
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bitfld.long 0x0 7. "CTL0_MENC,Manchester Encode enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
|
|
newline
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bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "LCRH,UART Line Control Register"
|
|
hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
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hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
|
|
newline
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bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
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|
bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
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|
newline
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bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
|
|
bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "STAT,UART Status Register"
|
|
bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
|
|
group.long 0x110C++0xF
|
|
line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
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|
bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_FULL,5: LVL_FULL,?,7: LVL_1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,?,5: LVL_EMPTY,?,7: LVL_1"
|
|
line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
|
|
line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
|
|
hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
|
|
line.long 0xC "GFCTL,Glitch Filter Control"
|
|
bitfld.long 0xC 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLED,1: ENABLED"
|
|
bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
newline
|
|
bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
hexmask.long.byte 0xC 0.--5. 1. "GFCTL_DGFSEL,Glitch Suppression Pulse Width"
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "TXDATA,UART Transmit Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
|
|
rgroup.long 0x1124++0x3
|
|
line.long 0x0 "RXDATA,UART Receive Data Register"
|
|
bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
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|
newline
|
|
bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
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|
newline
|
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bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Received Data. When read this field contains the data that was received by the UART."
|
|
group.long 0x1130++0x13
|
|
line.long 0x0 "LINCNT,UART LIN Mode Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCNT_VALUE,16 bit up counter clocked by the functional clock of the UART."
|
|
line.long 0x4 "LINCTL,UART LIN Mode Control Register"
|
|
bitfld.long 0x4 6. "LINCTL_LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 5. "LINCTL_LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: DISABLE,1: ENABLE"
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|
newline
|
|
bitfld.long 0x4 4. "LINCTL_LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 2. "LINCTL_CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 1. "LINCTL_ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 0. "LINCTL_CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: DISABLE,1: ENABLE"
|
|
line.long 0x8 "LINC0,UART LIN Mode Capture 0 Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "LINC0_DATA,16 Bit Capture / Compare Register"
|
|
line.long 0xC "LINC1,UART LIN Mode Capture 1 Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "LINC1_DATA,16 Bit Capture / Compare Register"
|
|
line.long 0x10 "IRCTL,eUSCI_Ax IrDA Control Word Register"
|
|
bitfld.long 0x10 9. "IRCTL_IRRXPL,IrDA receive input UCAxRXD polarity" "0: HIGHPULSE,1: LOWPULSE"
|
|
hexmask.long.byte 0x10 2.--7. 1. "IRCTL_IRTXPL,Transmit pulse length."
|
|
newline
|
|
bitfld.long 0x10 1. "IRCTL_IRTXCLK,IrDA transmit pulse clock select" "0: BITCLK,1: BRCLK"
|
|
bitfld.long 0x10 0. "IRCTL_IREN,IrDA encoder/decoder enable" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1148++0x7
|
|
line.long 0x0 "AMASK,Self Address Mask Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register.."
|
|
line.long 0x4 "ADDR,Self Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh."
|
|
group.long 0x1160++0x3
|
|
line.long 0x0 "CLKDIV2,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV2_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "UART1"
|
|
base ad:0x40100000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
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|
newline
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bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
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newline
|
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bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
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|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
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|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
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|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
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line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1098++0x3
|
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line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
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bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
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line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
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line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
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newline
|
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bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0x7
|
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line.long 0x0 "CTL0,UART Control Register 0"
|
|
bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 18. "CTL0_MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not.." "0: DISABLE,1: ENABLE"
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newline
|
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bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
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newline
|
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bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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newline
|
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bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
|
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bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: ENABLE"
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|
newline
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bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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newline
|
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bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "LCRH,UART Line Control Register"
|
|
hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
|
|
hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
|
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newline
|
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bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
|
|
bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
|
|
bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "STAT,UART Status Register"
|
|
bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
|
|
group.long 0x110C++0xF
|
|
line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
|
|
bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?"
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|
newline
|
|
bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
|
|
line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
|
|
hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
|
|
line.long 0xC "GFCTL,Glitch Filter Control"
|
|
bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "TXDATA,UART Transmit Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
|
|
rgroup.long 0x1124++0x3
|
|
line.long 0x0 "RXDATA,UART Receive Data Register"
|
|
bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Received Data. When read this field contains the data that was received by the UART."
|
|
group.long 0x1148++0x7
|
|
line.long 0x0 "AMASK,Self Address Mask Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register.."
|
|
line.long 0x4 "ADDR,Self Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L110*")||cpuis("MSPM0L130*")||cpuis("MSPM0L134*"))
|
|
tree "UART1"
|
|
base ad:0x40100000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
newline
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
newline
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
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newline
|
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bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
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group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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|
newline
|
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bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
newline
|
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bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
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|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: SET"
|
|
newline
|
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bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: SET"
|
|
newline
|
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bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: SET"
|
|
newline
|
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bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled" "0: Interrupt disabled,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_EVT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_EVT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0x7
|
|
line.long 0x0 "CTL0,UART Control Register 0"
|
|
bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 18. "CTL0_MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not.." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
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bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
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bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
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bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: UARTxTXD pin can be controlled by TXD_OUT"
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bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
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line.long 0x4 "LCRH,UART Line Control Register"
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hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
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hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
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bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
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bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
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bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
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rgroup.long 0x1108++0x3
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line.long 0x0 "STAT,UART Status Register"
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bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: CLEARED,1: SET"
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bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
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bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
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group.long 0x110C++0xF
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line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
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hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
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bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?"
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bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7"
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line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
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hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
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line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
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hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
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line.long 0xC "GFCTL,Glitch Filter Control"
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|
bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
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bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
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group.long 0x1120++0x3
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line.long 0x0 "TXDATA,UART Transmit Data Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
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rgroup.long 0x1124++0x3
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line.long 0x0 "RXDATA,UART Receive Data Register"
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bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
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bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
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bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
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bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
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bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
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group.long 0x1148++0x7
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line.long 0x0 "AMASK,Self Address Mask Register"
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hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UART9BITADDR.."
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line.long 0x4 "ADDR,Self Address Register"
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hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh."
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tree.end
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endif
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|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
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tree "UART1"
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base ad:0x4010A000
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group.long 0x800++0x3
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line.long 0x0 "PWREN,Power enable"
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hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
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bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
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wgroup.long 0x804++0x3
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line.long 0x0 "RSTCTL,Reset Control"
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hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
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bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
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newline
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bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
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group.long 0x808++0x3
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line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
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hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
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bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
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rgroup.long 0x814++0x3
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line.long 0x0 "GPRCM_STAT,Status Register"
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bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
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group.long 0x1000++0x3
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line.long 0x0 "CLKDIV,Clock Divider"
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bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
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group.long 0x1008++0x3
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line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
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bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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newline
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bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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group.long 0x1018++0x3
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line.long 0x0 "PDBGCTL,Peripheral Debug Control"
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bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
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bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
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rgroup.long 0x1020++0x3
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line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved"
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group.long 0x1028++0x3
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line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
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bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
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bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
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bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
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bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 9. "INT_EVENT0_IMASK_LINOVF,Enable LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 8. "INT_EVENT0_IMASK_LINC1,Enable LIN Capture 1 Interrupt." "0: CLR,1: SET"
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|
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|
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bitfld.long 0x0 7. "INT_EVENT0_IMASK_LINC0,Enable LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
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bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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|
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bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
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bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
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rgroup.long 0x1030++0x3
|
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line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
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bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
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bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
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newline
|
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bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
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bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
|
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bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
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bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 9. "INT_EVENT0_RIS_LINOVF,LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_RIS_LINC1,LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 7. "INT_EVENT0_RIS_LINC0,LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 9. "INT_EVENT0_MIS_LINOVF,Masked LIN Hardware Counter Overflow Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 8. "INT_EVENT0_MIS_LINC1,Masked LIN Capture 1 Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "INT_EVENT0_MIS_LINC0,Masked LIN Capture 0 / Match Interrupt ." "0: CLR,1: SET"
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
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bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 9. "INT_EVENT0_ISET_LINOVF,Set LIN Hardware Counter Overflow Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 8. "INT_EVENT0_ISET_LINC1,Set LIN Capture 1 Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 7. "INT_EVENT0_ISET_LINC0,Set LIN Capture 0 / Match Interrupt ." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
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|
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bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
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wgroup.long 0x1048++0x3
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line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
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bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 9. "INT_EVENT0_ICLR_LINOVF,Clear LIN Hardware Counter Overflow Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 8. "INT_EVENT0_ICLR_LINC1,Clear LIN Capture 1 Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 7. "INT_EVENT0_ICLR_LINC0,Clear LIN Capture 0 / Match Interrupt ." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1050++0x3
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line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
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group.long 0x1058++0x3
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line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
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bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1060++0x3
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line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
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bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1068++0x3
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line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
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bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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wgroup.long 0x1070++0x3
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line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
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bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
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wgroup.long 0x1078++0x3
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line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
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bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1080++0x3
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line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
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group.long 0x1088++0x3
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line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
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bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1090++0x3
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line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
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bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1098++0x3
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line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
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bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
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wgroup.long 0x10A0++0x3
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line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
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bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
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wgroup.long 0x10A8++0x3
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line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
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bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x10E0++0x3
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line.long 0x0 "EVT_MODE,Event Mode"
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bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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wgroup.long 0x10E4++0x3
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line.long 0x0 "INTCTL,Interrupt control register"
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bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
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group.long 0x1100++0x7
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line.long 0x0 "CTL0,UART Control Register 0"
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bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 18. "CTL0_MAJVOTE,Majority Vote Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
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bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
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bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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bitfld.long 0x0 7. "CTL0_MENC,Manchester Encode enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
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bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
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line.long 0x4 "LCRH,UART Line Control Register"
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hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
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hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
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bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
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bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
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bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
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rgroup.long 0x1108++0x3
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line.long 0x0 "STAT,UART Status Register"
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bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: CLEARED,1: SET"
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bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
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bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
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group.long 0x110C++0xF
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line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
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hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
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bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_FULL,5: LVL_FULL,?,7: LVL_1"
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bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,?,5: LVL_EMPTY,?,7: LVL_1"
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line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
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hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
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line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
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hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
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line.long 0xC "GFCTL,Glitch Filter Control"
|
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bitfld.long 0xC 11. "GFCTL_CHAIN,Analog and digital noise filters chaining enable." "0: DISABLED,1: ENABLED"
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bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
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bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
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hexmask.long.byte 0xC 0.--5. 1. "GFCTL_DGFSEL,Glitch Suppression Pulse Width"
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group.long 0x1120++0x3
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line.long 0x0 "TXDATA,UART Transmit Data Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
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rgroup.long 0x1124++0x3
|
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line.long 0x0 "RXDATA,UART Receive Data Register"
|
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bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
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bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
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bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
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bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
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bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Received Data. When read this field contains the data that was received by the UART."
|
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group.long 0x1130++0x13
|
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line.long 0x0 "LINCNT,UART LIN Mode Counter Register"
|
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hexmask.long.word 0x0 0.--15. 1. "LINCNT_VALUE,16 bit up counter clocked by the functional clock of the UART."
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line.long 0x4 "LINCTL,UART LIN Mode Control Register"
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bitfld.long 0x4 6. "LINCTL_LINC0_MATCH,Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 5. "LINCTL_LINC1CAP,Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 4. "LINCTL_LINC0CAP,Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 2. "LINCTL_CNTRXLOW,Count while low Signal on RXD When counter is enabled and the signal on RXD is low the counter increments." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 1. "LINCTL_ZERONE,Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 0. "LINCTL_CTRENA,LIN Counter Enable. LIN counter will only count when enabled." "0: DISABLE,1: ENABLE"
|
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line.long 0x8 "LINC0,UART LIN Mode Capture 0 Register"
|
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hexmask.long.word 0x8 0.--15. 1. "LINC0_DATA,16 Bit Capture / Compare Register"
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line.long 0xC "LINC1,UART LIN Mode Capture 1 Register"
|
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hexmask.long.word 0xC 0.--15. 1. "LINC1_DATA,16 Bit Capture / Compare Register"
|
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line.long 0x10 "IRCTL,eUSCI_Ax IrDA Control Word Register"
|
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bitfld.long 0x10 9. "IRCTL_IRRXPL,IrDA receive input UCAxRXD polarity" "0: HIGHPULSE,1: LOWPULSE"
|
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hexmask.long.byte 0x10 2.--7. 1. "IRCTL_IRTXPL,Transmit pulse length."
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|
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bitfld.long 0x10 1. "IRCTL_IRTXCLK,IrDA transmit pulse clock select" "0: BITCLK,1: BRCLK"
|
|
bitfld.long 0x10 0. "IRCTL_IREN,IrDA encoder/decoder enable" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1148++0x7
|
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line.long 0x0 "AMASK,Self Address Mask Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register.."
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line.long 0x4 "ADDR,Self Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh."
|
|
group.long 0x1160++0x3
|
|
line.long 0x0 "CLKDIV2,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV2_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "UART2"
|
|
base ad:0x40102000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0x7
|
|
line.long 0x0 "CTL0,UART Control Register 0"
|
|
bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 18. "CTL0_MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not.." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
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bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
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bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
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bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
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line.long 0x4 "LCRH,UART Line Control Register"
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hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
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hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
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bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
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bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
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bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
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rgroup.long 0x1108++0x3
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line.long 0x0 "STAT,UART Status Register"
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bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: CLEARED,1: SET"
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bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
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bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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newline
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bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
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group.long 0x110C++0xF
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line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
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hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
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bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?"
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bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7"
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line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
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hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
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line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
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hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
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line.long 0xC "GFCTL,Glitch Filter Control"
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bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
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bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
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group.long 0x1120++0x3
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line.long 0x0 "TXDATA,UART Transmit Data Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
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rgroup.long 0x1124++0x3
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line.long 0x0 "RXDATA,UART Receive Data Register"
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bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
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bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
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bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
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bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
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bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Received Data. When read this field contains the data that was received by the UART."
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group.long 0x1148++0x7
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line.long 0x0 "AMASK,Self Address Mask Register"
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hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register.."
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line.long 0x4 "ADDR,Self Address Register"
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hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh."
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tree.end
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endif
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sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
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tree "UART2"
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base ad:0x40100000
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group.long 0x800++0x3
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line.long 0x0 "PWREN,Power enable"
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hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
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bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
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wgroup.long 0x804++0x3
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line.long 0x0 "RSTCTL,Reset Control"
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hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
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bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
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newline
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bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
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group.long 0x808++0x3
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line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
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hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
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bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
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rgroup.long 0x814++0x3
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line.long 0x0 "GPRCM_STAT,Status Register"
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bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
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group.long 0x1000++0x3
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line.long 0x0 "CLKDIV,Clock Divider"
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bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
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group.long 0x1008++0x3
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line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
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bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
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group.long 0x1018++0x3
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line.long 0x0 "PDBGCTL,Peripheral Debug Control"
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bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
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bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
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rgroup.long 0x1020++0x3
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line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved"
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group.long 0x1028++0x3
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line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
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bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
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bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
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bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1030++0x3
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line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
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bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
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bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
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bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1038++0x3
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line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
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bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
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bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
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bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
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bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
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|
bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
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|
newline
|
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bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
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line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
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|
newline
|
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bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
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bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: SET"
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|
newline
|
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bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
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newline
|
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bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
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|
newline
|
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bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
|
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newline
|
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bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0x7
|
|
line.long 0x0 "CTL0,UART Control Register 0"
|
|
bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 18. "CTL0_MAJVOTE,Majority Vote Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
|
|
newline
|
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bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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newline
|
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bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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|
bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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|
newline
|
|
bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "LCRH,UART Line Control Register"
|
|
hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
|
|
hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
|
|
newline
|
|
bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
|
|
bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
|
|
bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "STAT,UART Status Register"
|
|
bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
|
|
group.long 0x110C++0xF
|
|
line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
|
|
bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_FULL,5: LVL_FULL,?,7: LVL_1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,?,5: LVL_EMPTY,?,7: LVL_1"
|
|
line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
|
|
line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
|
|
hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
|
|
line.long 0xC "GFCTL,Glitch Filter Control"
|
|
bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "TXDATA,UART Transmit Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
|
|
rgroup.long 0x1124++0x3
|
|
line.long 0x0 "RXDATA,UART Receive Data Register"
|
|
bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Received Data. When read this field contains the data that was received by the UART."
|
|
group.long 0x1148++0x7
|
|
line.long 0x0 "AMASK,Self Address Mask Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register.."
|
|
line.long 0x4 "ADDR,Self Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "UART3"
|
|
base ad:0x40500000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
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bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1030++0x3
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line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
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bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
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bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
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bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
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bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
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newline
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bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1038++0x3
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line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
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bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
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bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
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bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
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bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
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bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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wgroup.long 0x1040++0x3
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line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
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bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
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wgroup.long 0x1048++0x3
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line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
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bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
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newline
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bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1050++0x3
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line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
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group.long 0x1058++0x3
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line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
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bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1060++0x3
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line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
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bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1068++0x3
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line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
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bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
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wgroup.long 0x1070++0x3
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line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
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bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
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bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
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wgroup.long 0x1078++0x3
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line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
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bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
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bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x1080++0x3
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line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
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hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
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group.long 0x1088++0x3
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line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
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bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1090++0x3
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line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
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bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
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rgroup.long 0x1098++0x3
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line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
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bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
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wgroup.long 0x10A0++0x3
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line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
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bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
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wgroup.long 0x10A8++0x3
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line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
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bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
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rgroup.long 0x10E0++0x3
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line.long 0x0 "EVT_MODE,Event Mode"
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bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
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wgroup.long 0x10E4++0x3
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line.long 0x0 "INTCTL,Interrupt control register"
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bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
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group.long 0x1100++0x7
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line.long 0x0 "CTL0,UART Control Register 0"
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bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 18. "CTL0_MAJVOTE,When enabled with oversmapling of 16 samples samples 7 8 and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not.." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
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bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
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bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
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bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
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line.long 0x4 "LCRH,UART Line Control Register"
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hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
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hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
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bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
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bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
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bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
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bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
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rgroup.long 0x1108++0x3
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line.long 0x0 "STAT,UART Status Register"
|
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bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Mulitprocessor-Mode." "0: CLEARED,1: SET"
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bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
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bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
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bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
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group.long 0x110C++0xF
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line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
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hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
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bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,?,?,?,4: LVL_FULL,?,?,?"
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bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "0,1,2,3,4,5,6,7"
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line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
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hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
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line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
|
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hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
|
|
line.long 0xC "GFCTL,Glitch Filter Control"
|
|
bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "TXDATA,UART Transmit Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
|
|
rgroup.long 0x1124++0x3
|
|
line.long 0x0 "RXDATA,UART Receive Data Register"
|
|
bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Received Data. When read this field contains the data that was received by the UART."
|
|
group.long 0x1148++0x7
|
|
line.long 0x0 "AMASK,Self Address Mask Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register.."
|
|
line.long 0x4 "ADDR,Self Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "UART3"
|
|
base ad:0x40102000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
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|
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bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0x7
|
|
line.long 0x0 "CTL0,UART Control Register 0"
|
|
bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 18. "CTL0_MAJVOTE,Majority Vote Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
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bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
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|
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|
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bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
|
|
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|
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bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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|
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|
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bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: ENABLE"
|
|
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|
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bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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|
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|
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bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "LCRH,UART Line Control Register"
|
|
hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
|
|
hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
|
|
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|
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bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
|
|
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|
|
bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
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|
bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
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|
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|
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bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
|
|
bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "STAT,UART Status Register"
|
|
bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
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|
|
bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
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bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
|
|
group.long 0x110C++0xF
|
|
line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
|
|
bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_FULL,5: LVL_FULL,?,7: LVL_1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,?,5: LVL_EMPTY,?,7: LVL_1"
|
|
line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
|
|
line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
|
|
hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
|
|
line.long 0xC "GFCTL,Glitch Filter Control"
|
|
bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "TXDATA,UART Transmit Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
|
|
rgroup.long 0x1124++0x3
|
|
line.long 0x0 "RXDATA,UART Receive Data Register"
|
|
bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
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|
newline
|
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bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
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|
bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
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|
newline
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bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Received Data. When read this field contains the data that was received by the UART."
|
|
group.long 0x1148++0x7
|
|
line.long 0x0 "AMASK,Self Address Mask Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register.."
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|
line.long 0x4 "ADDR,Self Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh."
|
|
tree.end
|
|
endif
|
|
sif (cpuis("MSPM0L122*")||cpuis("MSPM0L222*"))
|
|
tree "UART4"
|
|
base ad:0x40104000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
newline
|
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bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
group.long 0x808++0x3
|
|
line.long 0x0 "CLKCFG,Peripheral Clock Configuration Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CLKCFG_KEY,KEY to Allow State Change -- 0xA9"
|
|
bitfld.long 0x0 8. "CLKCFG_BLOCKASYNC,Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "GPRCM_STAT,Status Register"
|
|
bitfld.long 0x0 16. "GPRCM_STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock" "0: DIV_BY_1,1: DIV_BY_2,2: DIV_BY_3,3: DIV_BY_4,4: DIV_BY_5,5: DIV_BY_6,6: DIV_BY_7,7: DIV_BY_8"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Select for Ultra Low Power peripherals"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUS CLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 1. "PDBGCTL_SOFT,Soft halt boundary control. This function is only available if [FREE] is set to 'STOP'" "0: IMMEDIATE,1: DELAYED"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "INT_EVENT0_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT0_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MIS registers. 15h-1Fh = Reserved"
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "INT_EVENT0_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 17. "INT_EVENT0_IMASK_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_IMASK_DMA_DONE_TX,Enable DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_IMASK_DMA_DONE_RX,Enable DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_IMASK_CTS,Enable UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_IMASK_ADDR_MATCH,Enable Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_IMASK_EOT,Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_IMASK_RXPE,Enable Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_IMASK_RXNE,Enable Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_IMASK_OVRERR,Enable UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_IMASK_BRKERR,Enable UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_IMASK_PARERR,Enable UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_IMASK_FRMERR,Enable UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "INT_EVENT0_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_RIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_RIS_DMA_DONE_TX,DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_RIS_DMA_DONE_RX,DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_RIS_CTS,UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_RIS_ADDR_MATCH,Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_RIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_RIS_RXPE,Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_RIS_RXNE,Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_RIS_OVRERR,UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_RIS_BRKERR,UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_RIS_PARERR,UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_RIS_FRMERR,UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "INT_EVENT0_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 17. "INT_EVENT0_MIS_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: CLR,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_MIS_DMA_DONE_TX,Masked DMA Done on TX Event Channel Interrupt" "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_MIS_DMA_DONE_RX,Masked DMA Done on RX Event Channel Interrupt" "0: CLR,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_MIS_CTS,Masked UART Clear to Send Modem Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_MIS_ADDR_MATCH,Masked Address Match Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_MIS_EOT,UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_MIS_RXPE,Masked Positive Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_MIS_RXNE,Masked Negative Edge on UARTxRXD Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_MIS_OVRERR,Masked UART Receive Overrun Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_MIS_BRKERR,Masked UART Break Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_MIS_PARERR,Masked UART Parity Error Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_MIS_FRMERR,Masked UART Framing Error Interrupt." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "INT_EVENT0_ISET,Interrupt set"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ISET_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ISET_DMA_DONE_TX,Set DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ISET_DMA_DONE_RX,Set DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ISET_CTS,Set UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ISET_ADDR_MATCH,Set Address Match Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ISET_EOT,Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ISET_RXPE,Set Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ISET_RXNE,Set Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ISET_OVRERR,Set UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ISET_BRKERR,Set UART Break Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ISET_PARERR,Set UART Parity Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ISET_FRMERR,Set UART Framing Error Interrupt." "0: NO_EFFECT,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "INT_EVENT0_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 17. "INT_EVENT0_ICLR_NERR,Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 16. "INT_EVENT0_ICLR_DMA_DONE_TX,Clear DMA Done on TX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 15. "INT_EVENT0_ICLR_DMA_DONE_RX,Clear DMA Done on RX Event Channel Interrupt" "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 14. "INT_EVENT0_ICLR_CTS,Clear UART Clear to Send Modem Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 13. "INT_EVENT0_ICLR_ADDR_MATCH,Clear Address Match Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 12. "INT_EVENT0_ICLR_EOT,Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 11. "INT_EVENT0_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 10. "INT_EVENT0_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 6. "INT_EVENT0_ICLR_RXPE,Clear Positive Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 5. "INT_EVENT0_ICLR_RXNE,Clear Negative Edge on UARTxRXD Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 4. "INT_EVENT0_ICLR_OVRERR,Clear UART Receive Overrun Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 3. "INT_EVENT0_ICLR_BRKERR,Clear UART Break Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 2. "INT_EVENT0_ICLR_PARERR,Clear UART Parity Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 1. "INT_EVENT0_ICLR_FRMERR,Clear UART Framing Error Interrupt." "0: NO_EFFECT,1: CLR"
|
|
newline
|
|
bitfld.long 0x0 0. "INT_EVENT0_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1050++0x3
|
|
line.long 0x0 "INT_EVENT1_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT1_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1058++0x3
|
|
line.long 0x0 "INT_EVENT1_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 10. "INT_EVENT1_IMASK_RXINT,Enable UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_IMASK_RTOUT,Enable UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1060++0x3
|
|
line.long 0x0 "INT_EVENT1_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_RIS_RXINT,UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_RIS_RTOUT,UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1068++0x3
|
|
line.long 0x0 "INT_EVENT1_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 10. "INT_EVENT1_MIS_RXINT,Masked UART Receive Interrupt." "0: CLR,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_MIS_RTOUT,Masked UARTOUT Receive Time-Out Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1070++0x3
|
|
line.long 0x0 "INT_EVENT1_ISET,Interrupt set"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ISET_RXINT,Set UART Receive Interrupt." "0: NO_EFFECT,1: SET"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ISET_RTOUT,Set UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1078++0x3
|
|
line.long 0x0 "INT_EVENT1_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 10. "INT_EVENT1_ICLR_RXINT,Clear UART Receive Interrupt." "0: NO_EFFECT,1: CLR"
|
|
bitfld.long 0x0 0. "INT_EVENT1_ICLR_RTOUT,Clear UARTOUT Receive Time-Out Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x1080++0x3
|
|
line.long 0x0 "INT_EVENT2_IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--7. 1. "INT_EVENT2_IIDX_STAT,UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"
|
|
group.long 0x1088++0x3
|
|
line.long 0x0 "INT_EVENT2_IMASK,Interrupt mask"
|
|
bitfld.long 0x0 11. "INT_EVENT2_IMASK_TXINT,Enable UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1090++0x3
|
|
line.long 0x0 "INT_EVENT2_RIS,Raw interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_RIS_TXINT,UART Transmit Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1098++0x3
|
|
line.long 0x0 "INT_EVENT2_MIS,Masked interrupt status"
|
|
bitfld.long 0x0 11. "INT_EVENT2_MIS_TXINT,Masked UART Transmit Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x10A0++0x3
|
|
line.long 0x0 "INT_EVENT2_ISET,Interrupt set"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ISET_TXINT,Set UART Transmit Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x10A8++0x3
|
|
line.long 0x0 "INT_EVENT2_ICLR,Interrupt clear"
|
|
bitfld.long 0x0 11. "INT_EVENT2_ICLR_TXINT,Clear UART Transmit Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 4.--5. "EVT_MODE_INT2_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT2]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
bitfld.long 0x0 2.--3. "EVT_MODE_INT1_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT1]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
wgroup.long 0x10E4++0x3
|
|
line.long 0x0 "INTCTL,Interrupt control register"
|
|
bitfld.long 0x0 0. "INTCTL_INTEVAL,Writing a 1 to this field re-evaluates the interrupt sources." "0: DISABLE,1: EVAL"
|
|
group.long 0x1100++0x7
|
|
line.long 0x0 "CTL0,UART Control Register 0"
|
|
bitfld.long 0x0 19. "CTL0_MSBFIRST,Most Significant Bit First" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 18. "CTL0_MAJVOTE,Majority Vote Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 17. "CTL0_FEN,UART Enable FIFOs" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 15.--16. "CTL0_HSE,High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration. The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)." "0: OVS16,1: OVS8,2: OVS3,?"
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|
newline
|
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bitfld.long 0x0 14. "CTL0_CTSEN,Enable Clear To Send" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 13. "CTL0_RTSEN,Enable hardware controlled Request to Send" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 12. "CTL0_RTS,Request to Send" "0: CLR,1: SET"
|
|
bitfld.long 0x0 8.--10. "CTL0_MODE,Set the communication mode and protocol used." "0: UART,1: RS485,2: IDLELINE,3: ADDR9BIT,4: SMART,5: DALI,?,?"
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|
newline
|
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bitfld.long 0x0 6. "CTL0_TXD_OUT,TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0." "0: LOW,1: HIGH"
|
|
bitfld.long 0x0 5. "CTL0_TXD_OUT_EN,TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0) the TXD pin can be controlled by the TXD_OUT bit." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 4. "CTL0_TXE,UART Transmit Enable If the UART is disabled in the middle of a transmission it completes the current character before stopping. #b#NOTE:#/b# To enable transmission the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 3. "CTL0_RXE,UART Receive Enable If the UART is disabled in the middle of a receive it completes the current character before stopping. #b#NOTE:#/b# To enable reception the UARTEN bit must be set." "0: DISABLE,1: ENABLE"
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|
newline
|
|
bitfld.long 0x0 2. "CTL0_LBE,UART Loop Back Enable" "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x0 0. "CTL0_ENABLE,UART Module Enable. If the UART is disabled in the middle of transmission or reception it completes the current character before stopping." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "LCRH,UART Line Control Register"
|
|
hexmask.long.byte 0x4 21.--25. 1. "LCRH_EXTDIR_HOLD,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"
|
|
hexmask.long.byte 0x4 16.--20. 1. "LCRH_EXTDIR_SETUP,Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"
|
|
newline
|
|
bitfld.long 0x4 7. "LCRH_SENDIDLE,UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards." "0: DISABLE,1: ENABLE"
|
|
bitfld.long 0x4 6. "LCRH_SPS,UART Stick Parity Select" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "LCRH_WLEN,UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:" "0: DATABIT5,1: DATABIT6,2: DATABIT7,3: DATABIT8"
|
|
bitfld.long 0x4 3. "LCRH_STP2,UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register) the number of stop bits is forced to 2." "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 2. "LCRH_EPS,UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The.." "0: The transferred byte is a data byte,1: The transferred byte is an address byte"
|
|
bitfld.long 0x4 1. "LCRH_PEN,UART Parity Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x4 0. "LCRH_BRK,UART Send Break (for LIN Protocol)" "0: DISABLE,1: ENABLE"
|
|
rgroup.long 0x1108++0x3
|
|
line.long 0x0 "STAT,UART Status Register"
|
|
bitfld.long 0x0 9. "STAT_IDLE,IDLE mode has been detected in Idleline-Multiprocessor-Mode." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 8. "STAT_CTS,Clear To Send" "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 7. "STAT_TXFF,UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 6. "STAT_TXFE,UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 3. "STAT_RXFF,UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
bitfld.long 0x0 2. "STAT_RXFE,UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register." "0: CLEARED,1: SET"
|
|
newline
|
|
bitfld.long 0x0 0. "STAT_BUSY,UART Busy" "0: CLEARED,1: SET"
|
|
group.long 0x110C++0xF
|
|
line.long 0x0 "IFLS,UART Interrupt FIFO Level Select Register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "IFLS_RXTOSEL,UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."
|
|
bitfld.long 0x0 4.--6. "IFLS_RXIFLSEL,UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:" "0: LVL_1_4,1: LVL_1_4,2: LVL_1_2,3: LVL_3_4,4: LVL_FULL,5: LVL_FULL,?,7: LVL_1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "IFLS_TXIFLSEL,UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:" "?,1: LVL_3_4,2: LVL_1_2,3: LVL_1_4,?,5: LVL_EMPTY,?,7: LVL_1"
|
|
line.long 0x4 "IBRD,UART Integer Baud-Rate Divisor Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "IBRD_DIVINT,Integer Baud-Rate Divisor"
|
|
line.long 0x8 "FBRD,UART Fractional Baud-Rate Divisor Register"
|
|
hexmask.long.byte 0x8 0.--5. 1. "FBRD_DIVFRAC,Fractional Baud-Rate Divisor"
|
|
line.long 0xC "GFCTL,Glitch Filter Control"
|
|
bitfld.long 0xC 9.--10. "GFCTL_AGFSEL,Analog Glitch Suppression Pulse Width" "0: AGLIT_5,1: AGLIT_10,2: AGLIT_25,3: AGLIT_50"
|
|
bitfld.long 0xC 8. "GFCTL_AGFEN,Analog Glitch Suppression Enable" "0: DISABLE,1: ENABLE"
|
|
group.long 0x1120++0x3
|
|
line.long 0x0 "TXDATA,UART Transmit Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA_DATA,Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read this field contains the data that was received by the UART."
|
|
rgroup.long 0x1124++0x3
|
|
line.long 0x0 "RXDATA,UART Receive Data Register"
|
|
bitfld.long 0x0 12. "RXDATA_NERR,Noise Error." "0: CLR,1: SET"
|
|
bitfld.long 0x0 11. "RXDATA_OVRERR,UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow the FIFO contents remain valid because no further data.." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 10. "RXDATA_BRKERR,UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs only one 0.." "0: CLR,1: SET"
|
|
bitfld.long 0x0 9. "RXDATA_PARERR,UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register." "0: CLR,1: SET"
|
|
newline
|
|
bitfld.long 0x0 8. "RXDATA_FRMERR,UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO." "0: CLR,1: SET"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA_DATA,Received Data. When read this field contains the data that was received by the UART."
|
|
group.long 0x1148++0x7
|
|
line.long 0x0 "AMASK,Self Address Mask Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "AMASK_VALUE,Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures that the corresponding bit in the ADDR bitfield of the UARTxADDR register.."
|
|
line.long 0x4 "ADDR,Self Address Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ADDR_VALUE,Self Address for 9-Bit Mode This field contains the address that should be matched when UARTxAMASK is FFh."
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "VREF (Voltage Reference)"
|
|
base ad:0x40030000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear the RESETSTKY bit in the STAT register" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1000++0x3
|
|
line.long 0x0 "CLKDIV,Clock Divider"
|
|
bitfld.long 0x0 0.--2. "CLKDIV_RATIO,Selects divide ratio of module clock to be used in sample and hold logic" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1008++0x3
|
|
line.long 0x0 "CLKSEL,Clock Selection"
|
|
bitfld.long 0x0 3. "CLKSEL_BUSCLK_SEL,Selects BUSCLK as clock source if enabled" "0,1"
|
|
bitfld.long 0x0 2. "CLKSEL_MFCLK_SEL,Selects MFCLK as clock source if enabled" "0,1"
|
|
bitfld.long 0x0 1. "CLKSEL_LFCLK_SEL,Selects LFCLK as clock source if enabled" "0,1"
|
|
sif (cpuis("MSPM0L110*"))
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
endif
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "CTL0,Control 0"
|
|
sif (cpuis("MSPM0L110*"))
|
|
hexmask.long.byte 0x0 9.--12. 1. "CTL0_SPARE,These bits are reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
hexmask.long.byte 0x0 9.--12. 1. "CTL0_SPARE,These bits are reserved"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
hexmask.long.byte 0x0 9.--12. 1. "CTL0_SPARE,These bits are reserved"
|
|
endif
|
|
bitfld.long 0x0 8. "CTL0_SHMODE,This bit enable sample and hold mode" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
bitfld.long 0x0 7. "CTL0_BUFCONFIG,These bits configure output buffer." "0: HV,1: LV"
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 2.--3. "CTL0_IBPROG,There bits configure current bias." "0: NOMIBIAS,1: IBPROG01,2: IBPROG10,3: IBPROG11"
|
|
bitfld.long 0x0 1. "CTL0_ENABLEBIAS,This bit enables the VREF Bias." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 2.--3. "CTL0_IBPROG,There bits configure current bias." "0: NOMIBIAS,1: IBPROG01,2: IBPROG10,3: IBPROG11"
|
|
newline
|
|
bitfld.long 0x0 1. "CTL0_ENABLEBIAS,This bit enables the VREF Bias." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 2.--3. "CTL0_IBPROG,There bits configure current bias." "0: NOMIBIAS,1: IBPROG01,2: IBPROG10,3: IBPROG11"
|
|
bitfld.long 0x0 1. "CTL0_ENABLEBIAS,This bit enables the VREF Bias." "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
bitfld.long 0x0 1. "CTL0_COMP_VREF_ENABLE,Comparator Vref Enable" "0: DISABLE,1: ENABLE"
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
bitfld.long 0x0 1. "CTL0_COMP_VREF_ENABLE,Comparator Vref Enable" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
bitfld.long 0x0 1. "CTL0_COMP_VREF_ENABLE,Comparator Vref Enable" "0: DISABLE,1: ENABLE"
|
|
endif
|
|
bitfld.long 0x0 0. "CTL0_ENABLE,This bit enables the VREF module." "0: DISABLE,1: ENABLE"
|
|
line.long 0x4 "CTL1,Control 1"
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x4 1. "CTL1_VREFLOSEL,This bit select VREFLO pin" "0,1"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x4 1. "CTL1_VREFLOSEL,This bit select VREFLO pin" "0,1"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x4 1. "CTL1_VREFLOSEL,This bit select VREFLO pin" "0,1"
|
|
endif
|
|
rbitfld.long 0x4 0. "CTL1_READY,These bits defines status of VREF" "0: NOTRDY,1: RDY"
|
|
line.long 0x8 "CTL2,Control 2"
|
|
hexmask.long.word 0x8 16.--31. 1. "CTL2_HCYCLE,Hold cycle count"
|
|
hexmask.long.word 0x8 0.--15. 1. "CTL2_SHCYCLE,Sample and Hold cycle count"
|
|
tree.end
|
|
tree "WUC (Wake Up Controller)"
|
|
base ad:0x40424000
|
|
group.long 0x400++0x7
|
|
line.long 0x0 "FSUB_0,Subscriber Port 0"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x0 0.--1. "FSUB_0_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "FSUB_0_CHANID,0 = disconnected."
|
|
endif
|
|
line.long 0x4 "FSUB_1,Subscriber Port 1"
|
|
sif (cpuis("MSPM0C110*")||cpuis("MSPS003*"))
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0G110*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G150*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G310*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0G350*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
newline
|
|
endif
|
|
sif (cpuis("MSPM0L110*"))
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L130*"))
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L134*"))
|
|
bitfld.long 0x4 0.--1. "FSUB_1_CHANID,0 = disconnected." "0: disconnected,?,?,?"
|
|
endif
|
|
sif (cpuis("MSPM0L122*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
sif (cpuis("MSPM0L222*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "FSUB_1_CHANID,0 = disconnected."
|
|
endif
|
|
tree.end
|
|
tree "WWDT (Window Watchdog Timer)"
|
|
base ad:0x0
|
|
tree "WWDT0"
|
|
base ad:0x40080000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear [GPRCM.STAT.RESETSTKY]" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--4. 1. "IIDX_STAT,Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC."
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 0. "IMASK_INTTIM,Interval Timer Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "RIS_INTTIM,Interval Timer Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "MIS_INTTIM,Interval Timer Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "ISET_INTTIM,Interval Timer Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "ICLR_INTTIM,Interval Timer Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "WWDTCTL0,Window Watchdog Timer Control Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WWDTCTL0_KEY,KEY to allow write access to this register."
|
|
bitfld.long 0x0 17. "WWDTCTL0_STISM,Stop In Sleep Mode." "0: CONT,1: STOP"
|
|
bitfld.long 0x0 16. "WWDTCTL0_MODE,Window Watchdog Timer Mode" "0: WINDOW,1: INTERVAL"
|
|
bitfld.long 0x0 12.--14. "WWDTCTL0_WINDOW1,Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)." "0: SIZE_0,1: SIZE_12,2: SIZE_18,3: SIZE_25,4: SIZE_50,5: SIZE_75,6: SIZE_81,7: SIZE_87"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "WWDTCTL0_WINDOW0,Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)." "0: SIZE_0,1: SIZE_12,2: SIZE_18,3: SIZE_25,4: SIZE_50,5: SIZE_75,6: SIZE_81,7: SIZE_87"
|
|
bitfld.long 0x0 4.--6. "WWDTCTL0_PER,Timer Period of the WWDT. These bits select the total watchdog timer count." "0: EN_25,1: EN_21,2: EN_18,3: EN_15,4: EN_12,5: EN_10,6: EN_8,7: EN_6"
|
|
bitfld.long 0x0 0.--2. "WWDTCTL0_CLKDIV,Module Clock Divider Divide the clock source by CLKDIV+1." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "WWDTCTL1,Window Watchdog Timer Control Register 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. "WWDTCTL1_KEY,KEY to allow write access to this register."
|
|
bitfld.long 0x4 0. "WWDTCTL1_WINSEL,Close Window Select" "0: WIN0,1: WIN1"
|
|
line.long 0x8 "WWDTCNTRST,Window Watchdog Timer Counter Reset Register"
|
|
hexmask.long 0x8 0.--31. 1. "WWDTCNTRST_RESTART,Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter."
|
|
rgroup.long 0x110C++0x3
|
|
line.long 0x0 "WWDTSTAT,Window Watchdog Timer Status Register"
|
|
bitfld.long 0x0 0. "WWDTSTAT_RUN,Watchdog running status flag." "0: OFF,1: ON"
|
|
tree.end
|
|
sif (cpuis("MSPM0G110*")||cpuis("MSPM0G150*")||cpuis("MSPM0G310*")||cpuis("MSPM0G350*"))
|
|
tree "WWDT1"
|
|
base ad:0x40082000
|
|
group.long 0x800++0x3
|
|
line.long 0x0 "PWREN,Power enable"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PWREN_KEY,KEY to allow Power State Change"
|
|
bitfld.long 0x0 0. "PWREN_ENABLE,Enable the power" "0: DISABLE,1: ENABLE"
|
|
wgroup.long 0x804++0x3
|
|
line.long 0x0 "RSTCTL,Reset Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RSTCTL_KEY,Unlock key"
|
|
bitfld.long 0x0 1. "RSTCTL_RESETSTKYCLR,Clear [GPRCM.STAT.RESETSTKY]" "0: NOP,1: CLR"
|
|
bitfld.long 0x0 0. "RSTCTL_RESETASSERT,Assert reset to the peripheral" "0: NOP,1: ASSERT"
|
|
rgroup.long 0x814++0x3
|
|
line.long 0x0 "STAT,Status Register"
|
|
bitfld.long 0x0 16. "STAT_RESETSTKY,This bit indicates if the peripheral was reset since this bit was cleared by RESETSTKYCLR in the RSTCTL register" "0: NORES,1: RESET"
|
|
group.long 0x1018++0x3
|
|
line.long 0x0 "PDBGCTL,Peripheral Debug Control"
|
|
bitfld.long 0x0 0. "PDBGCTL_FREE,Free run control" "0: STOP,1: RUN"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x0 "IIDX,Interrupt index"
|
|
hexmask.long.byte 0x0 0.--4. 1. "IIDX_STAT,Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC."
|
|
group.long 0x1028++0x3
|
|
line.long 0x0 "IMASK,Interrupt mask"
|
|
bitfld.long 0x0 0. "IMASK_INTTIM,Interval Timer Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "RIS,Raw interrupt status"
|
|
bitfld.long 0x0 0. "RIS_INTTIM,Interval Timer Interrupt." "0: CLR,1: SET"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "MIS,Masked interrupt status"
|
|
bitfld.long 0x0 0. "MIS_INTTIM,Interval Timer Interrupt." "0: CLR,1: SET"
|
|
wgroup.long 0x1040++0x3
|
|
line.long 0x0 "ISET,Interrupt set"
|
|
bitfld.long 0x0 0. "ISET_INTTIM,Interval Timer Interrupt." "0: NO_EFFECT,1: SET"
|
|
wgroup.long 0x1048++0x3
|
|
line.long 0x0 "ICLR,Interrupt clear"
|
|
bitfld.long 0x0 0. "ICLR_INTTIM,Interval Timer Interrupt." "0: NO_EFFECT,1: CLR"
|
|
rgroup.long 0x10E0++0x3
|
|
line.long 0x0 "EVT_MODE,Event Mode"
|
|
bitfld.long 0x0 0.--1. "EVT_MODE_INT0_CFG,Event line mode select for event corresponding to [IPSTANDARD.INT_EVENT][0]" "0: DISABLE,1: SOFTWARE,2: HARDWARE,?"
|
|
rgroup.long 0x10FC++0x3
|
|
line.long 0x0 "DESC,Module Description"
|
|
hexmask.long.word 0x0 16.--31. 1. "DESC_MODULEID,Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."
|
|
hexmask.long.byte 0x0 12.--15. 1. "DESC_FEATUREVER,Feature Set for the module *instance*"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DESC_INSTNUM,Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DESC_MAJREV,Major rev of the IP"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DESC_MINREV,Minor rev of the IP"
|
|
group.long 0x1100++0xB
|
|
line.long 0x0 "WWDTCTL0,Window Watchdog Timer Control Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "WWDTCTL0_KEY,KEY to allow write access to this register."
|
|
bitfld.long 0x0 17. "WWDTCTL0_STISM,Stop In Sleep Mode." "0: CONT,1: STOP"
|
|
bitfld.long 0x0 16. "WWDTCTL0_MODE,Window Watchdog Timer Mode" "0: WINDOW,1: INTERVAL"
|
|
bitfld.long 0x0 12.--14. "WWDTCTL0_WINDOW1,Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)." "0: SIZE_0,1: SIZE_12,2: SIZE_18,3: SIZE_25,4: SIZE_50,5: SIZE_75,6: SIZE_81,7: SIZE_87"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "WWDTCTL0_WINDOW0,Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)." "0: SIZE_0,1: SIZE_12,2: SIZE_18,3: SIZE_25,4: SIZE_50,5: SIZE_75,6: SIZE_81,7: SIZE_87"
|
|
bitfld.long 0x0 4.--6. "WWDTCTL0_PER,Timer Period of the WWDT. These bits select the total watchdog timer count." "0: EN_25,1: EN_21,2: EN_18,3: EN_15,4: EN_12,5: EN_10,6: EN_8,7: EN_6"
|
|
bitfld.long 0x0 0.--2. "WWDTCTL0_CLKDIV,Module Clock Divider Divide the clock source by CLKDIV+1." "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "WWDTCTL1,Window Watchdog Timer Control Register 0"
|
|
hexmask.long.byte 0x4 24.--31. 1. "WWDTCTL1_KEY,KEY to allow write access to this register."
|
|
bitfld.long 0x4 0. "WWDTCTL1_WINSEL,Close Window Select" "0: WIN0,1: WIN1"
|
|
line.long 0x8 "WWDTCNTRST,Window Watchdog Timer Counter Reset Register"
|
|
hexmask.long 0x8 0.--31. 1. "WWDTCNTRST_RESTART,Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter."
|
|
rgroup.long 0x110C++0x3
|
|
line.long 0x0 "WWDTSTAT,Window Watchdog Timer Status Register"
|
|
bitfld.long 0x0 0. "WWDTSTAT_RUN,Watchdog running status flag." "0: OFF,1: ON"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
AUTOINDENT.OFF
|