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Gen4_R-Car_Trace32/2_Trunk/permini58.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: MINI58 On-Chip Peripherals
; @Props: Released
; @Author: NEJ, KRZ
; @Changelog: 2023-09-06 NEJ
; 2023-11-09 KRZ
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
; @Doc: Generated (TRACE32, build: 164352.), based on:
; MINI58DE_v1.svd (Ver. 1.0)
; @Core: Cortex-M0
; @Chip: MINI58FDE, MINI58LDE, MINI58TDE, MINI58ZDE
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: permini58.per 16971 2023-11-09 16:09:22Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ACMP (Analog Comparator)"
base ad:0x400D0000
group.long 0x0++0xF
line.long 0x0 "ACMP_CTL0,Analog Comparator 0 Control Register"
bitfld.long 0x0 29.--30. "POSSEL,Analog Comparator 0 Positive Input Selection\n" "0: ACMP0_Px is from ACMP0_P0 (P1.5) pin,1: ACMP0_Px is from ACMP0_P1 (P1.0) pin,?,?"
hexmask.long.byte 0x0 20.--23. 1. "FILTSEL,Comparator Output Filter Count Selection\n"
newline
bitfld.long 0x0 9. "FTRGEN,Analog Comparator 0 Falling Edge Trigger Enable\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer." "0: Analog comparator 0 falling edge trigger PWM or..,1: Analog comparator 0 falling edge trigger disabled"
bitfld.long 0x0 8. "RTRGEN,Analog Comparator 0 Rising Edge Trigger Enable Bit\nNote: The bit is only effective while analog comparator 0 triggers PWM or Timer." "0: Analog comparator 0 rising edge trigger PWM or..,1: Analog comparator 0 rising edge trigger disabled"
newline
bitfld.long 0x0 4. "NEGSEL,Analog Comparator 0 Negative Input Select Bit\n" "0: The source of the negative comparator input is..,1: The source of the negative comparator input is.."
bitfld.long 0x0 2. "HYSSEL,Analog Comparator 0 Hysteresis Select Bit\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled"
newline
bitfld.long 0x0 1. "ACMPIE,Analog Comparator 0 Interrupt Enable Bit\n" "0: Interrupt function Disabled,1: Interrupt function Enabled"
bitfld.long 0x0 0. "ACMPEN,Analog Comparator 0 Enable Bit\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set." "0: Analog Comparator 0 Disabled,1: Analog Comparator 1 Enabled"
line.long 0x4 "ACMP_CTL1,Analog Comparator 1 Control Register"
bitfld.long 0x4 29.--30. "POSSEL,Analog Comparator 1 Positive Input Selection\n" "0: ACMP1_Px is from ACMP1_P0 (P3.1) pin,1: ACMP1_Px is from ACMP1_P1 (P3.2) pin,?,?"
hexmask.long.byte 0x4 20.--23. 1. "FILTSEL,Comparator Output Filter Count Selection\n"
newline
bitfld.long 0x4 9. "FTRGEN,Analog Comparator 1 Falling Edge Trigger Enable Bit\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer." "0: Analog comparator 1 falling edge trigger PWM or..,1: Analog comparator 1 falling edge trigger Disabled"
bitfld.long 0x4 8. "RTRGEN,Analog Comparator 1 Rising Edge Trigger Enable Bit\nNote: The bit is only effective while analog comparator 1 triggers PWM or Timer." "0: Analog comparator 1 rising edge trigger PWM or..,1: Analog comparator 1 rising edge trigger Disabled"
newline
bitfld.long 0x4 4. "NEGSEL,Analog Comparator 1 Negative Input Select Bit\n" "0: The source of the negative comparator input is..,1: The source of the negative comparator input is.."
bitfld.long 0x4 2. "HYSSEL,Analog Comparator 1 Hysteresis Select Bit\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled"
newline
bitfld.long 0x4 1. "ACMPIE,Analog Comparator 1 Interrupt Enable Bit\n" "0: Interrupt function Disabled,1: Interrupt function Enabled"
bitfld.long 0x4 0. "ACMPEN,Analog Comparator 1 Enable Bit\nNote: Analog comparator output needs to wait 2 us stable time after this bit is set." "0: Analog Comparator 1 Disabled,1: Analog Comparator 1 Enabled"
line.long 0x8 "ACMP_STATUS,Analog Comparator 0/1 Status Register"
bitfld.long 0x8 3. "ACMPO1,Analog Comparator 1 Output\n" "0: Analog comparator 1 outputs 0,1: Analog comparator 1 outputs 1"
bitfld.long 0x8 2. "ACMPO0,Analog Comparator 0 Output\n" "0: Analog comparator 0 outputs 0,1: Analog comparator 0 outputs 1"
newline
bitfld.long 0x8 1. "ACMPIF1,Analog Comparator 1 Flag\nNote: This bit can be cleared to 0 by software writing 1." "0: Analog comparator 1 output does not change,1: Analog comparator 1 output changed"
bitfld.long 0x8 0. "ACMPIF0,Analog Comparator 0 Flag\nNote: This bit can be cleared to 0 by software writing 1." "0: Analog comparator 0 output does not change,1: Analog comparator 0 output changed"
line.long 0xC "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
bitfld.long 0xC 7. "IREFSEL,CRV Internal Reference Selection\n" "0: Band-gap voltage,1: Internal comparator reference voltage"
hexmask.long.byte 0xC 0.--3. 1. "CRVCTL,Comparator Reference Voltage Control\n"
tree.end
tree "ADC (Analog-to-Digital Converter)"
base ad:0x400E0000
rgroup.long 0x0++0x3
line.long 0x0 "ADC_DAT,A/D Data Register"
bitfld.long 0x0 17. "VALID,Valid Flag \nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.\n" "0: Data in RESULT[9:0] bits not valid,1: Data in RESULT[9:0] bits valid"
bitfld.long 0x0 16. "OV,Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.\n" "0: Data in RESULT[9:0] is recent conversion result,1: Data in RESULT[9:0] overwrote"
newline
hexmask.long.word 0x0 0.--9. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC."
group.long 0x20++0x13
line.long 0x0 "ADC_CTL,A/D Control Register"
bitfld.long 0x0 11. "SWTRG,Software Trigger A/D Conversion Start\nSWTRG bit can be set to 1 from two sources: software and external pin STADC. SWTRG will be cleared to 0 by hardware automatically after conversion complete.\n" "0: Conversion stopped and A/D converter entered..,1: Conversion start"
bitfld.long 0x0 8. "HWTRGEN,Hardware External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled the SWTRG bit can be set to 1 by the selected hardware trigger source.\n" "0: External trigger Disabled,1: External trigger Enabled"
newline
bitfld.long 0x0 6. "HWTRGCOND,Hardware External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.\n" "0: Falling edge,1: Raising edge"
bitfld.long 0x0 4.--5. "HWTRGSEL,Hardware Trigger Source Select Bit\nNote: Software should disable TRGEN and SWTRG before change TRGS." "0: A/D conversion is started by external STADC pin,?,?,?"
newline
bitfld.long 0x0 1. "ADCIEN,A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADCIEN bit is set to 1.\n" "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
bitfld.long 0x0 0. "ADCEN,A/D Converter Enable Bit\nNote: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption." "0: A/D Converter Disabled,1: A/D Converter Enabled"
line.long 0x4 "ADC_CHEN,A/D Channel Enable Register"
bitfld.long 0x4 8. "CH7SEL,Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7 the ADC clock rate needs to be limited to lower than 300 kHz." "0: External analog input,1: Internal band-gap voltage (VBG)"
bitfld.long 0x4 7. "CHEN7,Analog Input Channel 7 Enable Bit\n" "0: Channel 7 Disabled,1: Channel 7 Enabled"
newline
bitfld.long 0x4 6. "CHEN6,Analog Input Channel 6 Enable Bit\n" "0: Channel 6 Disabled,1: Channel 6 Enabled"
bitfld.long 0x4 5. "CHEN5,Analog Input Channel 5 Enable Bit\n" "0: Channel 5 Disabled,1: Channel 5 Enabled"
newline
bitfld.long 0x4 4. "CHEN4,Analog Input Channel 4 Enable Bit\n" "0: Channel 4 Disabled,1: Channel 4 Enabled"
bitfld.long 0x4 3. "CHEN3,Analog Input Channel 3 Enable Bit\n" "0: Channel 3 Disabled,1: Channel 3 Enabled"
newline
bitfld.long 0x4 2. "CHEN2,Analog Input Channel 2 Enable Bit\n" "0: Channel 2 Disabled,1: Channel 2 Enabled"
bitfld.long 0x4 1. "CHEN1,Analog Input Channel 1 Enable Bit\n" "0: Channel 1 Disabled,1: Channel 1 Enabled"
newline
bitfld.long 0x4 0. "CHEN0,Analog Input Channel 0 Enable Bit\nNote: If software enables more than one channel the channel with the smallest number will be selected and the other enabled channels will be ignored." "0: Channel 0 Disabled,1: Channel 0 Enabled"
line.long 0x8 "ADC_CMP0,A/D Compare Register 0"
hexmask.long.word 0x8 16.--25. 1. "CMPDAT,Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel."
hexmask.long.byte 0x8 8.--11. 1. "CMPMCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT+1) the ADCMPFx.."
newline
bitfld.long 0x8 3.--5. "CMPCH,Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~7." "0,1,2,3,4,5,6,7"
bitfld.long 0x8 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMCNT+1) the ADCMPFx bit will be set." "0: Set the compare condition as that when a 10-bit..,1: Set the compare condition as that when a 10-bit.."
newline
bitfld.long 0x8 1. "ADCMPIE,A/D Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT ADCMPIE bit will be asserted in the meanwhile if ADCMPIE is set to 1 a compare interrupt request is.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0x8 0. "ADCMPEN,A/D Compare Enable Bit\nSet 1 to this bit to enable comparing CMPDAT (ADC_CMPx[25:16]) with specified channel conversion results when converted data is loaded into the ADC_DAT register.\n" "0: Compare function Disabled,1: Compare function Enabled"
line.long 0xC "ADC_CMP1,A/D Compare Register 1"
hexmask.long.word 0xC 16.--25. 1. "CMPDAT,Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel."
hexmask.long.byte 0xC 8.--11. 1. "CMPMCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT+1) the ADCMPFx.."
newline
bitfld.long 0xC 3.--5. "CMPCH,Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~7." "0,1,2,3,4,5,6,7"
bitfld.long 0xC 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMCNT+1) the ADCMPFx bit will be set." "0: Set the compare condition as that when a 10-bit..,1: Set the compare condition as that when a 10-bit.."
newline
bitfld.long 0xC 1. "ADCMPIE,A/D Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT ADCMPIE bit will be asserted in the meanwhile if ADCMPIE is set to 1 a compare interrupt request is.." "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0xC 0. "ADCMPEN,A/D Compare Enable Bit\nSet 1 to this bit to enable comparing CMPDAT (ADC_CMPx[25:16]) with specified channel conversion results when converted data is loaded into the ADC_DAT register.\n" "0: Compare function Disabled,1: Compare function Enabled"
line.long 0x10 "ADC_STATUS,A/D Status Register"
rbitfld.long 0x10 16. "OV,Overrun Flag (Read Only)\nIt is a mirror to OV bit in ADC_DAT register." "0,1"
rbitfld.long 0x10 8. "VALID,Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in ADC_DAT register." "0,1"
newline
rbitfld.long 0x10 4.--6. "CHANNEL,Current Conversion Channel (Read Only)\n" "0,1,2,3,4,5,6,7"
rbitfld.long 0x10 3. "BUSY,BUSY/IDLE (Read Only)\nThis bit is mirror of as SWTRG bit in ADC_CTL\n" "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
newline
bitfld.long 0x10 2. "ADCMPF1,A/D Compare Flag 1\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP1 this bit is set to 1.\nNote: This bit can be cleared to 0 by software writing 1." "0: Conversion result in ADC_DAT does not meet the..,1: Conversion result in ADC_DAT meets the ADC_CMP1.."
bitfld.long 0x10 1. "ADCMPF0,A/D Compare Flag 0\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP0 this bit is set to 1.\nNote: This bit can be cleared to 0 by software writing 1." "0: Conversion result in ADC_DAT does not meet the..,1: Conversion result in ADC_DAT meets the ADC_CMP0.."
newline
bitfld.long 0x10 0. "ADIF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. ADIF is set to 1 When A/D conversion ends.\nNote: This bit can be cleared to 0 by software writing 1." "0,1"
group.long 0x44++0xB
line.long 0x0 "ADC_TRGDLY,A/D Trigger Delay Control Register"
hexmask.long.byte 0x0 0.--7. 1. "DELAY,PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * DELAY) * system clock."
line.long 0x4 "ADC_EXTSMPT,A/D Sampling Time Counter Register"
hexmask.long.byte 0x4 0.--3. 1. "EXTSMPT,Additional ADC Sample Clock\nIf the ADC input is unstable user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clocks. The additional clock number will be inserted to.."
line.long 0x8 "ADC_SEQCTL,A/D PWM Sequential Mode Control Register"
hexmask.long.byte 0x8 16.--19. 1. "TRG2CTL,PWM Trigger Source Selection For TRG2CTL[3:2]\nNote: PWM trigger source is valid for 1-shunt type."
hexmask.long.byte 0x8 8.--11. 1. "TRG1CTL,PWM Trigger Source Selection For TRG1CTL[3:2]\nNote: PWM trigger source is valid for 1-shunt and 2/3-shunt type."
newline
bitfld.long 0x8 2.--3. "MODESEL,ADC Sequential Mode Selection\n" "0: Issue ADC_INT after Channel 0 then Channel 1..,1: Issue ADC_INT after Channel 1 then Channel 2..,?,?"
bitfld.long 0x8 1. "SEQTYPE,ADC Sequential Mode Type\n" "0: ADC delay time is only inserted before the first..,1: ADC delay time is inserted before each.."
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bitfld.long 0x8 0. "SEQEN,ADC Sequential Mode Enable Bit\nWhen ADC sequential mode is enabled two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0 1] or channel[1 2] or channel[0 2] defined by MODESEL.." "0: ADC sequential mode Disabled,1: ADC sequential mode Enabled"
rgroup.long 0x50++0x7
line.long 0x0 "ADC_SEQDAT1,A/D PWM Sequential Mode First Result Register1"
bitfld.long 0x0 17. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.\n" "0: Data in RESULT[9:0] bits not valid,1: Data in RESULT[9:0] bits valid"
bitfld.long 0x0 16. "OV,Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.\n" "0: Data in RESULT[9:0] is recent conversion result,1: Data in RESULT[9:0] overwritten"
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hexmask.long.word 0x0 0.--9. 1. "RESULT,A/D PWM Sequential Mode Conversion Result\nThis field contains conversion result of ADC."
line.long 0x4 "ADC_SEQDAT2,A/D PWM Sequential Mode Second Result Register1"
bitfld.long 0x4 17. "VALID,Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.\n" "0: Data in RESULT[9:0] bits not valid,1: Data in RESULT[9:0] bits valid"
bitfld.long 0x4 16. "OV,Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.\n" "0: Data in RESULT[9:0] is recent conversion result,1: Data in RESULT[9:0] overwritten"
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hexmask.long.word 0x4 0.--9. 1. "RESULT,A/D PWM Sequential Mode Conversion Result\nThis field contains conversion result of ADC."
tree.end
tree "CLK (Clock Controller)"
base ad:0x50000200
group.long 0x0++0x27
line.long 0x0 "CLK_PWRCTL,System Power-down Control Register"
bitfld.long 0x0 9. "PDLXT,Enable LXT In Power-down Mode\nThis bit controls the crystal oscillator active or not in Power-down mode.\n" "0: No effect to Power-down mode,1: If XTLEN[1:0] = 10 LXT is still active in.."
bitfld.long 0x0 7. "PDEN,System Power-down Enable Bit (Write Protect)\nWhen chip wakes up from Power-down mode this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode 4~24 MHz external high speed crystal oscillator (HXT) .." "0: Chip operating normally or chip in Idle mode..,1: Chip enters Power-down mode instantly or waits.."
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bitfld.long 0x0 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' which indicates that resume from Power-down mode'\nThe flag is set if the GPIO UART WDT ACMP Timer or BOD wake-up occurred.\nNote: This bit works only if PDWKIEN.." "0,1"
bitfld.long 0x0 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are high." "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled"
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bitfld.long 0x0 4. "PDWKDLY,Wake-up Delay Counter Enable Bit (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
bitfld.long 0x0 3. "LIRCEN,LIRC Enable Bit (Write Protect)\n" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
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bitfld.long 0x0 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote: The default of HIRCEN bit is 1." "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.."
bitfld.long 0x0 0.--1. "XTLEN,External HXT Or LXT Crystal Oscillator Enable Bit (Write Protect)\nThe default clock source is from HIRC. These two bits are default set to '00' and the XT1_IN and XT1_OUT pins are GPIO.\nNote: To enable external XTAL function ALT[1:0] and.." "0: XT1_IN and XT1_OUT are GPIO disable both LXT HXT..,1: HXT Enabled,?,?"
line.long 0x4 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit\n" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
line.long 0x8 "CLK_APBCLK,APB Devices Clock Enable Control Register"
bitfld.long 0x8 30. "ACMPCKEN,Analog Comparator Clock Enable Bit\n" "0: Analog Comparator clock Disabled,1: Analog Comparator clock Enabled"
bitfld.long 0x8 28. "ADCCKEN,Analog-digital-converter (ADC) Clock Enable Bit\n" "0: ADC peripheral clock Disabled,1: ADC peripheral clock Enabled"
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bitfld.long 0x8 22. "PWMCH45CKEN,PWM_45 Clock Enable Bit\n" "0: PWM45 clock Disabled,1: PWM45 clock Enabled"
bitfld.long 0x8 21. "PWMCH23CKEN,PWM_23 Clock Enable Bit\n" "0: PWM23 clock Disabled,1: PWM23 clock Enabled"
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bitfld.long 0x8 20. "PWMCH01CKEN,PWM_01 Clock Enable Bit\n" "0: PWM01 clock Disabled,1: PWM01 clock Enabled"
bitfld.long 0x8 17. "UART1CKEN,UART1 Clock Enable Bit\n" "0: UART1 clock Disabled,1: UART1 clock Enabled"
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bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Bit\n" "0: UART0 clock Disabled,1: UART0 clock Enabled"
bitfld.long 0x8 12. "SPICKEN,SPI Clock Enable Bit\n" "0: SPI peripheral clock Disabled,1: SPI peripheral clock Enabled"
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bitfld.long 0x8 9. "I2C1CKEN,I2C1 Clock Enable Bit\n" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Bit\n" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
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bitfld.long 0x8 6. "CLKOCKEN,Frequency Divider Output Clock Enable Bit\n" "0: CLKO clock Disabled,1: CLKO clock Enabled"
bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Bit\n" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
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bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Bit\n" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
bitfld.long 0x8 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address.." "0: Watchdog Timer clock Disabled,1: Watchdog Timer clock Enabled"
line.long 0xC "CLK_STATUS,Clock Status Monitor Register"
rbitfld.long 0xC 7. "CLKSFAIL,Clock Switch Fail Flag (Read Only)\nThis bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1.\nNote: This bit is.." "0: Clock switching success,1: Clock switching failure"
rbitfld.long 0xC 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)\n" "0: HIRC clock is not stable or disabled,1: HIRC clock is stable and enabled"
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rbitfld.long 0xC 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)\n" "0: LIRC clock is not stable or disabled,1: LIRC clock is stable and enabled"
rbitfld.long 0xC 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)\n" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled"
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bitfld.long 0xC 0. "XTLSTB,HXT Or LXT Clock Source Stable Flag\n" "0: HXT or LXT clock is not stable or disabled,1: HXT or LXT clock is stable and enabled"
line.long 0x10 "CLK_CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x10 3.--5. "STCLKSEL,Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote3: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Reserved,?,3: To set CLK_PWRCTL[1:0],?,?,?,?"
bitfld.long 0x10 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nNote1: Before clock switching the related clock sources (both pre-select and new-select) must be turn-on and stable.\nNote2: These bits are protected bit and programming them needs to write 0x59 .." "0: Clock source is from HXT or LXT,1: Before clock switching,2: These bits are protected bit,3: To set CLK_PWRCTL[1:0] to select HXT or LXT..,?,?,?,?"
line.long 0x14 "CLK_CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x14 30.--31. "PWMCH23SEL,PWM2 And PWM3 Clock Source Selection\nPWM2 and PWM3 use the same peripheral clock source; Both of them use the same prescaler.\n" "0: Reserved,1: Reserved,?,?"
bitfld.long 0x14 28.--29. "PWMCH01SEL,PWM0 And PWM1 Clock Source Selection\nPWM0 and PWM1 use the same peripheral clock source. Both of them use the same prescaler.\n" "0: Reserved,1: Reserved,?,?"
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bitfld.long 0x14 24.--25. "UARTSEL,UART Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from PLL,?,?"
bitfld.long 0x14 12.--14. "TMR1SEL,TIMER1 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from LIRC,?,?,?,?,?,?"
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bitfld.long 0x14 8.--10. "TMR0SEL,TIMER0 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from LIRC,?,?,?,?,?,?"
bitfld.long 0x14 4.--5. "SPISEL,SPI Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from HCLK,?,?"
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bitfld.long 0x14 2.--3. "ADCSEL,ADC Peripheral Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from PLL,?,?"
bitfld.long 0x14 0.--1. "WDTSEL,WDT CLK Clock Source Selection (Write Protect)\nNote1: These bits are the protected bit and programming them needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address.." "0: Clock source is from HXT or LXT,1: These bits are the protected bit,2: To set CLK_PWRCTL[1:0],?"
line.long 0x18 "CLK_CLKDIV,Clock Divider Number Register"
hexmask.long.byte 0x18 16.--23. 1. "ADCDIV,ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source\n"
hexmask.long.byte 0x18 8.--11. 1. "UARTDIV,UART Clock Divide Number From UART Clock Source\n"
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hexmask.long.byte 0x18 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source\n"
line.long 0x1C "CLK_CLKSEL2,Clock Source Select Control Register 2"
bitfld.long 0x1C 16.--17. "WWDTSEL,Window Watchdog Timer Clock Source Selection\n" "0: Reserved,1: Reserved,?,?"
bitfld.long 0x1C 4.--5. "PWMCH45SEL,PWM4 And PWM5 Clock Source Selection\nPWM4 and PWM5 use the same peripheral clock source; Both of them use the same prescaler.\n" "0: Reserved,1: Reserved,?,?"
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bitfld.long 0x1C 2.--3. "FREQSEL,Clock Divider Clock Source Selection\nNote: To set CLK_PWRCTL[1:0] select HXT or LXT crystal clock." "0: Clock source is from HXT or LXT,1: Clock source is from LIRC,?,?"
line.long 0x20 "CLK_PLLCTL,PLL Control Register"
bitfld.long 0x20 19. "PLLSRC,PLL Source Clock Selection\n" "0: PLL source clock from HXT,1: PLL source clock from HIRC"
bitfld.long 0x20 18. "OE,PLL OE (FOUT Enable) Pin Control\n" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
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bitfld.long 0x20 17. "BP,PLL Bypass Control\n" "0: PLL is in Normal mode (default),1: PLL clock output is same as PLL source clock input"
bitfld.long 0x20 16. "PD,Power-down Mode\nIf the PDEN bit is set to 1 in CLK_PWRCTL register the PLL will enter Power-down mode too.\n" "0: PLL is in Normal mode,1: PLL is in Power-down mode (default)"
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bitfld.long 0x20 14.--15. "OUTDIV,PLL Output Divider Control\nRefer to the formulas below the table." "0,1,2,3"
hexmask.long.byte 0x20 9.--13. 1. "INDIV,PLL Input Divider Control\nRefer to the formulas below the table."
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hexmask.long.word 0x20 0.--8. 1. "FBDIV,PLL Feedback Divider Control\nRefer to the formulas below the table."
line.long 0x24 "CLK_CLKOCTL,Frequency Divider Control Register"
bitfld.long 0x24 5. "DIV1EN,Frequency Divider One Enable Bit\n" "0: Divider output frequency is depended on FREQSEL..,1: Divider output frequency is the same as input.."
bitfld.long 0x24 4. "CLKOEN,Frequency Divider Enable Bit\n" "0: Frequency Divider Disabled,1: Frequency Divider Enabled"
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hexmask.long.byte 0x24 0.--3. 1. "FREQSEL,Divider Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL(CLK_CLKOCTL[3:0])."
tree.end
tree "EPWM (Enhanced PWM Generator)"
base ad:0x40040000
group.long 0x0++0x3B
line.long 0x0 "PWM_CLKPSC,PWM Clock Pre-scale Register"
hexmask.long.byte 0x0 16.--23. 1. "CLKPSC45,Clock Prescaler 4 For PWM Counter 4 And 5\nClock input is divided by (CLKPSC45 + 1) before it is fed to the corresponding PWM counter.\n"
hexmask.long.byte 0x0 8.--15. 1. "CLKPSC23,Clock Prescaler 2 For PWM Counter 2 And 3\nClock input is divided by (CLKPSC23 + 1) before it is fed to the corresponding PWM counter.\n"
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hexmask.long.byte 0x0 0.--7. 1. "CLKPSC01,Clock Prescaler 0 For PWM Counter 0 And 1\nClock input is divided by (CLKPSC01 + 1) before it is fed to the corresponding PWM counter.\n"
line.long 0x4 "PWM_CLKDIV,PWM Clock Select Register"
bitfld.long 0x4 20.--22. "CLKDIV5,Counter 5 Clock Divider Selection\nSelect clock input for PWM counter.\n" "0: Clock input / (CLKPSC45/2),1: Clock input / (CLKPSC45/4),?,?,?,?,?,?"
bitfld.long 0x4 16.--18. "CLKDIV4,Counter 4 Clock Divider Selection\nSelect clock input for PWM counter.\n" "0: Clock input / (CLKPSC45/2),1: Clock input / (CLKPSC45/4),?,?,?,?,?,?"
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bitfld.long 0x4 12.--14. "CLKDIV3,Counter 3 Clock Divider Selection\nSelect clock input for PWM counter.\n" "0: Clock input / (CLKPSC23/2),1: Clock input / (CLKPSC23/4),?,?,?,?,?,?"
bitfld.long 0x4 8.--10. "CLKDIV2,Counter 2 Clock Divider Selection\nSelect clock input for PWM counter.\n" "0: Clock input / (CLKPSC23/2),1: Clock input / (CLKPSC23/4),?,?,?,?,?,?"
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bitfld.long 0x4 4.--6. "CLKDIV1,Counter 1 Clock Divider Selection\nSelect clock input for PWM counter.\n" "0: Clock input / (CLKPSC01/2),1: Clock input / (CLKPSC01/4),?,?,?,?,?,?"
bitfld.long 0x4 0.--2. "CLKDIV0,Counter 0 Clock Divider Selection\nSelect clock input for PWM counter.\n" "0: Clock input / (CLKPSC01/2),1: Clock input / (CLKPSC01/4),?,?,?,?,?,?"
line.long 0x8 "PWM_CTL,PWM Control Register"
bitfld.long 0x8 31. "CNTTYPE,PWM Counter-aligned Type Select Bit\n" "0: Edge-aligned type,1: Center-aligned type"
bitfld.long 0x8 30. "GROUPEN,Group Function Enable Bit\n" "0: The signals timing of all PWM channels are..,1: Unify the signals timing of PWM0_CH0 PWM0_CH2.."
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bitfld.long 0x8 28.--29. "MODE,PWM Operating Mode Select Bit\n" "0: Independent mode,1: Complementary mode,?,?"
bitfld.long 0x8 27. "CNTCLR,Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware." "0: Do not clear PWM counter,1: All 16-bit PWM counters cleared to 0x0000"
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bitfld.long 0x8 26. "DTCNT45,Dead-time 4 Counter Enable Bit (PWM0_CH4 And PWM0_CH5 Pair For PWMC Group)\nNote: When the dead-time generator is enabled the pair of PWM0_CH4 and PWM0_CH5 becomes a complementary pair for PWMC group." "0: Dead-time 4 generator Disabled,1: Dead-time 4 generator Enabled"
bitfld.long 0x8 25. "DTCNT23,Dead-time 2 Counter Enable Bit (PWM0_CH2 And PWM0_CH3 Pair For PWMB Group)\nNote: When the dead-time generator is enabled the pair of PWM0_CH2 and PWM0_CH3 becomes a complementary pair for PWMB group." "0: Dead-time 2 generator Disabled,1: Dead-time 2 generator Enabled"
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bitfld.long 0x8 24. "DTCNT01,Dead-time 0 Counter Enable Bit (PWM0_CH0 And PWM0_CH1 Pair For PWMA Group)\nNote: When the dead-time generator is enabled the pair of PWM0_CH0 and PWM0_CH1 becomes a complementary pair for PWMA group." "0: Dead-time 0 generator Disabled,1: Dead-time 0 generator Enabled"
bitfld.long 0x8 23. "CNTMODE5,PWM Counter 5 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause PERIOD5 and CMP5 cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 22. "PINV5,PWM0_CH5 Output Inverter Enable Bit\n" "0: PWM0_CH5 output inverter Disabled,1: PWM0_CH5 output inverter Enabled"
bitfld.long 0x8 21. "ASYMEN,Asymmetric Mode In Center-aligned Type \n" "0: Symmetric mode in center-aligned type,1: Asymmetric mode in center-aligned type"
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bitfld.long 0x8 20. "CNTEN5,PWM Counter 5 Enable Start Run\n" "0: Corresponding PWM counter running Stopped,1: Corresponding PWM counter start run Enabled"
bitfld.long 0x8 19. "CNTMODE4,PWM Counter 4 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause PERIOD4 and CMP4 cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 18. "PINV4,PWM0_CH4 Output Inverter Enable Bit\n" "0: PWM0_CH4 output inverter Disabled,1: PWM0_CH4 output inverter Enabled"
bitfld.long 0x8 16. "CNTEN4,PWM Counter 4 Enable Start Run\n" "0: Corresponding PWM counter running Stopped,1: Corresponding PWM counter start run Enabled"
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bitfld.long 0x8 15. "CNTMODE3,PWM Counter 3 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause PERIOD3 and CMP3 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 14. "PINV3,PWM0_CH 3 Output Inverter Enable Bit\n" "0: PWM0_CH3 output inverter Disabled,1: PWM0_CH3 output inverter Enabled"
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bitfld.long 0x8 12. "CNTEN3,PWM Counter 3 Enable Start Run\n" "0: Corresponding PWM counter running Stopped,1: Corresponding PWM counter start run Enabled"
bitfld.long 0x8 11. "CNTMODE2,PWM Counter 2 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause PERIOD2 and CMP2 cleared." "0: One-shot mode,1: Auto-reload mode"
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bitfld.long 0x8 10. "PINV2,PWM0_CH2 Output Inverter Enable Bit\n" "0: PWM0_CH2 output inverter Disabled,1: PWM0_CH2 output inverter Enabled"
bitfld.long 0x8 8. "CNTEN2,PWM Counter 2 Enable Start Run\n" "0: Corresponding PWM counter running Stopped,1: Corresponding PWM counter start run Enabled"
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bitfld.long 0x8 7. "CNTMODE1,PWM Counter 1 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause PERIOD1 and CMP1 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 6. "PINV1,PWM0_CH1 Output Inverter Enable Bit\n" "0: PWM0_CH1 output inverter Disable,1: PWM0_CH1 output inverter Enable"
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bitfld.long 0x8 5. "HCUPDT,Half Cycle Update Enable for Center-aligned Type\n" "0: Disable half cycle update PERIOD CMP,1: Enable half cycle update PERIOD CMP"
bitfld.long 0x8 4. "CNTEN1,PWM Counter 1 Enable/Disable Start Run\n" "0: Corresponding PWM counter running Stopped,1: Corresponding PWM counter start run Enabled"
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bitfld.long 0x8 3. "CNTMODE0,PWM Counter 0 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit it will cause PERIOD0 and CMP0 cleared." "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x8 2. "PINV0,PWM0_CH0 Output Inverter Enable Bit\n" "0: PWM0_CH0 output inverter Disabled,1: PWM0_CH0 output inverter Enabled"
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bitfld.long 0x8 1. "DBGTRIOFF,Disable PWM Output Tri-state Under Debug Mode (Available In DEBUG Mode Only)\n" "0: Safe mode: The counter is frozen and PWM outputs..,1: Normal mode: The counter continues to operate.."
bitfld.long 0x8 0. "CNTEN0,PWM Counter 0 Enable Start Run\n" "0: Corresponding PWM counter running Stopped,1: Corresponding PWM counter start run Enabled"
line.long 0xC "PWM_PERIOD0,PWM Counter Period Register 0"
hexmask.long.word 0xC 0.--15. 1. "PERIODn,PWM Counter Period Value\nPERIODn determines the PWM counter period.\nEdge-aligned type:\nNote: Any write to PERIODn will take effect in the next PWM cycle."
line.long 0x10 "PWM_PERIOD1,PWM Counter Period Register 1"
hexmask.long.word 0x10 0.--15. 1. "PERIODn,PWM Counter Period Value\nPERIODn determines the PWM counter period.\nEdge-aligned type:\nNote: Any write to PERIODn will take effect in the next PWM cycle."
line.long 0x14 "PWM_PERIOD2,PWM Counter Period Register 2"
hexmask.long.word 0x14 0.--15. 1. "PERIODn,PWM Counter Period Value\nPERIODn determines the PWM counter period.\nEdge-aligned type:\nNote: Any write to PERIODn will take effect in the next PWM cycle."
line.long 0x18 "PWM_PERIOD3,PWM Counter Period Register 3"
hexmask.long.word 0x18 0.--15. 1. "PERIODn,PWM Counter Period Value\nPERIODn determines the PWM counter period.\nEdge-aligned type:\nNote: Any write to PERIODn will take effect in the next PWM cycle."
line.long 0x1C "PWM_PERIOD4,PWM Counter Period Register 4"
hexmask.long.word 0x1C 0.--15. 1. "PERIODn,PWM Counter Period Value\nPERIODn determines the PWM counter period.\nEdge-aligned type:\nNote: Any write to PERIODn will take effect in the next PWM cycle."
line.long 0x20 "PWM_PERIOD5,PWM Counter Period Register 5"
hexmask.long.word 0x20 0.--15. 1. "PERIODn,PWM Counter Period Value\nPERIODn determines the PWM counter period.\nEdge-aligned type:\nNote: Any write to PERIODn will take effect in the next PWM cycle."
line.long 0x24 "PWM_CMPDAT0,PWM Comparator Register 0"
hexmask.long.word 0x24 16.--31. 1. "CMPDn,PWM Comparator Register For Down Counter In Asymmetric Mode\nOthers: PWM output is always high."
hexmask.long.word 0x24 0.--15. 1. "CMPn,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned type:\nNote: Any write to CMPn will take effect in the next PWM cycle."
line.long 0x28 "PWM_CMPDAT1,PWM Comparator Register 1"
hexmask.long.word 0x28 16.--31. 1. "CMPDn,PWM Comparator Register For Down Counter In Asymmetric Mode\nOthers: PWM output is always high."
hexmask.long.word 0x28 0.--15. 1. "CMPn,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned type:\nNote: Any write to CMPn will take effect in the next PWM cycle."
line.long 0x2C "PWM_CMPDAT2,PWM Comparator Register 2"
hexmask.long.word 0x2C 16.--31. 1. "CMPDn,PWM Comparator Register For Down Counter In Asymmetric Mode\nOthers: PWM output is always high."
hexmask.long.word 0x2C 0.--15. 1. "CMPn,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned type:\nNote: Any write to CMPn will take effect in the next PWM cycle."
line.long 0x30 "PWM_CMPDAT3,PWM Comparator Register 3"
hexmask.long.word 0x30 16.--31. 1. "CMPDn,PWM Comparator Register For Down Counter In Asymmetric Mode\nOthers: PWM output is always high."
hexmask.long.word 0x30 0.--15. 1. "CMPn,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned type:\nNote: Any write to CMPn will take effect in the next PWM cycle."
line.long 0x34 "PWM_CMPDAT4,PWM Comparator Register 4"
hexmask.long.word 0x34 16.--31. 1. "CMPDn,PWM Comparator Register For Down Counter In Asymmetric Mode\nOthers: PWM output is always high."
hexmask.long.word 0x34 0.--15. 1. "CMPn,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned type:\nNote: Any write to CMPn will take effect in the next PWM cycle."
line.long 0x38 "PWM_CMPDAT5,PWM Comparator Register 5"
hexmask.long.word 0x38 16.--31. 1. "CMPDn,PWM Comparator Register For Down Counter In Asymmetric Mode\nOthers: PWM output is always high."
hexmask.long.word 0x38 0.--15. 1. "CMPn,PWM Comparator Register\nCMP determines the PWM duty.\nEdge-aligned type:\nNote: Any write to CMPn will take effect in the next PWM cycle."
group.long 0x54++0x3B
line.long 0x0 "PWM_INTEN,PWM Interrupt Enable Register"
bitfld.long 0x0 29. "CMPUIEN5,PWM Compare Up Interrupt Enable Bit\n" "0: PWM0_CHn compare up interrupt Disabled,1: PWM0_CHn compare up interrupt Enabled"
bitfld.long 0x0 28. "CMPUIEN4,PWM Compare Up Interrupt Enable Bit\n" "0: PWM0_CHn compare up interrupt Disabled,1: PWM0_CHn compare up interrupt Enabled"
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bitfld.long 0x0 27. "CMPUIEN3,PWM Compare Up Interrupt Enable Bit\n" "0: PWM0_CHn compare up interrupt Disabled,1: PWM0_CHn compare up interrupt Enabled"
bitfld.long 0x0 26. "CMPUIEN2,PWM Compare Up Interrupt Enable Bit\n" "0: PWM0_CHn compare up interrupt Disabled,1: PWM0_CHn compare up interrupt Enabled"
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bitfld.long 0x0 25. "CMPUIEN1,PWM Compare Up Interrupt Enable Bit\n" "0: PWM0_CHn compare up interrupt Disabled,1: PWM0_CHn compare up interrupt Enabled"
bitfld.long 0x0 24. "CMPUIEN0,PWM Compare Up Interrupt Enable Bit\n" "0: PWM0_CHn compare up interrupt Disabled,1: PWM0_CHn compare up interrupt Enabled"
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bitfld.long 0x0 23. "PIEN5,PWM Period Interrupt Enable Bit\n" "0: PWM0_CHn period interrupt Disabled,1: PWM0_CHn period interrupt Enabled"
bitfld.long 0x0 22. "PIEN4,PWM Period Interrupt Enable Bit\n" "0: PWM0_CHn period interrupt Disabled,1: PWM0_CHn period interrupt Enabled"
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bitfld.long 0x0 21. "PIEN3,PWM Period Interrupt Enable Bit\n" "0: PWM0_CHn period interrupt Disabled,1: PWM0_CHn period interrupt Enabled"
bitfld.long 0x0 20. "PIEN2,PWM Period Interrupt Enable Bit\n" "0: PWM0_CHn period interrupt Disabled,1: PWM0_CHn period interrupt Enabled"
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bitfld.long 0x0 19. "PIEN1,PWM Period Interrupt Enable Bit\n" "0: PWM0_CHn period interrupt Disabled,1: PWM0_CHn period interrupt Enabled"
bitfld.long 0x0 18. "PIEN0,PWM Period Interrupt Enable Bit\n" "0: PWM0_CHn period interrupt Disabled,1: PWM0_CHn period interrupt Enabled"
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bitfld.long 0x0 17. "PINTTYPE,PWM Interrupt Type Selection\nNote: This bit is effective when PWM is in center-aligned type only." "0: ZIFn will be set if PWM counter underflows,1: ZIFn will be set if PWM counter matches PERIODn.."
bitfld.long 0x0 16. "BRKIEN,Fault Brake0 And Fault Brake1 Interrupt Enable Bit\n" "0: BRKIF0 and BRKIF1 trigger PWM interrupt Disabled,1: BRKIF0 and BRKIF1 trigger PWM interrupt Enabled"
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bitfld.long 0x0 13. "CMPDIEN5,PWM Compare Down Interrupt Enable Bit\n" "0: PWM0_CHn compare down interrupt Disabled,1: PWM0_CHn compare down interrupt Enabled"
bitfld.long 0x0 12. "CMPDIEN4,PWM Compare Down Interrupt Enable Bit\n" "0: PWM0_CHn compare down interrupt Disabled,1: PWM0_CHn compare down interrupt Enabled"
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bitfld.long 0x0 11. "CMPDIEN3,PWM Compare Down Interrupt Enable Bit\n" "0: PWM0_CHn compare down interrupt Disabled,1: PWM0_CHn compare down interrupt Enabled"
bitfld.long 0x0 10. "CMPDIEN2,PWM Compare Down Interrupt Enable Bit\n" "0: PWM0_CHn compare down interrupt Disabled,1: PWM0_CHn compare down interrupt Enabled"
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bitfld.long 0x0 9. "CMPDIEN1,PWM Compare Down Interrupt Enable Bit\n" "0: PWM0_CHn compare down interrupt Disabled,1: PWM0_CHn compare down interrupt Enabled"
bitfld.long 0x0 8. "CMPDIEN0,PWM Compare Down Interrupt Enable Bit\n" "0: PWM0_CHn compare down interrupt Disabled,1: PWM0_CHn compare down interrupt Enabled"
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bitfld.long 0x0 5. "ZIEN5,PWM Zero Point Interrupt Enable Bit\n" "0: PWM0_CHn zero point interrupt Disabled,1: PWM0_CHn zero point interrupt Enabled"
bitfld.long 0x0 4. "ZIEN4,PWM Zero Point Interrupt Enable Bit\n" "0: PWM0_CHn zero point interrupt Disabled,1: PWM0_CHn zero point interrupt Enabled"
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bitfld.long 0x0 3. "ZIEN3,PWM Zero Point Interrupt Enable Bit\n" "0: PWM0_CHn zero point interrupt Disabled,1: PWM0_CHn zero point interrupt Enabled"
bitfld.long 0x0 2. "ZIEN2,PWM Zero Point Interrupt Enable Bit\n" "0: PWM0_CHn zero point interrupt Disabled,1: PWM0_CHn zero point interrupt Enabled"
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bitfld.long 0x0 1. "ZIEN1,PWM Zero Point Interrupt Enable Bit\n" "0: PWM0_CHn zero point interrupt Disabled,1: PWM0_CHn zero point interrupt Enabled"
bitfld.long 0x0 0. "ZIEN0,PWM Zero Point Interrupt Enable Bit\n" "0: PWM0_CHn zero point interrupt Disabled,1: PWM0_CHn zero point interrupt Enabled"
line.long 0x4 "PWM_INTSTS,PWM Interrupt Status Register"
bitfld.long 0x4 29. "CMPUIF5,PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 28. "CMPUIF4,PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 27. "CMPUIF3,PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 26. "CMPUIF2,PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 25. "CMPUIF1,PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 24. "CMPUIF0,PWM Compare Up Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter up count reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 23. "PIF5,PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 22. "PIF4,PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 21. "PIF3,PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 20. "PIF2,PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 19. "PIF1,PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 18. "PIF0,PWM Period Interrupt Flag\nFlag is set by hardware when PWM0_CHn counter reaches PERIODn. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 17. "BRKIF1,PWM Brake1 Flag\nNote: This bit can be cleared by software writing 1." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.."
bitfld.long 0x4 16. "BRKIF0,PWM Brake0 Flag\nNote: This bit can be cleared by software writing 1." "0: PWM Brake does not recognize a falling signal at..,1: When PWM Brake detects a falling signal at pin.."
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bitfld.long 0x4 13. "CMPDIF5,PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 12. "CMPDIF4,PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 11. "CMPDIF3,PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 10. "CMPDIF2,PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 9. "CMPDIF1,PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 8. "CMPDIF0,PWM Compare Down Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches CMPn. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 5. "ZIF5,PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 4. "ZIF4,PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 3. "ZIF3,PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 2. "ZIF2,PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x4 1. "ZIF1,PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x4 0. "ZIF0,PWM Zero Point Interrupt Flag\nFlag is set by hardware when PWMn counter downcount reaches zero point. \nNote: This bit can be cleared by software writing 1." "0,1"
line.long 0x8 "PWM_POEN,PWM Output Enable Register"
bitfld.long 0x8 5. "POEN5,PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel n output to pin Disabled,1: PWM channel n output to pin Enabled"
bitfld.long 0x8 4. "POEN4,PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel n output to pin Disabled,1: PWM channel n output to pin Enabled"
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bitfld.long 0x8 3. "POEN3,PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel n output to pin Disabled,1: PWM channel n output to pin Enabled"
bitfld.long 0x8 2. "POEN2,PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel n output to pin Disabled,1: PWM channel n output to pin Enabled"
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bitfld.long 0x8 1. "POEN1,PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel n output to pin Disabled,1: PWM channel n output to pin Enabled"
bitfld.long 0x8 0. "POEN0,PWM Output Enable Bits\nNote: The corresponding GPIO pin must be switched to PWM function." "0: PWM channel n output to pin Disabled,1: PWM channel n output to pin Enabled"
line.long 0xC "PWM_BRKCTL,PWM Fault Brake Control Register"
bitfld.long 0xC 31. "D7BKOD,Channel 7 Brake Output Data Select Bit\n" "0: Channel 7 output low when fault brake conditions..,1: Channel 7 output high when fault brake.."
bitfld.long 0xC 30. "D6BKOD,Channel 6 Brake Output Data Select Bit\n" "0: Channel 6 output low when fault brake conditions..,1: Channel 6 output high when fault brake.."
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bitfld.long 0xC 29. "BKOD5,PWM Brake Output Data Select Bits\n" "0: PWM channel n output low when fault brake..,1: PWM channel n output high when fault brake.."
bitfld.long 0xC 28. "BKOD4,PWM Brake Output Data Select Bits\n" "0: PWM channel n output low when fault brake..,1: PWM channel n output high when fault brake.."
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bitfld.long 0xC 27. "BKOD3,PWM Brake Output Data Select Bits\n" "0: PWM channel n output low when fault brake..,1: PWM channel n output high when fault brake.."
bitfld.long 0xC 26. "BKOD2,PWM Brake Output Data Select Bits\n" "0: PWM channel n output low when fault brake..,1: PWM channel n output high when fault brake.."
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bitfld.long 0xC 25. "BKOD1,PWM Brake Output Data Select Bits\n" "0: PWM channel n output low when fault brake..,1: PWM channel n output high when fault brake.."
bitfld.long 0xC 24. "BKOD0,PWM Brake Output Data Select Bits\n" "0: PWM channel n output low when fault brake..,1: PWM channel n output high when fault brake.."
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bitfld.long 0xC 9. "SWBRK,Software Brake\n" "0: Disable PWM Software brake and back to normal..,1: Assert PWM Brake immediately"
bitfld.long 0xC 8. "BRKACT,PWM Brake Action Type\n" "0: PWM counter stop when brake is asserted,1: PWM counter keep going when brake is asserted"
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bitfld.long 0xC 7. "BRKSTS,PWM Fault Brake Event Status Flag\nNote: This bit can be cleared by software writing 1 and must be cleared before restarting the PWM counter." "0: PWM output initial state when fault brake..,1: PWM output fault brake state when fault brake.."
bitfld.long 0xC 3. "BRK1SEL,BKP0 Fault Brake Function Source Select Bit\n" "0: EINT0 as one brake source in BKP0,1: CPO1 as one brake source in BKP0"
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bitfld.long 0xC 2. "BRK0SEL,BKP1 Fault Brake Function Source Select Bit\n" "0: EINT1 as one brake source in BKP1,1: CPO0 as one brake source in BKP1"
bitfld.long 0xC 1. "BRK1EN,Enable BKP1 Pin Trigger Fault Brake Function 1\n" "0: Disabling BKP1 pin can trigger brake function 1..,1: Enabling a falling at BKP1 pin can trigger brake.."
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bitfld.long 0xC 0. "BRK0EN,Enable BKP0 Pin Trigger Fault Brake Function 0\n" "0: Disabling BKP0 pin can trigger brake function 0..,1: Enabling a falling at BKP0 pin can trigger brake.."
line.long 0x10 "PWM_DTCTL,PWM Dead-time Control Register"
hexmask.long.byte 0x10 16.--23. 1. "DTI45,Dead-time Interval Register For Pair Of Channel4 And Channel5 (PWM0_CH4 And PWM0_CH5 Pair)\nThese 8 bits determine dead-time length.\nThe unit time of dead-time length is received from corresponding PWM_CLKDIV bits."
hexmask.long.byte 0x10 8.--15. 1. "DTI23,Dead-time Interval Register For Pair Of Channel2 And Channel3 (PWM0_CH2 And PWM0_CH3 Pair)\nThese 8 bits determine dead-time length.\nThe unit time of dead-time length is received from corresponding PWM_CLKDIV bits."
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hexmask.long.byte 0x10 0.--7. 1. "DTI01,Dead-time Interval Register For Pair Of Channel0 And Channel1 (PWM0_CH0 And PWM0_CH1 Pair)\nThese 8 bits determine dead-time length.\nThe unit time of dead-time length is received from corresponding PWM_CLKDIV bits."
line.long 0x14 "PWM_ADCTCTL0,PWM Trigger Control Register 0"
bitfld.long 0x14 27. "ZPTRGEN3,Channel 3 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching 0\nNote: This bit is valid for both center-aligned type and edged aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x14 26. "CDTRGEN3,Channel 3 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching CMP3 in down-count direction\nNote: This bit is valid for both center-aligned type and edged aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
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bitfld.long 0x14 25. "CPTRGEN3,Channel 3 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching PERIOD3\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged aligned type setting this bit is.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x14 24. "CUTRGEN3,Channel 3 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel3's counter matching CMP3 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged aligned type setting.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
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bitfld.long 0x14 19. "ZPTRGEN2,Channel 2 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x14 18. "CDTRGEN2,Channel 2 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching CMP2 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
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bitfld.long 0x14 17. "CPTRGEN2,Channel 2 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching PERIOD2\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type setting this bit is.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x14 16. "CUTRGEN2,Channel 2 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel2's counter matching CMP2 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type setting.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
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bitfld.long 0x14 11. "ZPTRGEN1,Channel 1 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function While channel1's Counter Matching 0 \nNote: This bit is valid for both center-aligned type and edged-aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x14 10. "CDTRGEN1,Channel 1 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel1's counter matching CMP1 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
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bitfld.long 0x14 9. "CPTRGEN1,Channel 1 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel1's counter matching PERIOD1\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type setting this bit is.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x14 8. "CUTRGEN1,Channel 1 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel1's counter matching CMP1 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type setting.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
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bitfld.long 0x14 3. "ZPTRGEN0,Channel 0 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel0's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x14 2. "CDTRGEN0,Channel 0 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel0's counter matching CMP0 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
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bitfld.long 0x14 1. "CPTRGEN0,Channel 0 Center Point Trigger ADC Enable Bit\nEnable PWM Trigger ADC Function While channel0's Counter Matching PERIOD0\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type setting this bit is.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x14 0. "CUTRGEN0,Channel 0 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel0's counter matching CMP0 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type setting.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
line.long 0x18 "PWM_ADCTCTL1,PWM Trigger Control Register 1"
bitfld.long 0x18 11. "ZPTRGEN5,Channel 5 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x18 10. "CDTRGEN5,Channel 5 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching CMP5 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
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bitfld.long 0x18 9. "CPTRGEN5,Channel 5 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching PERIOD5\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type setting this bit is.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x18 8. "CUTRGEN5,Channel 5 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel5's counter matching CMP5 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type setting.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
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bitfld.long 0x18 3. "ZPTRGEN4,Channel 4 Zero Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching 0\nNote: This bit is valid for both center-aligned type and edged-aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x18 2. "CDTRGEN4,Channel 4 Compare Down Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching CMP4 in down-count direction\nNote: This bit is valid for both center-aligned type and edged-aligned type." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
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bitfld.long 0x18 1. "CPTRGEN4,Channel 4 Center Point Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching PERIOD4\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type setting this bit is.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
bitfld.long 0x18 0. "CUTRGEN4,Channel 4 Compare Up Trigger ADC Enable Bit\nEnable PWM trigger ADC function while channel4's counter matching CMP4 in up-count direction\nNote: This bit is only valid for PWM in center-aligned type. When PWM is in edged-aligned type setting.." "0: PWM condition trigger ADC function Disabled,1: PWM condition trigger ADC function Enabled"
line.long 0x1C "PWM_ADCTSTS0,PWM Trigger Status Register 0"
bitfld.long 0x1C 27. "ZPTRGF3,Channel 3 Zero Point Trigger ADC Flag\nWhen the channel3's counter is counting to zero point this bit will be set for trigger ADC.\nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x1C 26. "CDTRGF3,Channel 3 Compare Down Trigger ADC Flag\nWhen the channel3's counter is counting down to CMP3 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x1C 25. "CPTRGF3,Channel 3 Center Point Trigger ADC Flag\nWhen the channel3's counter is counting to PERIOD3 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x1C 24. "CUTRGF3,Channel 3 Compare Up Trigger ADC Flag\nWhen the channel3's counter is counting up to CMP3 this bit will be set for trigger ADC.\nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x1C 19. "ZPTRGF2,Channel 2 Zero Point Trigger ADC Enable Bit\nWhen the channel2's counter is counting to zero point this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x1C 18. "CDTRGF2,Channel 2 Compare Down Trigger ADC Flag\nWhen the channel2's counter is counting down to CMP2 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x1C 17. "CPTRGF2,Channel 2 Center Point Trigger ADC Flag\nWhen the channel2's counter is counting to PERIOD2 this bit will be set for trigger ADC. Note: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x1C 16. "CUTRGF2,Channel 2 Compare Up Trigger ADC Flag\nWhen the channel2's counter is counting up to CMP2 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x1C 11. "ZPTRGF1,Channel 1 Zero Point Trigger ADC Flag\nWhen the channel1's counter is counting to zero point this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x1C 10. "CDTRGF1,Channel 1 Compare Down Trigger ADC Flag\nWhen the channel1's counter is counting down to CMP1 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x1C 9. "CPTRGF1,Channel 1 Center Point Trigger ADC Flag\nWhen the channel1's counter is counting to PERIOD1 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x1C 8. "CUTRGF1,Channel 1 Compare Up Trigger ADC Flag\nWhen the channel1's counter is counting up to CMP1 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x1C 3. "ZPTRGF0,Channel 0 Zero Point Trigger ADC Flag\nWhen the channel0's counter is counting to zero point this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x1C 2. "CDTRGF0,Channel 0 Compare Down Trigger ADC Flag\nWhen the channel0's counter is counting down to CMP0 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x1C 1. "CPTRGF0,Channel 0 Center Point Trigger ADC Flag\nWhen the channel0's counter is counting to PERIOD0 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x1C 0. "CUTRGF0,Channel 0 Compare Up Trigger ADC Flag\nWhen the channel0's counter is counting up to CMP0 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
line.long 0x20 "PWM_ADCTSTS1,PWM Trigger Status Register 1"
bitfld.long 0x20 11. "ZPTRGF5,Channel 5 Zero Point Trigger ADC Flag\nWhen the channel5's counter is counting to zero point this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x20 10. "CDTRGF5,Channel 5 Compare Down Trigger ADC Flag\nWhen the channel5's counter is counting down to CMP5 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x20 9. "CPTRGF5,Channel 5 Center Point Trigger ADC Flag\nWhen the channel5's counter is counting to PERIOD5 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x20 8. "CUTRGF5,Channel 5 Compare Up Trigger ADC Flag\nWhen the channel5's counter is counting up to CMP5 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x20 3. "ZPTRGF4,Channel 4 Zero Point Trigger ADC Flag\nWhen the channel4's counter is counting to zero point this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x20 2. "CDTRGF4,Channel 4 Compare Down Trigger ADC Flag\nWhen the channel4's counter is counting down to CMP4 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
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bitfld.long 0x20 1. "CPTRGF4,Channel 4 Center Point Trigger ADC Flag\nWhen the channel4's counter is counting to PERIOD4 this bit will be set for trigger ADC. \nNote: This bit can be cleared by software writing 1." "0,1"
bitfld.long 0x20 0. "CUTRGF4,Channel 4 Compare Up Trigger ADC Flag\nWhen the channel4's counter is counting up to CMP4 this bit will be set for trigger ADC. Note: This bit can be cleared by software writing 1." "0,1"
line.long 0x24 "PWM_PHCHG,PWM Phase Changed Register"
bitfld.long 0x24 31. "ACMP0TEN,ACMP0 Trigger PWM Function Enable Bit\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set." "0: ACMP0 trigger PWM function Disabled,1: ACMP0 trigger PWM function Enabled"
bitfld.long 0x24 30. "TMR0TEN,TIMER0 Trigger PWM Function Enable Bit\nWhen this bit is set TIMER0 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n" "0: TIMER0 trigger PWM function Disabled,1: TIMER0 trigger PWM function Enabled"
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bitfld.long 0x24 28.--29. "A0POSSEL,ACMP0 Positive Input Source Select Bits\n" "0: Select P1.5 as the input of ACMP0,1: Select P1.0 as the input of ACMP0,?,?"
bitfld.long 0x24 27. "AOFFEN30,ACMP0 Trigger Channel 3 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH3 one period cycle output low Disabled,1: PWM0_CH3 one period cycle output low Enabled"
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bitfld.long 0x24 26. "AOFFEN20,ACMP0 Trigger Channel 2 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH2 one period cycle output low Disabled,1: PWM0_CH2 one period cycle output low Enabled"
bitfld.long 0x24 25. "AOFFEN10,ACMP0 Trigger Channel 1 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH1 one period cycle output low Disabled,1: PWM0_CH1 one period cycle output low Enabled"
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bitfld.long 0x24 24. "AOFFEN00,ACMP0 Trigger Channel 0 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH0 one period cycle output low Disabled,1: PWM0_CH0 one period cycle output low Enabled"
bitfld.long 0x24 23. "ACMP1TEN,ACMP1 Trigger Function Enable Bit\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set." "0: ACMP1 trigger PWM function Disabled,1: ACMP1 trigger PWM function Enabled"
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bitfld.long 0x24 22. "TMR1TEN,TIMER1 Trigger PWM Function Enable Bit\nWhen this bit is set TIMER1 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n" "0: TIMER1 trigger PWM function Disabled,1: TIMER1 trigger PWM function Enabled"
bitfld.long 0x24 20.--21. "A1POSSEL,ACMP1 Positive Input Source Select Bits\n" "0: Select P3.1 as the input of ACMP1,1: Select P3.2 as the input of ACMP1,?,?"
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bitfld.long 0x24 19. "AOFFEN31,ACMP1 Trigger Channel 3 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH3 one period cycle output low Disabled,1: PWM0_CH3 one period cycle output low Enabled"
bitfld.long 0x24 18. "AOFFEN21,ACMP1 Trigger Channel 2 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH2 one period cycle output low Disabled,1: PWM0_CH2 one period cycle output low Enabled"
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bitfld.long 0x24 17. "AOFFEN11,ACMP1 Trigger Channel 1 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH1 one period cycle output low Disabled,1: PWM0_CH1 one period cycle output low Enabled"
bitfld.long 0x24 16. "AOFFEN01,ACMP1 Trigger Channel 0 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH0 one period cycle output low Disabled,1: PWM0_CH0 one period cycle output low Enabled"
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bitfld.long 0x24 15. "AUTOCLR1,Hardware Auto Clear ACMP1TEN \n" "0: Hardware will auto clear ACMP1TEN when ACMP1..,1: Hardware will not auto clear ACMP1TEN when ACMP1.."
bitfld.long 0x24 14. "AUTOCLR0,Hardware Auto Clear ACMP0TEN\n" "0: Hardware will auto clear ACMP0TEN when ACMP0..,1: Hardware will not auto clear ACMP0TEN when ACMP0.."
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bitfld.long 0x24 13. "MSKEN5,PWMn Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
bitfld.long 0x24 12. "MSKEN4,PWMn Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
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bitfld.long 0x24 11. "MSKEN3,PWMn Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
bitfld.long 0x24 10. "MSKEN2,PWMn Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
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bitfld.long 0x24 9. "MSKEN1,PWMn Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
bitfld.long 0x24 8. "MSKEN0,PWMn Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
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bitfld.long 0x24 7. "MSKDAT7,PWM0_CH7 (GPIO P0.0) Mask Data \nWhen MASKEND7 Is 1 channel 7's output level is MSKDAT7.\n" "0: PWM0_CH7 output low level,1: PWM0_CH7 output high level"
bitfld.long 0x24 6. "MSKDAT6,PWM0_CH6 (GPIO P0.1) Mask Data \nWhen MASKEND6 Is 1 channel 6's output level is MSKDAT6.\n" "0: PWM0_CH6 output low level,1: PWM0_CH6 output high level"
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bitfld.long 0x24 5. "MSKDAT5,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
bitfld.long 0x24 4. "MSKDAT4,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
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bitfld.long 0x24 3. "MSKDAT3,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
bitfld.long 0x24 2. "MSKDAT2,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
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bitfld.long 0x24 1. "MSKDAT1,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
bitfld.long 0x24 0. "MSKDAT0,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
line.long 0x28 "PWM_PHCHGNXT,PWM Next Phase Change Register"
bitfld.long 0x28 31. "ACMP0TEN,ACMP0 Trigger Function Enable Bit\nNote: This bit will be auto cleared when ACMP0 trigger PWM if AUTOCLR0 is set." "0: ACMP0 trigger PWM function Disabled,1: ACMP0 trigger PWM function Enabled"
bitfld.long 0x28 30. "TMR0TEN,TMR0 Trigger PWM Function Enable Bit\nWhen this bit is set TMR0 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n" "0: TMR0 trigger PWM function Disabled,1: TMR0 trigger PWM function Enabled"
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bitfld.long 0x28 28.--29. "A0POSSEL,ACMP0 Positive Input Source Select Bits\n" "0: Select P1.5 as the input of ACMP0,1: Select P1.0 as the input of ACMP0,?,?"
bitfld.long 0x28 27. "AOFFEN30,ACMP0 Trigger Channel 3 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH3 one period cycle output low Disabled,1: PWM0_CH3 one period cycle output low Enabled"
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bitfld.long 0x28 26. "AOFFEN20,ACMP0 Trigger Channel 2 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH2 one period cycle output low Disabled,1: PWM0_CH2 one period cycle output low Enabled"
bitfld.long 0x28 25. "AOFFEN10,ACMP0 Trigger Channel 1 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH1 one period cycle output low Disabled,1: PWM0_CH1 one period cycle output low Enabled"
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bitfld.long 0x28 24. "AOFFEN00,ACMP0 Trigger Channel 0 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP0 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH0 one period cycle output low Disabled,1: PWM0_CH0 one period cycle output low Enabled"
bitfld.long 0x28 23. "ACMP1TEN,ACMP1 Trigger Function Enable Bit\nNote: This bit will be auto cleared when ACMP1 trigger PWM if AUTOCLR1 is set." "0: ACMP1 trigger PWM function Disabled,1: ACMP1 trigger PWM function Enabled"
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bitfld.long 0x28 22. "TMR1TEN,TMR1 Trigger PWM Function Enable Bit\nWhen this bit is set TMR1 time-out event will update PWM_PHCHG with PHCHG_NXT register.\n" "0: TMR1 trigger PWM function Disabled,1: TMR1 trigger PWM function Enabled"
bitfld.long 0x28 20.--21. "A1POSSEL,ACMP1 Positive Input Source Select Bits\n" "0: Select P3.1 as the input of ACMP1,1: Select P3.2 as the input of ACMP1,?,?"
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bitfld.long 0x28 19. "AOFFEN31,ACMP1 Trigger Channel 3 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 3 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH3 one period cycle output low Disabled,1: PWM0_CH3 one period cycle output low Enabled"
bitfld.long 0x28 18. "AOFFEN21,ACMP1 Trigger Channel 2 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 2 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH2 one period cycle output low Disabled,1: PWM0_CH2 one period cycle output low Enabled"
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bitfld.long 0x28 17. "AOFFEN11,ACMP1 Trigger Channel 1 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 1 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH1 one period cycle output low Disabled,1: PWM0_CH1 one period cycle output low Enabled"
bitfld.long 0x28 16. "AOFFEN01,ACMP1 Trigger Channel 0 One Cycle Output Off Enable Bit\nSetting this bit will force PWM channel 0 to output low lasting for at most one period cycle as long as ACMP1 trigger It; This feature is usually in step motor application.\nNote: This.." "0: PWM0_CH0 one period cycle output low Disabled,1: PWM0_CH0 one period cycle output low Enabled"
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bitfld.long 0x28 15. "AUTOCLR1,Hardware Auto Clear ACMP1TEN \n" "0: Hardware will auto clear ACMP1TEN when ACMP1..,1: Hardware will not auto clear ACMP1TEN when ACMP1.."
bitfld.long 0x28 14. "AUTOCLR0,Hardware Auto Clear ACMP0TEN\n" "0: Hardware will auto clear ACMP0TEN when ACMP0..,1: Hardware will not auto clear ACMP0TEN when ACMP0.."
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bitfld.long 0x28 13. "MSKEN5,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
bitfld.long 0x28 12. "MSKEN4,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
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bitfld.long 0x28 11. "MSKEN3,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
bitfld.long 0x28 10. "MSKEN2,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
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bitfld.long 0x28 9. "MSKEN1,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
bitfld.long 0x28 8. "MSKEN0,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
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bitfld.long 0x28 7. "MSKDAT7,PWM0_CH7 (GPIO P0.0) Mask Data \nWhen MASKEND7 Is 1 channel 7's output level is MSKDAT7.\n" "0: PWM0_CH7 output low level,1: PWM0_CH7 output high level"
bitfld.long 0x28 6. "MSKDAT6,PWM0_CH6 (GPIO P0.1) Mask Data \nWhen MASKEND6 Is 1 channel 6's output level is MSKDAT6.\n" "0: PWM0_CH6 output low level,1: PWM0_CH6 output high level"
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bitfld.long 0x28 5. "MSKDAT5,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
bitfld.long 0x28 4. "MSKDAT4,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
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bitfld.long 0x28 3. "MSKDAT3,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
bitfld.long 0x28 2. "MSKDAT2,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
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bitfld.long 0x28 1. "MSKDAT1,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
bitfld.long 0x28 0. "MSKDAT0,PWM0_CHn Mask Data \nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
line.long 0x2C "PWM_PHCHGMSK,PWM Phase Change Mask Register"
bitfld.long 0x2C 9. "POSCTL1,Positive Input Control For ACMP1\nNote: Register CMP1CR is described in Comparator Controller chapter." "0: The input of ACMP is controlled by CMP1CR,1: The input of ACMP is controlled by CMP1SEL of.."
bitfld.long 0x2C 8. "POSCTL0,Positive Input Control For ACMP0 \nNote: Register CMP0CR is described in Comparator Controller chapter." "0: The input of ACMP is controlled by CMP0CR,1: The input of ACMP is controlled by CMP0SEL of.."
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bitfld.long 0x2C 7. "MASKEND7,PWM0_CH7 (GPIO P0.0) Output Mask Enable Bit\n" "0: Output the original GPIO P0.0,1: Output MSKDAT7 specified in bit 7 of PWM_PHCHG.."
bitfld.long 0x2C 6. "MASKEND6,PWM0_CH6 (GPIO P0.1) Output Mask Enable Bit\n" "0: Output the original GPIO P0.1,1: Output MSKDAT6 specified in bit 6 of PWM_PHCHG.."
line.long 0x30 "PWM_IFA,PWM Period Interrupt Accumulation Control Register"
hexmask.long.byte 0x30 4.--7. 1. "IFCNT,Interrupt Accumulation Counter \nWhen IFAEN is set IFCNT will decrease when every ZIFn flag is set and when IFCNT reach to zero the PWMn interrupt will occurred and IFCNT will reload itself."
bitfld.long 0x30 0. "IFAEN,Interrupt Accumulation Function Enable Bit\n" "0: Interrupt accumulation function Disabled,1: Interrupt accumulation function Enabled"
line.long 0x34 "PWM_PCACTL,PWM Precise Center-aligned Type Control Register"
bitfld.long 0x34 0. "PCAEN,PWM Precise Center-aligned Type Enable Bit\n" "0: Precise center-aligned type Disabled,1: Precise center-aligned type Enabled"
line.long 0x38 "PWM_MSKALIGN,PWM Phase Change Mask Aligned Register"
hexmask.long.byte 0x38 16.--21. 1. "ALIGNn,PWM0_CHn Output Mask Aligned Enable Bit\n"
bitfld.long 0x38 13. "MSKEN5,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
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bitfld.long 0x38 12. "MSKEN4,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
bitfld.long 0x38 11. "MSKEN3,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
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bitfld.long 0x38 10. "MSKEN2,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
bitfld.long 0x38 9. "MSKEN1,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
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bitfld.long 0x38 8. "MSKEN0,PWM Output Mask Enable Bits\n" "0: Output MSKDATn specified in bit n of PWM_PHCHG..,1: Output the original channel n waveform"
bitfld.long 0x38 5. "MSKDAT5,PWM0_CHn Mask Data\nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
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bitfld.long 0x38 4. "MSKDAT4,PWM0_CHn Mask Data\nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
bitfld.long 0x38 3. "MSKDAT3,PWM0_CHn Mask Data\nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
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bitfld.long 0x38 2. "MSKDAT2,PWM0_CHn Mask Data\nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
bitfld.long 0x38 1. "MSKDAT1,PWM0_CHn Mask Data\nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
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bitfld.long 0x38 0. "MSKDAT0,PWM0_CHn Mask Data\nWhen MSKENn is 0 channel n's output level is MSKDATn.\n" "0: PWM0_CHn output low level,1: PWM0_CHn output high level"
tree.end
tree "FMC (Flash Memory Controller)"
base ad:0x5000C000
group.long 0x0++0x13
line.long 0x0 "FMC_ISPCTL,ISP Control Register"
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself.." "0,1"
bitfld.long 0x0 5. "LDUEN,LDROM Update Enable (Write Protect)\nLDROM update enable bit.\n" "0: LDROM cannot be updated,1: LDROM can be updated"
bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\n" "0: CONFIG cannot be updated,1: CONFIG can be updated"
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bitfld.long 0x0 3. "APUEN,APROM Update Enable Bit (Write Protect)\n" "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in APROM"
bitfld.long 0x0 2. "SPUEN,SPROM Update Enable Bit (Write Protect)\n" "0: SPROM cannot be updated,1: SPROM can be updated"
bitfld.long 0x0 1. "BS,Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Booting from APROM,1: Booting from LDROM"
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bitfld.long 0x0 0. "ISPEN,ISP Enable Bit (Write Protect)\nSet this bit to enable the ISP function.\n" "0: ISP function Disabled,1: ISP function Enabled"
line.long 0x4 "FMC_ISPADDR,ISP Address Register"
hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address\nThe Mini58 series is equipped with embedded flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command\nFor CRC32 Checksum Calculation command this field is the.."
line.long 0x8 "FMC_ISPDAT,ISP Data Register"
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.\n"
line.long 0xC "FMC_ISPCMD,ISP Command Register"
hexmask.long.byte 0xC 0.--6. 1. "CMD,ISP CMD\nISP command table is shown below:\nThe other commands are invalid."
line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register"
bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n" "0: ISP operation is finished,1: ISP is progressed"
rgroup.long 0x14++0x3
line.long 0x0 "FMC_DFBA,Data Flash Base Address"
hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1\n"
group.long 0x18++0x3
line.long 0x0 "FMC_FATCTL,Flash Access Time Control Register"
bitfld.long 0x0 4.--6. "FOM,Frequency Optimization Mode (Write Protect)\nThe Mini58 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency.\n" "?,1: Frequency 24MHz,?,?,?,?,?,?"
group.long 0x40++0x3
line.long 0x0 "FMC_ISPSTS,ISP Status Register"
bitfld.long 0x0 31. "SCODE,Security Code Active Flag\nThis bit is set to 1 by hardware when detecting SPROM secured code is active at flash initialization or software writes 1 to this bit to make secured code active; this bit is only cleared by SPROM page erase operation.\n" "0: SPROM secured code is inactive,1: SPROM secured code is active"
hexmask.long.word 0x0 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}"
bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1).." "0,1"
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rbitfld.long 0x0 1.--2. "CBS,Boot Selection Of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.\n" "0: LDROM with IAP mode,1: LDROM without IAP mode,?,?"
rbitfld.long 0x0 0. "ISPBUSY,ISP BUSY (Read Only)\n" "0: ISP operation is finished,1: ISP operation is busy"
tree.end
tree "GPIO (General Purpose I/O)"
base ad:0x50004000
group.long 0x0++0xF
line.long 0x0 "P0_MODE,P0 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P0_DINOFF,P0 Digital Input Path Disable Control"
bitfld.long 0x4 23. "DINOFF7,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "P0_DOUT,P0 Data Output Value"
bitfld.long 0x8 7. "DOUT7,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "P0_DATMSK,P0 Data Output Write Mask"
bitfld.long 0xC 7. "DATMSK7,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x3
line.long 0x0 "P0_PIN,P0 Pin Value"
bitfld.long 0x0 7. "PIN7,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 6. "PIN6,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 4. "PIN4,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 2. "PIN2,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 0. "PIN0,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
group.long 0x14++0xF
line.long 0x0 "P0_DBEN,P0 De-bounce Enable Control"
bitfld.long 0x0 7. "DBEN7,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "P0_INTTYPE,P0 Interrupt Mode Control"
bitfld.long 0x4 7. "TYPE7,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "P0_INTEN,P0 Interrupt Enable Control"
bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "P0_INTSRC,P0 Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
group.long 0x40++0xF
line.long 0x0 "P1_MODE,P1 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P1_DINOFF,P1 Digital Input Path Disable Control"
bitfld.long 0x4 23. "DINOFF7,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "P1_DOUT,P1 Data Output Value"
bitfld.long 0x8 7. "DOUT7,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "P1_DATMSK,P1 Data Output Write Mask"
bitfld.long 0xC 7. "DATMSK7,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x50++0x3
line.long 0x0 "P1_PIN,P1 Pin Value"
bitfld.long 0x0 7. "PIN7,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 6. "PIN6,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 4. "PIN4,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 2. "PIN2,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 0. "PIN0,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
group.long 0x54++0xF
line.long 0x0 "P1_DBEN,P1 De-bounce Enable Control"
bitfld.long 0x0 7. "DBEN7,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "P1_INTTYPE,P1 Interrupt Mode Control"
bitfld.long 0x4 7. "TYPE7,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "P1_INTEN,P1 Interrupt Enable Control"
bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "P1_INTSRC,P1 Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
group.long 0x80++0xF
line.long 0x0 "P2_MODE,P2 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P2_DINOFF,P2 Digital Input Path Disable Control"
bitfld.long 0x4 23. "DINOFF7,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "P2_DOUT,P2 Data Output Value"
bitfld.long 0x8 7. "DOUT7,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "P2_DATMSK,P2 Data Output Write Mask"
bitfld.long 0xC 7. "DATMSK7,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x90++0x3
line.long 0x0 "P2_PIN,P2 Pin Value"
bitfld.long 0x0 7. "PIN7,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 6. "PIN6,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 4. "PIN4,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 2. "PIN2,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 0. "PIN0,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
group.long 0x94++0xF
line.long 0x0 "P2_DBEN,P2 De-bounce Enable Control"
bitfld.long 0x0 7. "DBEN7,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "P2_INTTYPE,P2 Interrupt Mode Control"
bitfld.long 0x4 7. "TYPE7,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "P2_INTEN,P2 Interrupt Enable Control"
bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "P2_INTSRC,P2 Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
group.long 0xC0++0xF
line.long 0x0 "P3_MODE,P3 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P3_DINOFF,P3 Digital Input Path Disable Control"
bitfld.long 0x4 23. "DINOFF7,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "P3_DOUT,P3 Data Output Value"
bitfld.long 0x8 7. "DOUT7,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "P3_DATMSK,P3 Data Output Write Mask"
bitfld.long 0xC 7. "DATMSK7,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0xD0++0x3
line.long 0x0 "P3_PIN,P3 Pin Value"
bitfld.long 0x0 7. "PIN7,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 6. "PIN6,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 4. "PIN4,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 2. "PIN2,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 0. "PIN0,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
group.long 0xD4++0xF
line.long 0x0 "P3_DBEN,P3 De-bounce Enable Control"
bitfld.long 0x0 7. "DBEN7,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "P3_INTTYPE,P3 Interrupt Mode Control"
bitfld.long 0x4 7. "TYPE7,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "P3_INTEN,P3 Interrupt Enable Control"
bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "P3_INTSRC,P3 Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
group.long 0x100++0xF
line.long 0x0 "P4_MODE,P4 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P4_DINOFF,P4 Digital Input Path Disable Control"
bitfld.long 0x4 23. "DINOFF7,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "P4_DOUT,P4 Data Output Value"
bitfld.long 0x8 7. "DOUT7,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "P4_DATMSK,P4 Data Output Write Mask"
bitfld.long 0xC 7. "DATMSK7,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x110++0x3
line.long 0x0 "P4_PIN,P4 Pin Value"
bitfld.long 0x0 7. "PIN7,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 6. "PIN6,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 4. "PIN4,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 2. "PIN2,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 0. "PIN0,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
group.long 0x114++0xF
line.long 0x0 "P4_DBEN,P4 De-bounce Enable Control"
bitfld.long 0x0 7. "DBEN7,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "P4_INTTYPE,P4 Interrupt Mode Control"
bitfld.long 0x4 7. "TYPE7,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "P4_INTEN,P4 Interrupt Enable Control"
bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "P4_INTSRC,P4 Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
group.long 0x140++0xF
line.long 0x0 "P5_MODE,P5 I/O Mode Control"
bitfld.long 0x0 14.--15. "MODE7,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 12.--13. "MODE6,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 10.--11. "MODE5,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 8.--9. "MODE4,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 6.--7. "MODE3,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 4.--5. "MODE2,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
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bitfld.long 0x0 2.--3. "MODE1,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
bitfld.long 0x0 0.--1. "MODE0,Port 0-5 I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,?"
line.long 0x4 "P5_DINOFF,P5 Digital Input Path Disable Control"
bitfld.long 0x4 23. "DINOFF7,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 22. "DINOFF6,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 20. "DINOFF4,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 18. "DINOFF2,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
bitfld.long 0x4 16. "DINOFF0,Port 0-5 Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
line.long 0x8 "P5_DOUT,P5 Data Output Value"
bitfld.long 0x8 7. "DOUT7,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 6. "DOUT6,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 4. "DOUT4,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 2. "DOUT2,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x8 0. "DOUT0,Port 0-5 Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
line.long 0xC "P5_DATMSK,P5 Data Output Write Mask"
bitfld.long 0xC 7. "DATMSK7,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 6. "DATMSK6,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 4. "DATMSK4,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 2. "DATMSK2,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0xC 0. "DATMSK0,Port 0-5 Pin[N] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x150++0x3
line.long 0x0 "P5_PIN,P5 Pin Value"
bitfld.long 0x0 7. "PIN7,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 6. "PIN6,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 5. "PIN5,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 4. "PIN4,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 3. "PIN3,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 2. "PIN2,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
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bitfld.long 0x0 1. "PIN1,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
bitfld.long 0x0 0. "PIN0,Port 0-5 Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.\nNote: \n" "0,1"
group.long 0x154++0xF
line.long 0x0 "P5_DBEN,P5 De-bounce Enable Control"
bitfld.long 0x0 7. "DBEN7,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 6. "DBEN6,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 4. "DBEN4,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 2. "DBEN2,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x0 0. "DBEN0,Port 0-5 Pin[N] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
line.long 0x4 "P5_INTTYPE,P5 Interrupt Mode Control"
bitfld.long 0x4 7. "TYPE7,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 6. "TYPE6,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 4. "TYPE4,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 2. "TYPE2,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x4 0. "TYPE0,Port 0-5 Pin[N] Edge Or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
line.long 0x8 "P5_INTEN,P5 Interrupt Enable Control"
bitfld.long 0x8 23. "RHIEN7,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 22. "RHIEN6,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 20. "RHIEN4,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 18. "RHIEN2,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
bitfld.long 0x8 16. "RHIEN0,Port 0-5 Pin[N] Rising Edge Or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 6. "FLIEN6,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 4. "FLIEN4,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 2. "FLIEN2,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x8 0. "FLIEN0,Port 0-5 Pin[N] Falling Edge Or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
line.long 0xC "P5_INTSRC,P5 Interrupt Source Flag"
bitfld.long 0xC 15. "INTSRC15,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 14. "INTSRC14,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 13. "INTSRC13,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 12. "INTSRC12,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 11. "INTSRC11,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 10. "INTSRC10,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 9. "INTSRC9,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 8. "INTSRC8,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 7. "INTSRC7,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 6. "INTSRC6,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 5. "INTSRC5,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 4. "INTSRC4,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 3. "INTSRC3,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 2. "INTSRC2,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
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bitfld.long 0xC 1. "INTSRC1,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
bitfld.long 0xC 0. "INTSRC0,Port 0-5 Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending interrupt.\nPx.n.."
group.long 0x180++0x3
line.long 0x0 "GPIO_DBCTL,De-bounce Cycle Control"
bitfld.long 0x0 5. "ICLKON,Interrupt Clock On Mode\nNote: It is recommended to disable this bit to save system power if no special application concern." "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
bitfld.long 0x0 4. "DBCLKSRC,De-bounce Counter Clock Source Selection\n" "0: De-bounce counter clock source is HCLK,1: De-bounce counter clock source is 10 kHz.."
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hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection\n"
group.long 0x200++0x7
line.long 0x0 "P00_PDIO,GPIO P0.0 Pin Data Input/Output"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "P01_PDIO,GPIO P0.1 Pin Data Input/Output"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x210++0x13
line.long 0x0 "P04_PDIO,GPIO P0.4 Pin Data Input/Output"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "P05_PDIO,GPIO P0.5 Pin Data Input/Output"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "P06_PDIO,GPIO P0.6 Pin Data Input/Output"
bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "P07_PDIO,GPIO P0.7 Pin Data Input/Output"
bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "P10_PDIO,GPIO P1.0 Pin Data Input/Output"
bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x228++0xF
line.long 0x0 "P12_PDIO,GPIO P1.2 Pin Data Input/Output"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "P13_PDIO,GPIO P1.3 Pin Data Input/Output"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "P14_PDIO,GPIO P1.4 Pin Data Input/Output"
bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "P15_PDIO,GPIO P1.5 Pin Data Input/Output"
bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x248++0x13
line.long 0x0 "P22_PDIO,GPIO P2.2 Pin Data Input/Output"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "P23_PDIO,GPIO P2.3 Pin Data Input/Output"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "P24_PDIO,GPIO P2.4 Pin Data Input/Output"
bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "P25_PDIO,GPIO P2.5 Pin Data Input/Output"
bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "P26_PDIO,GPIO P2.6 Pin Data Input/Output"
bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x260++0xB
line.long 0x0 "P30_PDIO,GPIO P3.0 Pin Data Input/Output"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "P31_PDIO,GPIO P3.1 Pin Data Input/Output"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "P32_PDIO,GPIO P3.2 Pin Data Input/Output"
bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x270++0xB
line.long 0x0 "P34_PDIO,GPIO P3.4 Pin Data Input/Output"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "P35_PDIO,GPIO P3.5 Pin Data Input/Output"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "P36_PDIO,GPIO P3.6 Pin Data Input/Output"
bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x298++0x1F
line.long 0x0 "P46_PDIO,GPIO P4.6 Pin Data Input/Output"
bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x4 "P47_PDIO,GPIO P4.7 Pin Data Input/Output"
bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x8 "P50_PDIO,GPIO P5.0 Pin Data Input/Output"
bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0xC "P51_PDIO,GPIO P5.1 Pin Data Input/Output"
bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x10 "P52_PDIO,GPIO P5.2 Pin Data Input/Output"
bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x14 "P53_PDIO,GPIO P5.3 Pin Data Input/Output"
bitfld.long 0x14 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x18 "P54_PDIO,GPIO P5.4 Pin Data Input/Output"
bitfld.long 0x18 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
line.long 0x1C "P55_PDIO,GPIO P5.5 Pin Data Input/Output"
bitfld.long 0x1C 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\n" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
tree.end
tree "I2C (I2C Serial Interface Controller)"
base ad:0x0
tree "I2C0"
base ad:0x40020000
group.long 0x0++0xB
line.long 0x0 "I2C_CTL,I2C Control Register"
bitfld.long 0x0 7. "INTEN,Interrupt Enable Bit\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit\n" "0: I2C Controller Disabled,1: I2C Controller Enabled"
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bitfld.long 0x0 5. "STA,I2C START Control Bit\nSet STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free." "0,1"
bitfld.long 0x0 4. "STO,I2C STOP Control Bit\nIn Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode setting STO resets.." "0,1"
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register the SI flag is set by hardware and if bit INTEN (I2C_CTL[7]) is set the I2C interrupt is requested. SI must be cleared by software. This bit can be cleared by software.." "0,1"
bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit\n" "0,1"
line.long 0x4 "I2C_ADDR0,I2C Slave Address Register 0"
hexmask.long.byte 0x4 1.--7. 1. "ADDR,I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x4 0. "GC,General Call Function Control\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x8 "I2C_DAT,I2C DATA Register"
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port."
rgroup.long 0xC++0x3
line.long 0x0 "I2C_STATUS,I2C Status Register"
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status Register\n"
group.long 0x10++0x23
line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock Divided Register\nNote: The minimum value of I2C_CLKDIV is 4."
line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nNote: When the 14-bit time-out counter is enabled it will start counting when SI is cleared. Setting 1 to the SI flag will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 1. "TOCURIEN,Time-out Counter Input Clock Divided By 4\nNote: When enabled the time-out period is extended 4 times." "0: Time-out counter input clock divided by 4 Disabled,1: Time-out counter input clock divided by 4 Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: This bit can be cleared by software writing '1'." "0,1"
line.long 0x8 "I2C_ADDR1,I2C Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "ADDR,I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x8 0. "GC,General Call Function Control\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "I2C_ADDR2,I2C Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0xC 0. "GC,General Call Function Control\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x10 "I2C_ADDR3,I2C Slave Address Register 3"
hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x10 0. "GC,General Call Function Control\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register 0"
hexmask.long.byte 0x14 1.--7. 1. "ADDRMSK,I2C Address Mask Bits\n"
line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register 1"
hexmask.long.byte 0x18 1.--7. 1. "ADDRMSK,I2C Address Mask Bits\n"
line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register 2"
hexmask.long.byte 0x1C 1.--7. 1. "ADDRMSK,I2C Address Mask Bits\n"
line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register 3"
hexmask.long.byte 0x20 1.--7. 1. "ADDRMSK,I2C Address Mask Bits\n"
group.long 0x3C++0x7
line.long 0x0 "I2C_CTL1,I2C Control Register 1"
bitfld.long 0x0 4. "URIEN,I2C Under Run Interrupt Control\nSetting URIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is under run event happened in transmitted buffer.\n" "0: Under run Interrupt Disabled,1: Under run Interrupt Enabled"
bitfld.long 0x0 3. "OVIEN,I2C Overrun Interrupt Control\nSetting OVIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is overrun event in received buffer.\n" "0: Overrun Interrupt Disabled,1: Overrun Interrupt Enabled"
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bitfld.long 0x0 2. "NSTRETCH,No Stretch On The I2C Bus\n" "0: The I2C SCL bus is stretched by hardware if the..,1: The I2C SCL bus is not stretched by hardware if.."
bitfld.long 0x0 1. "TWOLVFIFO,Two-level Buffer Enable Bit\n" "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit\nThe system can be woken up by I2C bus when the system is set into Power mode and the received data matched one of the addresses in Address Register.\nNote: Only I2C0 channel supports wake-up function. This bit is not valid on.." "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
line.long 0x4 "I2C_STATUS1,I2C Status Register 1"
bitfld.long 0x4 4. "URIF,I2C Under Run Status\n" "0,1"
bitfld.long 0x4 3. "OVIF,I2C Overrun Status\n" "0,1"
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bitfld.long 0x4 2. "EMPTY,I2C Two-level Buffer Empty\n" "0,1"
bitfld.long 0x4 1. "FULL,I2C Two-level Buffer Full\n" "0,1"
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1. This bit can be cleared by software writing '1'.\nNote: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel." "0,1"
tree.end
tree "I2C1"
base ad:0x40120000
group.long 0x0++0xB
line.long 0x0 "I2C_CTL,I2C Control Register"
bitfld.long 0x0 7. "INTEN,Interrupt Enable Bit\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit\n" "0: I2C Controller Disabled,1: I2C Controller Enabled"
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bitfld.long 0x0 5. "STA,I2C START Control Bit\nSet STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free." "0,1"
bitfld.long 0x0 4. "STO,I2C STOP Control Bit\nIn Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode setting STO resets.." "0,1"
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register the SI flag is set by hardware and if bit INTEN (I2C_CTL[7]) is set the I2C interrupt is requested. SI must be cleared by software. This bit can be cleared by software.." "0,1"
bitfld.long 0x0 2. "AA,Assert Acknowledge Control Bit\n" "0,1"
line.long 0x4 "I2C_ADDR0,I2C Slave Address Register 0"
hexmask.long.byte 0x4 1.--7. 1. "ADDR,I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x4 0. "GC,General Call Function Control\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x8 "I2C_DAT,I2C DATA Register"
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port."
rgroup.long 0xC++0x3
line.long 0x0 "I2C_STATUS,I2C Status Register"
hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status Register\n"
group.long 0x10++0x23
line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock Divided Register\nNote: The minimum value of I2C_CLKDIV is 4."
line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit\nNote: When the 14-bit time-out counter is enabled it will start counting when SI is cleared. Setting 1 to the SI flag will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 1. "TOCURIEN,Time-out Counter Input Clock Divided By 4\nNote: When enabled the time-out period is extended 4 times." "0: Time-out counter input clock divided by 4 Disabled,1: Time-out counter input clock divided by 4 Enabled"
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bitfld.long 0x4 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: This bit can be cleared by software writing '1'." "0,1"
line.long 0x8 "I2C_ADDR1,I2C Slave Address Register 1"
hexmask.long.byte 0x8 1.--7. 1. "ADDR,I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x8 0. "GC,General Call Function Control\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0xC "I2C_ADDR2,I2C Slave Address Register 2"
hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0xC 0. "GC,General Call Function Control\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x10 "I2C_ADDR3,I2C Slave Address Register 3"
hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Address\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched."
bitfld.long 0x10 0. "GC,General Call Function Control\n" "0: General Call Function Disabled,1: General Call Function Enabled"
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register 0"
hexmask.long.byte 0x14 1.--7. 1. "ADDRMSK,I2C Address Mask Bits\n"
line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register 1"
hexmask.long.byte 0x18 1.--7. 1. "ADDRMSK,I2C Address Mask Bits\n"
line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register 2"
hexmask.long.byte 0x1C 1.--7. 1. "ADDRMSK,I2C Address Mask Bits\n"
line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register 3"
hexmask.long.byte 0x20 1.--7. 1. "ADDRMSK,I2C Address Mask Bits\n"
group.long 0x3C++0x7
line.long 0x0 "I2C_CTL1,I2C Control Register 1"
bitfld.long 0x0 4. "URIEN,I2C Under Run Interrupt Control\nSetting URIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is under run event happened in transmitted buffer.\n" "0: Under run Interrupt Disabled,1: Under run Interrupt Enabled"
bitfld.long 0x0 3. "OVIEN,I2C Overrun Interrupt Control\nSetting OVIEN to 1 will send a interrupt to system when the TWOLVFF bit is enabled and there is overrun event in received buffer.\n" "0: Overrun Interrupt Disabled,1: Overrun Interrupt Enabled"
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bitfld.long 0x0 2. "NSTRETCH,No Stretch On The I2C Bus\n" "0: The I2C SCL bus is stretched by hardware if the..,1: The I2C SCL bus is not stretched by hardware if.."
bitfld.long 0x0 1. "TWOLVFIFO,Two-level Buffer Enable Bit\n" "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
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bitfld.long 0x0 0. "WKEN,Wake-up Enable Bit\nThe system can be woken up by I2C bus when the system is set into Power mode and the received data matched one of the addresses in Address Register.\nNote: Only I2C0 channel supports wake-up function. This bit is not valid on.." "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
line.long 0x4 "I2C_STATUS1,I2C Status Register 1"
bitfld.long 0x4 4. "URIF,I2C Under Run Status\n" "0,1"
bitfld.long 0x4 3. "OVIF,I2C Overrun Status\n" "0,1"
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bitfld.long 0x4 2. "EMPTY,I2C Two-level Buffer Empty\n" "0,1"
bitfld.long 0x4 1. "FULL,I2C Two-level Buffer Full\n" "0,1"
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1. This bit can be cleared by software writing '1'.\nNote: Only I2C0 channel supports wake-up function. This bit is not valid on I2C1 channel." "0,1"
tree.end
tree.end
tree "INT (Interrupt Multiplexer Control Registers)"
base ad:0x50000300
rgroup.long 0x0++0x27
line.long 0x0 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity"
bitfld.long 0x0 0. "BOD_INT,IRQ0 Source Identity\n" "0: IRQ0 source is not from BOD interrupt (BOD_INT),1: IRQ0 source is from BOD interrupt (BOD_INT)"
line.long 0x4 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity"
bitfld.long 0x4 1. "WWDT_INT,IRQ1 Source Identity\n" "0: IRQ1 source is not from window watchdog..,1: IRQ1 source is from window watchdog interrupt.."
bitfld.long 0x4 0. "WDT_INT,IRQ1 Source Identity\n" "0: IRQ1 source is not from watchdog interrupt (WDT..,1: IRQ1 source is from watchdog interrupt (WDT_INT)"
line.long 0x8 "IRQ2_SRC,IRQ2 (EINT0) Interrupt Source Identity"
bitfld.long 0x8 0. "EINT0,IRQ2 Source Identity\n" "0: IRQ2 source is not from external signal..,1: IRQ2 source is from external signal interrupt 0.."
line.long 0xC "IRQ3_SRC,IRQ3 (EINT1) Interrupt Source Identity"
bitfld.long 0xC 0. "EINT1,IRQ3 Source Identity\n" "0: IRQ3 source is not from external signal..,1: IRQ3 source is from external signal interrupt 1.."
line.long 0x10 "IRQ4_SRC,IRQ4 (GP0/1) Interrupt Source Identity"
bitfld.long 0x10 1. "GP1_INT,IRQ4 Source Identity\n" "0: IRQ4 source is not from GP1 interrupt (GP1_INT),1: IRQ4 source is from GP1 interrupt (GP1_INT)"
bitfld.long 0x10 0. "GP0_INT,IRQ4 Source Identity\n" "0: IRQ4 source is not from GP0 interrupt (GP0_INT),1: IRQ4 source is from GP0 interrupt (GP0_INT)"
line.long 0x14 "IRQ5_SRC,IRQ5 (GP2/3/4) Interrupt Source Identity"
bitfld.long 0x14 2. "GP4_INT,IRQ5 Source Identity\n" "0: IRQ5 source is not from GP4 interrupt (GP4_INT),1: IRQ5 source is from GP4 interrupt (GP4_INT)"
bitfld.long 0x14 1. "GP3_INT,IRQ5 Source Identity\n" "0: IRQ5 source is not from GP3 interrupt (GP3_INT),1: IRQ5 source is from GP3 interrupt (GP3_INT)"
newline
bitfld.long 0x14 0. "GP2_INT,IRQ5 Source Identity\n" "0: IRQ5 source is not from GP2 interrupt (GP2_INT),1: IRQ5 source is from GP2 interrupt (GP2_INT)"
line.long 0x18 "IRQ6_SRC,IRQ6 (PWM) Interrupt Source Identity"
bitfld.long 0x18 0. "PWM_INT,IRQ6 Source Identity\n" "0: IRQ6 source is not from PWM interrupt (PWM_INT),1: IRQ6 source is from PWM interrupt (PWM_INT)"
line.long 0x1C "IRQ7_SRC,IRQ7 (BRAKE) Interrupt Source Identity"
bitfld.long 0x1C 0. "BRAKE_INT,IRQ7 Source Identity \n" "0: IRQ7 source is not from Brake interrupt..,1: IRQ7 source is from Brake interrupt (BRAKE_INT)"
line.long 0x20 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity"
bitfld.long 0x20 0. "TMR0_INT,IRQ8 Source Identity \n" "0: IRQ8 source is not from Timer0 interrupt..,1: IRQ8 source is from Timer0 interrupt (TMR0_INT)"
line.long 0x24 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity"
bitfld.long 0x24 0. "TMR1_INT,IRQ9 Source Identity \n" "0: IRQ9 source is not from Timer1 interrupt..,1: IRQ9 source is from Timer1 interrupt (TMR1_INT)"
group.long 0x28++0x7
line.long 0x0 "IRQ10_SRC,Reserved"
line.long 0x4 "IRQ11_SRC,Reserved"
rgroup.long 0x30++0xB
line.long 0x0 "IRQ12_SRC,IRQ12 (UART0) Interrupt Source Identity"
bitfld.long 0x0 0. "UART0_INT,IRQ12 Source Identity\n" "0: IRQ12 source is not from UART0 interrupt..,1: IRQ12 source is from UART0 interrupt (UART0_INT)"
line.long 0x4 "IRQ13_SRC,IRQ13 (UART1) Interrupt Source Identity"
bitfld.long 0x4 0. "UART1_INT,IRQ13 Source Identity\n" "0: IRQ13 source is not from UART1 interrupt..,1: IRQ13 source is from UART1 interrupt (UART1_INT)"
line.long 0x8 "IRQ14_SRC,IRQ14 (SPI) Interrupt Source Identity"
bitfld.long 0x8 0. "SPI_INT,IRQ14 Source Identity\n" "0: IRQ14 source is not from SPI interrupt (SPI_INT),1: IRQ14 source is from SPI interrupt (SPI_INT)"
group.long 0x3C++0x3
line.long 0x0 "IRQ15_SRC,Reserved"
rgroup.long 0x40++0xF
line.long 0x0 "IRQ16_SRC,IRQ16 (GP5) Interrupt Source Identity"
bitfld.long 0x0 0. "GP5_INT,IRQ16 Source Identity\n" "0: IRQ16 source is not from GP5 interrupt (GP5_INT),1: IRQ16 source is from GP5 interrupt (GP5_INT)"
line.long 0x4 "IRQ17_SRC,IRQ17 (HIRC Trim) Interrupt Source Identity"
bitfld.long 0x4 0. "HIRC_TRIM_INT,IRQ17 Source Identity\n" "0: IRQ17 source is not from HIRC trim interrupt..,1: IRQ17 source is from HIRC trim interrupt.."
line.long 0x8 "IRQ18_SRC,IRQ18 (I2C0) Interrupt Source Identity"
bitfld.long 0x8 0. "I2C0_INT,IRQ18 Source Identity\n" "0: IRQ18 source is not from I2C0 interrupt (I2C0_INT),1: IRQ18 source is from I2C0 interrupt (I2C0_INT)"
line.long 0xC "IRQ19_SRC,IRQ19 (I2C1) Interrupt Source Identity"
bitfld.long 0xC 0. "I2C1_INT,IRQ19 Source Identity\n" "0: IRQ19 source is not from I2C1 interrupt (I2C1_INT),1: IRQ19 source is from I2C1 interrupt (I2C1_INT)"
group.long 0x50++0x13
line.long 0x0 "IRQ20_SRC,Reserved"
line.long 0x4 "IRQ21_SRC,Reserved"
line.long 0x8 "IRQ22_SRC,Reserved"
line.long 0xC "IRQ23_SRC,Reserved"
line.long 0x10 "IRQ24_SRC,Reserved"
rgroup.long 0x64++0x3
line.long 0x0 "IRQ25_SRC,IRQ25 (ACMP) Interrupt Source Identity"
bitfld.long 0x0 0. "ACMP_INT,IRQ25 Source Identity\n" "0: IRQ25 source is not from ACMP interrupt (ACMP_INT),1: IRQ25 source is from ACMP interrupt (ACMP_INT)"
group.long 0x68++0x7
line.long 0x0 "IRQ26_SRC,Reserved"
line.long 0x4 "IRQ27_SRC,Reserved"
rgroup.long 0x70++0x7
line.long 0x0 "IRQ28_SRC,IRQ28 (PWRWU) Interrupt Source Identity"
bitfld.long 0x0 0. "PWRWU_INT,IRQ28 Source Identity\n" "0: IRQ28 source is not from PWRWU interrupt..,1: IRQ28 source is from PWREU interrupt (PWRWU_INT)"
line.long 0x4 "IRQ29_SRC,IRQ29 (ADC) Interrupt Source Identity"
bitfld.long 0x4 0. "ADC_INT,IRQ29 Source Identity \n" "0: IRQ29 source is not from ADC interrupt (ADC_INT),1: IRQ29 source is from ADC interrupt (ADC_INT)"
group.long 0x78++0xF
line.long 0x0 "IRQ30_SRC,Reserved"
line.long 0x4 "IRQ31_SRC,Reserved"
line.long 0x8 "NMI_CON,NMI Source Interrupt Select Control Register"
bitfld.long 0x8 8. "NMI_SEL_EN,NMI Interrupt Enable Bit (Write Protected)\nNote: This bit is the protected bit and programming it needs to write 0x59 0x16 and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address.." "0: NMI interrupt Disabled,1: NMI interrupt Enabled"
hexmask.long.byte 0x8 0.--4. 1. "NMI_SEL,NMI Interrupt Source Select Bit\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL."
line.long 0xC "MCU_IRQ,MCU IRQ Number Identity Register"
hexmask.long 0xC 0.--31. 1. "MCU_IRQ,MCU IRQ Source Bits\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core. There are two modes to generate interrupt to Cortex-M0 - the normal mode and test mode.\nThe MCU_IRQ.."
tree.end
tree "SCS (System Controllers Space)"
base ad:0xE000E000
group.long 0x10++0xB
line.long 0x0 "SYST_CSR,SysTick Control and Status Register"
bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register." "0,1"
bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Select Bit\n" "0: Clock source is optional refer to STCLKSEL,1: Core clock used for SysTick timer"
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bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enable Bit\n" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
bitfld.long 0x0 0. "ENABLE,System Tick Counter Enable Bit\n" "0: Counter Disabled,1: Counter Enabled and will operate in a multi-shot.."
line.long 0x4 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0."
line.long 0x8 "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the.."
group.long 0x100++0x3
line.long 0x0 "NVIC_ISER,IRQ0 ~ IRQ31 Set-enable Control Register"
hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Enable Bits\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status."
group.long 0x180++0x3
line.long 0x0 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-enable Control Register"
hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt Disable Bits\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite Operation:\nNote: Read value indicates the current enable status."
group.long 0x200++0x3
line.long 0x0 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-pending Control Register"
hexmask.long 0x0 0.--31. 1. "SETPEND,Set Interrupt Pending Bits\nWrite Operation:\nNote: Read value indicates the current pending status."
group.long 0x280++0x3
line.long 0x0 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-pending Control Register"
hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear Interrupt Pending Bits\nWrite Operation:\nNote: Read value indicates the current pending status."
group.long 0x400++0x1F
line.long 0x0 "NVIC_IPR0,IRQ0 ~ IRQ3 Interrupt Priority Control Register"
bitfld.long 0x0 30.--31. "PRI_3,Priority of IRQ3\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x0 22.--23. "PRI_2,Priority of IRQ2\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x0 14.--15. "PRI_1,Priority of IRQ1\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x0 6.--7. "PRI_0,Priority of IRQ0\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x4 "NVIC_IPR1,IRQ4 ~ IRQ7 Interrupt Priority Control Register"
bitfld.long 0x4 30.--31. "PRI_7,Priority of IRQ7\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x4 22.--23. "PRI_6,Priority of IRQ6\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x4 14.--15. "PRI_5,Priority of IRQ5\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x4 6.--7. "PRI_4,Priority of IRQ4\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x8 "NVIC_IPR2,IRQ8 ~ IRQ11 Interrupt Priority Control Register"
bitfld.long 0x8 30.--31. "PRI_11,Priority of IRQ11\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x8 22.--23. "PRI_10,Priority of IRQ10\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x8 14.--15. "PRI_9,Priority of IRQ9\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x8 6.--7. "PRI_8,Priority of IRQ8\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0xC "NVIC_IPR3,IRQ12 ~ IRQ15 Interrupt Priority Control Register"
bitfld.long 0xC 30.--31. "PRI_15,Priority of IRQ15\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0xC 22.--23. "PRI_14,Priority of IRQ14\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0xC 14.--15. "PRI_13,Priority of IRQ13\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0xC 6.--7. "PRI_12,Priority of IRQ12\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x10 "NVIC_IPR4,IRQ16 ~ IRQ19 Interrupt Priority Control Register"
bitfld.long 0x10 30.--31. "PRI_19,Priority of IRQ19\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x10 22.--23. "PRI_18,Priority of IRQ18\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x10 14.--15. "PRI_17,Priority of IRQ17\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x10 6.--7. "PRI_16,Priority of IRQ16\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x14 "NVIC_IPR5,IRQ20 ~ IRQ23 Interrupt Priority Control Register"
bitfld.long 0x14 30.--31. "PRI_23,Priority of IRQ23\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x14 22.--23. "PRI_22,Priority of IRQ22\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x14 14.--15. "PRI_21,Priority of IRQ21\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x14 6.--7. "PRI_20,Priority of IRQ20\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x18 "NVIC_IPR6,IRQ24 ~ IRQ27 Interrupt Priority Control Register"
bitfld.long 0x18 30.--31. "PRI_27,Priority of IRQ27\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x18 22.--23. "PRI_26,Priority of IRQ26\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x18 14.--15. "PRI_25,Priority of IRQ25\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x18 6.--7. "PRI_24,Priority of IRQ24\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x1C "NVIC_IPR7,IRQ28 ~ IRQ31 Interrupt Priority Control Register"
bitfld.long 0x1C 30.--31. "PRI_31,Priority of IRQ31\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x1C 22.--23. "PRI_30,Priority of IRQ30\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x1C 14.--15. "PRI_29,Priority of IRQ29\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x1C 6.--7. "PRI_28,Priority of IRQ28\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
rgroup.long 0xD00++0x3
line.long 0x0 "SCS_CPUID,CPUID Base Register"
hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer Code\n"
hexmask.long.byte 0x0 16.--19. 1. "PART,Architecture of the Processor\nRead as 0xC for ARMv6-M parts."
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hexmask.long.word 0x0 4.--15. 1. "PARTNO,Part Number of the Processor\nRead as 0xC20."
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Revision Number\nRead as 0x0."
group.long 0xD04++0x3
line.long 0x0 "SCS_ICSR,Interrupt Control State Register"
bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0." "0: No effect.\nNMI exception is not pending,1: Changes NMI exception state to pending.\nNMI.."
bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending." "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
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bitfld.long 0x0 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nNote: This bit is write-only. To clear the PENDSV bit you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time." "0: No effect,1: Removes the pending state from the PendSV.."
bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation:\n" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
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bitfld.long 0x0 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This bit is write-only. When you want to clear PENDST bit you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time." "0: No effect,1: Removes the pending state from the SysTick.."
bitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preemption Bit\nIf set a pending exception will be serviced on exit from the debug halt state.\nNote: This bit is read only." "0,1"
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bitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults\nNote: This bit is read only." "0: Interrupt not pending,1: Interrupt pending"
hexmask.long.word 0x0 12.--20. 1. "VECTPENDING,Exception Number of the Highest Priority Pending Enabled Exception\nNote: These bits are read only."
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hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Contains the Active Exception Number\nNote: These bits are read only."
group.long 0xD0C++0x7
line.long 0x0 "SCS_AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x0 16.--31. 1. "VECTORKEY,Register Access Key\nWrite Operation:\nWhen writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from.."
bitfld.long 0x0 2. "SYSRESETREQ,System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence." "0,1"
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bitfld.long 0x0 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nReserved for debug use. When writing to the register user must write 0 to this bit otherwise behavior is unpredictable." "0,1"
line.long 0x4 "SCS_SCR,System Control Register"
bitfld.long 0x4 4. "SEVONPEND,Send Event On Pending Bit\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE. If the processor is not waiting for an event the event is registered and affects next WFE.\nThe processor also wakes.." "0: Only enabled interrupts or events can wake-up..,1: Enabled events and all interrupts including.."
bitfld.long 0x4 2. "SLEEPDEEP,Processor Deep Sleep And Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n" "0: Sleep mode,1: Deep Sleep mode"
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bitfld.long 0x4 1. "SLEEPONEXIT,Sleep-on-exit Enable\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application." "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep on return from ISR to.."
group.long 0xD1C++0x7
line.long 0x0 "SCS_SHPR2,System Handler Priority Register 2"
bitfld.long 0x0 30.--31. "PRI_11,Priority Of System Handler 11 - SVCall\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
line.long 0x4 "SCS_SHPR3,System Handler Priority Register 3"
bitfld.long 0x4 30.--31. "PRI_15,Priority of System Handler 15 - SysTick\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
bitfld.long 0x4 22.--23. "PRI_14,Priority of System Handler 14 - PendSV\n0 denotes the highest priority and 3 denotes the lowest priority." "0,1,2,3"
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x40030000
group.long 0x0++0xB
line.long 0x0 "SPI_CTL,SPI Control and Status Register"
rbitfld.long 0x0 27. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[27]." "0: The transmit FIFO buffer is not full,1: The transmit FIFO buffer is full"
rbitfld.long 0x0 26. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STAUTS[26]." "0: The transmit FIFO buffer is not empty,1: The transmit FIFO buffer is empty"
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rbitfld.long 0x0 25. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[25]" "0: The receive FIFO buffer is not full,1: The receive FIFO buffer is full"
rbitfld.long 0x0 24. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[24]." "0: The receive FIFO buffer is not empty,1: The receive FIFO buffer is empty"
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bitfld.long 0x0 21. "FIFOEN,FIFO Mode Enable Bit\nNote 1: Before enabling FIFO mode the other related settings should be set in advance.\nNote 2: In Master mode if the FIFO mode is enabled the SPIEN bit will be set to 1 automatically after writing data into the 4-layer.." "0: FIFO Mode Disabled,1: Before enabling FIFO mode"
bitfld.long 0x0 19. "REORDER,Byte Reorder Function\nNote: This setting is only available if DWIDTH is defined as 16 24 or 32 bits." "0: Byte reorder function Disabled,1: Byte reorder function Enabled"
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control\n" "0: Master mode,1: Slave mode"
bitfld.long 0x0 17. "UNITIEN,Unit-transfer Interrupt Enable Bit\n" "0: SPI unit-transfer interrupt Disabled,1: SPI unit-transfer interrupt Enabled"
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bitfld.long 0x0 16. "UNITIF,Unit-transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: It's a mutual mirror bit of SPI_STATUS[16]." "0: The transfer does not finish yet,1: This bit will be cleared by writing 1 to itself"
hexmask.long.byte 0x0 12.--15. 1. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction.."
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bitfld.long 0x0 11. "CLKPOL,Clock Polarity\n" "0: SPI_CLK idle low,1: SPI_CLK idle high"
bitfld.long 0x0 10. "LSB,LSB First\n" "0: The MSB is transmitted/received first,1: The LSB is transmitted/received first"
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hexmask.long.byte 0x0 3.--7. 1. "DWIDTH,Transmit Bit Length\nThis field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits.\n"
bitfld.long 0x0 2. "TXNEG,Transmit On Negative Edge\n" "0: The transmitted data output signal is driven on..,1: The transmitted data output signal is driven on.."
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bitfld.long 0x0 1. "RXNEG,Receive On Negative Edge\n" "0: The received data input signal latched on the..,1: The received data input signal latched on the.."
bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Bit And Busy Status\nIf FIFO mode is enabled this bit will be controlled by hardware and it's read only.\nIf FIFO mode is disabled during the data transfer this bit keeps the value of 1. As the transfer is finished this bit.." "0: Writing 0 to this bit to stop data transfer if..,1: When FIFO mode is disabled"
line.long 0x4 "SPI_CLKDIV,SPI Clock Divider Register"
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider Register (Master Only)\nThe value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi and the SPI master's bus clock frequency on the SPI_CLK output pin. The frequency is obtained according.."
line.long 0x8 "SPI_SSCTL,SPI Slave Select Register"
rbitfld.long 0x8 5. "LTF,Level Trigger Flag (Read Only Slave Only)\nWhen the SSLTEN bit is set in Slave mode this bit can be read to indicate the received bit number is met the requirement or not.\n" "0: The transaction number or the transferred bit..,1: The transaction number and the transferred bit.."
bitfld.long 0x8 4. "SSLTEN,Slave Select Level Trigger Enable Bit (Slave Only)\n" "0: The input slave select signal is edge-trigger,1: The input slave select signal is level-trigger"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)\n" "0: SPI_SS pin signal will be asserted/de-asserted..,1: SPI_SS pin signal will be generated.."
bitfld.long 0x8 2. "SSACTPOL,Slave Select Active Level (Slave Only)\nIt defines the active status of slave select signal (SPI_SS).\nIf SSLTEN bit is 1:\n" "0: The slave select signal SPI_SS is active at..,1: The slave select signal SPI_SS is active at.."
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bitfld.long 0x8 0. "SS,Slave Select Control Bits (Master Only)\nIf AUTOSS bit is 0 \n" "0: Set the SPI_SS line to inactive state.\nKeep the..,1: Set the SPI_SS line to active state.\nSelect the.."
rgroup.long 0x10++0x3
line.long 0x0 "SPI_RX,SPI Data Receive Register"
hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register (Read Only)\nThe Data Receive Register holds the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field DWIDTH in the SPI_CTL register.\nFor example if DWIDTH is set to 0x08 the.."
wgroup.long 0x20++0x3
line.long 0x0 "SPI_TX,SPI Data Transmit Register"
hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register\nThe Data Transmit Register holds the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field DWIDTH in the SPI_CTL register.\nFor example if DWIDTH is set to 0x08 the bit filed TX[7:0].."
group.long 0x3C++0xB
line.long 0x0 "SPI_SLVCTL,SPI Slave Control and Status Register"
bitfld.long 0x0 31. "DIVMOD,Clock Configuration Backward Compatible Option\nNote: Refer to the description of SPI_CLKDIV register for details." "0: The clock configuration is backward compatible,1: The clock configuration is not backward compatible"
bitfld.long 0x0 16. "SSINAIEN,Slave Select Inactive Interrupt Option (Slave Only)\nNote: This setting is only available if the SPI controller is configured as level trigger in slave device." "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
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bitfld.long 0x0 11. "SLVSTIF,Slave 3-wire Mode Start Interrupt Status (Slave Only)\nThis bit dedicates if a transaction has started in Slave 3-wire mode. \nNote 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit.\nNote 2: It is a.." "0: Slave does not detect any SPI bus clock transfer..,1: It will be cleared automatically when a.."
bitfld.long 0x0 10. "SLVSTIEN,Slave 3-wire Mode Start Interrupt Enable (Slave Only)\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer.." "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled"
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bitfld.long 0x0 9. "SLVABT,Slave 3-wire Mode Abort Control Bit (Slave Only)\nIn normal operation there is an interrupt event when the number of received bits meets the requirement which defined in DWIDTH.\nIf the number of received bits is less than the requirement and.." "0: No force the transfer done when the SLV3WIRE bit..,1: Force the transfer done when the SLV3WIRE bit is.."
bitfld.long 0x0 8. "SLV3WIRE,Slave 3-wire Mode Enable Bit (Slave Only)\nThe SPI controller work with 3-wire interface including SPI_CLK SPI_MISO and SPI_MOSI.\nNote: In Slave 3-wire mode the SSLTEN bit (SPI_SSCTL[4]) shall be set as 1." "0: The controller is 4-wire bi-direction interface..,1: The controller is 3-wire bi-direction interface.."
line.long 0x4 "SPI_FIFOCTL,SPI FIFO Control Register"
bitfld.long 0x4 28.--29. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
bitfld.long 0x4 24.--25. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0." "0,1,2,3"
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bitfld.long 0x4 21. "RXTOIEN,Receive FIFO Time-out Interrupt Enable Bit\n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled"
bitfld.long 0x4 6. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x4 3. "TXTHIEN,Transmit Threshold Interrupt Enable Bit\n" "0: Transmit threshold interrupt Disabled,1: Transmit threshold interrupt Enabled"
bitfld.long 0x4 2. "RXTHIEN,Receive Threshold Interrupt Enable Bit\n" "0: Receive threshold interrupt Disabled,1: Receive threshold interrupt Enabled"
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bitfld.long 0x4 1. "TXRST,Clear Transmit FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared." "0: No effect,1: Clear transmit FIFO buffer"
bitfld.long 0x4 0. "RXRST,Clear Receive FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared." "0: No effect,1: Clear receive FIFO buffer"
line.long 0x8 "SPI_STATUS,SPI Status Register"
hexmask.long.byte 0x8 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer."
rbitfld.long 0x8 27. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CTL[27]." "0: The transmit FIFO buffer is not full,1: The transmit FIFO buffer is full"
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rbitfld.long 0x8 26. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CTL[26]." "0: The transmit FIFO buffer is not empty,1: The transmit FIFO buffer is empty"
rbitfld.long 0x8 25. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CTL[25]." "0: The receive FIFO buffer is not full,1: The receive FIFO buffer is full"
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rbitfld.long 0x8 24. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CTL[24]." "0: The receive FIFO buffer is not empty,1: The receive FIFO buffer is empty"
bitfld.long 0x8 20. "SLVTOIF,Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself." "0: No receive FIFO time-out event,1: The receive FIFO buffer is not empty and it does.."
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bitfld.long 0x8 16. "UNITIF,SPI Unit-transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: It's a mutual mirror bit of SPI_CTL[16]." "0: The transfer does not finish yet,1: This bit will be cleared by writing 1 to itself"
hexmask.long.byte 0x8 12.--15. 1. "RXCNT,Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer."
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bitfld.long 0x8 11. "SLVSTIF,Slave Start Interrupt Status (Slave Only)\nIt is used to dedicate that the transfer has started in slave 3-wire mode. \nNote 1: It will be cleared as transfer done or by writing one to this bit.\nNote 2: It's a mutual mirror bit of SPI_SLVCTL[11]." "0: Slave does not detect any SPI bus clock transfer..,1: It will be cleared as transfer done or by.."
rbitfld.long 0x8 4. "TXTHIF,Transmit FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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bitfld.long 0x8 2. "RXOVIF,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself." "0: No overrun in receive FIFO,1: Overrun in receive FIFO"
rbitfld.long 0x8 0. "RXTHIF,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
tree.end
tree "SYS (System Manager)"
base ad:0x50000000
rgroup.long 0x0++0x3
line.long 0x0 "SYS_PDID,Part Device Identification Number Register"
hexmask.long 0x0 0.--31. 1. "PDID,Product Device Identification Number (Read Only)\nThis register reflects the device part number code. Software can read this register to identify which device is used.\nFor example the MINI58LDE PDID code is '0x00A05800'."
group.long 0x4++0xB
line.long 0x0 "SYS_RSTSTS,System Reset Status Register"
bitfld.long 0x0 8. "CPULKRF,The Cortex-M0 LOCKUP Flag\nNote: Software can write 1 to clear this bit to zero." "0: No reset from Cortex-M0 LOCKUP happened,1: The Cortex-M0 LOCKUP happened and chip is reset"
bitfld.long 0x0 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: Software can write 1 to clear this bit to zero." "0: No reset from CPU,1: The Cortex-M0 Core and FMC are reset by software.."
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bitfld.long 0x0 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to zero." "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.."
bitfld.long 0x0 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to zero." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.."
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bitfld.long 0x0 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to zero." "0: No reset from watchdog timer or window watchdog..,1: The watchdog timer or window watchdog timer had.."
bitfld.long 0x0 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET pin to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to zero." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.."
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bitfld.long 0x0 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Software can write 1 to clear this bit to zero." "0: No reset from POR or CHIPRST,1: Power-on-Reset (POR) or CHIPRST had issued the.."
line.long 0x4 "SYS_IPRST0,Peripheral Reset Control Register 0"
bitfld.long 0x4 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller (FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer.." "0: Processor core normal operation,1: Processor core one-shot reset"
bitfld.long 0x4 0. "CHIPRST,CHIP One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is the same as the POR reset all.." "0: Chip normal operation,1: CHIP one-shot reset"
line.long 0x8 "SYS_IPRST1,Peripheral Reset Control Register 1"
bitfld.long 0x8 28. "ADCRST,ADC Controller Reset\n" "0: ADC controller normal operation,1: ADC controller reset"
bitfld.long 0x8 22. "ACMPRST,ACMP Controller Reset\n" "0: ACMP controller normal operation,1: ACMP controller reset"
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bitfld.long 0x8 20. "PWM0RST,PWM0 Controller Reset\n" "0: PWM0 controller normal operation,1: PWM0 controller reset"
bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset\n" "0: UART1 controller normal operation,1: UART1 controller reset"
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bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset\n" "0: UART0 controller normal operation,1: UART0 controller reset"
bitfld.long 0x8 12. "SPI0RST,SPI0 Controller Reset\n" "0: SPI controller normal operation,1: SPI controller reset"
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bitfld.long 0x8 9. "I2C1RST,I2C1 Controller Reset\n" "0: I2C1 controller normal operation,1: I2C1 controller reset"
bitfld.long 0x8 8. "I2C0RST,I2C0 Controller Reset\n" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset\n" "0: Timer1 controller normal operation,1: Timer1 controller reset"
bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset\n" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x8 1. "GPIORST,GPIO (P0~P5) Controller Reset\n" "0: GPIO controller normal operation,1: GPIO controller reset"
group.long 0x18++0x3
line.long 0x0 "SYS_BODCTL,Brown-out Detector Control Register"
bitfld.long 0x0 6. "BODOUT,Brown-out Detector Output Status\n" "0: Brown-out Detector status output is 0 the..,1: Brown-out Detector status output is 1 the.."
bitfld.long 0x0 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\nNote: The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response." "0: BOD operate in normal mode (default),1: BOD Low Power mode Enabled"
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bitfld.long 0x0 4. "BODIF,Brown-out Detector Interrupt Flag\n" "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.."
bitfld.long 0x0 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit.\nNote: When the BOD_EN is enabled and the interrupt is asserted the interrupt will be kept till the.." "0: Brown-out 'INTERRUPT' function Enabled; when the..,1: Brown-out 'RESET' function Enabled; when the.."
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bitfld.long 0x0 1.--2. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0[22:21]).\n" "0: Reserved,1: Brown-out Detector threshold voltage is 2.7V,?,?"
bitfld.long 0x0 0. "BODEN,Brown-out Detector Selection Extension (Initiated Write-protected Bit)\n" "0: Brown-out detector threshold voltage is selected..,1: Brown-out detector threshold voltage is selected.."
group.long 0x30++0x17
line.long 0x0 "SYS_P0_MFP,P0 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x0 16.--23. 1. "TYPE,P0[7:0] Input Schmitt Trigger Function Enable Bits\n"
bitfld.long 0x0 15. "ALT7,P0.7 Alternate Function Select Bit\nBits ALT[7] (SYS_P0_MFP[15]) and MFP[7] (SYS_P0_MFP[7]) determine the P0.7 function.\n" "0,1"
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bitfld.long 0x0 14. "ALT6,P0.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P0_MFP[14]) and MFP[6] (SYS_P0_MFP[6]) determine the P0.6 function.\n" "0,1"
bitfld.long 0x0 13. "ALT5,P0.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P0_MFP[13]) and MFP[5] (SYS_P0_MFP[5]) determine the P0.5 function.\n" "0,1"
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bitfld.long 0x0 12. "ALT4,P0.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P0_MFP[12]) and MFP[4] (SYS_P0_MFP[4]) determine the P0.4 function.\n" "0,1"
bitfld.long 0x0 9. "ALT1,P0.1 Alternate Function Select Bit\nBits ALT[1] (SYS_P0_MFP[9]) and MFP[1] (SYS_P0_MFP[1]) determine the P0.1 function.\n" "0,1"
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bitfld.long 0x0 8. "ALT0,P0.0 Alternate Function Select Bit\nBits ALT[0] (SYS_P0_MFP[8]) and MFP[0] (SYS_P0_MFP[0]) determine the P0.0 function.\n" "0,1"
hexmask.long.byte 0x0 0.--7. 1. "MFP,P0 Multiple Function Select Bit\nThe pin function of P0 depends on MFP and ALT.\nRefer to ALT Description for details."
line.long 0x4 "SYS_P1_MFP,P1 Multiple Function and Input Type Control Register"
bitfld.long 0x4 28. "P14EXT,P1.4 Alternate Function Selection Extension\nBits P14EXT (SYS_P1_MFP[28]) ALT[4] (SYS_P1_MFP[12]) and MFP[4] (SYS_P1_MFP[4]) determine the P1.4 function.\n" "0,1"
bitfld.long 0x4 27. "P13EXT,P1.3 Alternate Function Selection Extension\nBits P13EXT (SYS_P1_MFP[27]) ALT[3] (SYS_P1_MFP[11]) and MFP[3] (SYS_P1_MFP[3]) determine the P1.3 function.\n" "0,1"
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bitfld.long 0x4 26. "P12EXT,P1.2 Alternate Function Selection Extension\nBits P12EXT (SYS_P1_MFP[26]) ALT[2] (SYS_P1_MFP[10]) and MFP[2] (SYS_P1_MFP[2]) determine the P1.2 function.\n" "0,1"
hexmask.long.byte 0x4 16.--23. 1. "TYPE,P1[7:0] Input Schmitt Trigger Function Enable Bit\n"
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bitfld.long 0x4 13. "ALT5,P1.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P1_MFP[13]) and MFP[5] (SYS_P1_MFP[5]) determine the P1.5 function.\n" "0,1"
bitfld.long 0x4 12. "ALT4,P1.4 Alternate Function Select Bit\nBits P14EXT (SYS_P1_MFP[28]) ALT[4] (SYS_P1_MFP[12]) and MFP[4] (SYS_P1_MFP[4]) determine the P1.4 function.\n" "0,1"
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bitfld.long 0x4 11. "ALT3,P1.3 Alternate Function Select Bit\nBits P13EXT (SYS_P1_MFP[27]) ALT[3] (SYS_P1_MFP[11]) and MFP[3] (SYS_P1_MFP[3]) determine the P1.3 function.\n" "0,1"
bitfld.long 0x4 10. "ALT2,P1.2 Alternate Function Select Bit\nBits P12EXT (SYS_P1_MFP[26]) ALT[2] (SYS_P1_MFP[10]) and MFP[2] (SYS_P1_MFP[2]) determine the P1.2 function.\n" "0,1"
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bitfld.long 0x4 8. "ALT0,P1.0 Alternate Function Select Bit\nBits ALT[0] (SYS_P1_MFP[8]) and MFP[0] (SYS_P1_MFP[0]) determine the P1.0 function.\n" "0,1"
hexmask.long.byte 0x4 0.--7. 1. "MFP,P1 Multiple Function Select Bit\nThe pin function of P1 depends on MFP and ALT.\nRefer to ALT Description for details."
line.long 0x8 "SYS_P2_MFP,P2 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x8 16.--23. 1. "TYPE,P2[7:0] Input Schmitt Trigger Function Enable Bits\n"
bitfld.long 0x8 14. "ALT6,P2.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P2_MFP[14]) and MFP[6] (SYS_P2_MFP[6]) determine the P2.6 function.\n" "0,1"
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bitfld.long 0x8 13. "ALT5,P2.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P2_MFP[13]) and MFP[5] (SYS_P2_MFP[5]) determine the P2.5 function.\n" "0,1"
bitfld.long 0x8 12. "ALT4,P2.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P2_MFP[12]) and MFP[4] (SYS_P2_MFP[4]) determine the P2.4 function.\n" "0,1"
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bitfld.long 0x8 11. "ALT3,P2.3 Alternate Function Select Bit\nBits ALT[3] (SYS_P2_MFP[11]) and MFP[3] (SYS_P2_MFP[3]) determine the P2.3 function.\n" "0,1"
bitfld.long 0x8 10. "ALT2,P2.2 Alternate Function Select Bit\nBits ALT[2] (SYS_P2_MFP[10]) and MFP[2] (SYS_P2_MFP[2]) determine the P2.2 function.\n" "0,1"
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hexmask.long.byte 0x8 0.--7. 1. "MFP,P2 Multiple Function Select Bit\nThe pin function of P2 depends on MFP and ALT.\nRefer to ALT Description for details."
line.long 0xC "SYS_P3_MFP,P3 Multiple Function and Input Type Control Register"
bitfld.long 0xC 26. "P32EXT,P3.2 Alternate Function Selection Extension\nBits P32EXT (SYS_P3_MFP[26]) ALT[2] (SYS_P3_MFP[10]) and MFP[2] (SYS_P3_MFP[2]) determine the P3.2 function.\n" "0,1"
hexmask.long.byte 0xC 16.--23. 1. "TYPE,P3[7:0] Input Schmitt Trigger Function Enable Bits\n"
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bitfld.long 0xC 14. "ALT6,P3.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P3_MFP[14]) and MFP[6] (SYS_P3_MFP[6]) determine the P3.6 function.\n" "0,1"
bitfld.long 0xC 13. "ALT5,P3.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P3_MFP[13]) and MFP[5] (SYS_P3_MFP[5]) determine the P3.5 function.\n" "0,1"
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bitfld.long 0xC 12. "ALT4,P3.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P3_MFP[12]) and MFP[4] (SYS_P3_MFP[4]) determine the P3.4 function.\n" "0,1"
bitfld.long 0xC 10. "ALT2,P3.2 Alternate Function Select Bit\nBits P32EXT (SYS_P3_MFP[26]) ALT[2] (SYS_P3_MFP[10]) and MFP[2] (SYS_P3_MFP[2]) determine the P3.2 function.\n" "0,1"
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bitfld.long 0xC 9. "ALT1,P3.1 Alternate Function Select Bit\nThe pin function of P3.1 depends on P3_MFP[1] and P3_ALT[1].\nBits ALT[1] (SYS_P3_MFP[9]) and MFP[1] (SYS_P3_MFP[1]) determine the P3.1 function.\n" "0,1"
bitfld.long 0xC 8. "ALT0,P3.0 Alternate Function Select Bit\nBits ALT[0] (SYS_P3_MFP[8]) and MFP[0] (SYS_P3_MFP[0]) determine the P3.0 function.\n" "0,1"
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hexmask.long.byte 0xC 0.--7. 1. "MFP,P3 Multiple Function Select Bits\nThe pin function of P3 depends on MFP and ALT.\nRefer to ALT Description for details."
line.long 0x10 "SYS_P4_MFP,P4 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x10 16.--23. 1. "TYPE,P4[7:0] Input Schmitt Trigger Function Enable Bits\n"
bitfld.long 0x10 15. "ALT7,P4.7 Alternate Function Select Bit\nBits ALT[7] (SYS_P4_MFP[15]) and MFP[7] (SYS_P4_MFP[7]) determine the P4.7 function.\n" "0,1"
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bitfld.long 0x10 14. "ALT6,P4.6 Alternate Function Select Bit\nBits ALT[6] (SYS_P4_MFP[14]) and MFP[6] (SYS_P4_MFP[6]) determine the P4.6 function.\n" "0,1"
hexmask.long.byte 0x10 0.--7. 1. "MFP,P4 Multiple Function Select Bits\nThe pin function of P4 depends on MFP and ALT.\nRefer to ALT Description for details."
line.long 0x14 "SYS_P5_MFP,P5 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x14 16.--23. 1. "TYPE,P5[7:0] Input Schmitt Trigger Function Enable Bits\n"
bitfld.long 0x14 13. "ALT5,P5.5 Alternate Function Select Bit\nBits ALT[5] (SYS_P5_MFP[13]) and MFP[5] (SYS_P5_MFP[5]) determine the P5.5 function.\n" "0,1"
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bitfld.long 0x14 12. "ALT4,P5.4 Alternate Function Select Bit\nBits ALT[4] (SYS_P5_MFP[12]) and MFP[4] (SYS_P5_MFP[4]) determine the P5.4 function.\n" "0,1"
bitfld.long 0x14 11. "ALT3,P5.3 Alternate Function Select Bit\nBits ALT[3] (SYS_P5_MFP[11]) and MFP[3] (SYS_P5_MFP[3]) determine the P5.3 function.\n" "0,1"
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bitfld.long 0x14 10. "ALT2,P5.2 Alternate Function Select Bit\nBits ALT[2] (SYS_P5_MFP[10]) and MFP[2] (SYS_P5_MFP[2]) determine the P5.2 function.\n" "0,1"
bitfld.long 0x14 9. "ALT1,P5.1 Alternate Function Select Bit\nBits ALT[1] (SYS_P5_MFP[9]) and MFP[1] (SYS_P5_MFP[1]) determine the P5.1 function.\nNote: To enable external XTAL function the CLK_PWRCTL bit [1:0] (XTLEN) external HXT or LXT crystal oscillator control.." "0,1"
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bitfld.long 0x14 8. "ALT0,P5.0 Alternate Function Select Bit\nThe pin function of P5.0 depends on MFP[0] and ALT[0].\nBits ALT[0] (SYS_P5_MFP[8]) and MFP[0] (SYS_P5_MFP[0]) determine the P5.0 function.\nNote: To enable external XTAL function the CLK_PWRCTL bit [1:0].." "0,1"
hexmask.long.byte 0x14 0.--7. 1. "MFP,P5 Multiple Function Select Bits\nThe pin function of P5 depends on MFP and ALT.\nRefer to ALT Description for details."
group.long 0x80++0xB
line.long 0x0 "SYS_IRCTCTL,HIRC Trim Control Register"
bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop\nThis field defines trim value calculation based on the number of LXT clock.\nFor example if LOOPSEL is set as '00' auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
bitfld.long 0x0 0. "FREQSEL,Trim Frequency Select Bit\nThis bit is to enable the HIRC auto trim.\nWhen setting this bit to 1 the HIRC auto trim function will trim HIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation if LXT clock.." "0: HIRC auto trim function Disabled,1: HIRC auto trim function Enabled and HIRC trimmed.."
line.long 0x4 "SYS_IRCTIEN,HIRC Trim Interrupt Enable Register"
bitfld.long 0x4 2. "CLKEIEN,LXT Clock Error Interrupt Enable Bit\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high and CLKERRIF (SYS_IRCTISTS[2]) is set during auto trim operation an interrupt.." "0: CLKERRIF (SYS_IRCTISTS[2]) status Disabled to..,1: CLKERRIF (SYS_IRCTISTS[2]) status Enabled to.."
bitfld.long 0x4 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency is still not locked on target frequency set by FREQSEL (SYS_IRCTCTL[1:0]).\nIf.." "0: TFAILIF (SYS_IRCTISTS[1]) status Disabled to..,1: TFAILIF (SYS_IRCTISTS[1]) status Enabled to.."
line.long 0x8 "SYS_IRCTISTS,HIRC Trim Interrupt Status Register"
bitfld.long 0x8 2. "CLKERRIF,LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set the auto trim operation stopped and FREQSEL (SYS_IRCTCTL[0]) will be cleared to 0 by hardware automatically.\nIf this bit is set.." "0: LXT clock frequency is accuracy,1: LXT clock frequency is inaccuracy"
bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set the auto trim operation stopped and FREQSEL (SYS_IRCTCTL[1:0]) will be.." "0: Trim value update limitation count is not reached,1: Trim value update limitation count is reached.."
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bitfld.long 0x8 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency locked in 22.1184 MHz.\nThis is a read only status bit and doesn't trigger any interrupt." "0,1"
group.long 0x100++0x3
line.long 0x0 "SYS_REGLCTL,Register Write-protection Control Register"
hexmask.long.byte 0x0 0.--7. 1. "REGLCTL,Register Write-protection Code \nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59 0x16 0x88 to this field. After this sequence is completed the.."
tree.end
tree "TMR (Timer Controller)"
base ad:0x40010000
group.long 0x0++0xB
line.long 0x0 "TIMER0_CTL,Timer0 Control and Status Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal will be generated and inform CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Selection\n" "0: The Timer controller is operated in one-shot mode,1: The Timer controller is operated in periodic mode,?,?"
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bitfld.long 0x0 26. "RSTCNT,Timer Counter Reset\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.."
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit\nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled"
bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while the timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 19. "CAPSRC,Capture Pin Source Select Bit\n" "0: Capture Function source is from TMx_EXT (x= 0~1)..,1: Capture Function source is from internal ACMP.."
bitfld.long 0x0 18. "TGLPINSEL,Toggle-output Pin Select Bit\n" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 17. "CMPCTL,Timer Compared Mode Select Bit \nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in one-shot or periodic..,1: The behavior selection in one-shot or periodic.."
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\n"
line.long 0x4 "TIMER0_CMP,Timer0 Compare Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field or.."
line.long 0x8 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER0_CNT,Timer0 Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24- bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value for getting current 24- bit event input counter value."
line.long 0x4 "TIMER0_CAP,Timer0 Capture Data Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
group.long 0x14++0x7
line.long 0x0 "TIMER0_EXTCTL,Timer0 External Control Register"
bitfld.long 0x0 9. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nFor Timer 0:\n" "0: Capture Function source is from ACMP0 output..,1: Capture Function source is from ACMP1 output.."
bitfld.long 0x0 8. "CAPSEL,Capture Mode Select Bit\n" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~1) pin de-bounce Disabled,1: TMx (x= 0~1) pin de-bounce Enabled"
bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote1: If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit.\nNote2: The de-bounce circuit doesn't support ACMP output." "0: TMx_EXT (x= 0~1) pin de-bounce Disabled,1: If this bit is enabled"
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit\n" "0: TMx_EXT (x= 0~1) pin detection Interrupt Disabled,1: TMx_EXT (x= 0~1) pin detection Interrupt Enabled"
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Select Bit\n" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT pin. \n" "0: TMx_EXT (x= 0~1) pin Disabled,1: TMx_EXT (x= 0~1) pin Enabled"
bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detection\n" "0: A falling edge on TMx_EXT (x= 0~1) pin will be..,1: A rising edge on TMx_EXT (x= 0~1) pin will be..,?,?"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase \n" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
line.long 0x4 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will.." "0: TMx_EXT (x= 0~1) pin interrupt did not occur,1: TMx_EXT (x= 0~1) pin interrupt occurred"
group.long 0x20++0xB
line.long 0x0 "TIMER1_CTL,Timer1 Control and Status Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal will be generated and inform CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Selection\n" "0: The Timer controller is operated in one-shot mode,1: The Timer controller is operated in periodic mode,?,?"
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bitfld.long 0x0 26. "RSTCNT,Timer Counter Reset\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.."
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit\nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter this bit should be set to 1 and select HCLK as timer clock source." "0: Event counter mode Disabled,1: Event counter mode Enabled"
bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while the timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 19. "CAPSRC,Capture Pin Source Select Bit\n" "0: Capture Function source is from TMx_EXT (x= 0~1)..,1: Capture Function source is from internal ACMP.."
bitfld.long 0x0 18. "TGLPINSEL,Toggle-output Pin Select Bit\n" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 17. "CMPCTL,Timer Compared Mode Select Bit \nIf updated CMPDAT value CNT CNT will be reset to default value." "0: The behavior selection in one-shot or periodic..,1: The behavior selection in one-shot or periodic.."
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter\n"
line.long 0x4 "TIMER1_CMP,Timer1 Compare Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field or.."
line.long 0x8 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x8 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
rgroup.long 0x2C++0x7
line.long 0x0 "TIMER1_CNT,Timer1 Data Register"
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register\nIf EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24- bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value for getting current 24- bit event input counter value."
line.long 0x4 "TIMER1_CAP,Timer1 Capture Data Register"
hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
group.long 0x34++0x7
line.long 0x0 "TIMER1_EXTCTL,Timer1 External Control Register"
bitfld.long 0x0 9. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nFor Timer 0:\n" "0: Capture Function source is from ACMP0 output..,1: Capture Function source is from ACMP1 output.."
bitfld.long 0x0 8. "CAPSEL,Capture Mode Select Bit\n" "0: Timer counter reset function or free-counting..,1: Trigger-counting mode of timer capture function"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~1) pin de-bounce Disabled,1: TMx (x= 0~1) pin de-bounce Enabled"
bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote1: If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit.\nNote2: The de-bounce circuit doesn't support ACMP output." "0: TMx_EXT (x= 0~1) pin de-bounce Disabled,1: If this bit is enabled"
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit\n" "0: TMx_EXT (x= 0~1) pin detection Interrupt Disabled,1: TMx_EXT (x= 0~1) pin detection Interrupt Enabled"
bitfld.long 0x0 4. "CAPFUNCS,Capture Function Select Bit\n" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT pin. \n" "0: TMx_EXT (x= 0~1) pin Disabled,1: TMx_EXT (x= 0~1) pin Enabled"
bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detection\n" "0: A falling edge on TMx_EXT (x= 0~1) pin will be..,1: A rising edge on TMx_EXT (x= 0~1) pin will be..,?,?"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase \n" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
line.long 0x4 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will.." "0: TMx_EXT (x= 0~1) pin interrupt did not occur,1: TMx_EXT (x= 0~1) pin interrupt occurred"
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x0
tree "UART0"
base ad:0x40050000
group.long 0x0++0x1B
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. \nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 13. "ATOCTSEN,CTS Auto Flow Control Enable Bit (Only Available In UART0)\nNote: When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
bitfld.long 0x4 12. "ATORTSEN,RTS Auto Flow Control Enable Bit (Only Available In UART0)\nNote: When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Time-out Counter Enable Bit\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 9. "WKCTSIEN,Wake-up CPU Function Interrupt Enable Bit (Only Available In UART0)\nNote: When the chip is in Power-down mode an external CTS change will wake-up chip from Power-down mode." "0: UART wake-up function Disabled,1: UART Wake-up function Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit\n" "0: Buffer Error Interrupt Masked Disabled,1: Buffer Error Interrupt Masked Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit\n" "0: RXTOINT Masked off,1: RXTOINT Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit\n" "0: MODEMINT Masked off,1: MODEMINT Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\n" "0: RLSINT Masked off,1: RLSINT Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit\n" "0: THREINT Masked off,1: THREINT Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit\n" "0: RDAINT Masked off,1: RDAINT Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,RTS Trigger Level (For Auto-flow Control Use) (Only Available In UART0)\nNote: This field is used for RTS auto-flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Register (Only Available In UART0)\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is.." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt (RDAINT) Trigger Level (Only Available In UART0)\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable an interrupt will generated).\n"
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: Reset TX internal state machine and pointers reset"
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: Reset RX internal state machine and pointers reset"
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.\n" "0: Break control Disabled,1: Break control Enabled"
bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\n" "0: Stick parity Disabled,1: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are.."
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nThis bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit\n" "0: No parity bit,1: Parity bit is generated on each outgoing.."
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'\n" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
bitfld.long 0xC 0.--1. "WLS,Word Length Select Bit\n" "0: Word length is 5-bit,1: Word length is 6-bit,?,?"
line.long 0x10 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x10 13. "RTSSTS,RTS Pin State (Read Only)\nThis bit mirror from RTS pin output of voltage logic status.\n" "0: RTS pin output is low level voltage logic state,1: RTS pin output is high level voltage logic state"
bitfld.long 0x10 9. "RTSACTLV,RTS Pin Active Level\nThis bit defines the active level state of RTS pin output.\nNote1: Refer to Figure 6.1013 and Figure 6.1014 UART function mode.\nNote2: Refer to Figure 6.1017 and Figure 6.1018 for RS-485 function mode." "0: RTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,RTS (Request-to-send) Signal Control\nThis bit is direct control internal RTS signal active or not and then drive the RTS pin output with RTSACTLV bit configuration.\nNote1: This RTS signal control bit is not effective when RTS auto-flow control is.." "0: RTS signal is active,1: This RTS signal control bit is not effective.."
line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x14 8. "CTSACTLV,CTS Pin Active Level\nThis bit defines the active level state of CTS pin input.\n" "0: CTS pin input is high level active,1: CTS pin input is low level active. (Default)"
rbitfld.long 0x14 4. "CTSSTS,CTS Pin Status (Read Only)\nThis bit mirror from CTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and CTS multi-function port is selected." "0: CTS pin input is low level voltage logic state,1: CTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect CTS State Change Flag\nThis bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is cleared by writing 1 to it." "0: CTS input has not change state,1: CTS input has change state"
line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty"
bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it." "0: TX FIFO did not overflow,1: TX FIFO overflowed"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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rbitfld.long 0x18 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
rbitfld.long 0x18 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit follows the last data bit or parity bit is detected as logic 0).\nNote: This bit is read only but can.." "0: No framing error is generated,1: Framing error is generated"
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rbitfld.long 0x18 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated."
bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detection Flag (Only Available In UART0)\nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it." "?,1: This field is used for RS-485 function mode"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it." "0: RX FIFO did not overflow,1: RX FIFO overflowed"
rgroup.long 0x1C++0x3
line.long 0x0 "UART_INTSTS,UART Interrupt Status Register"
bitfld.long 0x0 16. "CTSWKIF,NCTS Wake-up Interrupt Flag (Read Only) (Only Available In UART0)\nNote1: If WKCTSIEN (UART_IER[9])is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSIEN"
bitfld.long 0x0 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_INTSTS[5]) are both set to 1.\n" "0: No buffer error interrupt is generated,1: buffer error interrupt is generated"
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bitfld.long 0x0 12. "RXTOINT,Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1.\n" "0: No Time-out interrupt is generated,1: Time-out interrupt is generated"
bitfld.long 0x0 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and MODENIF (UART_INTSTS[3]) are both set to 1.\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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bitfld.long 0x0 10. "RLSINT,Receive Line Status Interrupt (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
bitfld.long 0x0 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x0 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x0 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TXOVIF (UART_FIFOSTS[24] or RXOVIF(UART_FIFOSTS[0])) is set. \nWhen BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x0 4. "RXTOIF,Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UARTTOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the Tout interrupt will be.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
bitfld.long 0x0 3. "MODEMIF,MODEM Interrupt Flag (Read Only) (Only Available In UART0)\nNote: This bit is read only and reset to 0 when bit CTSDETF (UART_MODEMSTS[0]) is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x0 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set). If RLSIEN (UART_INTEN [2]) is enabled the RLS interrupt will be.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
bitfld.long 0x0 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN [1]) is enabled the THRE interrupt will be generated.\nNote: This bit.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x0 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL(UART_FIFO[7:4]) then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x13
line.long 0x0 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit. The Unit is bit time."
hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator\n"
line.long 0x4 "UART_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x4 29. "BAUDM1,Divider X Enable Bit\nNote: In IrDA mode this bit must be disabled." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.."
bitfld.long 0x4 28. "BAUDM0,Divider X Equal 1\nNote: Refer to section 'UART Controller Baud Rate Generator' for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
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hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Divider X\n"
hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider."
line.long 0x8 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x8 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal. (Default)"
bitfld.long 0x8 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal. (Default),1: Inverse transmitting output signal"
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bitfld.long 0x8 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit\n" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
line.long 0xC "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0xC 24.--31. 1. "ADDRMV,Address Match Values\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode."
bitfld.long 0xC 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode.\nNote: This field is used for RS-485 any operation mode." "0: RS-485 address detection mode Disabled,1: RS-485 address detection mode Enabled"
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bitfld.long 0xC 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) Control\nNote: It cannot be active with RS485_NMM operation mode." "0: RS-485 Auto Direction Function Mode (AUD) Disabled,1: RS-485 Auto Direction Function Mode (AUD) Enabled"
bitfld.long 0xC 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485_NMM operation mode." "0: RS-485 Auto Address Detection Operation Mode..,1: RS-485 Auto Address Detection Operation Mode.."
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bitfld.long 0xC 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM) Control\nNote: It cannot be active with RS485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation Mode (NMM)..,1: RS-485 Normal Multi-drop Operation Mode (NMM).."
line.long 0x10 "UART_FUNSEL,UART Function Select Register"
bitfld.long 0x10 0.--1. "FUN_SEL,Function Selection\n" "0: UART function mode,1: Reserved,?,?"
tree.end
tree "UART1"
base ad:0x40150000
group.long 0x0++0xF
line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
hexmask.long.byte 0x0 0.--7. 1. "DAT,Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. \nRead.."
line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x4 13. "ATOCTSEN,CTS Auto Flow Control Enable Bit (Only Available In UART0)\nNote: When CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)." "0: CTS auto flow control Disabled,1: CTS auto flow control Enabled"
bitfld.long 0x4 12. "ATORTSEN,RTS Auto Flow Control Enable Bit (Only Available In UART0)\nNote: When RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO [19:16]) the UART will de-assert RTS signal." "0: RTS auto flow control Disabled,1: RTS auto flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Time-out Counter Enable Bit\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x4 9. "WKCTSIEN,Wake-up CPU Function Interrupt Enable Bit (Only Available In UART0)\nNote: When the chip is in Power-down mode an external CTS change will wake-up chip from Power-down mode." "0: UART wake-up function Disabled,1: UART Wake-up function Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit\n" "0: Buffer Error Interrupt Masked Disabled,1: Buffer Error Interrupt Masked Enabled"
bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit\n" "0: RXTOINT Masked off,1: RXTOINT Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit\n" "0: MODEMINT Masked off,1: MODEMINT Enabled"
bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\n" "0: RLSINT Masked off,1: RLSINT Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit\n" "0: THREINT Masked off,1: THREINT Enabled"
bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit\n" "0: RDAINT Masked off,1: RDAINT Enabled"
line.long 0x8 "UART_FIFO,UART FIFO Control Register"
hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,RTS Trigger Level (For Auto-flow Control Use) (Only Available In UART0)\nNote: This field is used for RTS auto-flow control."
bitfld.long 0x8 8. "RXOFF,Receiver Disable Register (Only Available In UART0)\nThe receiver is disabled or not (setting 1 to disable the receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is.." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt (RDAINT) Trigger Level (Only Available In UART0)\nWhen the number of bytes in the receive FIFO equals the RFITL then the RDAIF will be set (if RDAIEN in UART_INTEN register is enable an interrupt will generated).\n"
bitfld.long 0x8 2. "TXRST,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: Reset TX internal state machine and pointers reset"
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART Controller peripheral clock cycles." "0: No effect,1: Reset RX internal state machine and pointers reset"
line.long 0xC "UART_LINE,UART Line Control Register"
bitfld.long 0xC 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.\n" "0: Break control Disabled,1: Break control Enabled"
bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit\n" "0: Stick parity Disabled,1: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are.."
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit\nThis bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit\n" "0: No parity bit,1: Parity bit is generated on each outgoing.."
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'\n" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
bitfld.long 0xC 0.--1. "WLS,Word Length Select Bit\n" "0: Word length is 5-bit,1: Word length is 6-bit,?,?"
group.long 0x18++0x3
line.long 0x0 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x0 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty"
bitfld.long 0x0 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is cleared by writing 1 to it." "0: TX FIFO did not overflow,1: TX FIFO overflowed"
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rbitfld.long 0x0 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x0 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into THR (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x0 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.\nThe Maximum.."
rbitfld.long 0x0 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x0 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
hexmask.long.byte 0x0 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.\nThe Maximum value shown in RXPTR is.."
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rbitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
rbitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit follows the last data bit or parity bit is detected as logic 0).\nNote: This bit is read only but can.." "0: No framing error is generated,1: Framing error is generated"
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rbitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x0 3. "ADDRDETF,RS-485 Address Byte Detection Flag (Only Available In UART0)\nNote1: This field is used for RS-485 function mode.\nNote2: This bit is cleared by writing 1 to it." "?,1: This field is used for RS-485 function mode"
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bitfld.long 0x0 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it." "0: RX FIFO did not overflow,1: RX FIFO overflowed"
rgroup.long 0x1C++0x3
line.long 0x0 "UART_INTSTS,UART Interrupt Status Register"
bitfld.long 0x0 16. "CTSWKIF,NCTS Wake-up Interrupt Flag (Read Only) (Only Available In UART0)\nNote1: If WKCTSIEN (UART_IER[9])is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSIEN"
bitfld.long 0x0 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_INTSTS[5]) are both set to 1.\n" "0: No buffer error interrupt is generated,1: buffer error interrupt is generated"
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bitfld.long 0x0 12. "RXTOINT,Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1.\n" "0: No Time-out interrupt is generated,1: Time-out interrupt is generated"
bitfld.long 0x0 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and MODENIF (UART_INTSTS[3]) are both set to 1.\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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bitfld.long 0x0 10. "RLSINT,Receive Line Status Interrupt (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
bitfld.long 0x0 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x0 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
bitfld.long 0x0 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX/RX FIFO overflow flag (TXOVIF (UART_FIFOSTS[24] or RXOVIF(UART_FIFOSTS[0])) is set. \nWhen BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x0 4. "RXTOIF,Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UARTTOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the Tout interrupt will be.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
bitfld.long 0x0 3. "MODEMIF,MODEM Interrupt Flag (Read Only) (Only Available In UART0)\nNote: This bit is read only and reset to 0 when bit CTSDETF (UART_MODEMSTS[0]) is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x0 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set). If RLSIEN (UART_INTEN [2]) is enabled the RLS interrupt will be.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
bitfld.long 0x0 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN [1]) is enabled the THRE interrupt will be generated.\nNote: This bit.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x0 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL(UART_FIFO[7:4]) then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x7
line.long 0x0 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value\nThis field is used to program the transfer delay time between the last stop bit and next start bit. The Unit is bit time."
hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator\n"
line.long 0x4 "UART_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x4 29. "BAUDM1,Divider X Enable Bit\nNote: In IrDA mode this bit must be disabled." "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1 but.."
bitfld.long 0x4 28. "BAUDM0,Divider X Equal 1\nNote: Refer to section 'UART Controller Baud Rate Generator' for more information." "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
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hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Divider X\n"
hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider."
group.long 0x30++0x3
line.long 0x0 "UART_FUNSEL,UART Function Select Register"
bitfld.long 0x0 0.--1. "FUN_SEL,Function Selection\n" "0: UART function mode,1: Reserved,?,?"
tree.end
tree.end
tree "WDT (Watchdog Timer)"
base ad:0x40004000
group.long 0x0++0x7
line.long 0x0 "WDT_CTL,WDT Control Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x0 8.--10. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 24 * WDT_CLK,1: 26 * WDT_CLK,?,?,?,?,?,?"
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bitfld.long 0x0 7. "WDTEN,WDT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: WDT Disabled (This action will reset the..,1: WDT Enabled"
bitfld.long 0x0 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register." "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x0 5. "WKF,WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: This bit is write protected"
bitfld.long 0x0 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT time-out..,1: This bit is write protected"
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bitfld.long 0x0 3. "IF,WDT Time-out Interrupt Flag\nThis bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
bitfld.long 0x0 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
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bitfld.long 0x0 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write-protected." "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
bitfld.long 0x0 0. "RSTCNT,Reset WDT Up Counter (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit will be automatically cleared by hardware." "0: No effect,1: This bit is write protected"
line.long 0x4 "WDT_ALTCTL,WDT Alternative Control Register"
bitfld.long 0x4 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened. User can select a suitable setting of.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: This bit is write protected,2: This register will be reset to 0 if WDT time-out..,?"
tree.end
tree "WWDT (Window Watchdog Timer)"
base ad:0x40004100
wgroup.long 0x0++0x3
line.long 0x0 "WWDT_RLDCNT,WWDT Reload Counter Register"
hexmask.long 0x0 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.."
group.long 0x4++0x7
line.long 0x0 "WWDT_CTL,WWDT Control Register"
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
hexmask.long.byte 0x0 16.--21. 1. "CMPDAT,WWDT Window Compare Bits\nSet this register to adjust the valid reload window. \nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT register.."
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hexmask.long.byte 0x0 8.--11. 1. "PSCSEL,WWDT Counter Prescale Period Select Bits\n"
bitfld.long 0x0 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU.\n" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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bitfld.long 0x0 0. "WWDTEN,WWDT Enable Bit\nSet this bit to enable WWDT counter counting.\n" "0: WWDT counter is stopped,1: WWDT counter is starting counting"
line.long 0x4 "WWDT_STATUS,WWDT Status Register"
bitfld.long 0x4 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it." "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it." "0: No effect,1: WWDT counter value matches CMPDAT"
rgroup.long 0xC++0x3
line.long 0x0 "WWDT_CNT,WWDT Counter Value Register"
hexmask.long.byte 0x0 0.--5. 1. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value."
tree.end
AUTOINDENT.OFF
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