31582 lines
2.3 MiB
31582 lines
2.3 MiB
; --------------------------------------------------------------------------------
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; @Title: iMX51 On-Chip Peripherals
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; @Props: Released
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; @Author: ADI, FIL, KRU, MPO, PAC
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; @Changelog:
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; 2009-03-12
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; 2009-12-08
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; 2010-04-12
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; @Manufacturer: NXP
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; @Doc: MX51_UsersGuide.pdf (Rev. 0.3); MCIMX51RM.pdf
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; MCIMX51RM_new.pdf (Rev. 1 - 2010-02)
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; @Core: Cortex-A8
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: permcimx51.per 7912 2017-06-06 08:29:07Z askoncej $
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config 16. 8.
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width 0xb
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tree "Core Registers (Cortex-A8)"
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup c15:0x0--0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x100--0x100
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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textline " "
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup c15:0x200--0x200
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line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "ARMv6,ARMv6,ARMv6,ARMv6,ARMv7,ARMv6,ARMv6,ARMv6"
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bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x300--0x300
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line.long 0x0 "TLBTR,TLB Type Register"
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hexmask.long.byte 0x0 16.--23. 0x1 " ITLBLOCK ,Specifies the number of instruction TLB lockable entries"
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hexmask.long.byte 0x0 8.--15. 0x1 " DTLBLOCK ,Specifies the number of unified or data TLB lockable entries"
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bitfld.long 0x0 0. " S ,Unified or Separate TLBs" "Unified,Separate"
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rgroup c15:0x400--0x400
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line.long 0x0 "MPUTR,MPU type register"
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rgroup c15:0x500--0x500
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitniy Level 2"
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hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitniy Level 1"
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hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitniy Level 0"
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textline " "
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rgroup c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
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rgroup c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
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rgroup c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup c15:0x0010++0x00
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line.long 0x00 "PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup c15:0x0110++0x00
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line.long 0x00 "PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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textline " "
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rgroup c15:0x0210++0x00
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line.long 0x00 "DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
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rgroup c15:0x0310++0x00
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line.long 0x00 "AFR0,Auxiliary Feature Register 0"
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hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group c15:0x1--0x1
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
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bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
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textline " "
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group c15:0x101--0x101
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 31. " L2RD ,L2 hardware reset disable" "Enable,Disable"
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bitfld.long 0x00 30. " L1RD ,L1 hardware reset disable" "Enable,Disable"
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textline " "
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bitfld.long 0x00 18. " CPISEL ,CP14/CP15 instruction serialization" "No,Yes"
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bitfld.long 0x00 17. " CPWAI ,CP14/CP15 wait on idle" "No,Yes"
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bitfld.long 0x00 16. " CPFL ,CP14/CP15 pipeline flush" "No,Yes"
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textline " "
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bitfld.long 0x00 15. " FETMCLK ,Force ETM clock" "No,Yes"
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bitfld.long 0x00 14. " FNCLK ,Force NEON clock" "No,Yes"
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bitfld.long 0x00 13. " FMCLK ,Force main clock" "No,Yes"
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textline " "
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bitfld.long 0x00 12. " FNSI ,Force NEON single issue" "No,Yes"
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bitfld.long 0x00 11. " FLSSI ,Force load/store single issue" "No,Yes"
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bitfld.long 0x00 10. " FSI ,Force single issue" "No,Yes"
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textline " "
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bitfld.long 0x00 9. " PLDNOP ,PLD executes as NOP" "Execute,NOP"
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bitfld.long 0x00 8. " WFINOP ,WFI executes as NOP" "Execute,NOP"
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textline " "
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bitfld.long 0x00 7. " DBSM ,Disable branch size mispredicts" "Enable,Disable"
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bitfld.long 0x00 6. " IBE ,Invalidate BTB Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 5. " L1NEON ,NEON Data Caching Within the L1 Data Cache Enable" "Disable,Enable"
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bitfld.long 0x00 4. " ASA ,Speculative Accesses on AXI Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 3. " L1PE ,L1 Cache Parity Detection Enable" "Disable,Enable"
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bitfld.long 0x00 1. " L2EN ,L2 Cache Enable" "Disable,Enable"
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bitfld.long 0x00 0. " L1ALIAS ,L1 Data Cache Hardware Alias Checks Enable" "Enable,Disable"
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group c15:0x201--0x201
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line.long 0x0 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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group c15:0x11--0x11
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line.long 0x0 "SCR,Secure Configuration Register"
|
|
bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
|
|
bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
|
|
bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
|
|
group c15:0x111--0x111
|
|
line.long 0x0 "SDER,Secure Debug Enable Register"
|
|
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
group c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " PLE ,PLE Registers Access in Nonsecure World" "Denied,Permitted"
|
|
bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CL ,Lockdown Entries Allocation Within the L2 Cache in Nonsecure World" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CP13 ,Coprocessor 13 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 12. " CP12 ,Coprocessor 12 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CP9 ,Coprocessor 9 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 8. " CP8 ,Coprocessor 8 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CP7 ,Coprocessor 7 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 6. " CP6 ,Coprocessor 6 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CP5 ,Coprocessor 5 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 4. " CP4 ,Coprocessor 4 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CP3 ,Coprocessor 3 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 2. " CP2 ,Coprocessor 2 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CP1 ,Coprocessor 1 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " CP0 ,Coprocessor 0 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
group c15:0x000c++0x00
|
|
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
|
|
group c15:0x10c--0x10c
|
|
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
|
|
textline " "
|
|
rgroup c15:0x1C--0x1C
|
|
line.long 0x0 "ISR,Interrupt status Register"
|
|
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
|
|
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
|
|
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
|
|
tree.end
|
|
width 0x0d
|
|
tree "Memory Management Unit"
|
|
width 8.
|
|
group c15:0x1--0x1
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
|
|
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
|
|
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
|
|
textline " "
|
|
group c15:0x3--0x3
|
|
line.long 0x0 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
group c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/decode,Reserved,Imprecise/parity/ECC,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/slave,?..."
|
|
group c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
group c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/parity,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,?..."
|
|
group c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
group c15:0x0015++0x00
|
|
line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register"
|
|
group c15:0x0115++0x00
|
|
line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register"
|
|
textline " "
|
|
group c15:0x002A--0x002A
|
|
line.long 0x00 "PMRRR,Primary Memory Region Remap Register"
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group c15:0x012A--0x012A
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
group c15:0x000d++0x00
|
|
line.long 0x00 "FCSEPID,FCSE PID Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " FCSEPID ,Process for Fast Context Switch Identification and Specification"
|
|
group c15:0x10d--0x10d
|
|
line.long 0x0 "CONTEXT,Context ID Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
|
|
group c15:0x020d++0x00
|
|
line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID"
|
|
group c15:0x030d++0x00
|
|
line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID"
|
|
group c15:0x040d++0x00
|
|
line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup c15:0x1100--0x1100
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
rgroup c15:0x1000--0x1000
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
|
|
group c15:0x2000--0x2000
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/unified,Instruction"
|
|
tree.end
|
|
width 0x8
|
|
tree "L2 Cache Control and Configuration"
|
|
group c15:0x1009++0x00
|
|
line.long 0x00 "L2CLR,L2 Cache Lockdown Register"
|
|
bitfld.long 0x00 7. " LOCK_way_7 ,Way 7 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LOCK_way_6 ,Way 6 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LOCK_way_5 ,Way 5 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOCK_way_4 ,Way 4 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LOCK_way_3 ,Way 3 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LOCK_way_2 ,Way 2 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCK_way_1 ,Way 1 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LOCK_way_0 ,Way 0 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
group c15:0x1209++0x00
|
|
line.long 0x00 "L2CACR,L2 Cache Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " ECCP ,ECC/Parity Selection" "Parity,ECC"
|
|
bitfld.long 0x00 27. " PLDFD ,PLD Forwarding to LS Request Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " PLDD ,PLD Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCD ,Write Combining Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " WADD ,External Linefill When Storing an Entire Line With Write Allocate Permission Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " WACD ,Combining of Data in the L2 Write Combining Buffers Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAD ,Allocate on Write Miss in L2 Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " PECCE ,Parity/ECC Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " L2I ,L2 Inner" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " TRAML ,Program Tag RAM Latency" "2 cycles,2 cycles,3 cycles,4 cycles,4 cycles,4 cycles,4 cycles,4 cycles"
|
|
bitfld.long 0x00 0.--3. " DRAML ,Program Data RAM Latency" "3 cycles,3 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,13 cycles,13 cycles,13 cycles"
|
|
textline " "
|
|
rgroup c15:0x000b++0x00
|
|
line.long 0x00 "PLEISR0,PLE Identification and Status Register 0"
|
|
bitfld.long 0x00 1. " CH1P ,Channel 1 Present" "Not present,Present"
|
|
bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present"
|
|
rgroup c15:0x010b++0x00
|
|
line.long 0x00 "PLEISR1,PLE Identification and Status Register 1"
|
|
bitfld.long 0x00 1. " CH1Q ,Channel 1 Queue" "Not queued,Queued"
|
|
bitfld.long 0x00 0. " CH0Q ,Channel 0 Queue" "Not queued,Queued"
|
|
rgroup c15:0x020b++0x00
|
|
line.long 0x00 "PLEISR2,PLE Identification and Status Register 2"
|
|
bitfld.long 0x00 1. " CH1R ,Channel 1 Run" "Not running,Running"
|
|
bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running"
|
|
rgroup c15:0x030b++0x00
|
|
line.long 0x00 "PLEISR3,PLE Identification and Status Register 3"
|
|
bitfld.long 0x00 1. " CH1I ,Channel 1 Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " CH0I ,Channel 0 Interrupt" "No interrupt,Interrupt"
|
|
group c15:0x001b++0x00
|
|
line.long 0x00 "PLEUAR,PLE User Accessibility Register"
|
|
bitfld.long 0x00 1. " U1 ,User Mode Process Access Registers for Channel 1 Permission" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted"
|
|
group c15:0x002b++0x00
|
|
line.long 0x00 "PLECNR,PLE Channel Number Register"
|
|
bitfld.long 0x00 0. " CN ,PLE Channel Selection" "Channel 0,Channel 1"
|
|
wgroup c15:0x003b++0x00
|
|
line.long 0x00 "PLEER0,PLE Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PLEE_STOP ,PLE Enable Stop"
|
|
wgroup c15:0x013b++0x00
|
|
line.long 0x00 "PLEER1,PLE Enable Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PLEE_START ,PLE Enable Start"
|
|
wgroup c15:0x023b++0x00
|
|
line.long 0x00 "PLEER2,PLE Enable Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PLEES_CLEAR ,PLE Enable Clear"
|
|
group c15:0x004b++0x00
|
|
line.long 0x00 "PLECR,PLE Control Register"
|
|
bitfld.long 0x00 30. " DT ,Transfer Direction" "Memory->cache,Cache->memory"
|
|
bitfld.long 0x00 29. " IC ,Interrupt on Completion of the PLE Transfer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IE ,Interrupt on an Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " UM ,Permission Checks Type" "Privileged,User"
|
|
bitfld.long 0x00 0.--2. " Wy ,L2 Cache Way for Filling Data" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7"
|
|
textline " "
|
|
group c15:0x005b++0x00
|
|
line.long 0x00 "PLEISAR,PLE Internal Start Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " PLEISA ,PLE Internal Start Address"
|
|
group c15:0x007b++0x00
|
|
line.long 0x00 "PLEIEAR,PLE Internal End Address Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " Lines ,Number of Cache Lines Transferred"
|
|
rgroup c15:0x008b++0x00
|
|
line.long 0x00 "PLECSR,PLE Channel Status Register"
|
|
hexmask.long.byte 0x00 2.--8. 1. " EC ,External Address Error Status"
|
|
bitfld.long 0x00 0.--1. " Status ,PLE Channel Status" "Idle,Queued,Running,Complete/error"
|
|
group c15:0x00fb++0x00
|
|
line.long 0x00 "PLECIDR,PLE Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,ASID Extension to Form the Process ID and Current Process Identification"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID of the Current Process and the Current ASID Identification"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group c15:0xC9--0xC9
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group c15:0x1C9--0x1C9
|
|
line.long 0x0 "CNTENS,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x2C9--0x2C9
|
|
line.long 0x0 "CNTENC,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x3C9--0x3C9
|
|
line.long 0x0 "FLAG,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group c15:0x4C9--0x4C9
|
|
line.long 0x0 "SWINCR,Software Increment Register"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group c15:0x5C9--0x5C9
|
|
line.long 0x0 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,..."
|
|
group c15:0xD9--0xD9
|
|
line.long 0x0 "PMCCNTR,Cycle Count Register"
|
|
group c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
line.long 0x00 "PMCNT,Performance Monitor Count Register"
|
|
group c15:0xE9--0xE9
|
|
line.long 0x0 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group c15:0x1E9--0x1E9
|
|
line.long 0x0 "INTENS,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group c15:0x2E9--0x2E9
|
|
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Debug Registers"
|
|
width 10.
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CONTEXT ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 10.
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DBGDSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
textline " "
|
|
width 10.
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
width 10.
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "DBGECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
|
|
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "CPUID,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
width 0xC
|
|
tree "Coresight Management Registers"
|
|
width 17.
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "DBGLAR,Lock Access Register"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
width 17.
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
width 17.
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DBGDEVTYPE,Device Type"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 7.
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 6.
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
tree.end
|
|
tree "ARM CORTEX Platform Control"
|
|
base ad:0x83fa0000
|
|
width 6.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PVID,Platform Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SPEC ,Major architectural or significant spec changes"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IMPL ,Implementation changes"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MINOR ,Minor changes"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ECO ,ECO changes"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPC,General Purpose Control Register"
|
|
bitfld.long 0x00 31. " DBGACTIVE ,Status of debug" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " NOCLKSTP ,Control clock-gating within the CORTEX-A8n" "Within the CORTEX-A8n,Normal"
|
|
bitfld.long 0x00 17. " ATRDY ,Platform boundary ATB interface disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
hexmask.long.word 0x00 0.--15. 1. " GPC ,General Purpose Control"
|
|
endif
|
|
sif (cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&cpu()!="IMX508"&&cpu()!="IMX507"&&cpu()!="IMX503"&&cpu()!="IMX502"&&cpu()!="IMX50")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PIC,Platform Internal Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PIC ,Platform Internal Control"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "LPC,Low Power Control Register"
|
|
bitfld.long 0x00 1. " DBGDSM ,Debug Deep Sleep Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSM ,Deep Sleep Mode Enable" "Disabled,Enabled"
|
|
line.long 0x04 "NLPC,NEON Low Power Control Register"
|
|
bitfld.long 0x04 0. " NEONRST ,Neon Reset State" "From reset,Into reset"
|
|
line.long 0x08 "ICGC,Internal Clock Generation Control Register"
|
|
bitfld.long 0x08 11. " DT_PRLD ,Debug AMBA Trace Bus Clock Down Counter Preload" "No effect,Forced"
|
|
bitfld.long 0x08 8.--10. " DT_CLK_DIVR ,Debug AMBA Trace Bus Clock Divide Ratio" "1:1,2:1,3:1,4:1,5:1,6:1,7:1,8:1"
|
|
bitfld.long 0x08 7. " ACLK_PRLD ,AXI Master Port Clock Down Counter Preload" "No effect,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " ACLK_DIVR ,AXI Master Port Clock Divide Ratio" "1:1,2:1,3:1,4:1,5:1,6:1,7:1,8:1"
|
|
bitfld.long 0x08 3. " IPG_PRLD ,Platform IP-Bus Port Clock Down Counter Preload" "No effect,Forced"
|
|
bitfld.long 0x08 0.--2. " IPG_CLK_DIVR ,Platform IP-Bus Port Clock Divide Ratio" "1:1,2:1,3:1,4:1,5:1,6:1,7:1,8:1"
|
|
line.long 0x0C "AMC,ARM Memory Configuration Register"
|
|
bitfld.long 0x0C 3. " ALPEN ,ALP Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0.--2. " ALP ,Memory leakage configuration" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "NMC,NEON Monitor Control Register"
|
|
bitfld.long 0x00 31. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " NME ,NEON Monitor Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--19. 1. " PL ,Preload value for the upper 8 bits of the 16 bit NEON activity counter"
|
|
line.long 0x04 "NMS,NEON Monitor Status Register"
|
|
eventfld.long 0x04 31. " NI ,NEON Idle Status" "Not expired,Expired"
|
|
width 0xb
|
|
tree.end
|
|
tree.open "TIGER DEBUG"
|
|
tree "DAP ROM"
|
|
base ad:0x60000000
|
|
width 9.
|
|
rgroup.long 0xfd0++0x03
|
|
line.long 0x00 "PERID4,Peripheral ID4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID3 Register"
|
|
line.long 0x10 "COMPID0,Component ID0 Register"
|
|
line.long 0x14 "COMPID1,Component ID1 Register"
|
|
line.long 0x18 "COMPID2,Component ID2 Register"
|
|
line.long 0x1c "COMPID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "CSCTI0"
|
|
base ad:0x60004000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTICONTROL,CTICONTROL Register"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CTIINTACK,CTIINTACK Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTIAPPSET,CTIAPPSET Register"
|
|
wgroup.long 0x18++0x07
|
|
line.long 0x00 "CTIAPPCLEAR,CTIAPPCLEAR Register"
|
|
line.long 0x04 "CTIAPPPULSE,CTIAPPPULSE Register"
|
|
group.long 0x20++0x01f
|
|
line.long 0x0 "CTIINEN0,CTIINEN Register 0"
|
|
line.long 0x4 "CTIINEN1,CTIINEN Register 1"
|
|
line.long 0x8 "CTIINEN2,CTIINEN Register 2"
|
|
line.long 0xC "CTIINEN3,CTIINEN Register 3"
|
|
line.long 0x10 "CTIINEN4,CTIINEN Register 4"
|
|
line.long 0x14 "CTIINEN5,CTIINEN Register 5"
|
|
line.long 0x18 "CTIINEN6,CTIINEN Register 6"
|
|
line.long 0x1C "CTIINEN7,CTIINEN Register 7"
|
|
group.long 0xa0++0x1f
|
|
line.long 0x0 "CTIOUTEN0,CTIOUTEN Register 0"
|
|
line.long 0x4 "CTIOUTEN1,CTIOUTEN Register 1"
|
|
line.long 0x8 "CTIOUTEN2,CTIOUTEN Register 2"
|
|
line.long 0xC "CTIOUTEN3,CTIOUTEN Register 3"
|
|
line.long 0x10 "CTIOUTEN4,CTIOUTEN Register 4"
|
|
line.long 0x14 "CTIOUTEN5,CTIOUTEN Register 5"
|
|
line.long 0x18 "CTIOUTEN6,CTIOUTEN Register 6"
|
|
line.long 0x1C "CTIOUTEN7,CTIOUTEN Register 7"
|
|
rgroup.long 0x130++0x0f
|
|
line.long 0x00 "CTITRIGINSTATUS,CTITRIGINSTATUS Register"
|
|
line.long 0x04 "CTITRIGOUTSTATUS,CTITRIGOUTSTATUS Register"
|
|
line.long 0x08 "CTICHINSTATUS,CTICHINSTATUS Register"
|
|
line.long 0x0c "CTICHOUTSTATUS,CTICHOUTSTATUS Register"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CGR,Channel gate Register"
|
|
line.long 0x04 "EMCR,External multiplexor control Register"
|
|
wgroup.long 0xedc++0x0f
|
|
line.long 0x00 "ITCHINACK,ITCHINACK Register"
|
|
line.long 0x04 "ITTRIGINACK,ITTRIGINACK Register"
|
|
line.long 0x08 "ITCHOUT,ITCHOUT Register"
|
|
line.long 0x0c "ITTRIGOUT,ITTRIGOUT Register"
|
|
rgroup.long 0xeec++0x0f
|
|
line.long 0x00 "ITCHOUTACK,ITCHOUTACK Register"
|
|
line.long 0x04 "ITTRIGOUTACK,ITTRIGOUTACK Register"
|
|
line.long 0x08 "ITCHIN,ITCHIN Register"
|
|
line.long 0x0c "ITTRIGIN,ITTRIGIN Register"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "ITCTRL,ITCTRL Register"
|
|
group.long 0xfa0++0x07
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
line.long 0x04 "CTCR,Claim Tag Clear Register"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
rgroup.long 0xfc8++0x0b
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DTIR,Device Type Identifier Register"
|
|
line.long 0x08 "PERID4,Peripheral ID 4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID 0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID 1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID 2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID 3 Register"
|
|
line.long 0x10 "COMPID0,Component ID0 Register"
|
|
line.long 0x14 "COMPID1,Component ID1 Register"
|
|
line.long 0x18 "COMPID2,Component ID2 Register"
|
|
line.long 0x1C "COMPID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "CSCTI1"
|
|
base ad:0x60005000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTICONTROL,CTICONTROL Register"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CTIINTACK,CTIINTACK Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTIAPPSET,CTIAPPSET Register"
|
|
wgroup.long 0x18++0x07
|
|
line.long 0x00 "CTIAPPCLEAR,CTIAPPCLEAR Register"
|
|
line.long 0x04 "CTIAPPPULSE,CTIAPPPULSE Register"
|
|
group.long 0x20++0x01f
|
|
line.long 0x0 "CTIINEN0,CTIINEN Register 0"
|
|
line.long 0x4 "CTIINEN1,CTIINEN Register 1"
|
|
line.long 0x8 "CTIINEN2,CTIINEN Register 2"
|
|
line.long 0xC "CTIINEN3,CTIINEN Register 3"
|
|
line.long 0x10 "CTIINEN4,CTIINEN Register 4"
|
|
line.long 0x14 "CTIINEN5,CTIINEN Register 5"
|
|
line.long 0x18 "CTIINEN6,CTIINEN Register 6"
|
|
line.long 0x1C "CTIINEN7,CTIINEN Register 7"
|
|
group.long 0xa0++0x1f
|
|
line.long 0x0 "CTIOUTEN0,CTIOUTEN Register 0"
|
|
line.long 0x4 "CTIOUTEN1,CTIOUTEN Register 1"
|
|
line.long 0x8 "CTIOUTEN2,CTIOUTEN Register 2"
|
|
line.long 0xC "CTIOUTEN3,CTIOUTEN Register 3"
|
|
line.long 0x10 "CTIOUTEN4,CTIOUTEN Register 4"
|
|
line.long 0x14 "CTIOUTEN5,CTIOUTEN Register 5"
|
|
line.long 0x18 "CTIOUTEN6,CTIOUTEN Register 6"
|
|
line.long 0x1C "CTIOUTEN7,CTIOUTEN Register 7"
|
|
rgroup.long 0x130++0x0f
|
|
line.long 0x00 "CTITRIGINSTATUS,CTITRIGINSTATUS Register"
|
|
line.long 0x04 "CTITRIGOUTSTATUS,CTITRIGOUTSTATUS Register"
|
|
line.long 0x08 "CTICHINSTATUS,CTICHINSTATUS Register"
|
|
line.long 0x0c "CTICHOUTSTATUS,CTICHOUTSTATUS Register"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CGR,Channel gate Register"
|
|
line.long 0x04 "EMCR,External multiplexor control Register"
|
|
wgroup.long 0xedc++0x0f
|
|
line.long 0x00 "ITCHINACK,ITCHINACK Register"
|
|
line.long 0x04 "ITTRIGINACK,ITTRIGINACK Register"
|
|
line.long 0x08 "ITCHOUT,ITCHOUT Register"
|
|
line.long 0x0c "ITTRIGOUT,ITTRIGOUT Register"
|
|
rgroup.long 0xeec++0x0f
|
|
line.long 0x00 "ITCHOUTACK,ITCHOUTACK Register"
|
|
line.long 0x04 "ITTRIGOUTACK,ITTRIGOUTACK Register"
|
|
line.long 0x08 "ITCHIN,ITCHIN Register"
|
|
line.long 0x0c "ITTRIGIN,ITTRIGIN Register"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "ITCTRL,ITCTRL Register"
|
|
group.long 0xfa0++0x07
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
line.long 0x04 "CTCR,Claim Tag Clear Register"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
rgroup.long 0xfc8++0x0b
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DTIR,Device Type Identifier Register"
|
|
line.long 0x08 "PERID4,Peripheral ID 4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID 0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID 1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID 2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID 3 Register"
|
|
line.long 0x10 "COMPID0,Component ID0 Register"
|
|
line.long 0x14 "COMPID1,Component ID1 Register"
|
|
line.long 0x18 "COMPID2,Component ID2 Register"
|
|
line.long 0x1C "COMPID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "CSCTI2"
|
|
base ad:0x60006000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTICONTROL,CTICONTROL Register"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CTIINTACK,CTIINTACK Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTIAPPSET,CTIAPPSET Register"
|
|
wgroup.long 0x18++0x07
|
|
line.long 0x00 "CTIAPPCLEAR,CTIAPPCLEAR Register"
|
|
line.long 0x04 "CTIAPPPULSE,CTIAPPPULSE Register"
|
|
group.long 0x20++0x01f
|
|
line.long 0x0 "CTIINEN0,CTIINEN Register 0"
|
|
line.long 0x4 "CTIINEN1,CTIINEN Register 1"
|
|
line.long 0x8 "CTIINEN2,CTIINEN Register 2"
|
|
line.long 0xC "CTIINEN3,CTIINEN Register 3"
|
|
line.long 0x10 "CTIINEN4,CTIINEN Register 4"
|
|
line.long 0x14 "CTIINEN5,CTIINEN Register 5"
|
|
line.long 0x18 "CTIINEN6,CTIINEN Register 6"
|
|
line.long 0x1C "CTIINEN7,CTIINEN Register 7"
|
|
group.long 0xa0++0x1f
|
|
line.long 0x0 "CTIOUTEN0,CTIOUTEN Register 0"
|
|
line.long 0x4 "CTIOUTEN1,CTIOUTEN Register 1"
|
|
line.long 0x8 "CTIOUTEN2,CTIOUTEN Register 2"
|
|
line.long 0xC "CTIOUTEN3,CTIOUTEN Register 3"
|
|
line.long 0x10 "CTIOUTEN4,CTIOUTEN Register 4"
|
|
line.long 0x14 "CTIOUTEN5,CTIOUTEN Register 5"
|
|
line.long 0x18 "CTIOUTEN6,CTIOUTEN Register 6"
|
|
line.long 0x1C "CTIOUTEN7,CTIOUTEN Register 7"
|
|
rgroup.long 0x130++0x0f
|
|
line.long 0x00 "CTITRIGINSTATUS,CTITRIGINSTATUS Register"
|
|
line.long 0x04 "CTITRIGOUTSTATUS,CTITRIGOUTSTATUS Register"
|
|
line.long 0x08 "CTICHINSTATUS,CTICHINSTATUS Register"
|
|
line.long 0x0c "CTICHOUTSTATUS,CTICHOUTSTATUS Register"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CGR,Channel gate Register"
|
|
line.long 0x04 "EMCR,External multiplexor control Register"
|
|
wgroup.long 0xedc++0x0f
|
|
line.long 0x00 "ITCHINACK,ITCHINACK Register"
|
|
line.long 0x04 "ITTRIGINACK,ITTRIGINACK Register"
|
|
line.long 0x08 "ITCHOUT,ITCHOUT Register"
|
|
line.long 0x0c "ITTRIGOUT,ITTRIGOUT Register"
|
|
rgroup.long 0xeec++0x0f
|
|
line.long 0x00 "ITCHOUTACK,ITCHOUTACK Register"
|
|
line.long 0x04 "ITTRIGOUTACK,ITTRIGOUTACK Register"
|
|
line.long 0x08 "ITCHIN,ITCHIN Register"
|
|
line.long 0x0c "ITTRIGIN,ITTRIGIN Register"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "ITCTRL,ITCTRL Register"
|
|
group.long 0xfa0++0x07
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
line.long 0x04 "CTCR,Claim Tag Clear Register"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
rgroup.long 0xfc8++0x0b
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DTIR,Device Type Identifier Register"
|
|
line.long 0x08 "PERID4,Peripheral ID 4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID 0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID 1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID 2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID 3 Register"
|
|
line.long 0x10 "COMPID0,Component ID0 Register"
|
|
line.long 0x14 "COMPID1,Component ID1 Register"
|
|
line.long 0x18 "COMPID2,Component ID2 Register"
|
|
line.long 0x1C "COMPID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "CSCTI3"
|
|
base ad:0x60007000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTICONTROL,CTICONTROL Register"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "CTIINTACK,CTIINTACK Register"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CTIAPPSET,CTIAPPSET Register"
|
|
wgroup.long 0x18++0x07
|
|
line.long 0x00 "CTIAPPCLEAR,CTIAPPCLEAR Register"
|
|
line.long 0x04 "CTIAPPPULSE,CTIAPPPULSE Register"
|
|
group.long 0x20++0x01f
|
|
line.long 0x0 "CTIINEN0,CTIINEN Register 0"
|
|
line.long 0x4 "CTIINEN1,CTIINEN Register 1"
|
|
line.long 0x8 "CTIINEN2,CTIINEN Register 2"
|
|
line.long 0xC "CTIINEN3,CTIINEN Register 3"
|
|
line.long 0x10 "CTIINEN4,CTIINEN Register 4"
|
|
line.long 0x14 "CTIINEN5,CTIINEN Register 5"
|
|
line.long 0x18 "CTIINEN6,CTIINEN Register 6"
|
|
line.long 0x1C "CTIINEN7,CTIINEN Register 7"
|
|
group.long 0xa0++0x1f
|
|
line.long 0x0 "CTIOUTEN0,CTIOUTEN Register 0"
|
|
line.long 0x4 "CTIOUTEN1,CTIOUTEN Register 1"
|
|
line.long 0x8 "CTIOUTEN2,CTIOUTEN Register 2"
|
|
line.long 0xC "CTIOUTEN3,CTIOUTEN Register 3"
|
|
line.long 0x10 "CTIOUTEN4,CTIOUTEN Register 4"
|
|
line.long 0x14 "CTIOUTEN5,CTIOUTEN Register 5"
|
|
line.long 0x18 "CTIOUTEN6,CTIOUTEN Register 6"
|
|
line.long 0x1C "CTIOUTEN7,CTIOUTEN Register 7"
|
|
rgroup.long 0x130++0x0f
|
|
line.long 0x00 "CTITRIGINSTATUS,CTITRIGINSTATUS Register"
|
|
line.long 0x04 "CTITRIGOUTSTATUS,CTITRIGOUTSTATUS Register"
|
|
line.long 0x08 "CTICHINSTATUS,CTICHINSTATUS Register"
|
|
line.long 0x0c "CTICHOUTSTATUS,CTICHOUTSTATUS Register"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CGR,Channel gate Register"
|
|
line.long 0x04 "EMCR,External multiplexor control Register"
|
|
wgroup.long 0xedc++0x0f
|
|
line.long 0x00 "ITCHINACK,ITCHINACK Register"
|
|
line.long 0x04 "ITTRIGINACK,ITTRIGINACK Register"
|
|
line.long 0x08 "ITCHOUT,ITCHOUT Register"
|
|
line.long 0x0c "ITTRIGOUT,ITTRIGOUT Register"
|
|
rgroup.long 0xeec++0x0f
|
|
line.long 0x00 "ITCHOUTACK,ITCHOUTACK Register"
|
|
line.long 0x04 "ITTRIGOUTACK,ITTRIGOUTACK Register"
|
|
line.long 0x08 "ITCHIN,ITCHIN Register"
|
|
line.long 0x0c "ITTRIGIN,ITTRIGIN Register"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "ITCTRL,ITCTRL Register"
|
|
group.long 0xfa0++0x07
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
line.long 0x04 "CTCR,Claim Tag Clear Register"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
rgroup.long 0xfc8++0x0b
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DTIR,Device Type Identifier Register"
|
|
line.long 0x08 "PERID4,Peripheral ID 4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID 0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID 1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID 2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID 3 Register"
|
|
line.long 0x10 "COMPID0,Component ID0 Register"
|
|
line.long 0x14 "COMPID1,Component ID1 Register"
|
|
line.long 0x18 "COMPID2,Component ID2 Register"
|
|
line.long 0x1C "COMPID3,Component ID3 Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "TPIU"
|
|
base ad:0x60003000
|
|
width 0xb
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SPSR,Supported port sizes Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CPCR,Current port size Register"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "STMR,Supported trigger modes Register"
|
|
group.long 0x104++0x07
|
|
line.long 0x00 "TCVR,Trigger counter value Register"
|
|
line.long 0x04 "TMR,Trigger multiplier Register"
|
|
rgroup.long 0x200++0x07
|
|
line.long 0x00 "STPMR,Supported test pattern/modes Register"
|
|
line.long 0x04 "CTPMR,Current test pattern/mode Register"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "TPRCR,Test pattern repeat counter Register"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "FFSR,Formatter flush and status Register"
|
|
group.long 0x304++0x07
|
|
line.long 0x00 "FFCR,Fomatter flush and control Register"
|
|
line.long 0x04 "FSCR,Formatter synchronization counter Register"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "EIPR,EXTCTL In Port Register"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "EOPR,EXTCTL Out Port Register"
|
|
wgroup.long 0xee4++0x0f
|
|
line.long 0x00 "ITTRFLINACK,Integration Register"
|
|
line.long 0x04 "ITTRFLIN,Integration Register"
|
|
line.long 0x08 "ITATBDATA0,Integration Register"
|
|
line.long 0x0c "ITATBCTR2,Integration Register"
|
|
rgroup.long 0xef4++0x07
|
|
line.long 0x00 "ITATBCTR1,Integration Register"
|
|
line.long 0x04 "ITATBCTR0,Integration Register"
|
|
group.long 0xf00++0x03
|
|
line.long 0x00 "ITATBCTR0,Integration Register"
|
|
group.long 0xfa0++0x07
|
|
line.long 0x00 "CTSR,Claim Tag Set Register"
|
|
line.long 0x04 "CTCR,Claim Tag Clear Register"
|
|
wgroup.long 0xfb0++0x03
|
|
line.long 0x00 "LAR,Lock Access Register"
|
|
rgroup.long 0xfb4++0x07
|
|
line.long 0x00 "LSR,Lock Status Register"
|
|
line.long 0x04 "ASR,Authentication Status Register"
|
|
rgroup.long 0xfc8++0x0b
|
|
line.long 0x00 "DEVID,Device ID Register"
|
|
line.long 0x04 "DTIR,Device Type Identifier Register"
|
|
line.long 0x08 "PERID4,Peripheral ID 4 Register"
|
|
rgroup.long 0xfe0++0x1f
|
|
line.long 0x00 "PERID0,Peripheral ID 0 Register"
|
|
line.long 0x04 "PERID1,Peripheral ID 1 Register"
|
|
line.long 0x08 "PERID2,Peripheral ID 2 Register"
|
|
line.long 0x0c "PERID3,Peripheral ID 3 Register"
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|
line.long 0x10 "COMPID0,Component ID0 Register"
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|
line.long 0x14 "COMPID1,Component ID1 Register"
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|
line.long 0x18 "COMPID2,Component ID2 Register"
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|
line.long 0x1C "COMPID3,Component ID3 Register"
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|
width 0xb
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|
tree.end
|
|
tree.end
|
|
tree "CCM (Clock Controller Module)"
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|
base ad:0x73fd4000
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|
width 9.
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|
group.long 0x00++0x07
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line.long 0x00 "CCR,CCM Control Register"
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|
bitfld.long 0x00 12. " COSC_EN ,On chip oscillator enable" "Disabled,Enabled"
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|
bitfld.long 0x00 11. " FPM_MULT ,Controlls the multiplicatin of fpm" "*512,*1024"
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|
textline " "
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bitfld.long 0x00 10. " CAMP2_EN ,CAMP2 Enable" "Disabled,Enabled"
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|
bitfld.long 0x00 9. " CAMP1_EN ,CAMP1 Enable" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x00 8. " FPM_EN ,FPM Enable" "Disabled,Enabled"
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|
hexmask.long.byte 0x00 0.--7. 1. " OSCNT ,Oscillator ready counter value"
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line.long 0x04 "CCDR,CCM Control Divider Register"
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|
bitfld.long 0x04 17. " IPU_HS_MASK ,During load_dividers procedure mask handshake with ipu module" "Not masked,Masked"
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|
bitfld.long 0x04 16. " EMI_HS_MASK ,During load_dividers procedure mask handshake with emi module" "Not masked,Masked"
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|
rgroup.long 0x08++0x03
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|
line.long 0x00 "CSR,CCM Status Register"
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|
bitfld.long 0x00 5. " COSC_READY ,Status indication of on board oscillator" "Not ready,Ready"
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|
bitfld.long 0x00 4. " LVS_VALUE ,Status of the value of pll_lvs output of ccm" "0,1"
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|
textline " "
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|
bitfld.long 0x00 3. " CAMP2_READY ,Status indication of camp2" "Not ready,Ready"
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|
bitfld.long 0x00 2. " CAMP1_READY ,Status indication of camp1" "Not ready,Ready"
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|
textline " "
|
|
bitfld.long 0x00 1. " FPM_READY ,Status indication of fpm" "Not ready,Ready"
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|
bitfld.long 0x00 0. " REF_EN_B ,Status of the value of ref_en_b output of ccm" "0,1"
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|
group.long 0x0c++0x27
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|
line.long 0x00 "CCSR,CCM Clock Switcher Register"
|
|
bitfld.long 0x00 9. " LP_APM ,Low Power Audio Playback source clock selection" "Oscillator,FPM"
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bitfld.long 0x00 7.--8. " STEP_SEL ,Step frequency when shifting ARM frequency" "Source 4,Pll bypass,Divided pll2,Divided pll3"
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|
textline " "
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|
bitfld.long 0x00 5.--6. " PLL2_DIV_PODF ,Divider for pll2 clock" "/1,/2,/3,/4"
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|
bitfld.long 0x00 3.--4. " PLL3_DIV_PODF ,Divider for pll3 clock" "/1,/2,/3,/4"
|
|
textline " "
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|
bitfld.long 0x00 2. " PLL1_SW_CLK_SEL ,Selects source to generate pll1_sw_clk" "Pll1_main_clk,Step_clk"
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|
bitfld.long 0x00 1. " PLL2_SW_CLK_SEL ,Selects source to generate pll2_sw_clk" "Pll2_main_clk,Pll2 bypass"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PLL3_SW_CLK_SEL ,Selects source to generate pll3_sw_clk" "Pll3_main_clk,Pll3 bypass"
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line.long 0x04 "CACRR,CCM Arm Clock Root Register"
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|
bitfld.long 0x04 0.--2. " ARM_PODF ,Divider for ARM clock root" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x08 "CBCDR,CCM Bus Clock Divider Register"
|
|
bitfld.long 0x08 30. " DDR_HIGH_FREQ_CLK_SEL ,Selector for DDR main clock" "DDR mux clock,PLL1 clock"
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bitfld.long 0x08 27.--29. " DDR_CLK_PODF ,Divider for DDR podf" "/1,/2,/3,/4,/5,/6,/7,/8"
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|
textline " "
|
|
bitfld.long 0x08 26. " EMI_CLK_SEL ,Selector for emi clock group" "Dvfs divider,Ahb clock root"
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|
bitfld.long 0x08 25. " PERIPH_CLK_SEL ,Selector for peripheral main clock" "pll2_sw_clk,periph_apm_clk"
|
|
textline " "
|
|
bitfld.long 0x08 22.--24. " EMI_SLOW_PODF ,Divider for emi slow podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x08 19.--21. " AXI_B_PODF ,Divider for axi b podf" "/1,/2,/3,/4,/5,/6,/7,/8"
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|
textline " "
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|
bitfld.long 0x08 16.--18. " AXI_A_PODF ,Divider for axi a podf" "/1,/2,/3,/4,/5,/6,/7,/8"
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|
bitfld.long 0x08 13.--15. " NFC_PODF ,Divider for nfc podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
bitfld.long 0x08 10.--12. " AHB_PODF ,Divider for ahb podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x08 8.--9. " IPG_PODF ,Divider for ipg podf" "/1,/2,/3,/4"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " PERCLK_PRED1 ,Divider for perclk pred1" "/1,/2,/3,/4"
|
|
bitfld.long 0x08 3.--5. " PERCLK_PRED2 ,Divider for perclk pred2" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
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|
bitfld.long 0x08 0.--2. " PERCLK_PODF ,Divider for perclk podf" "/1,/2,/3,/4,/5,/6,/7,/8"
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|
width 9.
|
|
line.long 0x0c "CBCMR,CCM Bus Clock Multiplexer Register"
|
|
bitfld.long 0x0c 16.--17. " GPU2D_CLK_SEL ,Selector for gpu2d clock multiplexer" "Axi a,Axi b,Emi_slow_clk_root,Ahb clock root"
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|
bitfld.long 0x0C 14.--15. " VPU_AXI_CLK_SEL ,Selector for VPU axi clock multiplexer" "Axi a,Axi b,Emi_slow_clk_root,Ahb clock root"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PERIPH_APM_SEL ,Selector for peripheral clock multiplexer" "Pll1_sw_clk,Pll3_sw_clk,Lp_apm,?..."
|
|
bitfld.long 0x0C 10.--11. " DDR_CLK_SEL ,Selector for ddr clock multiplexer" "Axi a,Axi b,Emi_slow_clk_root,Ahb clock root"
|
|
textline " "
|
|
bitfld.long 0x0C 8.--9. " ARM_AXI_CLK_SEL ,Selector for ARM axi clock multiplexer" "Axi a,Axi b,Emi_slow_clk_root,Ahb clock root"
|
|
bitfld.long 0x0C 6.--7. " IPU_HSP_CLK_SEL ,Selector for ipu hsp clock multiplexer" "Axi a,Axi b,Emi_slow_clk_root,Ahb clock root"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " GPU_CLK_SEL ,Selector for gpu clock multiplexer" "Axi a,Axi b,Emi_slow_clk_root,Ahb clock root"
|
|
bitfld.long 0x0C 2.--3. " DEBUG_APB_CLK_SEL ,Selector for debug apb clock multiplexer" "Axi a,Axi b,Emi_slow_clk_root,Ahb clock root"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " PERCLK_LP_APM_SEL ,Peripherals main clock/lp_apm selection" "Peripherals main clock,Lp_apm"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " PERCLK_IPG_SEL ,Selector for perclk multiplexer" "Division of pll frequency,Ipg_clk"
|
|
line.long 0x10 "CSCMR1,CCM Serial Clock Multiplexer Register 1"
|
|
bitfld.long 0x10 30.--31. " SSI_EXT2_CLK_SEL ,Selector for ssi_ext2 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Ssi_lp_apm_clk"
|
|
bitfld.long 0x10 28.--29. " SSI_EXT1_CLK_SEL ,Selector for ssi_ext1 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Ssi_lp_apm_clk"
|
|
textline " "
|
|
bitfld.long 0x10 26. " USB_PHY_CLK_SEL ,Selector for usb_phy clock multiplexer" "Oscillator,Div. out. of PLL3"
|
|
bitfld.long 0x10 24.--25. " UART_CLK_SEL ,Selector for uart clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
|
|
textline " "
|
|
bitfld.long 0x10 22.--23. " USBOH3_CLK_SEL ,Selector for usboh3 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
|
|
bitfld.long 0x10 20.--21. " ESDHC1_CLK_SEL ,Selector for esdhc1 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
|
|
textline " "
|
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bitfld.long 0x10 19. " ESDHC3_CLK_SEL ,Selector for esdhc3 clock multiplexer" "Esdhc1_clk_sel,Esdhc2_clk_sel"
|
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bitfld.long 0x10 18. " ESDHC4_CLK_SEL ,Selector for esdhc4 clock multiplexer" "Esdhc1_clk_sel,Esdhc2_clk_sel"
|
|
textline " "
|
|
bitfld.long 0x10 16.--17. " ESDHC2_CLK_SEL ,Selector for esdhc2 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
|
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bitfld.long 0x10 14.--15. " SSI1_CLK_SEL ,Selector for ssi1 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Ssi_lp_apm_clk"
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textline " "
|
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bitfld.long 0x10 12.--13. " SSI2_CLK_SEL ,Selector for ssi2 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Ssi_lp_apm_clk"
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bitfld.long 0x10 11. " SSI3_CLK_SEL ,Selector for ssi3 clock multiplexer" "Ssi1_clk_root,Ssi2_clk_root"
|
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textline " "
|
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bitfld.long 0x10 10. " VPU_RCLK_SEL ,Selector for vpu_rclk clock multiplexer" "Osc_clk,Ckih_camp1_clk"
|
|
textline " "
|
|
bitfld.long 0x10 8.--9. " SSI_APM_CLK_SEL ,Controlls the multiplexer for the ssi_lp_apm_clk clock generation" "CAMP1 of CKIH,LP-APM clk. sel. out,CAMP2 of CKIH2,?..."
|
|
textline " "
|
|
bitfld.long 0x10 7. " TVE_CLK_SEL ,Controlls the multiplexer for the tve clock generation" "PLL3 div. clk,External clk src"
|
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textline " "
|
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bitfld.long 0x10 6. " TVE_EXT_CLK_SEL ,Controlls the multiplexer for the tve external clock input" "Oscillator out,CKIh through CAMP1"
|
|
textline " "
|
|
bitfld.long 0x10 4.--5. " ECSPI_CLK_SEL ,Selector for ecspi clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
|
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bitfld.long 0x10 2.--3. " SPDIF_XTAL_CLK_SEL ,Controlls the multiplexer for the spdif_xtal_clk clock generation" "Oscillator out,CAMP1 of CKIH,CAMP2 of CKIH2,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1. " SSI_EXT2_COM ,Controlls the multiplexer to communize ssi_ext2 clock generation based on ssi2 clock root" "Dividers,Ssi2_clk_root"
|
|
bitfld.long 0x10 0. " SSI_EXT1_COM ,Controlls the multiplexer to communize ssi_ext1 clock generation based on ssi1 clock root" "Dividers,Ssi1_clk_root"
|
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line.long 0x14 "CSCMR2,CCM Serial Clock Multiplexer Register 2"
|
|
bitfld.long 0x14 29.--31. " DI1_CLK_SEL ,Selector for DI1 clock multiplexer" "Divided pll3,Oscillator,Ckih camp1 clock,Tve_di_clock,Ipp_di1_clk,?..."
|
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bitfld.long 0x14 26.--28. " DI0_CLK_SEL ,Selector for di clock multiplexer" "Divided pll3,Oscillator,Ckih camp1 clock,Tve_di_clock,Ipp_di0_clk,?..."
|
|
textline " "
|
|
bitfld.long 0x14 14.--15. " HSI2C_CLK_SEL ,Selector for hsi2c clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
|
|
bitfld.long 0x14 12.--13. " FIRI_CLK_SEL ,Selector for firi clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
|
|
textline " "
|
|
bitfld.long 0x14 10.--11. " SIM_CLK_SEL ,Selector for sim clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Lp_apm clock"
|
|
bitfld.long 0x14 5. " SPDIF1_COM ,Controlls the multiplexer to communize spdif1 clock generation based on ssi2 clock root" "Dividers,Ssi2_clk_root"
|
|
textline " "
|
|
bitfld.long 0x14 4. " SPDIF0_COM ,Controlls the multiplexer to communize spdif0 clock generation based on ssi1 clock root" "Dividers,Ssi1_clk_root"
|
|
bitfld.long 0x14 2.--3. " SPDIF1_CLK_SEL ,Selector for spdif1 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Spdif_xtal_clk"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " SPDIF0_CLK_SEL ,Selector for spdif0 clock multiplexer" "Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Spdif_xtal_clk"
|
|
width 9.
|
|
line.long 0x18 "CSCDR1,CCM Serial Clock Divider Register 1"
|
|
bitfld.long 0x18 22.--24. " ESDHC2_CLK_PRED ,Divider for esdhc2 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x18 19.--21. " ESDHC2_CLK_PODF ,Divider for esdhc2 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " ESDHC1_CLK_PRED ,Divider for esdhc1 clock pred" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x18 14.--15. " PGC_CLK_PODF ,Divider for pgc (power gating controler) clock podf" "/1,/2,/4,/8"
|
|
textline " "
|
|
bitfld.long 0x18 11.--13. " ESDHC1_CLK_PODF ,Divider for esdhc1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x18 8.--10. " USBOH3_CLK_PRED ,Divider for usboh3 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
bitfld.long 0x18 6.--7. " USBOH3_CLK_PODF ,Divider for usboh3 clock podf" "/1,/2,/3,/4"
|
|
bitfld.long 0x18 3.--5. " UART_CLK_PRED ,Divider for uart clock pred" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " UART_CLK_PODF ,Divider for uart clock podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
line.long 0x1c "CS1CDR,CCM SSI1 Clock Divider Register"
|
|
bitfld.long 0x1C 22.--24. " SSI_EXT1_CLK_PRED ,Divider for ssi_ext1 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x1C 16.--21. " SSI_EXT1_CLK_PODF ,Divider for ssi_ext1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
textline " "
|
|
bitfld.long 0x1C 6.--8. " SSI1_CLK_PRED ,Divider for ssi1 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x1C 0.--5. " SSI1_CLK_PODF ,Divider for ssi1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
line.long 0x20 "CS2CDR,CCM SSI2 Clock Divider Register"
|
|
bitfld.long 0x20 22.--24. " SSI_EXT2_CLK_PRED ,Divider for ssi_ext2 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x20 16.--21. " SSI_EXT2_CLK_PODF ,Divider for ssi_ext2 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
textline " "
|
|
bitfld.long 0x20 6.--8. " SSI2_CLK_PRED ,Divider for ssi2 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x20 0.--5. " SSI2_CLK_PODF ,Divider for ssi2 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
line.long 0x24 "CDCDR,CCM DI Clock Divider Register"
|
|
bitfld.long 0x24 28.--30. " TVE_CLK_PRED ,Divider for tve clock pred" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x24 25.--27. " SPDIF0_CLK_PRED ,Divider for spdif0 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
bitfld.long 0x24 19.--24. " SPDIF0_CLK_PODF ,Divider for spdif0 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
bitfld.long 0x24 16.--18. " SPDIF1_CLK_PRED ,Divider for spdif1 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
bitfld.long 0x24 9.--14. " SPDIF1_CLK_PODF ,Divider for spdif1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
bitfld.long 0x24 6.--8. " DI_CLK_PRED ,Divider for di clock pred" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
textline " "
|
|
bitfld.long 0x24 3.--5. " USB_PHY_PRED ,Divider for usb_phy clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
|
|
bitfld.long 0x24 0.--2. " USB_PHY_PODF ,Divider for usb_phy clock podf" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
group.long 0x38++0x0f
|
|
line.long 0x00 "CSCDR2,CCM Serial Clock Divider Register 2"
|
|
bitfld.long 0x00 25.--27. " ECSPI_CLK_PRED ,Divider for ecspi clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x00 19.--24. " ECSPI_CLK_PODF ,Divider for ecspi clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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textline " "
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bitfld.long 0x00 16.--18. " SIM_CLK_PRED ,Divider for sim clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x00 9.--14. " SIM_CLK_PODF ,Divider for sim clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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line.long 0x04 "CSCDR3,CCM Serial Clock Divider Register 3"
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bitfld.long 0x04 16.--18. " HSI2C_CLK_PRED ,Divider for sim clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x04 9.--14. " HSI2C_CLK_PODF ,Divider for sim clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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textline " "
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bitfld.long 0x04 6.--8. " FIRI_CLK_PRED ,Divider for firi clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x04 0.--5. " FIRI_CLK_PODF ,Divider for firi clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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line.long 0x08 "CSCDR4,CCM Serial Clock Divider Register 4"
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bitfld.long 0x08 16.--18. " CSI_MCLK2_CLK_PRED ,Divider for csi mclk2 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x08 9.--14. " CSI_MCLK2_CLK_PODF ,Divider for csi mclk2 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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textline " "
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bitfld.long 0x08 6.--8. " CSI_MCLK1_CLK_PRED ,Divider for csi mclk1 clock pred" "Reserved,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x08 0.--5. " CSI_MCLK1_CLK_PODF ,Divider for csi mclk1 clock podf" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
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line.long 0x0c "CWDR,CCM Wakeup Detector Register"
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bitfld.long 0x0c 21. " GPIO1_9_DIR ,Defines direction of gpio 1_9" "Input,Output"
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bitfld.long 0x0c 20. " GPIO1_8_DIR ,Defines direction of gpio 1_8" "Input,Output"
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textline " "
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bitfld.long 0x0c 19. " GPIO1_7_DIR ,Defines direction of gpio 1_7" "Input,Output"
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bitfld.long 0x0c 18. " GPIO1_6_DIR ,Defines direction of gpio 1_6" "Input,Output"
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textline " "
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bitfld.long 0x0c 17. " GPIO1_5_DIR ,Defines direction of gpio 1_5" "Input,Output"
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bitfld.long 0x0c 16. " GPIO1_4_DIR ,Defines direction of gpio 1_4" "Input,Output"
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textline " "
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bitfld.long 0x0c 10.--11. " GPIO1_9_ICR ,Interrupt sensitivity configuration bits for gpio1_9" "Low level,High level,Rise edge,Fall edge"
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bitfld.long 0x0c 8.--9. " GPIO1_8_ICR ,Interrupt sensitivity configuration bits for gpio1_8" "Low level,High level,Rise edge,Fall edge"
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textline " "
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bitfld.long 0x0c 6.--7. " GPIO1_7_ICR ,Interrupt sensitivity configuration bits for gpio1_7" "Low level,High level,Rise edge,Fall edge"
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bitfld.long 0x0c 4.--5. " GPIO1_6_ICR ,Interrupt sensitivity configuration bits for gpio1_6" "Low level,High level,Rise edge,Fall edge"
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textline " "
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bitfld.long 0x0c 2.--3. " GPIO1_5_ICR ,Interrupt sensitivity configuration bits for gpio1_5" "Low level,High level,Rise edge,Fall edge"
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bitfld.long 0x0c 0.--1. " GPIO1_4_ICR ,Interrupt sensitivity configuration bits for gpio1_4" "Low level,High level,Rise edge,Fall edge"
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rgroup.long 0x48++0x03
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line.long 0x00 "CDHIPR,CCM Divider Handshake In-Process Register"
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bitfld.long 0x00 16. " ARM_PODF_BUSY ,Busy indicator for arm_podf" "Not busy,Busy"
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bitfld.long 0x00 8. " DDR_HIGH_FREQ_CLK_SEL_BUSY ,Busy indicator for ddr_high_freq_clk_sel mux control" "Not busy,Busy"
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textline " "
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bitfld.long 0x00 7. " DDR_PODF_BUSY ,Busy indicator for ddr_podf" "Not busy,Busy"
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bitfld.long 0x00 6. " EMI_CLK_SEL_BUSY ,Busy indicator for emi_clk_sel" "Not busy,Busy"
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textline " "
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bitfld.long 0x00 5. " PERIPH_CLK_SEL_BUSY ,Busy indicator for periph_clk_sel mux control" "Not busy,Busy"
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bitfld.long 0x00 4. " NFC_PODF_BUSY ,Busy indicator for nfc_podf" "Not busy,Busy"
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textline " "
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bitfld.long 0x00 3. " AHB_PODF_BUSY ,Busy indicator for ahb_podf" "Not busy,Busy"
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bitfld.long 0x00 2. " EMI_SLOW_PODF_BUSY ,Busy indicator for emi_slow_podf" "Not busy,Busy"
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textline " "
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bitfld.long 0x00 1. " AXI_B_PODF_BUSY ,Busy indicator for axi_b_podf" "Not busy,Busy"
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bitfld.long 0x00 0. " AXI_A_PODF_BUSY ,Busy indicator for axi_a_podf" "Not busy,Busy"
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width 9.
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group.long 0x4c++0x3b
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line.long 0x00 "CDCR,CCM DVFS Control Register"
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eventfld.long 0x00 7. " SW_PERIPH_CLK_DIV_REQ_STATUS ,Status bit to define the operation of DVFS driver in case of software control of DVFS divider" "Not finished,Finished"
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textline " "
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bitfld.long 0x00 6. " SW_PERIPH_CLK_DIV_REQ ,Start DVFS frequency division operation" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 5. " SOFTWARE_DVFS_EN ,Software DVFS Enabled" "Periph_clk_div_req,Sw_periph_clk_div_req"
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textline " "
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bitfld.long 0x00 2. " ARM_FREQ_SHIFT_DIVIDER ,ARM domain done through" "Pll relock,Arm_podf change"
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textline " "
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bitfld.long 0x00 0.--1. " PERIPH_CLK_DVFS_PODF ,Divider value for next operation of peripheral dvfs" "Reserved,/2,/3,/4"
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line.long 0x04 "CTOR,CCM Testing Observability Register"
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bitfld.long 0x04 13. " OBS_EN ,Observability enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 8.--12. " OBS_SPARE_OUTPUT_0_SEL ,Selection of the signal to be generated on obs_output_0 for observability on the pads" "Ccm_system_in_stop_mode,Lpm_current_state[0],Hndsk_current_state[0],Shd_current_state[0],Ccm_ipg_stop,Ccm_pdn_4arm_req,Emi_freq_change_req,Ipu_freq_change_req,Reserved,Reserved,Pll_lrf_sticky1,Fpm_lrf,Clk_src_on,Ipu_lpsr_wakeup_ack,Src_warm_dvfs_req,Periph_clk_div_req,Arm_clk_switch_req,Ccm_clk_switch_ack,Ipu_clk_changed,Emi_lpmd,Emi_lpmd_fast,Emi_lpmd_int1,Emi_lpmd_slow,Reserved,Reserved,Reserved,Obs_input_0,Obs_input_1,Obs_input_2,Obs_input_3,Obs_input_4,Obs_input_5"
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textline " "
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bitfld.long 0x04 4.--7. " OBS_SPARE_OUTPUT_1_SEL ,Selection of the signal to be generated on obs_output_1 for observability on the pads" "Ccm_system_in_wait_mode,Lpm_current_state[1],Hndsk_current_state[1],Ccm_fpm_en,Ccm_ipg_wait,Ccm_camp_dis,Dpll_en_dpllip,Ccm_pdn_4all_req,Emi_freq_change_ack,Ipu_freq_change_ack,Reserved,Reserved,Arm_dsm_request,Ccm_lpsr_ipu,Gpc_pup_ack,Pll_lrf_sticky2"
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textline " "
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bitfld.long 0x04 0.--3. " OBS_SPARE_OUTPUT_2_SEL ,Selection of the signal to be generated on obs_output_2 for observability on the pads" "Ccm_int_mem_ipg_stop,Lpm_current_state[2],Hndsk_current_state[2],Shd_current_state[1],Pll_lvs,Src_clock_ready,Ref_clk_en_dpllip,Ccm_pup_req,Emi_lpack,Emi_lpack_fast,Emi_lpack_slow,Emi_lpack_int1,Src_power_gating_reset_done,Tzic_dsm_wakeup,Gpc_pdn_ack,Pll_lrf_sticky3"
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line.long 0x08 "CLPCR,CCM Low Power Control Register"
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bitfld.long 0x08 22. " BYPASS_SCC_LPM_HS ,Bypass handshake with scc on next entrance to stop mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 21. " BYPASS_MAX_LPM_HS ,Bypass handshake with max on next entrance to low power mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 20. " BYPASS_SDMA_LPM_HS ,Bypass handshake with sdma on next entrance to low power mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 19. " BYPASS_EMI_LPM_HS ,Bypass handshake with emi on next entrance to low power mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 18. " BYPASS_IPU_LPM_HS ,Bypass handshake with ipu on next entrance to low power mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 17. " BYPASS_RTIC_LPM_HS ,Bypass handshake with rtic on next entrance to low power mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 16. " BYPASS_SAHARA_LPM_HS ,Bypass handshake with sahara on next entrance to low power mode" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 12. " APM_SDMA_CLK_GATE_EN_BIT ,APM SDMA Automatic Clock Gating Enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x08 11. " COSC_PWRDOWN ,Control powering down of on chip oscillator" "Not powered down,Powered down"
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textline " "
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bitfld.long 0x08 9.--10. " STBY_COUNT ,Standby counter definition" "2 ckil clocks,4 ckil clocks,8 ckil clocks,16 ckil clocks"
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textline " "
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bitfld.long 0x08 8. " VSTBY ,Voltage standby request" "Not requested,Requested"
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textline " "
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bitfld.long 0x08 7. " DIS_REF_OSC ,External reference oscillator clock disable" "No,Yes"
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textline " "
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bitfld.long 0x08 6. " SBYOS ,Standby clock oscillator" "Enabled/Not powered down,Disabled/Powered down"
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textline " "
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bitfld.long 0x08 5. " ARM_CLK_DIS_ON_LPM ,ARM clocks disabled on wait mode" "No,Yes"
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textline " "
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bitfld.long 0x08 3.--4. " LPSR_CLK_SEL ,Controlls the mux to select the lpsr_clk_root generation" "Reserved,Fpm,Fpm/2,GND"
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textline " "
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bitfld.long 0x08 2. " BYPASS_PMIC_VFUNCTIONAL_READY ,Bypass pmic vfunctional" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x08 0.--1. " LPM ,Low power mode" "Remain in run mode,Transfer to wait mode,Transfer to stop mode,Transfer to LPSR mode"
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line.long 0x0c "CISR,CCM Interrupt Status Register"
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eventfld.long 0x0C 26. " ARM_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of arm_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 25. " DDR_HIGH_FREQ_CLK_SEL_LOADED ,Interrupt ipi_int_1 generated due to update of ddr_high_freq_clk_sel" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 24. " DDR_CLK_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of ddr_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 23. " EMI_CLK_SEL_LOADED ,Interrupt ipi_int_1 generated due to update of emi_clk_sel" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 22. " PERIPH_CLK_SEL_LOADED ,Interrupt ipi_int_1 generated due to update of periph_clk_sel" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 21. " NFC_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of nfc_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 20. " AHB_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of ahb_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 19. " EMI_SLOW_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of emi_slow_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 18. " AXI_B_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of axi_b_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 17. " AXI_A_PODF_LOADED ,Interrupt ipi_int_1 generated due to frequency change of axi_a_podf" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 16. " DIVIDERS_LOADED ,Interrupt ipi_int_1 generated due to updated of axi_a_podf/axi_b_podf/emi_slow_podf/ahb_podf/nfc_podf/periph_clk_sel/emi_clk_sel" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 15. " GPIO1_9_WAKEUP_DET ,Interrupt ipi_int_2 generated due to change of gpio1_9 input" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 14. " GPIO1_8_WAKEUP_DET ,Interrupt ipi_int_2 generated due to change of gpio1_8 input" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 13. " GPIO1_7_WAKEUP_DET ,Interrupt ipi_int_2 generated due to change of gpio1_7 input" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 12. " GPIO1_6_WAKEUP_DET ,Interrupt ipi_int_2 generated due to change of gpio1_6 input" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 11. " GPIO1_5_WAKEUP_DET ,Interrupt ipi_int_2 generated due to change of gpio1_5 input" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 10. " GPIO1_4_WAKEUP_DET ,Interrupt ipi_int_2 generated due to change of gpio1_4 input" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 9. " SDHC2_WAKEUP_DET ,Interrupt ipi_int_2 generated due to insertion of sdhc2 card" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 8. " SDHC1_WAKEUP_DET ,Interrupt ipi_int_2 generated due to insertion of sdhc1 card" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 7. " KPP_WAKEUP_DET ,Interrupt ipi_int_2 generated due to key press detection" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 6. " COSC_READY ,Interrupt ipi_int_2 generated due to on board oscillator ready" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 5. " CAMP2_READY ,Interrupt ipi_int_2 generated due to camp2 ready" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 4. " CAMP1_READY ,Interrupt ipi_int_2 generated due to camp1 ready" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 3. " FPM_READY ,Interrupt ipi_int_2 generated due to fpm ready" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 2. " LRF_PLL3 ,Interrupt ipi_int_2 generated due to lock of pll3" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 1. " LRF_PLL2 ,Interrupt ipi_int_2 generated due to lock of pll2" "No interrupt,Interrupt"
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textline " "
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eventfld.long 0x0C 0. " LRF_PLL1 ,Interrupt ipi_int_2 generated due to lock of pll1" "No interrupt,Interrupt"
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line.long 0x10 "CIMR,CCM Interrupt Mask Register"
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bitfld.long 0x10 26. " MASK_ARM_PODF_LOADED ,Mask interrupt generation due to frequency change of arm_podf" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 25. " MASK_DDR_HIGH_FREQ_CLK_SEL_LOADED ,Mask interrupt generation due to update of ddr_high_freq_clk_sel" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 24. " MASK_DDR_PODF_LOADED ,mask interrupt generation due to frequency change of ddr_podf" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 23. " MASK_EMI_CLK_SEL_LOADED ,Mask interrupt generation due to update of emi_clk_sel" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 22. " MASK_PERIPH_CLK_SEL_LOADED ,Mask interrupt generation due to update of periph_clk_sel" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 21. " MASK_NFC_PODF_LOADED ,Mask interrupt generation due to frequency change of nfc_podf or ipg_int_mem_podf" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 20. " MASK_AHB_PODF_LOADED ,Mask interrupt generation due to frequency change of ahb_podf" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 19. " MASK_EMI_SLOW_PODF_LOADED ,Mask interrupt generation due to frequency change of emi_slow_podf" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 18. " MASK_AXI_B_PODF_LOADED ,Mask interrupt generation due to frequency change of axi_b_podf" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 17. " MASK_AXI_A_PODF_LOADED ,Mask interrupt generation due to frequency change of axi_a_podf" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 16. " MASK_DIVIDERS_LOADED ,Mask interrupt generation due to updated of axi_a_podf, axi_b_podf, emi_slow_podf, ahb_podf, nfc_podf, periph_clk_sel, emi_clk_sel" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 15. " MASK_GPIO1_9_WAKEUP_DET ,Mask Interrupt generated due to change of gpio1_9 input" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 14. " MASK_GPIO1_8_WAKEUP_DET ,Mask Interrupt generated due to change of gpio1_8 input" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 13. " MASK_GPIO1_7_WAKEUP_DET ,Mask Interrupt generated due to change of gpio1_7 input" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 12. " MASK_GPIO1_6_WAKEUP_DET ,Mask Interrupt generated due to change of gpio1_6 input" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 11. " MASK_GPIO1_5_WAKEUP_DET ,Mask Interrupt generated due to change of gpio1_5 input" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 10. " MASK_GPIO1_4_WAKEUP_DET ,Mask Interrupt generated due to change of gpio1_4 input" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 9. " MASK_SDHC2_WAKEUP_DET ,Mask Interrupt generation due to insertion of sdhc2 card" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 8. " MASK_SDHC1_WAKEUP_DET ,Mask Interrupt generation due to insertion of sdhc1 card" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 7. " MASK_KPP_WAKEUP_DET ,Mask interrupt generation due to key press detection" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 6. " MASK_COSC_READY ,Mask interrupt generation due to on board oscillator ready" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 5. " MASK_CAMP2_READY ,Mask interrupt generation due to camp2 ready" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 4. " MASK_CAMP1_READY ,Mask interrupt generation due to camp1 ready" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 3. " MASK_FPM_READY ,Mask interrupt generation due to fpm ready" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 2. " MASK_LRF_PLL3 ,Mask interrupt generation due to lrf of pll3" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 1. " MASK_LRF_PLL2 ,Mask interrupt generation due to lrf of pll2" "Not masked,Masked"
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textline " "
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bitfld.long 0x10 0. " MASK_LRF_PLL1 ,Mask interrupt generation due to lrf of pll1" "Not masked,Masked"
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width 9.
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line.long 0x14 "CCOSR,CCM Clock Output Source Register"
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bitfld.long 0x14 24. " CKO2_EN ,Enable of CKO2 clock" "Disabled,Enabled"
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bitfld.long 0x14 21.--23. " CKO2_DIV ,Setting the divider of CKO2" "/1,/2,/3,/4,/5,/6,/7,/8"
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textline " "
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bitfld.long 0x14 16.--20. " CKO2_SEL ,Selection of the clock to be generated on cko2" "Dptc_core,Dptc_periph,Reserved,Esdhc1_mshc1_clk_root,Usboh3_clk_root,Wrck_clk _root,Cspi_clk_root,Pll1_ref_clk,Esdhc3_clk_root,Ddr_clk_root,Arm_axi_clk_root,Usbphy_pll_out_480,Vpu_rclk_root,Ipu_hsp_clk_root,Osc_clk,Ckih_CAMP1_clk,Fpm_clk,Esdhc2_clk_root,Ssi1_clk_root,Ssi2_clk_root,Reserved,Reserved,Lpsr_clk_root,Pgc_clk_root,Tve_ext_clk,Usb_phy_clk_root,Tve_216_54_clk_root,Lp_apm clock,Uart_clk_root,Spdif0_clk_root,Spdif1_clk_root,Spare_input_1 div 8"
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bitfld.long 0x14 7. " CKO1_EN ,Enable of CKO1 clock" "Disabled,Enabled"
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textline " "
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bitfld.long 0x14 4.--6. " CKO1_DIV ,Setting the divider of CKO1" "/1,/2,/3,/4,/5,/6,/7,/8"
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bitfld.long 0x14 0.--3. " CKO1_SEL ,Selection of the clock to be generated on cko1" "Arm_clk_root,Pll1_sw_clk,Pll2_sw_clk,Pll3_sw_clk,Emi_core_clk_root,Reserved,Enfc_clk_root,Reserved,Di_clk_root,Reserved,Reserved,Ahb_clk_root,Ipg_clk_root,Perclk_root,Ckil_sync_clk_root,?..."
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width 9.
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line.long 0x18 "CGPR,CCM General Purpose Register"
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bitfld.long 0x18 23. " ARM_ASYNC_REF_EN ,Enable of ARM async ref circuit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 22. " ARM_ASYNC_REF_SEL[7] ,Bit 7 of frequency select of async refrence circuit" "Arm_async_ref_sel,Refer. num. 7"
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textline " "
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bitfld.long 0x18 21. " ARM_ASYNC_REF_SEL[6] ,Bit 6 of frequency select of async refrence circuit" "Arm_async_ref_sel,Refer. num. 6"
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textline " "
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bitfld.long 0x18 20. " ARM_ASYNC_REF_SEL[4] ,Bit 4 of frequency select of async refrence circuit" "Arm_async_ref_sel,Refer. num. 4"
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|
textline " "
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bitfld.long 0x18 19. " ARM_ASYNC_REF_SEL[3] ,Bit 3 of frequency select of async refrence circuit" "Arm_async_ref_sel,Refer. num. 3"
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|
textline " "
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bitfld.long 0x18 18. " ARM_ASYNC_REF_SEL[2] ,Bit 2 of frequency select of async refrence circuit" "Arm_async_ref_sel,Refer. num. 2"
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textline " "
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bitfld.long 0x18 17. " ARM_ASYNC_REF_SEL[1] ,Bit 1of frequency select of async refrence circuit" "Arm_async_ref_sel,Refer. num. 1"
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textline " "
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bitfld.long 0x18 16. " ARM_ASYNC_REF_SEL[0] ,Bit 0 of frequency select of async refrence circuit" "Arm_async_ref_sel,Refer. num. 0"
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textline " "
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bitfld.long 0x18 15. " ARM_ASYNC_REF_SEL[5] ,Bit 5 of frequency select of async refrence circuit" "Arm_async_ref_sel,Refer. num. 5"
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textline " "
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|
bitfld.long 0x18 5. " OVERIDE_APM_EMI_INTR_CLOCK_GATING ,Override of the automatic clock gating control of EMI clock" "Not gated,Gated"
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|
textline " "
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|
bitfld.long 0x18 4. " EFUSE_PROG_SUPPLY_GATE ,Value of the output signal cgpr_dout[4]" "Not gated,Gated"
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textline " "
|
|
bitfld.long 0x18 3. " FPM_MUX_SELECT ,Value of the output signal cgpr_dout[3] going to fpm" "0,1"
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width 9.
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|
line.long 0x1c "CCGR0,CCM Clock Gating Register 0"
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bitfld.long 0x1C 30.--31. " CG15 ,Clock gating for power reduction of iim clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x1C 28.--29. " CG14 ,Clock gating for power reduction of ahb_max clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x1C 26.--27. " CG13 ,Clock gating for power reduction of aips_tz2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x1C 24.--25. " CG12 ,Clock gating for power reduction of aips_tz1 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
textline " "
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|
bitfld.long 0x1C 22.--23. " CG11 ,Clock gating for power reduction of rom clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x1C 20.--21. " CG10 ,Clock gating for power reduction of romcp clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x1C 18.--19. " CG09 ,Clock gating for power reduction of ahbmux2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
bitfld.long 0x1C 16.--17. " CG08 ,Clock gating for power reduction of ahbmux1 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
textline " "
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|
bitfld.long 0x1C 14.--15. " CG07 ,Clock gating for power reduction of cti3 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x1C 12.--13. " CG06 ,Clock gating for power reduction of cti2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x1C 10.--11. " CG05 ,Clock gating for power reduction of tpiu clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x1C 8.--9. " CG04 ,Clock gating for power reduction of dap clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
textline " "
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|
bitfld.long 0x1C 6.--7. " CG03 ,Clock gating for power reduction of tzic (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
bitfld.long 0x1C 4.--5. " CG02 ,Clock gating for power reduction of arm_debug (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
bitfld.long 0x1C 2.--3. " CG01 ,Clock gating for power reduction of arm_axi (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
bitfld.long 0x1C 0.--1. " CG00 ,Clock gating for power reduction of arm_bus (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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line.long 0x20 "CCGR1,CCM Clock Gating Register 1"
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bitfld.long 0x20 30.--31. " CG15 ,Clock gating for power reduction of SCC clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 28.--29. " CG14 ,Clock gating for power reduction of firi serial clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 26.--27. " CG13 ,Clock gating for power reduction of firi ipg clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
bitfld.long 0x20 24.--25. " CG12 ,Clock gating for power reduction of hs2ic_serial clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
textline " "
|
|
bitfld.long 0x20 22.--23. " CG11 ,Clock gating for power reduction of hsi2c_ipg_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 20.--21. " CG10 ,Clock gating for power reduction of i2c2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 18.--19. " CG09 ,Clock gating for power reduction of i2c1 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 16.--17. " CG08 ,Clock gating for power reduction of uart3_perclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
textline " "
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|
bitfld.long 0x20 14.--15. " CG07 ,Clock gating for power reduction of uart3_ipg_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 12.--13. " CG06 ,Clock gating for power reduction of uart2_perclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 10.--11. " CG05 ,Clock gating for power reduction of uart2_ipg_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 8.--9. " CG04 ,Clock gating for power reduction of uart1_perclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
textline " "
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|
bitfld.long 0x20 6.--7. " CG03 ,Clock gating for power reduction of uart1_ipg_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 4.--5. " CG02 ,Clock gating for power reduction of tmax3 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 2.--3. " CG01 ,Clock gating for power reduction of tmax2 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x20 0.--1. " CG00 ,Clock gating for power reduction of tmax1 clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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line.long 0x24 "CCGR2,CCM Clock Gating Register 2"
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bitfld.long 0x24 30.--31. " CG15 ,Clock gating for power reduction of tve clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 28.--29. " CG14 ,Clock gating for power reduction of usboh3_60M (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 26.--27. " CG13 ,Clock gating for power reduction of usboh3_ipg_ahb (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 24.--25. " CG12 ,Clock gating for power reduction of fec clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
textline " "
|
|
bitfld.long 0x24 22.--23. " CG11 ,Clock gating for power reduction of owire clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 20.--21. " CG10 ,Clock gating for power reduction of gpt_highfreq (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 18.--19. " CG09 ,Clock gating for power reduction of gpt_ipg_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 16.--17. " CG08 ,Clock gating for power reduction of pwm2_highfreq (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
textline " "
|
|
bitfld.long 0x24 14.--15. " CG07 ,Clock gating for power reduction of pwm2_ipg_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 12.--13. " CG06 ,Clock gating for power reduction of pwm1_highfreq (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 10.--11. " CG05 ,Clock gating for power reduction of pwm1_ipg_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 8.--9. " CG04 ,Clock gating for power reduction of epit2_highfreq (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
textline " "
|
|
bitfld.long 0x24 6.--7. " CG03 ,Clock gating for power reduction of epit2_ipg_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 4.--5. " CG02 ,Clock gating for power reduction of epit1_highfreq (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 2.--3. " CG01 ,Clock gating for power reduction of epit1_ipg_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x24 0.--1. " CG00 ,Clock gating for power reduction of usb phy clock Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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line.long 0x28 "CCGR3,CCM Clock Gating Register 3"
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bitfld.long 0x28 30.--31. " CG15 ,Clock gating for power reduction of ssi_ext2 (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 28.--29. " CG14 ,Clock gating for power reduction of ssi_ext1 (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 26.--27. " CG13 ,Clock gating for power reduction of ssi3_ssi_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 24.--25. " CG12 ,Clock gating for power reduction of ssi3_ipg (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
textline " "
|
|
bitfld.long 0x28 22.--23. " CG11 ,Clock gating for power reduction of ssi2_ssi_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 20.--21. " CG10 ,Clock gating for power reduction of ssi2_ipg (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 18.--19. " CG09 ,Clock gating for power reduction of ssi1_ssi_clk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 16.--17. " CG08 ,Clock gating for power reduction of ssi1_ipg (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
textline " "
|
|
bitfld.long 0x28 14.--15. " CG07 ,Clock gating for power reduction of esdhc4_perclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 12.--13. " CG06 ,Clock gating for power reduction of esdhc4_ipg_hclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 10.--11. " CG05 ,Clock gating for power reduction of esdhc3_perclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 8.--9. " CG04 ,Clock gating for power reduction of esdhc3_ipg_hclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
textline " "
|
|
bitfld.long 0x28 6.--7. " CG03 ,Clock gating for power reduction of esdhc2_perclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 4.--5. " CG02 ,Clock gating for power reduction of esdhc2_ipg_hclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 2.--3. " CG01 ,Clock gating for power reduction of esdhc1_perclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x28 0.--1. " CG00 ,Clock gating for power reduction of esdhc1_ipg_hclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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line.long 0x2c "CCGR4,CCM Clock Gating Register 4"
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bitfld.long 0x2c 30.--31. " CG15 ,Clock gating for power reduction of sdma clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x2c 28.--29. " CG14 ,Clock gating for power reduction of srtc clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x2c 26.--27. " CG13 ,Clock gating for power reduction of cspi_ipg (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x2c 24.--25. " CG12 ,Clock gating for power reduction of ecspi2_perclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
textline " "
|
|
bitfld.long 0x2c 22.--23. " CG11 ,Clock gating for power reduction of ecspi2_ipg (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x2c 20.--21. " CG10 ,Clock gating for power reduction of ecspi1_perclk (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x2c 18.--19. " CG09 ,Clock gating for power reduction of ecspi1_ipg (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x2c 16.--17. " CG08 ,Clock gating for power reduction of rtic clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
textline " "
|
|
bitfld.long 0x2c 14.--15. " CG07 ,Clock gating for power reduction of sahara (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x2c 4.--5. " CG02 ,Clock gating for power reduction of sim serial clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
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bitfld.long 0x2c 2.--3. " CG01 ,Clock gating for power reduction of sim ipg clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x2c 0.--1. " CG00 ,Clock gating for power reduction of pata (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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line.long 0x30 "CCGR5,CCM Clock Gating Register 5"
|
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bitfld.long 0x30 30.--31. " CG15 ,Clock gating for power reduction of spdif ipg clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x30 28.--29. " CG14 ,Clock gating for power reduction of spdif1 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x30 26.--27. " CG13 ,Clock gating for power reduction of spdif0 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x30 24.--25. " CG12 ,Clock gating for power reduction of gpc ipg clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
textline " "
|
|
bitfld.long 0x30 22.--23. " CG11 ,Clock gating for power reduction of emi wrck clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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bitfld.long 0x30 20.--21. " CG10 ,Clock gating for power reduction of emi_enfc (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
bitfld.long 0x30 18.--19. " CG09 ,Clock gating for power reduction of emi_int1 (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
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|
bitfld.long 0x30 16.--17. " CG08 ,Clock gating for power reduction of emi_slow (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
textline " "
|
|
bitfld.long 0x30 14.--15. " CG07 ,Clock gating for power reduction of emi_fast (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x30 12.--13. " CG06 ,Clock gating for power reduction of ipmux1/ipmux2 (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x30 10.--11. " CG05 ,Clock gating for power reduction of ipu clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x30 8.--9. " CG04 ,Clock gating for power reduction of vpu reference clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
textline " "
|
|
bitfld.long 0x30 6.--7. " CG03 ,Clock gating for power reduction of vpu clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x30 4.--5. " CG02 ,Clock gating for power reduction of garb clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x30 2.--3. " CG01 ,Clock gating for power reduction of gpu clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x30 0.--1. " CG00 ,Clock gating for power reduction of spba clocks (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
line.long 0x34 "CCGR6,CCM Clock Gating Register 6"
|
|
bitfld.long 0x34 14.--15. " CG07 ,Clock gating for power reduction of gpu2d clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x34 12.--13. " CG06 ,Clock gating for power reduction of ipu di1 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x34 10.--11. " CG05 ,Clock gating for power reduction of ipu di0 clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x34 8.--9. " CG04 ,Clock gating for power reduction of emi_garb (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
textline " "
|
|
bitfld.long 0x34 6.--7. " CG03 ,Clock gating for power reduction of CSI mclk2 (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x34 4.--5. " CG02 ,Clock gating for power reduction of CSI mclk1 (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x34 2.--3. " CG01 ,Clock gating for power reduction of slimbus serial clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
bitfld.long 0x34 0.--1. " CG00 ,Clock gating for power reduction of slimbus clock (Run/Wait/Stop)" "Off/Off/Off,On/Off/Off,Reserved,On/On/Off"
|
|
width 9.
|
|
line.long 0x38 "CMEOR,CCM Module Enable Override Register"
|
|
bitfld.long 0x38 23. " MOD_EN_OV_EMI_M7 ,Overide clock enable signal from emi_m7" "Not overridden,Overridden"
|
|
bitfld.long 0x38 22. " MOD_EN_OV_EMI_M6 ,Overide clock enable signal from emi_m6" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x38 21. " MOD_EN_OV_EMI_M5 ,Overide clock enable signal from emi_m5" "Not overridden,Overridden"
|
|
bitfld.long 0x38 20. " MOD_EN_OV_EMI_M4 ,Overide clock enable signal from emi_m4" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x38 19. " MOD_EN_OV_EMI_M3 ,Overide clock enable signal from emi_m3" "Not overridden,Overridden"
|
|
bitfld.long 0x38 18. " MOD_EN_OV_EMI_M2 ,Overide clock enable signal from emi_m2" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x38 17. " MOD_EN_OV_EMI_M1 ,Overide clock enable signal from emi_m1" "Not overridden,Overridden"
|
|
bitfld.long 0x38 16. " MOD_EN_OV_EMI_M0 ,Overide clock enable signal from emi_m0" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x38 15. " MOD_EN_OV_EMI_INT1 ,Overide clock enable signal from emi_int1" "Not overridden,Overridden"
|
|
bitfld.long 0x38 14. " MOD_EN_OV_EMI_SLOW ,Overide clock enable signal from emi_slow" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x38 13. " MOD_EN_OV_EMI_FAST ,Overide clock enable signal from emi_fast" "Not overridden,Overridden"
|
|
bitfld.long 0x38 12. " MOD_EN_OV_EMI_GARB ,Overide clock enable signal from emi_garb" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x38 10. " MOD_EN_OV_GPU2D ,Overide clock enable signal from gpu2d" "Not overridden,Overridden"
|
|
bitfld.long 0x38 9. " MOD_EN_OV_VPU ,Overide clock enable signal from vpu" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x38 8. " MOD_EN_OV_DAP ,Overide clock enable signal from dap" "Not overridden,Overridden"
|
|
bitfld.long 0x38 7. " MOD_EN_OV_GPU ,Overide clock enable signal from gpu" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x38 6. " MOD_EN_OV_EPIT ,Overide clock enable signal from epit" "Not overridden,Overridden"
|
|
bitfld.long 0x38 5. " MOD_EN_OV_GPT ,Overide clock enable signal from gpt" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x38 4. " MOD_EN_OV_ESDHC ,Overide clock enable signal from esdhc" "Not overridden,Overridden"
|
|
bitfld.long 0x38 3. " MOD_EN_OV_IIM ,Overide clock enable signal from iim-" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.long 0x38 2. " MOD_EN_OV_OWIRE ,Overide clock enable signal from owire" "Not overridden,Overridden"
|
|
bitfld.long 0x38 0. " MOD_EN_OV_SAHARA ,Overide clock enable signal from sahara" "Not overridden,Overridden"
|
|
width 0xb
|
|
tree.end
|
|
tree "MAX (Multi-Layer AHB Crossbar Switch)"
|
|
base ad:0x83f94000
|
|
width 8.
|
|
if (((per.long(ad:0x83f94000+0x10))&0x80000000)==0x00)
|
|
group.long 0x00++0x3 "Slave Port 0"
|
|
line.long 0x00 "MPR0,Master Priority Register 0"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SGPCR0,General Purpose Control Register 0"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
else
|
|
rgroup.long 0x00++0x3 "Slave Port 0"
|
|
line.long 0x00 "MPR0,Master Priority Register 0"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "SGPCR0,General Purpose Control Register 0"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
endif
|
|
if (((per.long(ad:0x83f94000+0x110))&0x80000000)==0x00)
|
|
group.long 0x100++0x3 "Slave Port 1"
|
|
line.long 0x00 "MPR1,Master Priority Register 1"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "SGPCR1,General Purpose Control Register 1"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
else
|
|
rgroup.long 0x100++0x3 "Slave Port 1"
|
|
line.long 0x00 "MPR1,Master Priority Register 1"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
rgroup.long 0x110++0x3
|
|
line.long 0x00 "SGPCR1,General Purpose Control Register 1"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
endif
|
|
if (((per.long(ad:0x83f94000+0x210))&0x80000000)==0x00)
|
|
group.long 0x200++0x3 "Slave Port 2"
|
|
line.long 0x00 "MPR2,Master Priority Register 2"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
group.long 0x210++0x3
|
|
line.long 0x00 "SGPCR2,General Purpose Control Register 2"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
else
|
|
rgroup.long 0x200++0x3 "Slave Port 2"
|
|
line.long 0x00 "MPR2,Master Priority Register 2"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x00 "SGPCR2,General Purpose Control Register 2"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
endif
|
|
if (((per.long(ad:0x83f94000+0x310))&0x80000000)==0x00)
|
|
group.long 0x300++0x3 "Slave Port 3"
|
|
line.long 0x00 "MPR3,Master Priority Register 3"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
group.long 0x310++0x3
|
|
line.long 0x00 "SGPCR3,General Purpose Control Register 3"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
else
|
|
rgroup.long 0x300++0x3 "Slave Port 3"
|
|
line.long 0x00 "MPR3,Master Priority Register 3"
|
|
bitfld.long 0x00 24.--26. " MSTR_6 ,Master 6 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 20.--22. " MSTR_5 ,Master 5 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 16.--18. " MSTR_4 ,Master 4 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 12.--14. " MSTR_3 ,Master 3 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " MSTR_2 ,Master 2 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 4.--6. " MSTR_1 ,Master 1 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 0.--2. " MSTR_0 ,Master 0 Priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
rgroup.long 0x310++0x3
|
|
line.long 0x00 "SGPCR3,General Purpose Control Register 3"
|
|
bitfld.long 0x00 31. " RO ,Read Only" "Read/Write,Read only"
|
|
bitfld.long 0x00 30. " HLP ,Halt Low Priority" "Highest,Lowest"
|
|
bitfld.long 0x00 8.--9. " ARB ,Arbitration Mode" "Fixed,Round robin,?..."
|
|
bitfld.long 0x00 4.--5. " PCTL ,Parking Control" "PARK,Last master,No master,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PARK ,PARK" "Port 0,Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,?..."
|
|
endif
|
|
group.long 0x800++0x3 "Master Port 0"
|
|
line.long 0x00 "MGPCR0,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0x900++0x3 "Master Port 1"
|
|
line.long 0x00 "MGPCR1,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0xa00++0x3 "Master Port 2"
|
|
line.long 0x00 "MGPCR2,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0xb00++0x3 "Master Port 3"
|
|
line.long 0x00 "MGPCR3,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0xc00++0x3 "Master Port 4"
|
|
line.long 0x00 "MGPCR4,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0xd00++0x3 "Master Port 5"
|
|
line.long 0x00 "MGPCR5,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
group.long 0xe00++0x3 "Master Port 6"
|
|
line.long 0x00 "MGPCR6,Master General Purpose Control Register"
|
|
bitfld.long 0x00 0.--2. " AULB ,Arbitrate on Undefined Length Bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "AUDMUX (Digital Audio Mux)"
|
|
base ad:0x83fd0000
|
|
width 8.
|
|
group.long (0x00+0x0)++0x07 "Port 1"
|
|
line.long 0x00 "PTCR1,Port Timing Control Register 1"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR1,Port Data Control Register 1"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x8)++0x07 "Port 2"
|
|
line.long 0x00 "PTCR2,Port Timing Control Register 2"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR2,Port Data Control Register 2"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x10)++0x07 "Port 3"
|
|
line.long 0x00 "PTCR3,Port Timing Control Register 3"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR3,Port Data Control Register 3"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x18)++0x07 "Port 4"
|
|
line.long 0x00 "PTCR4,Port Timing Control Register 4"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR4,Port Data Control Register 4"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x20)++0x07 "Port 5"
|
|
line.long 0x00 "PTCR5,Port Timing Control Register 5"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR5,Port Data Control Register 5"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x28)++0x07 "Port 6"
|
|
line.long 0x00 "PTCR6,Port Timing Control Register 6"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR6,Port Data Control Register 6"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
group.long (0x00+0x30)++0x07 "Port 7"
|
|
line.long 0x00 "PTCR7,Port Timing Control Register 7"
|
|
bitfld.long 0x00 31. " TFSDIR ,Transmit Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 30. " TFSEL[3] ,Transmit Frame Sync Select" "TxFS,RxFS"
|
|
bitfld.long 0x00 27.--29. " TFSEL[2:0] ,Transmit Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 26. " TCLKDIR ,Transmit Clock Direction Control" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TCSEL[3] ,Transmit Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 22.--24. " TCSEL[2:0] ,Transmit Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 21. " RFSDIR ,Receive Frame Sync Direction Control" "Input,Output"
|
|
bitfld.long 0x00 20. " RFSEL[3] ,Receive Frame Sync Select" "TxFS,RxFS"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " RFSEL[2:0] ,Receive Frame Sync Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x00 16. " RCLKDIR ,Receive Clock Direction Control" "Input,Output"
|
|
bitfld.long 0x00 15. " RCSEL[3] ,Receive Clock Select" "TxClk,RxClk"
|
|
bitfld.long 0x00 12.--14. " RCSEL[2:0] ,Receive Clock Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYN ,Synchronous/Asynchronous Select" "Asynchronous,Synchronous"
|
|
line.long 0x04 "PDCR7,Port Data Control Register 7"
|
|
bitfld.long 0x04 13.--15. " RXDSEL[2:0] ,Receive Data Select" "Port 1,Port 2,Port 3,Port 4,Port 5,Port 6,Port 7,?..."
|
|
bitfld.long 0x04 12. " TXRXEN ,Transmit/Receive Switch Enable" "No switch,Switch"
|
|
bitfld.long 0x04 8. " MODE ,Mode Select" "Normal,Internal Network"
|
|
bitfld.long 0x04 7. " INMMASK7 ,Internal Network Mode Mask 7" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INMMASK6 ,Internal Network Mode Mask 6" "Included,Excluded"
|
|
bitfld.long 0x04 5. " INMMASK5 ,Internal Network Mode Mask 5" "Included,Excluded"
|
|
bitfld.long 0x04 4. " INMMASK4 ,Internal Network Mode Mask 4" "Included,Excluded"
|
|
bitfld.long 0x04 3. " INMMASK3 ,Internal Network Mode Mask 3" "Included,Excluded"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INMMASK2 ,Internal Network Mode Mask 2" "Included,Excluded"
|
|
bitfld.long 0x04 1. " INMMASK1 ,Internal Network Mode Mask 1" "Included,Excluded"
|
|
bitfld.long 0x04 0. " INMMASK0 ,Internal Network Mode Mask 0" "Included,Excluded"
|
|
;group.long 0x38++0x03 "CE Bus Network Mode Control"
|
|
; line.long 0x00 "CNMCR,CE Bus Network Mode Control Register"
|
|
; bitfld.long 0x00 18. " CEN ,CE Bus Enable" "Held low,Generated"
|
|
; bitfld.long 0x00 17. " FSPOL ,Frame Sync Polarity Select" "0,1"
|
|
; bitfld.long 0x00 16. " CLKPOL ,Clock Sync Polarity Select" "0,1"
|
|
; hexmask.long.byte 0x00 8.--15. 1. " CNTHI[7:0] ,CE Bus Disable Signal High Period Count"
|
|
; textline " "
|
|
; hexmask.long.byte 0x00 0.--7. 1. " CNTLOW[7:0] ,CE Bus Disable Signal Low Period Count"
|
|
width 0xb
|
|
tree.end
|
|
tree "CSPI (Configurable Serial Peripheral Interface)"
|
|
base ad:0x83fc0000
|
|
width 11.
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RXDATA,Receive Data Register"
|
|
in
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "TXDATA,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " TXDATA ,Transmit Data"
|
|
if ((per.long(ad:0x83fc0000+0x8)&0x02)==0x02)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONREG,Control Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst Length"
|
|
bitfld.long 0x00 16.--18. " DATA_RATE ,SPI Data Rate Control" "Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128,Div by 256,Div by 512"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CHIP_SELECT ,Select one of four external SPI Master/Slave Devices" "/SS0,/SS1,/SS2,/SS3"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 8.--9. " DRCTL ,SPI Data Ready Control" "Ignore,Failing /SPI_RDY,Low level /SPI_RDY,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " DRCTL ,SPI Data Ready Control" "Ignore,Failing /SPI_RDY,Low level /SPI_RDY,/RSV"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " SSPOL ,SPI SS Polarity Select" "Low,High"
|
|
bitfld.long 0x00 6. " SSCTL ,SPI SS Wave Form Select" "Only one,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PHA ,SPI Clock/Data Phase Control" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 4. " POL ,SPI Clock Polarity Control" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMC ,Start Mode Control" "After write 1 to XCH,Immediately"
|
|
bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Exchanged/Busy"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MODE ,SPI Function Mode Select" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,SPI Module Enable Control" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONREG,Control Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst Length"
|
|
sif (cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&!cpuis("IMX50*"))
|
|
bitfld.long 0x00 16.--18. " DATA_RATE ,SPI Data Rate Control" "Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128,Div by 256,Div by 512"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CHIP_SELECT ,Select one of four external SPI Master/Slave Devices" "/SS0,/SS1,/SS2,/SS3"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SSPOL ,SPI SS Polarity Select" "Low,High"
|
|
bitfld.long 0x00 6. " SSCTL ,SPI SS Wave Form Select" "BURST LENGTH+1,/SS edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PHA ,SPI Clock/Data Phase Control" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 4. " POL ,SPI Clock Polarity Control" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MODE ,SPI Function Mode Select" "Slave,Master"
|
|
bitfld.long 0x00 0. " EN ,SPI Module Enable Control" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x0c++0x0f
|
|
line.long 0x00 "INTREG,Interrupt Control Register"
|
|
bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RHEN ,RXFIFO Half Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " THEN ,TXFIFO Half Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMAREG,DMA Control Register"
|
|
bitfld.long 0x04 5. " RFDEN ,RXFIFO Full DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RHDEN ,RXFIFO Half Full DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " THDEN ,TXFIFO Half Empty DMA Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled"
|
|
line.long 0x08 "STATREG,Status Register"
|
|
eventfld.long 0x08 7. " TC , Transfer Completed" "Busy,Completed"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x08 6. " RO ,RXFIFO Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x08 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
else
|
|
bitfld.long 0x08 6. " RO ,RXFIFO Overflow" "Available,Overflow"
|
|
bitfld.long 0x08 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 4. " RH ,RXFIFO Half Full" "Less than 4,4 or more"
|
|
bitfld.long 0x08 3. " RR ,RXFIFO Ready" "No data,More than 1 word"
|
|
bitfld.long 0x08 2. " TF ,TXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TH ,TXFIFO Half Empty" "More than 4 words,4 or fewer words"
|
|
bitfld.long 0x08 0. " TE ,TXFIFO Empty" "Not empty,Empty"
|
|
line.long 0x0c "PERIODREG,Sample Period Control Register"
|
|
sif (cpuis("IMX50*"))
|
|
bitfld.long 0x0c 15. " CSRC ,Clock Source Control" "SCLK,32.768kHz"
|
|
else
|
|
bitfld.long 0x0c 15. " CSRC ,Clock Source Control" "SPI Clock,CKIL"
|
|
endif
|
|
hexmask.long.word 0x0c 0.--14. 1. " SAMPLEPERIOD ,Sample Period Control"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
if ((per.long(ad:0x83fc0000+0x8)&0x02)==0x02)
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TESTREG,Test Control Register"
|
|
bitfld.long 0x00 15. " SWAP ,Data Swap" "Unchanged,Swapped"
|
|
bitfld.long 0x00 14. " LBC ,Loop Back Control" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " RXCNT ,RXFIFO Counter" "0 words,1 word,Reserved,Reserved,Reserved,Reserved,Reserved,7 words,8 words,?..."
|
|
bitfld.long 0x00 0.--3. " TXCNT ,TXFIFO Counter" "0 words,1 word,Reserved,Reserved,Reserved,Reserved,Reserved,7 words,8 words,?..."
|
|
else
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "TESTREG,Test Control Register"
|
|
bitfld.long 0x00 15. " SWAP ,Data Swap" "Unchanged,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " RXCNT ,RXFIFO Counter" "0 words,1 word,Reserved,Reserved,Reserved,Reserved,Reserved,7 words,8 words,?..."
|
|
bitfld.long 0x00 0.--3. " TXCNT ,TXFIFO Counter" "0 words,1 word,Reserved,Reserved,Reserved,Reserved,Reserved,7 words,8 words,?..."
|
|
endif
|
|
else
|
|
if ((per.long(ad:0x83fc0000+0x8)&0x02)==0x02)
|
|
group.long 0x1c0++0x03
|
|
line.long 0x00 "TESTREG,Test Control Register"
|
|
bitfld.long 0x00 15. " SWAP ,Data Swap" "Unchanged,Swapped"
|
|
bitfld.long 0x00 14. " LBC ,Loop Back Control" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SMSTATUS ,State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " RXCNT ,RXFIFO Counter" "0 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,?..."
|
|
bitfld.long 0x00 0.--3. " TXCNT ,TXFIFO Counter" "0 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,?..."
|
|
else
|
|
group.long 0x1c0++0x03
|
|
line.long 0x00 "TESTREG,Test Control Register"
|
|
bitfld.long 0x00 15. " SWAP ,Data Swap" "Unchanged,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SMSTATUS ,State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " RXCNT ,RXFIFO Counter" "0 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,?..."
|
|
bitfld.long 0x00 0.--3. " TXCNT ,TXFIFO Counter" "0 words,1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,?..."
|
|
endif
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.open "DPLL-IP (Digital Phase Lock Loop Interface)"
|
|
tree "DPLL1"
|
|
base ad:0x83f80000
|
|
width 13.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "DP_CTL,DPLL Control Register"
|
|
bitfld.long 0x00 13. " MUL_CTRL ,Multiple Control" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DPDCK0_2_EN ,Dpdck0_2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " REF_CLK_DIV ,Ref Clk Division factor" "Div by 1,Div by 2"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Reserved,Reserved,Clock2 (24MHz oscillator clock),?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Clk0,Clk1,Clk2,Clk3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " HFSM ,HFS-Mode Status" "LFS,HFS"
|
|
bitfld.long 0x00 6. " PRE ,Power Up Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " UPEN ,PLL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RST ,Restart" "Not restarted,Restarted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCP ,Reference Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 2. " PLM ,Phase Lock Mode" "Frequency,Frequency/Phase"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BRMO ,BRM Order" "First,Second"
|
|
bitfld.long 0x00 0. " LRF ,Lock Ready Flag" "Not locked,Locked"
|
|
line.long 0x04 "DP_CONFIG,DPLL Config Register"
|
|
bitfld.long 0x04 1. " AREN ,Auto Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LDREQ ,Load Request" "Not requested,Requested"
|
|
line.long 0x08 "DP_OP,DPLL Operation Register"
|
|
bitfld.long 0x08 4.--7. " MFI[3:0] ,Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x0c "DP_MFD,DPLL MFD Register"
|
|
hexmask.long 0x0c 0.--26. 1. " MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x10 "DP_MFN,DPLL MFN Register"
|
|
hexmask.long 0x10 0.--26. 1. " MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x14 "DP_MFNMINUS,DPLL MFNMINUS Register"
|
|
hexmask.long 0x14 0.--26. 1. " MFNMINUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x18 "DP_MFNPLUS,DPLL MFNPLUS Register"
|
|
hexmask.long 0x18 0.--26. 1. " MFNPLUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x1c "DP_HFS_OP,DPLL High Frequency Support Operation Register"
|
|
bitfld.long 0x1c 4.--7. " HFS_MFI[3:0] ,HFS Mode - Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x20 "DP_HFS_MFD,DPLL HFS MFD Register"
|
|
hexmask.long 0x20 0.--26. 1. " HFS_MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x24 "DP_HFS_MFN,DPLL HFS MFN Register"
|
|
hexmask.long 0x24 0.--26. 1. " HFS_MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x28 "DP_MFN_TOGC,DPLL Toggle Control Register"
|
|
bitfld.long 0x28 17. " TOG_DIS ,Desense Disable" "No,Yes"
|
|
bitfld.long 0x28 16. " TOG_EN ,Desense On" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--15. 1. " TOG_CNT[15:0] ,Toggle Counter Value"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "DP_DESTAT,Desense Status Register"
|
|
bitfld.long 0x0 31. " TOG_SEL ,Toggle Sel Status" "Inactive,Active"
|
|
hexmask.long 0x0 0.--26. 1. " TOG_MFN[26:0] ,MFN Value"
|
|
width 0xb
|
|
tree.end
|
|
tree "DPLL2"
|
|
base ad:0x83f84000
|
|
width 13.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "DP_CTL,DPLL Control Register"
|
|
bitfld.long 0x00 13. " MUL_CTRL ,Multiple Control" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DPDCK0_2_EN ,Dpdck0_2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " REF_CLK_DIV ,Ref Clk Division factor" "Div by 1,Div by 2"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Reserved,Reserved,Clock2 (24MHz oscillator clock),?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Clk0,Clk1,Clk2,Clk3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " HFSM ,HFS-Mode Status" "LFS,HFS"
|
|
bitfld.long 0x00 6. " PRE ,Power Up Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " UPEN ,PLL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RST ,Restart" "Not restarted,Restarted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCP ,Reference Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 2. " PLM ,Phase Lock Mode" "Frequency,Frequency/Phase"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BRMO ,BRM Order" "First,Second"
|
|
bitfld.long 0x00 0. " LRF ,Lock Ready Flag" "Not locked,Locked"
|
|
line.long 0x04 "DP_CONFIG,DPLL Config Register"
|
|
bitfld.long 0x04 1. " AREN ,Auto Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LDREQ ,Load Request" "Not requested,Requested"
|
|
line.long 0x08 "DP_OP,DPLL Operation Register"
|
|
bitfld.long 0x08 4.--7. " MFI[3:0] ,Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x0c "DP_MFD,DPLL MFD Register"
|
|
hexmask.long 0x0c 0.--26. 1. " MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x10 "DP_MFN,DPLL MFN Register"
|
|
hexmask.long 0x10 0.--26. 1. " MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x14 "DP_MFNMINUS,DPLL MFNMINUS Register"
|
|
hexmask.long 0x14 0.--26. 1. " MFNMINUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x18 "DP_MFNPLUS,DPLL MFNPLUS Register"
|
|
hexmask.long 0x18 0.--26. 1. " MFNPLUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x1c "DP_HFS_OP,DPLL High Frequency Support Operation Register"
|
|
bitfld.long 0x1c 4.--7. " HFS_MFI[3:0] ,HFS Mode - Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x20 "DP_HFS_MFD,DPLL HFS MFD Register"
|
|
hexmask.long 0x20 0.--26. 1. " HFS_MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x24 "DP_HFS_MFN,DPLL HFS MFN Register"
|
|
hexmask.long 0x24 0.--26. 1. " HFS_MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x28 "DP_MFN_TOGC,DPLL Toggle Control Register"
|
|
bitfld.long 0x28 17. " TOG_DIS ,Desense Disable" "No,Yes"
|
|
bitfld.long 0x28 16. " TOG_EN ,Desense On" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--15. 1. " TOG_CNT[15:0] ,Toggle Counter Value"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "DP_DESTAT,Desense Status Register"
|
|
bitfld.long 0x0 31. " TOG_SEL ,Toggle Sel Status" "Inactive,Active"
|
|
hexmask.long 0x0 0.--26. 1. " TOG_MFN[26:0] ,MFN Value"
|
|
width 0xb
|
|
tree.end
|
|
tree "DPLL3"
|
|
base ad:0x83f88000
|
|
width 13.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "DP_CTL,DPLL Control Register"
|
|
bitfld.long 0x00 13. " MUL_CTRL ,Multiple Control" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DPDCK0_2_EN ,Dpdck0_2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " REF_CLK_DIV ,Ref Clk Division factor" "Div by 1,Div by 2"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Reserved,Reserved,Clock2 (24MHz oscillator clock),?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " REF_CLK_SEL[1:0] ,Select the reference clock for DPLL" "Clk0,Clk1,Clk2,Clk3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " HFSM ,HFS-Mode Status" "LFS,HFS"
|
|
bitfld.long 0x00 6. " PRE ,Power Up Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " UPEN ,PLL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RST ,Restart" "Not restarted,Restarted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCP ,Reference Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 2. " PLM ,Phase Lock Mode" "Frequency,Frequency/Phase"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BRMO ,BRM Order" "First,Second"
|
|
bitfld.long 0x00 0. " LRF ,Lock Ready Flag" "Not locked,Locked"
|
|
line.long 0x04 "DP_CONFIG,DPLL Config Register"
|
|
bitfld.long 0x04 1. " AREN ,Auto Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LDREQ ,Load Request" "Not requested,Requested"
|
|
line.long 0x08 "DP_OP,DPLL Operation Register"
|
|
bitfld.long 0x08 4.--7. " MFI[3:0] ,Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x08 0.--3. " PDF[3:0] ,Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x0c "DP_MFD,DPLL MFD Register"
|
|
hexmask.long 0x0c 0.--26. 1. " MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x10 "DP_MFN,DPLL MFN Register"
|
|
hexmask.long 0x10 0.--26. 1. " MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x14 "DP_MFNMINUS,DPLL MFNMINUS Register"
|
|
hexmask.long 0x14 0.--26. 1. " MFNMINUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x18 "DP_MFNPLUS,DPLL MFNPLUS Register"
|
|
hexmask.long 0x18 0.--26. 1. " MFNPLUS[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x1c "DP_HFS_OP,DPLL High Frequency Support Operation Register"
|
|
bitfld.long 0x1c 4.--7. " HFS_MFI[3:0] ,HFS Mode - Multiplication Factor" "5,5,5,5,5,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
else
|
|
bitfld.long 0x1c 0.--3. " HFS_PDF[3:0] ,HFS Mode - Pre-division Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x20 "DP_HFS_MFD,DPLL HFS MFD Register"
|
|
hexmask.long 0x20 0.--26. 1. " HFS_MFD[26:0] ,Multiplication Factor Denominator"
|
|
line.long 0x24 "DP_HFS_MFN,DPLL HFS MFN Register"
|
|
hexmask.long 0x24 0.--26. 1. " HFS_MFN[26:0] ,Multiplication Factor Numerator"
|
|
line.long 0x28 "DP_MFN_TOGC,DPLL Toggle Control Register"
|
|
bitfld.long 0x28 17. " TOG_DIS ,Desense Disable" "No,Yes"
|
|
bitfld.long 0x28 16. " TOG_EN ,Desense On" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--15. 1. " TOG_CNT[15:0] ,Toggle Counter Value"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "DP_DESTAT,Desense Status Register"
|
|
bitfld.long 0x0 31. " TOG_SEL ,Toggle Sel Status" "Inactive,Active"
|
|
hexmask.long 0x0 0.--26. 1. " TOG_MFN[26:0] ,MFN Value"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "eCSPI (Enhanced Configurable Serial Peripheral Interface)"
|
|
tree "eCSPI 1"
|
|
base ad:0x70010000
|
|
width 15.
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RXDATA1,Receive Data Register 1"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RXDATA1,Receive Data Register 1"
|
|
in
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "TXDATA1,Transmit Data Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " TXDATA ,Transmit Data"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROLEG1,Control Register 1"
|
|
hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst Length"
|
|
bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI Channel Select" "0,1,2,3"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,/RSV"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master"
|
|
bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master"
|
|
bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMC ,Start Mode Control" "Normal,Automatic"
|
|
bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Exchanged/Busy"
|
|
textline " "
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1. " HW ,HW Trigger Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 0. " EN ,SPI Module Enable Control" "Disabled,Enabled"
|
|
if (((per.l(ad:0x70010000+0x08))&0xf0)==0x00)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0x20)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0x30)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0x40)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0x50)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0x60)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0x70)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0x80)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0x90)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0xa0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0xb0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0xc0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0xd0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x70010000+0x08))&0xf0)==0xe0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
else
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG1,Config Register 1"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "INTREG1,Interrupt Control Register 1"
|
|
bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMAREG1,DMA Control Register 1"
|
|
bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x04 24.--26. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x04 16.--21. " RX_WATER_MARK ,RX WATER MARK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TXDEN ,TXFIFO DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " TX_WATER_MARK ,TX WATER MARK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((per.l(ad:0x70010000+0x14))&0x80000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STATREG1,Status Register 1"
|
|
eventfld.long 0x00 7. " TC ,Transfer Completed" "Busy,Completed"
|
|
eventfld.long 0x00 6. " RO ,RXFIFO Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<=RX THRESHOLD,>RX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<RX DMA WATER MARK,>RX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RR ,RXFIFO Ready" "No valid data,>=1 word"
|
|
rbitfld.long 0x00 2. " TF ,TXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX THRESHOLD,<=TX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX DMA WATER MARK,<=TX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 0. " TE ,TXFIFO Empty" "Not empty,Empty"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STATREG1,Status Register 1"
|
|
eventfld.long 0x00 7. " TC ,Transfer Completed" "Busy,Completed"
|
|
eventfld.long 0x00 6. " RO ,RXFIFO Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("iMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA"
|
|
else
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Full" "<RX DMA WATER MARK,>RX DMA WATER MARK/DMA TAIL DMA matched"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RR ,RXFIFO Ready" "No valid data,>=1 word"
|
|
rbitfld.long 0x00 2. " TF ,TXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX THRESHOLD,<=TX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX DMA WATER MARK,<=TX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 0. " TE ,TXFIFO Empty" "Not empty,Empty"
|
|
endif
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "PERIODREG1,Sample Period Control Register 1"
|
|
bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip Select Delay Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Frequency Ref. Clock"
|
|
else
|
|
bitfld.long 0x00 15. " CSRC ,Clock Source Control" "SPI Clock,CKIL"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample Period Control"
|
|
line.long 0x04 "TESTREG1,Test Control Register 1"
|
|
bitfld.long 0x04 31. " LBC ,Loop Back Control" "Not connected,Connected"
|
|
sif (!(cpuis("IMX6*"))&&cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
bitfld.long 0x04 28.--29. " CL ,Catch Latency" "Normal,Half cycle,One cycle,One & half cycle"
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO Counter"
|
|
hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO Counter"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "MSGDATA1,Message Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "eCSPI 2"
|
|
base ad:0x83fac000
|
|
width 15.
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "RXDATA2,Receive Data Register 2"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "RXDATA2,Receive Data Register 2"
|
|
in
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "TXDATA2,Transmit Data Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " TXDATA ,Transmit Data"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROLEG2,Control Register 2"
|
|
hexmask.long.word 0x00 20.--31. 1. " BURST_LENGTH ,Burst Length"
|
|
bitfld.long 0x00 18.--19. " CHANNEL_SELECT ,SPI Channel Select" "0,1,2,3"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,?..."
|
|
else
|
|
bitfld.long 0x00 16.--17. " DRCTL ,SPI Data Ready Control" "Don't care /SPI_RDY,Falling edge of /SPI_RDY,Low level of /SPI_RDY,/RSV"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " PRE_DIVIDER ,SPI Pre Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 8.--11. " POST_DIVIDER ,SPI Post Divider" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHANNEL_MODE[3] ,Mode of each SPI channel 3" "Slave,Master"
|
|
bitfld.long 0x00 6. " CHANNEL_MODE[2] ,Mode of each SPI channel 2" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CHANNEL_MODE[1] ,Mode of each SPI channel 1" "Slave,Master"
|
|
bitfld.long 0x00 4. " CHANNEL_MODE[0] ,Mode of each SPI channel 0" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMC ,Start Mode Control" "Normal,Automatic"
|
|
bitfld.long 0x00 2. " XCH ,SPI Exchange Bit" "Idle,Exchanged/Busy"
|
|
textline " "
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 1. " HT ,Hardware Trigger Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1. " HW ,HW Trigger Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 0. " EN ,SPI Module Enable Control" "Disabled,Enabled"
|
|
if (((per.l(ad:0x83fac000+0x08))&0xf0)==0x00)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0x10)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0x20)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0x30)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0x40)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0x50)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0x60)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0x70)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0x80)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0x90)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0xa0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0xb0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0xc0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0xd0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
elif (((per.l(ad:0x83fac000+0x08))&0xf0)==0xe0)
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "(BURST_LENGTH+1) bits received,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
else
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "CONFIGREG2,Config Register 2"
|
|
bitfld.long 0x00 24.--28. " HT_LENGTH ,Length of message content in HT Mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x00 23. " SCLK_CTL[3] ,Control inactive state of SCLK line for SPI channel 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SCLK_CTL[2] ,Control inactive state of SCLK line for SPI channel 2" "Low,High"
|
|
bitfld.long 0x00 21. " SCLK_CTL[1] ,Control inactive state of SCLK line for SPI channel 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SCLK_CTL[0] ,Control inactive state of SCLK line for SPI channel 0" "Low,High"
|
|
bitfld.long 0x00 19. " DATA_CTL[3] ,Control inactive state of Data line for SPI channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DATA_CTL[2] ,Control inactive state of Data line for SPI channel 2" "High,Low"
|
|
bitfld.long 0x00 17. " DATA_CTL[1] ,Control inactive state of Data line for SPI channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DATA_CTL[0] ,Control inactive state of Data line for SPI channel 0" "High,Low"
|
|
bitfld.long 0x00 15. " SSB_POL[3] ,Control polarity of SSB for SPI channel 3" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SSB_POL[2] ,Control polarity of SSB for SPI channel 2" "Active Low,Active High"
|
|
bitfld.long 0x00 13. " SSB_POL[1] ,Control polarity of SSB for SPI channel 1" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSB_POL[0] ,Control polarity of SSB for SPI channel 0" "Active Low,Active High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SSB_CTRL[3] ,Control behavior of SSB for SPI channel 3" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SSB_CTRL[2] ,Control behavior of SSB for SPI channel 2" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSB_CTRL[1] ,Control behavior of SSB for SPI channel 1" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSB_CTRL[0] ,Control behavior of SSB for SPI channel 0" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLK_POL[3] ,Controls the SCLK Polarity of SPI channel 3" "Active high,Active low"
|
|
bitfld.long 0x00 6. " SCLK_POL[2] ,Controls the SCLK Polarity of SPI channel 2" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCLK_POL[1] ,Controls the SCLK Polarity of SPI channel 1" "Active high,Active low"
|
|
bitfld.long 0x00 4. " SCLK_POL[0] ,Controls the SCLK Polarity of SPI channel 0" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCLK_PHA[3] ,Controls the SSB Polarity of SPI channel 3" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 2. " SCLK_PHA[2] ,Controls the SSB Polarity of SPI channel 2" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SCLK_PHA[1] ,Controls the SSB Polarity of SPI channel 1" "Phase 0,Phase 1"
|
|
bitfld.long 0x00 0. " SCLK_PHA[0] ,Controls the SSB Polarity of SPI channel 0" "Phase 0,Phase 1"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "INTREG2,Interrupt Control Register 2"
|
|
bitfld.long 0x00 7. " TCEN ,Transfer Completed Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ROEN ,RXFIFO Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RFEN ,RXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RDREN ,RXFIFO Data Request Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RREN ,RXFIFO Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TFEN ,TXFIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TDREN ,TXFIFO Data Request Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TEEN ,TXFIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMAREG2,DMA Control Register 2"
|
|
bitfld.long 0x04 31. " RXTDEN ,RXFIFO TAIL DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x04 24.--29. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x04 24.--26. " RX_DMA_LENGTH ,RX DMA LENGTH" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 23. " RXDEN ,RXFIFO DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x04 16.--21. " RX_THRESHOLD ,RX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 7. " TEDEN ,TXFIFO Empty DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " TX_THRESHOLD ,TX THRESHOLD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x04 16.--21. " RX_WATER_MARK ,RX WATER MARK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TXDEN ,TXFIFO DMA Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--5. " TX_WATER_MARK ,TX WATER MARK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
if (((per.l(ad:0x83fac000+0x14))&0x80000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STATREG2,Status Register 2"
|
|
eventfld.long 0x00 7. " TC ,Transfer Completed" "Busy,Completed"
|
|
eventfld.long 0x00 6. " RO ,RXFIFO Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<=RX THRESHOLD,>RX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<RX DMA WATER MARK,>RX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RR ,RXFIFO Ready" "No valid data,>=1 word"
|
|
rbitfld.long 0x00 2. " TF ,TXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX THRESHOLD,<=TX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX DMA WATER MARK,<=TX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 0. " TE ,TXFIFO Empty" "Not empty,Empty"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "STATREG2,Status Register 2"
|
|
eventfld.long 0x00 7. " TC ,Transfer Completed" "Busy,Completed"
|
|
eventfld.long 0x00 6. " RO ,RXFIFO Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " RF ,RXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("iMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Request" "<=RX THRESHOLD,>RX THRESHOLD/DMA TAIL DMA"
|
|
else
|
|
rbitfld.long 0x00 4. " RDR ,RXFIFO Data Full" "<RX DMA WATER MARK,>RX DMA WATER MARK/DMA TAIL DMA matched"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 3. " RR ,RXFIFO Ready" "No valid data,>=1 word"
|
|
rbitfld.long 0x00 2. " TF ,TXFIFO Full" "Not full,Full"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX THRESHOLD,<=TX THRESHOLD"
|
|
else
|
|
rbitfld.long 0x00 1. " TDR ,TXFIFO Data Request" ">TX DMA WATER MARK,<=TX DMA WATER MARK"
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 0. " TE ,TXFIFO Empty" "Not empty,Empty"
|
|
endif
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "PERIODREG2,Sample Period Control Register 2"
|
|
bitfld.long 0x00 16.--21. " CSD_CTRL ,Chip Select Delay Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 15. " CSRC ,Clock Source Control" "SPI Clock,Low-Frequency Ref. Clock"
|
|
else
|
|
bitfld.long 0x00 15. " CSRC ,Clock Source Control" "SPI Clock,CKIL"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--14. 1. " SAMPLE_PERIOD ,Sample Period Control"
|
|
line.long 0x04 "TESTREG2,Test Control Register 2"
|
|
bitfld.long 0x04 31. " LBC ,Loop Back Control" "Not connected,Connected"
|
|
sif (!(cpuis("IMX6*"))&&cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
bitfld.long 0x04 28.--29. " CL ,Catch Latency" "Normal,Half cycle,One cycle,One & half cycle"
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--14. 1. " RXCNT ,RXFIFO Counter"
|
|
hexmask.long.byte 0x04 0.--6. 1. " TXCNT ,TXFIFO Counter"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "MSGDATA2,Message Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "EPIT (Enhanced Periodic Interrupt Timer)"
|
|
tree "EPIT 1"
|
|
base ad:0x73fac000
|
|
width 12.
|
|
if ((per.l(ad:0x73fac000)&0x8)==0x8)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EPITCR1,EPIT Control Register"
|
|
sif (cpuis("IMX6*")||cpuis("IMX50*"))
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Clock Source" "Clock is off,Peripheral clock,High-frequency reference clock,Low-frequency reference clock"
|
|
else
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Select Clock Source" "Clock is off,Ipg_clk,Ipg_clk_highfreq,Ipg_clk_32k"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OM ,EPIT Output Configuration" "Disconnected,Toggled,Cleared,Set"
|
|
bitfld.long 0x00 21. " STOPEN ,EPIT Stop Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WAITEN ,EPIT Wait Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DBGEN ,Debug Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOVW ,EPIT Counter Overwrite Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SWR ,Software Reset" "Out of reset,Reset"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value"
|
|
bitfld.long 0x00 3. " RLD ,Counter Reload Control" "Free running,Set and Forget"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OCIEN ,Output Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENMOD ,EPIT Enable Mode" "Current value,Load value"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,EPIT Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EPITCR1,EPIT Control Register"
|
|
sif (cpuis("IMX6*")||cpuis("IMX50*"))
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Clock Source" "Clock is off,Peripheral clock,High-frequency reference clock,Low-frequency reference clock"
|
|
else
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Select Clock Source" "Clock is off,Ipg_clk,Ipg_clk_highfreq,Ipg_clk_32k"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OM ,EPIT Output Configuration" "Disconnected,Toggled,Cleared,Set"
|
|
bitfld.long 0x00 21. " STOPEN ,EPIT Stop Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WAITEN ,EPIT Wait Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DBGEN ,Debug Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOVW ,EPIT Counter Overwrite Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SWR ,Software Reset" "Out of reset,Reset"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value"
|
|
bitfld.long 0x00 3. " RLD ,Counter Reload Control" "Free running,Set and Forget"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OCIEN ,Output Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENMOD ,EPIT Enable Mode" "Current value,0xFFFFFFFF"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,EPIT Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x0b
|
|
line.long 0x00 "EPITSR1,EPIT Status Register"
|
|
eventfld.long 0x00 0. " OCIF ,Output Compare Interrupt Flag" "Not occurred,Occurred"
|
|
line.long 0x04 "EPITLR1,EPIT Load Register"
|
|
line.long 0x08 "EPITCMPR1,EPIT Compare Register"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "EPITCNR1,EPIT Counter Register"
|
|
width 0xb
|
|
tree.end
|
|
tree "EPIT 2"
|
|
base ad:0x73fb0000
|
|
width 12.
|
|
if ((per.l(ad:0x73fb0000)&0x8)==0x8)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EPITCR2,EPIT Control Register"
|
|
sif (cpuis("IMX6*")||cpuis("IMX50*"))
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Clock Source" "Clock is off,Peripheral clock,High-frequency reference clock,Low-frequency reference clock"
|
|
else
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Select Clock Source" "Clock is off,Ipg_clk,Ipg_clk_highfreq,Ipg_clk_32k"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OM ,EPIT Output Configuration" "Disconnected,Toggled,Cleared,Set"
|
|
bitfld.long 0x00 21. " STOPEN ,EPIT Stop Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WAITEN ,EPIT Wait Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DBGEN ,Debug Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOVW ,EPIT Counter Overwrite Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SWR ,Software Reset" "Out of reset,Reset"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value"
|
|
bitfld.long 0x00 3. " RLD ,Counter Reload Control" "Free running,Set and Forget"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OCIEN ,Output Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENMOD ,EPIT Enable Mode" "Current value,Load value"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,EPIT Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EPITCR2,EPIT Control Register"
|
|
sif (cpuis("IMX6*")||cpuis("IMX50*"))
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Clock Source" "Clock is off,Peripheral clock,High-frequency reference clock,Low-frequency reference clock"
|
|
else
|
|
bitfld.long 0x00 24.--25. " CLKSRC ,Select Clock Source" "Clock is off,Ipg_clk,Ipg_clk_highfreq,Ipg_clk_32k"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OM ,EPIT Output Configuration" "Disconnected,Toggled,Cleared,Set"
|
|
bitfld.long 0x00 21. " STOPEN ,EPIT Stop Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WAITEN ,EPIT Wait Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DBGEN ,Debug Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOVW ,EPIT Counter Overwrite Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SWR ,Software Reset" "Out of reset,Reset"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value"
|
|
bitfld.long 0x00 3. " RLD ,Counter Reload Control" "Free running,Set and Forget"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OCIEN ,Output Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ENMOD ,EPIT Enable Mode" "Current value,0xFFFFFFFF"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,EPIT Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x0b
|
|
line.long 0x00 "EPITSR2,EPIT Status Register"
|
|
eventfld.long 0x00 0. " OCIF ,Output Compare Interrupt Flag" "Not occurred,Occurred"
|
|
line.long 0x04 "EPITLR2,EPIT Load Register"
|
|
line.long 0x08 "EPITCMPR2,EPIT Compare Register"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "EPITCNR2,EPIT Counter Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "GPC (Global Power Controller)"
|
|
tree "GPC Registers"
|
|
base ad:0x73fd8000
|
|
width 8.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CNTR,CNTR Register"
|
|
bitfld.long 0x00 26. " CSPI ,CSPI or I2C use" "I2C,CSPI"
|
|
bitfld.long 0x00 25. " IRQ2M ,Int2 (for I2C) masking" "Not masked,Masked"
|
|
eventfld.long 0x00 24. " IRQ2 ,Interrupt request 2 status bit" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPCIRQM ,GPC interrupt/event masking" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " GPCIRQ ,GPC will generate ARM IRQ or SDMA event" "SDMA event,ARM IRQ"
|
|
bitfld.long 0x00 19. " DPTC1CR ,DPTC1 (PER) Change request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DPTC0CR ,DPTC0 (ARM) Change request" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " DVFS1CR ,DVFS1 (PER) Change request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " DVFS0CR ,DVFS0 (ARM) Change request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ADU ,ARM domain freq/voltage update needed" "PER,ARM"
|
|
bitfld.long 0x00 14. " STRT ,Controller start" "Finished,In progress"
|
|
bitfld.long 0x00 13. " FUPD ,Frequency update needed" "Not needed,Needed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " HTRI ,Hardware Triggering Register Index" "Reg. 0,Reg. 1,Reg. 3,?..."
|
|
line.long 0x04 "PGR,Power Gating Register"
|
|
bitfld.long 0x04 29.--30. " DRCIC ,DPTC ref cir in mux control" "ref_clk_lp_0,ccm_cosr_1_clk_in,ccm_cosr_2_clk_in,io_pvt_clk_in"
|
|
bitfld.long 0x04 28. " IPCC ,IO PTV Control Configuration" "Internal,External"
|
|
hexmask.long.byte 0x04 22.--27. 1. " IPCO ,IO PTV Control Out"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--21. 1. " IPCI ,IO PTV Control In"
|
|
bitfld.long 0x04 8.--9. " CTA8PG ,CTA8 (TIGER) Power Gating" "Never,Wait Mode,Doze Mode,Stop Mode"
|
|
bitfld.long 0x04 4.--5. " GPU ,GPU Power Gating" "Never,Wait Mode,Doze Mode,Stop Mode"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " VPU ,VPU Power Gating" "Never,Wait Mode,Doze Mode,Stop Mode"
|
|
bitfld.long 0x04 0.--1. " IPU ,IPU Power Gating" "Never,Wait Mode,Doze Mode,Stop Mode"
|
|
line.long 0x08 "VCR,Voltage Counter Register"
|
|
bitfld.long 0x08 17. " VINC ,Voltage increase" "Decreased,Increased"
|
|
bitfld.long 0x08 16. " VCNTU ,Voltage Count Used" "Not used,Used"
|
|
hexmask.long.word 0x08 0.--14. 1. " VCNT ,Voltage update Count"
|
|
line.long 0x0c "ALL_PU,Register Control Power for all PUs"
|
|
bitfld.long 0x0C 10. " VPUSWSTATUS ,Status of VPU sw request" "Powered down,Powered up"
|
|
bitfld.long 0x0C 9. " GPUSWSTATUS ,Status of GPU sw request" "Powered down,Powered up"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " IPUSWSTATUS ,Status of IPU sw request" "Powered down,Powered up"
|
|
bitfld.long 0x0C 6. " VPUPUR ,Software VPU Power Up Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " GPUPUR ,Software GPU Power Up Request" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " IPUPUR ,Software IPU Power Up Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " VPUPDR ,Software VPU Power Down Request" "Not requested,Requested"
|
|
bitfld.long 0x0C 1. " GPUPDR ,Software GPU Power Down Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " IPUPDR ,Software IPU Power Down Request" "Not requested,Requested"
|
|
line.long 0x10 "NEON,Register Control Power for NEON"
|
|
bitfld.long 0x10 4.--5. " NEONFSMST ,Neon FSM status" "Power up acknowledge/Normal state,Power down request,Power down acknowledge,Power up request"
|
|
textline " "
|
|
bitfld.long 0x10 1. " NEONPUR ,NEON Power Up Request" "Not requested,Requested"
|
|
bitfld.long 0x10 0. " NEONPDR ,NEON Power Down Request" "Not requested,Requested"
|
|
width 0xb
|
|
tree.end
|
|
tree "DPTC_LP (Dynamic Process and Temperature Compensation)"
|
|
base ad:0x73fd8080
|
|
width 8.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DPTCCR,DPTC Control Register"
|
|
bitfld.long 0x00 22. " DRCE3 ,DPTC reference circuit3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DRCE2 ,DPTC reference circuit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DRCE1 ,DPTC reference circuit 1enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DRCE0 ,DPTC reference circuit 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " DCR ,DPTC counting range" "32 sys clk,64 sys clk,128 sys clk,256 sys clk"
|
|
bitfld.long 0x00 6. " DSMM ,IPG_STOP input masking" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DPNVCR ,DPTC No Voltage Change request" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DPVV ,DPTC voltage valid edge detect" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VAIM ,Voltage adjustment interrupt mask" "Enabled,Masked"
|
|
bitfld.long 0x00 1.--2. " VAI[1:0] ,Voltage adjustment status" "No interrupt,High-limit,Low-limit,Emergency-limit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DEN ,DPTC enable" "Disabled,Enabled"
|
|
line.long 0x04 "DPTCDBG,DPTC Debug Register"
|
|
bitfld.long 0x04 13. " RCLKON ,Reference circuit clock on" "Normal,Debug mode"
|
|
hexmask.long.word 0x04 1.--11. 1. " RCCR ,Reference circuit counter result"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RCCRV ,Reference circuit counter result valid" "Not valid,Valid"
|
|
line.long 0x08 "DCVR0,DPTC Comparator Value Register 0"
|
|
hexmask.long.word 0x08 21.--31. 1. " ULV ,Upper limit value"
|
|
hexmask.long.word 0x08 10.--20. 1. " LLV ,Lower limit value"
|
|
hexmask.long.word 0x08 0.--9. 1. " ELV ,Emergency limit value"
|
|
line.long 0x0c "DCVR1,DPTC Comparator Value Register 1"
|
|
hexmask.long.word 0x0c 21.--31. 1. " ULV ,Upper limit value"
|
|
hexmask.long.word 0x0c 10.--20. 1. " LLV ,Lower limit value"
|
|
hexmask.long.word 0x0c 0.--9. 1. " ELV ,Emergency limit value"
|
|
line.long 0x10 "DCVR2,DPTC Comparator Value Register 2"
|
|
hexmask.long.word 0x10 21.--31. 1. " ULV ,Upper limit value"
|
|
hexmask.long.word 0x10 10.--20. 1. " LLV ,Lower limit value"
|
|
hexmask.long.word 0x10 0.--9. 1. " ELV ,Emergency limit value"
|
|
line.long 0x14 "DCVR3,DPTC Comparator Value Register 3"
|
|
hexmask.long.word 0x14 21.--31. 1. " ULV ,Upper limit value"
|
|
hexmask.long.word 0x14 10.--20. 1. " LLV ,Lower limit value"
|
|
hexmask.long.word 0x14 0.--9. 1. " ELV ,Emergency limit value"
|
|
width 0xb
|
|
tree.end
|
|
tree "DPTC_GP (Dynamic Process and Temperature Compensation)"
|
|
base ad:0x73fd8100
|
|
width 8.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DPTCCR,DPTC Control Register"
|
|
bitfld.long 0x00 22. " DRCE3 ,DPTC reference circuit3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DRCE2 ,DPTC reference circuit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DRCE1 ,DPTC reference circuit 1enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DRCE0 ,DPTC reference circuit 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " DCR ,DPTC counting range" "32 sys clk,64 sys clk,128 sys clk,256 sys clk"
|
|
bitfld.long 0x00 6. " DSMM ,IPG_STOP input masking" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DPNVCR ,DPTC No Voltage Change request" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DPVV ,DPTC voltage valid edge detect" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VAIM ,Voltage adjustment interrupt mask" "Enabled,Masked"
|
|
bitfld.long 0x00 1.--2. " VAI[1:0] ,Voltage adjustment status" "No interrupt,High-limit,Low-limit,Emergency-limit"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DEN ,DPTC enable" "Disabled,Enabled"
|
|
line.long 0x04 "DPTCDBG,DPTC Debug Register"
|
|
bitfld.long 0x04 13. " RCLKON ,Reference circuit clock on" "Normal,Debug mode"
|
|
hexmask.long.word 0x04 1.--11. 1. " RCCR ,Reference circuit counter result"
|
|
textline " "
|
|
bitfld.long 0x04 0. " RCCRV ,Reference circuit counter result valid" "Not valid,Valid"
|
|
line.long 0x08 "DCVR0,DPTC Comparator Value Register 0"
|
|
hexmask.long.word 0x08 21.--31. 1. " ULV ,Upper limit value"
|
|
hexmask.long.word 0x08 10.--20. 1. " LLV ,Lower limit value"
|
|
hexmask.long.word 0x08 0.--9. 1. " ELV ,Emergency limit value"
|
|
line.long 0x0c "DCVR1,DPTC Comparator Value Register 1"
|
|
hexmask.long.word 0x0c 21.--31. 1. " ULV ,Upper limit value"
|
|
hexmask.long.word 0x0c 10.--20. 1. " LLV ,Lower limit value"
|
|
hexmask.long.word 0x0c 0.--9. 1. " ELV ,Emergency limit value"
|
|
line.long 0x10 "DCVR2,DPTC Comparator Value Register 2"
|
|
hexmask.long.word 0x10 21.--31. 1. " ULV ,Upper limit value"
|
|
hexmask.long.word 0x10 10.--20. 1. " LLV ,Lower limit value"
|
|
hexmask.long.word 0x10 0.--9. 1. " ELV ,Emergency limit value"
|
|
line.long 0x14 "DCVR3,DPTC Comparator Value Register 3"
|
|
hexmask.long.word 0x14 21.--31. 1. " ULV ,Upper limit value"
|
|
hexmask.long.word 0x14 10.--20. 1. " LLV ,Lower limit value"
|
|
hexmask.long.word 0x14 0.--9. 1. " ELV ,Emergency limit value"
|
|
width 0xb
|
|
tree.end
|
|
tree "DVFS-CORE (Dynamic Voltage Frequency Scaling)"
|
|
base ad:0x73fd8180
|
|
width 12.
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "DVFSTHRS,DVFSTHRS Register"
|
|
hexmask.long.byte 0x00 22.--27. 1. " UPTHR ,Upper treshold for load tracking"
|
|
hexmask.long.byte 0x00 16.--21. 1. " DWTHR ,Down treshold for load tracking"
|
|
hexmask.long.byte 0x00 0.--5. 1. " PNCTHR ,Panic treshold for load tracking"
|
|
line.long 0x04 "DVFSCOUN,DVFSCOUN Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DNCNT ,Down counter threshold value"
|
|
hexmask.long.byte 0x04 0.--7. 1. " UPCNT ,UP counter threshold value"
|
|
line.long 0x08 "DVFSSIG1,DVFSSIG1 Register"
|
|
bitfld.long 0x08 29.--31. " WSW15 ,General purpose load tracking signal weight dvfs_w_sig[15]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 26.--28. " WSW14 ,General purpose load tracking signal weight dvfs_w_sig[14]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 23.--25. " WSW13 ,General purpose load tracking signal weight dvfs_w_sig[13]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 20.--22. " WSW12 ,General purpose load tracking signal weight dvfs_w_sig[12]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 17.--19. " WSW11 ,General purpose load tracking signal weight dvfs_w_sig[11]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 14.--16. " WSW10 ,General purpose load tracking signal weight dvfs_w_sig[10]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 11.--13. " WSW9 ,General purpose load tracking signal weight dvfs_w_sig[9]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 8.--10. " WSW8 ,General purpose load tracking signal weight dvfs_w_sig[8]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " WSW7 ,General purpose load tracking signal weight dvfs_w_sig[7]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 2.--4. " WSW6 ,General purpose load tracking signal weight dvfs_w_sig[6]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0c "DVFSSIG0,DVFSSIG0 Register"
|
|
bitfld.long 0x0C 29.--31. " WSW5 ,General purpose load tracking signal weight dvfs_w_sig[5]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 26.--28. " WSW4 ,General purpose load tracking signal weight dvfs_w_sig[4]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 23.--25. " WSW3 ,General purpose load tracking signal weight dvfs_w_sig[3]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 20.--22. " WSW2 ,General purpose load tracking signal weight dvfs_w_sig[2]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 6.--11. " WSW1 ,General purpose load tracking signal weight dvfs_w_sig[1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 0.--5. " WSW0 ,General purpose load tracking signal weight dvfs_w_sig[0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "DVFSGPC0,DVFSGPC0 Register"
|
|
bitfld.long 0x10 31. " C0STRT ,Counter 0 start" "Not started,Started"
|
|
rbitfld.long 0x10 30. " C0ACT ,Counter 0 active indicator" "Reached,Not reached"
|
|
hexmask.long.tbyte 0x10 0.--16. 1. " GPBC0 ,General Purpose bits Counter 0"
|
|
line.long 0x14 "DVFSGPC1,DVFSGPC1 Register"
|
|
bitfld.long 0x14 31. " C1STRT ,Counter 1start" "Not started,Started"
|
|
rbitfld.long 0x14 30. " C1ACT ,Counter 1 active indicator" "Reached,Not reached"
|
|
hexmask.long.tbyte 0x14 0.--16. 1. " GPBC1 ,General Purpose bits Counter 1"
|
|
line.long 0x18 "DVFSGPBT,DVFSGPBT Register"
|
|
bitfld.long 0x18 15. " GPB15 ,General purpose bit 15" "Low,High"
|
|
bitfld.long 0x18 14. " GPB14 ,General purpose bit 14" "Low,High"
|
|
bitfld.long 0x18 13. " GPB13 ,General purpose bit 13" "Low,High"
|
|
bitfld.long 0x18 12. " GPB12 ,General purpose bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 11. " GPB11 ,General purpose bit 11" "Low,High"
|
|
bitfld.long 0x18 10. " GPB10 ,General purpose bit 10" "Low,High"
|
|
bitfld.long 0x18 9. " GPB09 ,General purpose bit 9" "Low,High"
|
|
bitfld.long 0x18 8. " GPB08 ,General purpose bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 7. " GPB07 ,General purpose bit 7" "Low,High"
|
|
bitfld.long 0x18 6. " GPB06 ,General purpose bit 6" "Low,High"
|
|
bitfld.long 0x18 5. " GPB05 ,General purpose bit 5" "Low,High"
|
|
bitfld.long 0x18 4. " GPB04 ,General purpose bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 3. " GPB03 ,General purpose bit 3" "Low,High"
|
|
bitfld.long 0x18 2. " GPB02 ,General purpose bit 2" "Low,High"
|
|
bitfld.long 0x18 1. " GPB01 ,General purpose bit 1" "Low,High"
|
|
bitfld.long 0x18 0. " GPB00 ,General purpose bit 0" "Low,High"
|
|
line.long 0x1c "DVFSEMAC,DVFSEMAC Register"
|
|
sif (cpuis("IMX6*"))
|
|
sif (cpu()!="IMX6SOLO"&&cpu()!="IMX6SOLOLITE"&&cpu()!="IMX6DUALLITE")
|
|
bitfld.long 0x1C 27. " WFIM3 ,DVFS Wait for Interrupt of core 3 mask" "Not masked,Masked"
|
|
bitfld.long 0x1C 26. " WFIM2 ,DVFS Wait for Interrupt of core 2 mask" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x1C 25. " WFIM1 ,DVFS Wait for Interrupt of core 1 mask" "Not masked,Masked"
|
|
bitfld.long 0x1C 24. " WFIM0 ,DVFS Wait for Interrupt of core 0 mask" "Not masked,Masked"
|
|
else
|
|
bitfld.long 0x1C 24. " WFIM0 ,DVFS Wait for Interrupt of core 0 mask" "Not masked,Masked"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLO"&&cpu()!="IMX6SOLOLITE"&&cpu()!="IMX6DUALLITE")
|
|
rbitfld.long 0x1C 22.--23. " FSVAI3 ,DVFS Frequency adjustment status of core 3" "Not changed,Increased,Decreased,Increased immediately"
|
|
rbitfld.long 0x1C 20.--21. " FSVAI2 ,DVFS Frequency adjustment status of core 2" "Not changed,Increased,Decreased,Increased immediately"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
rbitfld.long 0x1C 18.--19. " FSVAI1 ,DVFS Frequency adjustment status of core 1" "Not changed,Increased,Decreased,Increased immediately"
|
|
rbitfld.long 0x1C 16.--17. " FSVAI0 ,DVFS Frequency adjustment status of core 0" "Not changed,Increased,Decreased,Increased immediately"
|
|
else
|
|
rbitfld.long 0x1C 16.--17. " FSVAI0 ,DVFS Frequency adjustment status of core 0" "Not changed,Increased,Decreased,Increased immediately"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLO"&&cpu()!="IMX6SOLOLITE"&&cpu()!="IMX6DUALLITE")
|
|
bitfld.long 0x1C 12. " DVFEN3 ,DVFS tracking for core3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " DVFEN2 ,DVFS tracking for core2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x1C 10. " DVFEN1 ,DVFS tracking for core1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " DVFEN0 ,DVFS tracking for core0 enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x1C 9. " DVFEN0 ,DVFS tracking for core0 enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x1c 0.--8. 1. " EMAC ,EMA control value"
|
|
line.long 0x20 "DVFSCNTR,DVFS Register"
|
|
bitfld.long 0x20 29.--31. " DIV3CK ,Div_3_clk division ratio inside the DVFS module" "1,4,16,64,256,1024,?..."
|
|
bitfld.long 0x20 28. " DVFEV ,DVFS event" "Not given,Given"
|
|
bitfld.long 0x20 27. " LBMI ,Load buffer full mask interrupt" "Not masked,Masked"
|
|
eventfld.long 0x20 26. " LBFL1 ,Load buffer 1" "Not full,Full"
|
|
textline " "
|
|
eventfld.long 0x20 25. " LBFL0 ,Load buffer 0" "Not full,Full"
|
|
bitfld.long 0x20 24. " DVFIS ,DVFS Interrupt select" "SDMA,MCU"
|
|
eventfld.long 0x20 23. " PIRQS ,Pattern IRQ Sourse" "No pattern,Pattern"
|
|
bitfld.long 0x20 22. " FSVAIM ,DVFS Frequency adjustment interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
rbitfld.long 0x20 20.--21. " FSVAI ,DVFS Frequency adjustment interrupt" "No interrupt,Increased,Decreased,Increased immediately"
|
|
textline " "
|
|
sif (!cpuis("IMX6*"))
|
|
bitfld.long 0x20 19. " WFIM ,DVFS Wait for Interrupt mask bit" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x20 18. " MAXF ,Maximum frequency reached" "Not reached,Reached"
|
|
bitfld.long 0x20 17. " MINF ,Minimum frequency reached" "Not reached,Reached"
|
|
bitfld.long 0x20 11.--16. " DIV_RATO ,Divider value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
bitfld.long 0x20 9. " PFUE ,Period Frequency Update Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x20 6.--8. " PFUS ,Periodic Frequency Update Status" "No update,,,,DVFSPT0,DVFSPT1,DVFSPT2,DVFSPT3"
|
|
bitfld.long 0x20 5. " LTBRSH ,Load Tracking Buffer Register Shift" "[5:2] value,[4:1] value"
|
|
bitfld.long 0x20 3.--4. " LTBRSR ,Load Tracking Buffer Register Source" "Pre_ld_add,Ld_add,After ema,?..."
|
|
sif (!cpuis("IMX6*"))
|
|
textline " "
|
|
bitfld.long 0x20 0. " DVFEN ,DVFS enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x24++0x0f
|
|
line.long 0x00 "DVFSLTR0_0,DVFSLTR0_0 Register"
|
|
bitfld.long 0x00 28.--31. " LTS0_7 ,Load Tracking Sample 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " LTS0_6 ,Load Tracking Sample 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " LTS0_5 ,Load Tracking Sample 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " LTS0_4 ,Load Tracking Sample 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " LTS0_3 ,Load Tracking Sample 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " LTS0_2 ,Load Tracking Sample 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " LTS0_1 ,Load Tracking Sample 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LTS0_0 ,Load Tracking Sample 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "DVFSLTR0_1,DVFSLTR0_1 Register"
|
|
bitfld.long 0x04 28.--31. " LTS0_15 ,Load Tracking Sample 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " LTS0_14 ,Load Tracking Sample 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. " LTS0_13 ,Load Tracking Sample 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " LTS0_12 ,Load Tracking Sample 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " LTS0_11 ,Load Tracking Sample 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " LTS0_10 ,Load Tracking Sample 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " LTS0_9 ,Load Tracking Sample 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " LTS0_8 ,Load Tracking Sample 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "DVFSLTR1_0,DVFSLTR1_0 Register"
|
|
bitfld.long 0x08 28.--31. " LTS1_7 ,Load Tracking Sample 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " LTS1_6 ,Load Tracking Sample 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--23. " LTS1_5 ,Load Tracking Sample 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " LTS1_4 ,Load Tracking Sample 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " LTS1_3 ,Load Tracking Sample 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " LTS1_2 ,Load Tracking Sample 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 4.--7. " LTS1_1 ,Load Tracking Sample 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " LTS1_0 ,Load Tracking Sample 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0c "DVFSLTR1_1,DVFSLTR1_1 Register"
|
|
bitfld.long 0x0c 28.--31. " LTS1_15 ,Load Tracking Sample 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 24.--27. " LTS1_14 ,Load Tracking Sample 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 20.--23. " LTS1_13 ,Load Tracking Sample 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 16.--19. " LTS1_12 ,Load Tracking Sample 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0c 12.--15. " LTS1_11 ,Load Tracking Sample 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 8.--11. " LTS1_10 ,Load Tracking Sample 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 4.--7. " LTS1_9 ,Load Tracking Sample 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " LTS1_8 ,Load Tracking Sample 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x0f
|
|
line.long 0x00 "DVFSPT0,DVFSPT0 Register"
|
|
rbitfld.long 0x00 17. " PT0A ,Pattern 0 currently active" "Not active,Active"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " FPTN0 ,Frequency pattern 0 counter"
|
|
line.long 0x04 "DVFSPT1,DVFSPT1 Register"
|
|
rbitfld.long 0x04 17. " PT1A ,Pattern 1 currently active" "Not active,Active"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " FPTN1 ,Frequency pattern 1 counter"
|
|
line.long 0x08 "DVFSPT2,DVFSPT2 Register"
|
|
bitfld.long 0x08 26.--31. " P2THR ,Pattern 2 Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x08 17. " PT2A ,Pattern 2 currently active" "Not active,Active"
|
|
hexmask.long.tbyte 0x08 0.--16. 1. " FPTN2 ,Frequency pattern 2 counter"
|
|
line.long 0x0c "DVFSPT3,DVFSPT3 Register"
|
|
rbitfld.long 0x0C 17. " PT3A ,Pattern 3 currently active" "Not active,Active"
|
|
hexmask.long.tbyte 0x0C 0.--16. 1. " FPTN3 ,Frequency pattern 3 counter"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DVFS-PERIPHERALS (Dynamic Voltage Frequency Scaling for Peripherals)"
|
|
base ad:0x73fd81c0
|
|
width 7.
|
|
group.long 0x04++0x0f
|
|
line.long 0x00 "LTR0,LTR0 Register"
|
|
bitfld.long 0x00 31. " SIGD15 ,Detect way of general signal #15" "Level,Edge"
|
|
bitfld.long 0x00 30. " SIGD14 ,Detect way of general signal #14" "Level,Edge"
|
|
bitfld.long 0x00 29. " SIGD13 ,Detect way of general signal #13" "Level,Edge"
|
|
bitfld.long 0x00 22.--27. " UPTHR ,Upper threshold for load tracking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " DWTHR ,Down threshold for load tracking" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 15. " SIGD12 ,Detect way of general signal #12" "Level,Edge"
|
|
bitfld.long 0x00 14. " SIGD11 ,Detect way of general signal #11" "Level,Edge"
|
|
bitfld.long 0x00 13. " SIGD10 ,Detect way of general signal #10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SIGD9 ,Detect way of general signal #9" "Level,Edge"
|
|
bitfld.long 0x00 11. " SIGD8 ,Detect way of general signal #8" "Level,Edge"
|
|
bitfld.long 0x00 10. " SIGD7 ,Detect way of general signal #7" "Level,Edge"
|
|
bitfld.long 0x00 9. " SIGD6 ,Detect way of general signal #6" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SIGD5 ,Detect way of general signal #5" "Level,Edge"
|
|
bitfld.long 0x00 7. " SIGD4 ,Detect way of general signal #4" "Level,Edge"
|
|
bitfld.long 0x00 6. " SIGD3 ,Detect way of general signal #3" "Level,Edge"
|
|
bitfld.long 0x00 5. " SIGD2 ,Detect way of general signal #2" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SIGD1 ,Detect way of general signal #1" "Level,Edge"
|
|
bitfld.long 0x00 3. " SIGD0 ,Detect way of general signal #0" "Level,Edge"
|
|
bitfld.long 0x00 0.--2. " DIV3CK ,Div_3_clk division ratio inside the DVFS module" "1,4,16,64,256,1024,?..."
|
|
line.long 0x04 "LTR1,LTR1 Register"
|
|
bitfld.long 0x04 26.--31. " DIV_RATIO ,Divider value" "1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x04 23. " LTBRSH ,LTBR source shift" "Low,High"
|
|
bitfld.long 0x04 22. " LTBRSR ,LTBR source signal" "Pre_avg_l,Ld_add"
|
|
hexmask.long.byte 0x04 14.--21. 1. " DNCNT ,Down counter threshold value"
|
|
hexmask.long.byte 0x04 6.--13. 1. " UPCNT ,UP counter threshold value"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--5. 1. " PNCTHR ,Panic threshold value"
|
|
line.long 0x08 "LTR2,LTR2 Register"
|
|
bitfld.long 0x08 29.--31. " WSW15 ,General purpose load tracking signal weight dvfs_w_sig[15]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 26.--28. " WSW14 ,General purpose load tracking signal weight dvfs_w_sig[14]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 23.--25. " WSW13 ,General purpose load tracking signal weight dvfs_w_sig[13]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 20.--22. " WSW12 ,General purpose load tracking signal weight dvfs_w_sig[12]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 17.--19. " WSW11 ,General purpose load tracking signal weight dvfs_w_sig[11]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 14.--16. " WSW10 ,General purpose load tracking signal weight dvfs_w_sig[10]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 11.--13. " WSW9 ,General purpose load tracking signal weight dvfs_w_sig[9]" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x08 0.--8. 1. " EMAC ,EMA algoritm value"
|
|
line.long 0x0c "LTR3,LTR3 Register"
|
|
bitfld.long 0x0C 29.--31. " WSW8 ,General purpose load tracking signal weight dvfs_w_sig[8]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 26.--28. " WSW7 ,General purpose load tracking signal weight dvfs_w_sig[7]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 23.--25. " WSW6 ,General purpose load tracking signal weight dvfs_w_sig[6]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 20.--22. " WSW5 ,General purpose load tracking signal weight dvfs_w_sig[5]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 17.--19. " WSW4 ,General purpose load tracking signal weight dvfs_w_sig[4]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 14.--16. " WSW3 ,General purpose load tracking signal weight dvfs_w_sig[3]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 11.--13. " WSW2 ,General purpose load tracking signal weight dvfs_w_sig[2]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 8.--10. " WSW1 ,General purpose load tracking signal weight dvfs_w_sig[1]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 5.--7. " WSW0 ,General purpose load tracking signal weight dvfs_w_sig[0]" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "LTBR0,LTBR0 Register"
|
|
bitfld.long 0x00 28.--31. " LTS0_7 ,Load Tracking Sample 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " LTS0_6 ,Load Tracking Sample 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " LTS0_5 ,Load Tracking Sample 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " LTS0_4 ,Load Tracking Sample 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " LTS0_3 ,Load Tracking Sample 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " LTS0_2 ,Load Tracking Sample 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " LTS0_1 ,Load Tracking Sample 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " LTS0_0 ,Load Tracking Sample 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "LTBR1,LTBR1 Register"
|
|
bitfld.long 0x04 28.--31. " LTS0_15 ,Load Tracking Sample 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " LTS0_14 ,Load Tracking Sample 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. " LTS0_13 ,Load Tracking Sample 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " LTS0_12 ,Load Tracking Sample 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " LTS0_11 ,Load Tracking Sample 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " LTS0_10 ,Load Tracking Sample 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " LTS0_9 ,Load Tracking Sample 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " LTS0_8 ,Load Tracking Sample 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1c++0x07
|
|
line.long 0x00 "PMCR0,PMCR0 Register"
|
|
bitfld.long 0x00 27. " UDSC ,Up-down scaling" "Decreased,Increased"
|
|
bitfld.long 0x00 23. " DVFEV ,Always give a DVFS event" "Not given,Given"
|
|
bitfld.long 0x00 22. " DVFIS ,DVFS Interrupt select" "SDMA,MCU"
|
|
textline " "
|
|
bitfld.long 0x00 21. " LBMI ,Load buffer full mask interrupt" "Enabled,Masked"
|
|
bitfld.long 0x00 20. " LBFL ,Load buffer" "Not full,Full"
|
|
bitfld.long 0x00 18.--19. " LBCF ,Load tracking configuration" "4,8,12,16"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FSVAIM ,DVFS Frequency adjustment interrupt mask" "Enabled,Masked"
|
|
bitfld.long 0x00 13.--14. " FSVAI ,DVFS Frequency adjustment interrupt" "No interrupt,Increased,Decreased,Increased immediately"
|
|
bitfld.long 0x00 10. " WFIM ,WFI ARM signal masking" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DVFEN ,DVFS enable" "Disabled,Enabled"
|
|
line.long 0x04 "PMCR1,PMCR1 Register"
|
|
bitfld.long 0x04 20. " P1INM ,PER1 Idle NFC Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 19. " P1ISM ,PER1 Idle Slow Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 18. " P1IFM ,PER1 Idle Fast Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P4PM ,PER4 panic mask" "Not masked,Masked"
|
|
bitfld.long 0x04 16. " P2PM ,PER2 panic mask" "Not masked,Masked"
|
|
hexmask.long.word 0x04 0.--15. 1. " DVGP ,General purpose bits"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMPGC 0 (Embedded Memory Periphery Power Gating Controller 0)"
|
|
base ad:0x73fd82c0
|
|
width 8.
|
|
group.long 0x00++0x0f
|
|
line.long 0x00 "EMPGCR,EMPG Control Register"
|
|
bitfld.long 0x00 0. " PCR ,Power control" "Not switched off,Switched off"
|
|
line.long 0x04 "PUPSCR,Power-up Sequence Control Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PUP ,Number of clocks to de-assert PD (empgc_pd) from Power-up request"
|
|
line.long 0x08 "PDNSCR,Power-down Sequence Control Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PDN ,Number of clocks from Power down request to PD (empgc_pd) assertion"
|
|
line.long 0x0c "EMPGSR,EMPG Status Register"
|
|
eventfld.long 0x0c 0. " PSR ,Power status" "Powered up,Powered down"
|
|
width 0xb
|
|
tree.end
|
|
tree "EMPGC 1 (Embedded Memory Periphery Power Gating Controller 1)"
|
|
base ad:0x73fd82d0
|
|
width 8.
|
|
group.long 0x00++0x0f
|
|
line.long 0x00 "EMPGCR,EMPG Control Register"
|
|
bitfld.long 0x00 0. " PCR ,Power control" "Not switched off,Switched off"
|
|
line.long 0x04 "PUPSCR,Power-up Sequence Control Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PUP ,Number of clocks to de-assert PD (empgc_pd) from Power-up request"
|
|
line.long 0x08 "PDNSCR,Power-down Sequence Control Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PDN ,Number of clocks from Power down request to PD (empgc_pd) assertion"
|
|
line.long 0x0c "EMPGSR,EMPG Status Register"
|
|
eventfld.long 0x0c 0. " PSR ,Power status" "Powered up,Powered down"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "EMI (External Memory Interface)"
|
|
tree "ESDRAMC (Enhanced SDRAM Controller)"
|
|
base ad:0x83fd9000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ESDCTL0,Enhanced SDRAM Control Register 0"
|
|
bitfld.long 0x00 31. " SDE ,Enhanced SDRAM Controller Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " SREFR ,SDRAM Refresh Rate (Rows Each Refresh Clock/# Rows|64mS @ 32 kHz/Row Rate @ 32 kHz)" "Disabled,1/2048/31.15 us,2/4096/15.62 us,4/8192/7.81 us,8/16384/3.91us,16/32768/1.95 us,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ROW ,Row Address Width" "11,12,13,14,?..."
|
|
bitfld.long 0x00 23. " DBL_tRFC ,Double tRFC" "Normal,Double"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " COL ,Column Address Width" "8,9,10,?..."
|
|
bitfld.long 0x00 16.--17. " DSIZ ,SDRAM Memory Data Width" "16-bit D[31:16],16-bit D[15:0],32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " SRT ,Self Refresh Timer" "Disabled/Run Mode,No banks active/Self Refresh,256 clocks/Precharge all & Self Refresh,512 clocks/Precharge all & Self Refresh"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " PWDT ,Power Down Timer" "Disabled/Run Mode,No banks active/Precharge power down,64 clocks/Active power down,128 clocks/Active power down"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ESDCFG0,ESDRAMC Configuration Registers 0"
|
|
bitfld.long 0x00 28.--31. " TRFC ,Auto refresh to any command" "10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks"
|
|
bitfld.long 0x00 24.--27. " TXSR ,Exit self refresh to any command" "25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks,33 clocks,34 clocks,35 clocks,36 clocks,37 clocks,38 clocks,39 clocks,40 clocks"
|
|
bitfld.long 0x00 21.--23. " TXP ,LPDDR exit power down to next valid command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TWTR ,tLPDDR WRITE to READ Command Delay" "1 clock,2 clocks"
|
|
bitfld.long 0x00 18.--19. " TRP ,SDRAM Row Precharge Delay" "2 clock,3 clocks,4 clocks,5 clocks"
|
|
bitfld.long 0x00 16.--17. " TMRD ,tMRD - SDRAM Load Mode Register to ACTIVE Command" "1 clock,2 clocks,3 clocks,4 clocks"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TRAS ,SDRAM ACTIVE to PRECHARGE Command" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
bitfld.long 0x00 10.--11. " TRRD ,ACTIVE Bank A to ACTIVE Bank B Command" "1 clock,2 clocks,3 clocks,4 clocks"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TWR ,SDRAM WRITE to PRECHARGE Command (LPDDR)" "2 clocks,3 clocks"
|
|
bitfld.long 0x00 4.--6. " TRCD ,SDRAM Row to Column Delay" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks"
|
|
bitfld.long 0x00 0.--3. " TRC ,SDRAM Row Cycle Delay" "20 clocks,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ESDCTL1,Enhanced SDRAM Control Register 1"
|
|
bitfld.long 0x00 31. " SDE ,Enhanced SDRAM Controller Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " SREFR ,SDRAM Refresh Rate (Rows Each Refresh Clock/# Rows | 64mS @ 32 kHz/Row Rate @ 32 kHz)" "Disabled,1/2048/31.15 us,2/4096/15.62 us,4/8192/7.81 us,8/16384/3.91us,16/32768/1.95 us,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ROW ,Row Address Width" "11,12,13,14,?..."
|
|
bitfld.long 0x00 23. " DBL_tRFC ,Double tRFC" "Normal,Double"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " COL ,Column Address Width" "8,9,10,?..."
|
|
bitfld.long 0x00 16.--17. " DSIZ ,SDRAM Memory Data Width" "16-bit D[31:16],16-bit D[15:0],32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " SRT ,Self Refresh Timer" "Disabled/Run Mode,No banks active/Self Refresh,256 clocks/Precharge all & Self Refresh,512 clocks/Precharge all & Self Refresh"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " PWDT ,Power Down Timer" "Disabled/Run Mode,No banks active/Precharge power down,64 clocks/Active power down,128 clocks/Active power down"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "ESDCFG1,ESDRAMC Configuration Registers 1"
|
|
bitfld.long 0x00 28.--31. " TRFC ,Auto refresh to any command" "10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks"
|
|
bitfld.long 0x00 24.--27. " TXSR ,Exit self refresh to any command" "25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks,32 clocks,33 clocks,34 clocks,35 clocks,36 clocks,37 clocks,38 clocks,39 clocks,40 clocks"
|
|
bitfld.long 0x00 21.--23. " TXP ,LPDDR exit power down to next valid command delay" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TWTR ,tLPDDR WRITE to READ Command Delay" "1 clock,2 clocks"
|
|
bitfld.long 0x00 18.--19. " TRP ,SDRAM Row Precharge Delay" "2 clock,3 clocks,4 clocks,5 clocks"
|
|
bitfld.long 0x00 16.--17. " TMRD ,tMRD - SDRAM Load Mode Register to ACTIVE Command" "1 clock,2 clocks,3 clocks,4 clocks"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TRAS ,SDRAM ACTIVE to PRECHARGE Command" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
bitfld.long 0x00 10.--11. " TRRD ,ACTIVE Bank A to ACTIVE Bank B Command" "1 clock,2 clocks,3 clocks,4 clocks"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TWR ,SDRAM WRITE to PRECHARGE Command (LPDDR)" "2 clocks,3 clocks"
|
|
bitfld.long 0x00 4.--6. " TRCD ,SDRAM Row to Column Delay" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks"
|
|
bitfld.long 0x00 0.--3. " TRC ,SDRAM Row Cycle Delay" "20 clocks,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
width 10.
|
|
if (((per.l(ad:0x83fd9000+0x10))&0x10)==0x10)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ESDMISC,ESDMISC Miscellaneous Register"
|
|
bitfld.long 0x00 31. " CS0_RDY ,External SDRAM/LPDDR Device on CS0 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 30. " CS1_RDY ,External SDRAM/LPDDR Device on CS1 Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODT_IDLE_ON ,ODT behavior in IDLE mode" "Last value,Turn off"
|
|
bitfld.long 0x00 28. " SDCLK_EXT ,SDCLK extension" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " TERM_CTL3 ,Termination Control 3 (DQS[3] and DQ[31:24])" "No termination,150 Ohm,75 Ohm,50 Ohm"
|
|
bitfld.long 0x00 24.--25. " TERM_CTL2 ,Termination Control 2 (DQS[2] and DQ[23:16])" "No termination,150 Ohm,75 Ohm,50 Ohm"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " TERM_CTL1 ,Termination Control 1 (DQS[1] and DQ[15:8])" "No termination,150 Ohm,75 Oh,50 Ohm"
|
|
bitfld.long 0x00 20.--21. " TERM_CTL0 ,Termiantion Control 0 (DQS[3] and DQ[7:0])" "No termination,150 Ohm,75 Ohm,50 Ohm"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AP_BIT ,Auto Precharge bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " DIFF_DQS_EN ,Differential DQS Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " AUTO_DLL_PAUSE ,Auto DLL Pause Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ODT_EN ,ODT Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BI_ON ,Bank interleaving" "Not interleaved,Interleaved"
|
|
bitfld.long 0x00 11. " FRC_MSR ,Force measurement" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " MIF3_MODE ,Controlling the MIF3 mechanism" "Disable,Enable for pending access only,Enable for pending access only,Enable for pending/predicted access"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " RALAT ,Read Additional Latency for LPDDR SDRAM" "Fast,Normal,Slow,?..."
|
|
bitfld.long 0x00 6. " DDR2_8_BANK ,DDR2 device with 8 bank is in use" "4 bank,8 bank"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LHD ,Latency Hiding Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DDR2_EN ,Regular (non mobile DDR2) device" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DDR_EN ,Regular (non mobile) DDR1 device is connected" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Software Initiated Local Module Reset" "No reset,Reset"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ESDMISC,ESDMISC Miscellaneous Register"
|
|
bitfld.long 0x00 31. " CS0_RDY ,External SDRAM/LPDDR Device on CS0 Status" "Not ready,Ready"
|
|
bitfld.long 0x00 30. " CS1_RDY ,External SDRAM/LPDDR Device on CS1 Status" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ODT_IDLE_ON ,ODT behavior in IDLE mode" "Last value,Turn off"
|
|
bitfld.long 0x00 28. " SDCLK_EXT ,SDCLK extension" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " AP_BIT ,Auto Precharge bit location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BI_ON ,Bank interleaving" "Not interleaved,Interleaved"
|
|
bitfld.long 0x00 11. " FRC_MSR ,Force measurement" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " MIF3_MODE ,Controlling the MIF3 mechanism" "Disable,Enable for pending access only,Enable for pending access only,Enable for pending/predicted access"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " RALAT ,Read Additional Latency for LPDDR SDRAM" "Fast,Normal,Slow,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " LHD ,Latency Hiding Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DDR2_EN ,Regular (non mobile DDR2) device" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DDR_EN ,Regular (non mobile) DDR1 device is connected" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Software Initiated Local Module Reset" "No reset,Reset"
|
|
endif
|
|
width 10.
|
|
if (((per.l(ad:0x83fd9000+0x10))&0x18)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ESDSCR,SDRAM Special Command Register"
|
|
hexmask.long.word 0x00 16.--30. 1. " PSEUDO_ADDR ,Pseudo Address"
|
|
bitfld.long 0x00 15. " CON_REQ ,Configuration request" "Operating normally,Held low"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CON_ACK ,Configuration acknowledge" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CMD ,Command" "No command/Exit low power mode,Precharge,Auto-Refresh Command,Load Mode Register Command,Manual Self Refresh,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " CS ,Chip Select" "0,1"
|
|
bitfld.long 0x00 0.--1. " BA ,Bank Address" "0,1,2,3"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ESDSCR,SDRAM Special Command Register"
|
|
hexmask.long.word 0x00 16.--30. 1. " PSEUDO_ADDR ,Pseudo Address"
|
|
bitfld.long 0x00 15. " CON_REQ ,Configuration request" "Operating normally,Held low"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CON_ACK ,Configuration acknowledge" "Not idle,Idle"
|
|
bitfld.long 0x00 6. " MAN_DLL_PAUSE ,Manual DLL Pause" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CMD ,Command" "No command/Exit low power mode,Precharge,Auto-Refresh Command,Load Mode Register Command,Manual Self Refresh,Deep power down,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " CS ,Chip Select" "0,1"
|
|
bitfld.long 0x00 0.--1. " BA ,Bank Address" "0,1,2,3"
|
|
endif
|
|
width 10.
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "ESDDAR,SDRAM Debug Address Register"
|
|
group.long 0x20++0x1f
|
|
line.long 0x00 "ESDCDLY1,MDDR Delay Line 1 Configuration Debug Register"
|
|
bitfld.long 0x00 31. " SEL_DLY_REG_1 ,Line 1 Delay" "1/4 cycle +/- DLY_OFFSET_1,DLY_REG_1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLY_OFFSET_1 ,Delay line 1 offset value"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLY_ABS_OFFSET_1 ,Absolute delay offset"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DLY_REG_1 ,Line 1 Delay"
|
|
line.long 0x04 "ESDCDLY2,MDDR Delay Line 2 Configuration Debug Register"
|
|
bitfld.long 0x04 31. " SEL_DLY_REG_2 ,Line 2 Delay" "1/4 cycle +/- DLY_OFFSET_2,DLY_REG_2"
|
|
textline " "
|
|
hexmask.long.byte 0x04 16.--23. 1. " DLY_OFFSET_2 ,Delay line 2 offset value"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " DLY_ABS_OFFSET_2 ,Absolute delay offset"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DLY_REG_2 ,Line 2 Delay"
|
|
line.long 0x08 "ESDCDLY3,MDDR Delay Line 3 Configuration Debug Register"
|
|
bitfld.long 0x08 31. " SEL_DLY_REG_3 ,Line 3 Delay" "1/4 cycle +/- DLY_OFFSET_3,DLY_REG_3"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--23. 1. " DLY_OFFSET_3 ,Delay line 3 offset value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " DLY_ABS_OFFSET_3 ,Absolute delay offset"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DLY_REG_3 ,Line 3 Delay"
|
|
line.long 0x0c "ESDCDLY4,MDDR Delay Line 4 Configuration Debug Register"
|
|
bitfld.long 0x0c 31. " SEL_DLY_REG_4 ,Line 4 Delay" "1/4 cycle +/- DLY_OFFSET_4,DLY_REG_4"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 16.--23. 1. " DLY_OFFSET_4 ,Delay line 4 offset value"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 8.--15. 1. " DLY_ABS_OFFSET_4 ,Absolute delay offset"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " DLY_REG_4 ,Line 4 Delay"
|
|
line.long 0x10 "ESDCDLY5,MDDR Delay Line 5 Configuration Debug Register"
|
|
bitfld.long 0x10 31. " SEL_DLY_REG_5 ,Line 5 Delay" "1/4 cycle +/- DLY_OFFSET_5,DLY_REG_5"
|
|
textline " "
|
|
hexmask.long.byte 0x10 16.--23. 1. " DLY_OFFSET_5 ,Delay line 5 offset value"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " DLY_ABS_OFFSET_5 ,Absolute delay offset"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DLY_REG_5 ,Line 5 Delay"
|
|
width 10.
|
|
line.long 0x14 "ESDGPR,General-Purpose Register"
|
|
bitfld.long 0x14 31. " DIG_EN ,DQS-IN gating enable" "Off,On"
|
|
bitfld.long 0x14 29.--30. " DIG_CYC ,DQS-IN gating location in cycle units" "Not delayed,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x14 27.--28. " DIG_QTR ,DQS-IN gating location in 1/4 cycle units" "Not delayed,1/4 cycle,2/4 cycle,3/4 cycle"
|
|
bitfld.long 0x14 25.--26. " DIG_OFF0 ,DQS-IN gating location offset for DQS[0]" "Not delayed,1/4 cycle,2/4 cycle,3/4 cycle"
|
|
textline " "
|
|
bitfld.long 0x14 23.--24. " DIG_OFF1 ,DQS-IN gating location offset for DQS[1]" "Not delayed,1/4 cycle,2/4 cycle,3/4 cycle"
|
|
bitfld.long 0x14 21.--22. " DIG_OFF2 ,DQS-IN gating location offset for DQS[2]" "Not delayed,1/4 cycle,2/4 cycle,3/4 cycle"
|
|
textline " "
|
|
bitfld.long 0x14 19.--20. " DIG_OFF3 ,DQS-IN gating location offset for DQS[3]" "Not delayed,1/4 cycle,2/4 cycle,3/4 cycle"
|
|
bitfld.long 0x14 16.--17. " SCT ,Significant Change Threshold" "2 delay units,QTR_CYCLE_LENGTH/2,QTR_CYCLE_LENGTH/4,QTR_CYCLE_LENGTH/8"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " QTR_CYCLE_LENGTH ,Number of small delay units"
|
|
line.long 0x18 "ESDPRCT0,SDRAM Control 0 Register"
|
|
bitfld.long 0x18 21.--23. " PRCT7 ,Precharge Timer for bank 7" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
bitfld.long 0x18 18.--20. " PRCT6 ,Precharge Timer for bank 6" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
textline " "
|
|
bitfld.long 0x18 15.--17. " PRCT5 ,Precharge Timer for bank 5" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
bitfld.long 0x18 12.--14. " PRCT4 ,Precharge Timer for bank 4" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
textline " "
|
|
bitfld.long 0x18 9.--11. " PRCT3 ,Precharge Timer for bank 3" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
bitfld.long 0x18 6.--8. " PRCT2 ,Precharge Timer for bank 2" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
textline " "
|
|
bitfld.long 0x18 3.--5. " PRCT1 ,Precharge Timer for bank 1" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
bitfld.long 0x18 0.--2. " PRCT0 ,Precharge Timer for bank 0" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
line.long 0x1c "ESDPRCT1,SDRAM Control 1 Register"
|
|
bitfld.long 0x1c 21.--23. " PRCT7 ,Precharge Timer for bank 7" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
bitfld.long 0x1c 18.--20. " PRCT6 ,Precharge Timer for bank 6" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
textline " "
|
|
bitfld.long 0x1c 15.--17. " PRCT5 ,Precharge Timer for bank 5" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
bitfld.long 0x1c 12.--14. " PRCT4 ,Precharge Timer for bank 4" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
textline " "
|
|
bitfld.long 0x1c 9.--11. " PRCT3 ,Precharge Timer for bank 3" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
bitfld.long 0x1c 6.--8. " PRCT2 ,Precharge Timer for bank 2" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
textline " "
|
|
bitfld.long 0x1c 3.--5. " PRCT1 ,Precharge Timer for bank 1" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
bitfld.long 0x1c 0.--2. " PRCT0 ,Precharge Timer for bank 0" "Disabled,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks"
|
|
width 6.
|
|
base ad:0x90000000
|
|
hgroup.long 0x00++0x3 "Memory"
|
|
hide.long 0x00 "CSD0,CSD0 SDRAM/LPDDR Memory Region"
|
|
button "CSD0" "d ad:0x90000000--ad:0x9fffffff /long"
|
|
base ad:0xa0000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CSD1,CSD1 SDRAM/LPDDR Memory Region"
|
|
button "CSD1" "d ad:0xa0000000--ad:0xafffffff /long"
|
|
width 0xb
|
|
tree.end
|
|
tree "WEIM (Wireless External Interface Module)"
|
|
base ad:0x83fda000
|
|
width 0x9
|
|
group.long 0x0++0x3 "CS0"
|
|
line.long 0x00 "CS0GCR1,Chip Select 0 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x0 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x0 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" "Reserved,16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x0 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Control Register Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
group.long 0x4++0x3
|
|
line.long 0x00 "CS0GCR2,Chip Select 0 General Control Register 2"
|
|
bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles"
|
|
bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..."
|
|
group.long 0x8++0x3
|
|
line.long 0x00 "CS0RCR1,Chip Select 0 Read Control Register 1"
|
|
bitfld.long 0x00 24.--29. " RWSC ,Read Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " RADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAL ,Read ADV Low" "RADVN,Ignored"
|
|
bitfld.long 0x00 16.--18. " RADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OEA ,OE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 8.--10. " OEN ,OE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RCSA ,Read CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " RCSN ,Read CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
if (((per.long(ad:0x83fda000+0x0))&0x3000)==0x0)
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "CS0RCR2,Chip Select 0 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1,2,3,4"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "CS0RCR2,Chip Select 0 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1.5,2.5,3.5,4.5"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
if (((per.long(ad:0x83fda000+0x0))&0x2)==0x0)
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "CS0WCR1,Chip Select 0 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " WBEA ,BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 6.--8. " WEN ,WE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " WCSN ,Write CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "CS0WCR1,Chip Select 0 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "CS0WCR2,Chip Select 0 Write Configuration Register 2"
|
|
bitfld.long 0x00 0. " WBCDD ,Write Burst Clock Divisor Decrement" "No effect,Preformed"
|
|
group.long 0x18++0x3 "CS1"
|
|
line.long 0x00 "CS1GCR1,Chip Select 1 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x0 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x0 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" "Reserved,16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x0 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Control Register Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "CS1GCR2,Chip Select 1 General Control Register 2"
|
|
bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles"
|
|
bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..."
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "CS1RCR1,Chip Select 1 Read Control Register 1"
|
|
bitfld.long 0x00 24.--29. " RWSC ,Read Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " RADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAL ,Read ADV Low" "RADVN,Ignored"
|
|
bitfld.long 0x00 16.--18. " RADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OEA ,OE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 8.--10. " OEN ,OE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RCSA ,Read CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " RCSN ,Read CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
if (((per.long(ad:0x83fda000+0x18))&0x3000)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "CS1RCR2,Chip Select 1 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1,2,3,4"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "CS1RCR2,Chip Select 1 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1.5,2.5,3.5,4.5"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
if (((per.long(ad:0x83fda000+0x18))&0x2)==0x0)
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "CS1WCR1,Chip Select 1 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " WBEA ,BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 6.--8. " WEN ,WE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " WCSN ,Write CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "CS1WCR1,Chip Select 1 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "CS1WCR2,Chip Select 1 Write Configuration Register 2"
|
|
bitfld.long 0x00 0. " WBCDD ,Write Burst Clock Divisor Decrement" "No effect,Preformed"
|
|
group.long 0x30++0x3 "CS2"
|
|
line.long 0x00 "CS2GCR1,Chip Select 2 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x0 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x0 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" "Reserved,16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x0 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Control Register Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "CS2GCR2,Chip Select 2 General Control Register 2"
|
|
bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles"
|
|
bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..."
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "CS2RCR1,Chip Select 2 Read Control Register 1"
|
|
bitfld.long 0x00 24.--29. " RWSC ,Read Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " RADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAL ,Read ADV Low" "RADVN,Ignored"
|
|
bitfld.long 0x00 16.--18. " RADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OEA ,OE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 8.--10. " OEN ,OE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RCSA ,Read CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " RCSN ,Read CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
if (((per.long(ad:0x83fda000+0x30))&0x3000)==0x0)
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "CS2RCR2,Chip Select 2 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1,2,3,4"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "CS2RCR2,Chip Select 2 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1.5,2.5,3.5,4.5"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
if (((per.long(ad:0x83fda000+0x30))&0x2)==0x0)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "CS2WCR1,Chip Select 2 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " WBEA ,BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 6.--8. " WEN ,WE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " WCSN ,Write CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "CS2WCR1,Chip Select 2 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "CS2WCR2,Chip Select 2 Write Configuration Register 2"
|
|
bitfld.long 0x00 0. " WBCDD ,Write Burst Clock Divisor Decrement" "No effect,Preformed"
|
|
group.long 0x48++0x3 "CS3"
|
|
line.long 0x00 "CS3GCR1,Chip Select 3 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x0 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x0 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" "Reserved,16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x0 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Control Register Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "CS3GCR2,Chip Select 3 General Control Register 2"
|
|
bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles"
|
|
bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..."
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "CS3RCR1,Chip Select 3 Read Control Register 1"
|
|
bitfld.long 0x00 24.--29. " RWSC ,Read Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " RADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAL ,Read ADV Low" "RADVN,Ignored"
|
|
bitfld.long 0x00 16.--18. " RADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OEA ,OE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 8.--10. " OEN ,OE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RCSA ,Read CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " RCSN ,Read CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
if (((per.long(ad:0x83fda000+0x48))&0x3000)==0x0)
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "CS3RCR2,Chip Select 3 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1,2,3,4"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "CS3RCR2,Chip Select 3 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1.5,2.5,3.5,4.5"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
if (((per.long(ad:0x83fda000+0x48))&0x2)==0x0)
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "CS3WCR1,Chip Select 3 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " WBEA ,BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 6.--8. " WEN ,WE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " WCSN ,Write CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "CS3WCR1,Chip Select 3 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "CS3WCR2,Chip Select 3 Write Configuration Register 2"
|
|
bitfld.long 0x00 0. " WBCDD ,Write Burst Clock Divisor Decrement" "No effect,Preformed"
|
|
group.long 0x60++0x3 "CS4"
|
|
line.long 0x00 "CS4GCR1,Chip Select 4 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x0 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x0 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" "Reserved,16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x0 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Control Register Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "CS4GCR2,Chip Select 4 General Control Register 2"
|
|
bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles"
|
|
bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..."
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "CS4RCR1,Chip Select 4 Read Control Register 1"
|
|
bitfld.long 0x00 24.--29. " RWSC ,Read Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " RADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAL ,Read ADV Low" "RADVN,Ignored"
|
|
bitfld.long 0x00 16.--18. " RADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OEA ,OE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 8.--10. " OEN ,OE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RCSA ,Read CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " RCSN ,Read CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
if (((per.long(ad:0x83fda000+0x60))&0x3000)==0x0)
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "CS4RCR2,Chip Select 4 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1,2,3,4"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "CS4RCR2,Chip Select 4 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1.5,2.5,3.5,4.5"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
if (((per.long(ad:0x83fda000+0x60))&0x2)==0x0)
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "CS4WCR1,Chip Select 4 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " WBEA ,BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 6.--8. " WEN ,WE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " WCSN ,Write CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "CS4WCR1,Chip Select 4 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "CS4WCR2,Chip Select 4 Write Configuration Register 2"
|
|
bitfld.long 0x00 0. " WBCDD ,Write Burst Clock Divisor Decrement" "No effect,Preformed"
|
|
group.long 0x78++0x3 "CS5"
|
|
line.long 0x00 "CS5GCR1,Chip Select 5 General Control Register 1"
|
|
bitfld.long 0x00 28.--31. " PSZ ,Page Size" "8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,?..."
|
|
bitfld.long 0x0 27. " WP ,Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " GBC ,Gap Between Chip Selects" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x0 23. " AUS ,Address UnShifted" "Shifted,Unshifted"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CSREC ,CS Recovery" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 19. " SP ,Supervisor Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " DSZ ,Data Port Size" "Reserved,16-bit[15:0],16-bit[31:16],32-bit[31:0],8 bit[7:0],8 bit[15:8],8 bit[23:16],8 bit[31:24]"
|
|
bitfld.long 0x00 14.--15. " BCS ,Burst clock start delay" "No cycles,1 cycle,2 cycles,3 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " BCD ,Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x0 11. " WC ,Write Continuous" "Not continuous,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " BL ,Burst Length" "4 words,8 words,16 words,32 words,Continuous,?..."
|
|
bitfld.long 0x00 7. " CREP ,Control Register Enable Polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRE ,Control Register Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RFL ,Read Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WFL ,Write Fix Latency" "Wait,Terminated internally"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MUM ,Multiplexed Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SRD ,Synchronous Read Data" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWR ,Synchronous Write Data" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 0. " CSEN ,CS Enable" "Disabled,Enabled"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "CS5GCR2,Chip Select 5 General Control Register 2"
|
|
bitfld.long 0x00 9. " DAP ,Data Acknowledge Polarity" "Active high,Active low"
|
|
bitfld.long 0x00 8. " DAE ,Data Acknowledge Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DAPS ,Data Acknowledge Poling Start" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles"
|
|
bitfld.long 0x00 0.--1. " ADH ,Address hold time" "0 cycles,1 cycle,2 cycles,?..."
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "CS5RCR1,Chip Select 5 Read Control Register 1"
|
|
bitfld.long 0x00 24.--29. " RWSC ,Read Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " RADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RAL ,Read ADV Low" "RADVN,Ignored"
|
|
bitfld.long 0x00 16.--18. " RADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " OEA ,OE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 8.--10. " OEN ,OE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " RCSA ,Read CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " RCSN ,Read CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
if (((per.long(ad:0x83fda000+0x78))&0x3000)==0x0)
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "CS5RCR2,Chip Select 5 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1,2,3,4"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "CS5RCR2,Chip Select 5 Read Control Register 2"
|
|
bitfld.long 0x00 15. " APR ,Asynchronous Page Read" "Word,Page"
|
|
bitfld.long 0x00 12.--14. " PAT ,Page Access Time" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RL ,Read Latency" "1.5,2.5,3.5,4.5"
|
|
bitfld.long 0x00 4.--6. " RBEA ,Read BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RBE ,Read BE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " RBEN ,Read /BE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
if (((per.long(ad:0x83fda000+0x78))&0x2)==0x0)
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "CS5WCR1,Chip Select 5 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " WBEA ,BE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 12.--14. " WBEN ,BE[3:0] Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 6.--8. " WEN ,WE Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0.--2. " WCSN ,Write CS Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
else
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "CS5WCR1,Chip Select 5 Write Control Register 1"
|
|
bitfld.long 0x00 31. " WAL ,Write ADV Low" "As WADVN,Ignored"
|
|
bitfld.long 0x00 30. " WBED ,Write Byte Enable Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 24.--29. " WWSC ,Write Wait State Control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " WADVA ,ADV Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 18.--20. " WADVN ,ADV Negation" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " WEA ,WE Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 3.--5. " WCSA ,Write CS Assertion" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
endif
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "CS5WCR2,Chip Select 5 Write Configuration Register 2"
|
|
bitfld.long 0x00 0. " WBCDD ,Write Burst Clock Divisor Decrement" "No effect,Preformed"
|
|
group.long 0x90++3 "Common"
|
|
line.long 0x00 "WCR,WEIM Configuration Register"
|
|
bitfld.long 0x00 9.--10. " WDOG_LIMIT ,Memory Wdog cycle limit" "128 cycles,256 cycles,512 cycles,1024 cycles"
|
|
bitfld.long 0x00 8. " WDOG_EN ,Memory Wdog enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTPOL ,Interrupt Polarity" "Active low,Active high"
|
|
bitfld.long 0x00 4. " INTEN ,Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " GBCD ,General Burst Clock Divisor" "Div by 1,Div by 2,Div by 3,Div by 4"
|
|
bitfld.long 0x00 0. " BCM ,Burst Clock Mode" "Depend on CS config,When aclk active"
|
|
group.long 0x94++3
|
|
line.long 0x00 "WIAR,WEIM IP Access Register"
|
|
bitfld.long 0x00 4. " ACLK_EN ,ACLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ERRST ,Enable READY After Reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INT ,Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " IPS_ACK ,WEIM is ready for ips access" "Not accessed,Accessed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPS_REQ ,IPS request" "Not requested,Requested"
|
|
rgroup.long 0x98++3
|
|
line.long 0x00 "EAR,Error Address Register"
|
|
tree "Memory"
|
|
width 5.
|
|
base ad:0xb0000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS0,WEIM CS0 Memory Region"
|
|
button "CS0 " "d ad:0xb0000000--ad:0xb7ffffff /long"
|
|
base ad:0xb8000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS1,WEIM CS1 Memory Region"
|
|
button "CS1 " "d ad:0xb8000000--ad:0xbfffffff /long"
|
|
base ad:0xc0000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS2,WEIM CS2 Memory Region"
|
|
button "CS2 " "d ad:0xc0000000--ad:0xc7ffffff /long"
|
|
base ad:0xc8000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS3,WEIM CS3 Memory Region"
|
|
button "CS3 " "d ad:0xc8000000--ad:0xcbffffff /long"
|
|
base ad:0xcc000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS4,WEIM CS4 Memory Region"
|
|
button "CS4 " "d ad:0xcc000000--ad:0xcdffffff /long"
|
|
base ad:0xce000000
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "CS5,WEIM CS5 Memory Region"
|
|
button "CS5 " "d ad:0xce000000--ad:0xcffeffff /long"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "M4IF (Multi Master Multi Memory Interface)"
|
|
base ad:0x83fd8000
|
|
width 0xa
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "PSM0,Power saving masters 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " M1_PST ,Master #1 power saving timer"
|
|
bitfld.long 0x00 22. " M1_WIS ,Master #1 Write Idle Status" "Idle,Not idle"
|
|
textline " "
|
|
bitfld.long 0x00 21. " M1_RIS ,Master #1 Read Idle Status" "Idle,Not idle"
|
|
bitfld.long 0x00 20. " M1_PSS ,Master #1 Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " M1_ROC ,Master #1 ready off cycles" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 16. " M1_PSD ,Master #1 power saving disable" "No,Yes"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " M0_PST ,Master #0 power saving timer"
|
|
bitfld.long 0x00 6. " M0_WIS ,Master #0 Write Idle Status" "Idle,Not idle"
|
|
textline " "
|
|
bitfld.long 0x00 5. " M0_RIS ,Master #0 Read Idle Status" "Idle,Not idle"
|
|
bitfld.long 0x00 4. " M0_PSS ,Master #0 Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " M0_ROC ,Master #0 ready off cycles" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x00 0. " M0_PSD ,Master #0 power saving disable" "No,Yes"
|
|
line.long 0x04 "PSM1,Power saving masters 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " M3_PST ,Master #3 power saving timer"
|
|
bitfld.long 0x04 22. " M3_WIS ,Master #3 Write Idle Status" "Idle,Not idle"
|
|
textline " "
|
|
bitfld.long 0x04 21. " M3_RIS ,Master #3 Read Idle Status" "Idle,Not idle"
|
|
bitfld.long 0x04 20. " M3_PSS ,Master #3 Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " M3_ROC ,Master #3 ready off cycles" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x04 16. " M3_PSD ,Master #3 power saving disable" "No,Yes"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " M2_PST ,Master #2 power saving timer"
|
|
bitfld.long 0x04 6. " M2_WIS ,Master #2 Write Idle Status" "Idle,Not idle"
|
|
textline " "
|
|
bitfld.long 0x04 5. " M2_RIS ,Master #2 Read Idle Status" "Idle,Not idle"
|
|
bitfld.long 0x04 4. " M2_PSS ,Master #2 Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
bitfld.long 0x04 1.--3. " M2_ROC ,Master #2 ready off cycles" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.long 0x04 0. " M2_PSD ,Master #2 power saving disable" "No,Yes"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "MDSR6,M4IF Debug Status Register #6"
|
|
hexmask.long.tbyte 0x0 0.--20. 1. " REQ_ACC ,Number of accesses made by a specific request"
|
|
line.long 0x4 "MDSR7,M4IF Debug Status Register #7"
|
|
line.long 0x8 "MDSR8,M4IF Debug Status Register #8"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "MDSR0,M4IF Debug Status Register 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " MAX_TIME ,Maximum Time for Bus"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MAX_DPR ,Maximum Dynamic Priority"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "MDSR1,M4IF Debug Status Register 1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " TOT_ACC ,Total Accesses"
|
|
rgroup.long 0x2C++0xf
|
|
line.long 0x0 "MDSR2,M4IF Debug Status Register 2"
|
|
hexmask.long.word 0x0 16.--31. 1. " M1_ACC ,Master1 Accesses"
|
|
hexmask.long.word 0x0 0.--15. 1. " M0_ACC ,Master0 Accesses"
|
|
line.long 0x4 "MDSR3,M4IF Debug Status Register 3"
|
|
hexmask.long.word 0x4 16.--31. 1. " M3_ACC ,Master3 Accesses"
|
|
hexmask.long.word 0x4 0.--15. 1. " M2_ACC ,Master2 Accesses"
|
|
line.long 0x8 "MDSR4,M4IF Debug Status Register 4"
|
|
hexmask.long.word 0x8 16.--31. 1. " M5_ACC ,Master5 Accesses"
|
|
hexmask.long.word 0x8 0.--15. 1. " M4_ACC ,Master4 Accesses"
|
|
line.long 0xC "MDSR5,M4IF Debug Status Register 5"
|
|
hexmask.long.word 0xC 16.--31. 1. " M7_ACC ,Master7 Accesses"
|
|
hexmask.long.word 0xC 0.--15. 1. " M6_ACC ,Master6 Accesses"
|
|
group.long 0x40++7
|
|
line.long 0x00 "FBPM0,F_Basic Priority Reg 0"
|
|
bitfld.long 0x00 24.--26. " FBPM_M3 ,Basic priority value as configured by the user to master 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " FBPM_M2 ,Basic priority value as configured by the user to master 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " FBPM_M1 ,Basic priority value as configured by the user to master 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " FBPM_M0 ,Basic priority value as configured by the user to master 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "FBPM1,F_Basic Priority Reg 1"
|
|
bitfld.long 0x04 24.--26. " FBPM_M7 ,Basic priority value as configured by the user to master 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " FBPM_M6 ,Basic priority value as configured by the user to master 6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " FBPM_M5 ,Basic priority value as configured by the user to master 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " FBPM_M4 ,Basic priority value as configured by the user to master 4" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48++3
|
|
line.long 0x00 "MIF4,MIF4 Scoring"
|
|
bitfld.long 0x00 19.--21. " MIF4_PAG_HIT ,MIF4 Page Hit Rate" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " MIF4_ACC_HIT ,MIF4 Access Hit Rate" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MIF4_DYN_JMP ,MIF4 Dynamic Jump" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " MIF4_DYN_MAX ,MIF4 Dynamic Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " MIF4_GUARD ,MIF4 Guard" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4c++3
|
|
line.long 0x00 "SBAR0,Snooping Base Address Register 0"
|
|
hexmask.long.tbyte 0x00 11.--31. 0x8 " SWBA0 ,Snooping Window Base Address"
|
|
bitfld.long 0x00 5.--7. " SSW0 ,Snooping Strobe Width" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " SWSZ0 ,Snooping Window Size" "2 KByte,4 KByte,8 KByte,16 KByte,32 KByte,64 KByte,128 KByte,256 KByte,512 KByte,1 MByte,2 MByte,4 MByte,8 MByte,16 MByte,?..."
|
|
bitfld.long 0x00 0. " SE0 ,Snooping Enable" "Disabled,Enabled"
|
|
group.long 0x50++7
|
|
line.long 0x00 "SERL0,Snooping Enable Register Low"
|
|
bitfld.long 0x0 31. " SSEL0_31 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " SSEL0_30 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " SSEL0_29 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " SSEL0_28 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " SSEL0_27 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " SSEL0_26 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SSEL0_25 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " SSEL0_24 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 23. " SSEL0_23 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " SSEL0_22 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 21. " SSEL0_21 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " SSEL0_20 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SSEL0_19 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " SSEL0_18 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 17. " SSEL0_17 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " SSEL0_16 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " SSEL0_15 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " SSEL0_14 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " SSEL0_13 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " SSEL0_12 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " SSEL0_11 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " SSEL0_10 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " SSEL0_9 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " SSEL0_8 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " SSEL0_7 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " SSEL0_6 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SSEL0_5 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " SSEL0_4 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " SSEL0_3 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SSEL0_2 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " SSEL0_1 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " SSEL0_0 ,Snooping Segment Enable Low 0" "Disabled,Enabled"
|
|
line.long 0x04 "SERH0,Snooping Enable Register High"
|
|
bitfld.long 0x4 31. " SSEH0_63 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 30. " SSEH0_62 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " SSEH0_61 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 28. " SSEH0_60 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " SSEH0_59 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 26. " SSEH0_58 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " SSEH0_57 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 24. " SSEH0_56 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 23. " SSEH0_55 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 22. " SSEH0_54 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 21. " SSEH0_53 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " SSEH0_52 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 19. " SSEH0_51 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 18. " SSEH0_50 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 17. " SSEH0_49 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 16. " SSEH0_48 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 15. " SSEH0_47 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " SSEH0_46 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " SSEH0_45 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 12. " SSEH0_44 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " SSEH0_43 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 10. " SSEH0_42 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " SSEH0_41 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 8. " SSEH0_40 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " SSEH0_39 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " SSEH0_38 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " SSEH0_37 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 4. " SSEH0_36 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " SSEH0_35 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " SSEH0_34 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " SSEH0_33 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " SSEH0_32 ,Snooping Segment Enable High 0" "Disabled,Enabled"
|
|
group.long 0x58++7
|
|
line.long 0x00 "SSRL0,Snooping Status Register Low"
|
|
eventfld.long 0x0 31. " SSSL0_31 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 30. " SSSL0_30 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 29. " SSSL0_29 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 28. " SSSL0_28 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 27. " SSSL0_27 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 26. " SSSL0_26 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 25. " SSSL0_25 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 24. " SSSL0_24 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 23. " SSSL0_23 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 22. " SSSL0_22 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 21. " SSSL0_21 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 20. " SSSL0_20 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 19. " SSSL0_19 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 18. " SSSL0_18 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 17. " SSSL0_17 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 16. " SSSL0_16 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 15. " SSSL0_15 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 14. " SSSL0_14 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 13. " SSSL0_13 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 12. " SSSL0_12 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 11. " SSSL0_11 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 10. " SSSL0_10 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 9. " SSSL0_9 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 8. " SSSL0_8 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 7. " SSSL0_7 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 6. " SSSL0_6 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 5. " SSSL0_5 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 4. " SSSL0_4 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 3. " SSSL0_3 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 2. " SSSL0_2 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 1. " SSSL0_1 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
eventfld.long 0x0 0. " SSSL0_0 ,Snooping Segment Status Low 0" "Not occurred,Occurred"
|
|
line.long 0x04 "SSRH0,Snooping Status Register High"
|
|
eventfld.long 0x4 31. " SSSH0_63 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 30. " SSSH0_62 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 29. " SSSH0_61 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 28. " SSSH0_60 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 27. " SSSH0_59 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 26. " SSSH0_58 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 25. " SSSH0_57 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 24. " SSSH0_56 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 23. " SSSH0_55 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 22. " SSSH0_54 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 21. " SSSH0_53 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 20. " SSSH0_52 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 19. " SSSH0_51 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 18. " SSSH0_50 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 17. " SSSH0_49 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 16. " SSSH0_48 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 15. " SSSH0_47 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 14. " SSSH0_46 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 13. " SSSH0_45 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 12. " SSSH0_44 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 11. " SSSH0_43 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 10. " SSSH0_42 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 9. " SSSH0_41 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 8. " SSSH0_40 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 7. " SSSH0_39 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 6. " SSSH0_38 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 5. " SSSH0_37 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 4. " SSSH0_36 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 3. " SSSH0_35 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 2. " SSSH0_34 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 1. " SSSH0_33 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
eventfld.long 0x4 0. " SSSH0_32 ,Snooping Segment Status High 0" "Not occurred,Occurred"
|
|
group.long 0x60++3
|
|
line.long 0x00 "SBAR1,Snooping Base Address Register"
|
|
hexmask.long.tbyte 0x00 11.--31. 0x8 " SWBA1 ,Snooping Window Base Address"
|
|
bitfld.long 0x00 5.--7. " SSW1 ,Snooping Strobe Width" "No cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " SWSZ1 ,Snooping Window Size" "2 KByte,4 KByte,8 KByte,16 KByte,32 KByte,64 KByte,128 KByte,256 KByte,512 KByte,1 MByte,2 MByte,4 MByte,8 MByte,16 MByte,?..."
|
|
bitfld.long 0x00 0. " SE1 ,Snooping Enable" "Disabled,Enabled"
|
|
group.long 0x64++7
|
|
line.long 0x00 "SERL1,Snooping Enable Register Low"
|
|
bitfld.long 0x0 31. " SSEL1_31 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " SSEL1_30 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " SSEL1_29 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " SSEL1_28 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " SSEL1_27 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " SSEL1_26 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SSEL1_25 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " SSEL1_24 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 23. " SSEL1_23 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " SSEL1_22 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 21. " SSEL1_21 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " SSEL1_20 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SSEL1_19 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " SSEL1_18 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 17. " SSEL1_17 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " SSEL1_16 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " SSEL1_15 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " SSEL1_14 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " SSEL1_13 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " SSEL1_12 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " SSEL1_11 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " SSEL1_10 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " SSEL1_9 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " SSEL1_8 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " SSEL1_7 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " SSEL1_6 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SSEL1_5 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " SSEL1_4 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " SSEL1_3 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SSEL1_2 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " SSEL1_1 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " SSEL1_0 ,Snooping Segment Enable Low 1" "Disabled,Enabled"
|
|
line.long 0x04 "SERH1,Snooping Enable Register High"
|
|
bitfld.long 0x4 31. " SSEH1_63 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 30. " SSEH1_62 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " SSEH1_61 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 28. " SSEH1_60 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " SSEH1_59 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 26. " SSEH1_58 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " SSEH1_57 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 24. " SSEH1_56 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 23. " SSEH1_55 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 22. " SSEH1_54 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 21. " SSEH1_53 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " SSEH1_52 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 19. " SSEH1_51 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 18. " SSEH1_50 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 17. " SSEH1_49 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 16. " SSEH1_48 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 15. " SSEH1_47 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " SSEH1_46 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " SSEH1_45 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 12. " SSEH1_44 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " SSEH1_43 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 10. " SSEH1_42 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " SSEH1_41 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 8. " SSEH1_40 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " SSEH1_39 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " SSEH1_38 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " SSEH1_37 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 4. " SSEH1_36 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " SSEH1_35 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " SSEH1_34 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " SSEH1_33 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " SSEH1_32 ,Snooping Segment Enable High 1" "Disabled,Enabled"
|
|
group.long 0x6c++7
|
|
line.long 0x00 "SSRL1,Snooping Status Register Low"
|
|
eventfld.long 0x0 31. " SSSL1_31 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 30. " SSSL1_30 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 29. " SSSL1_29 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 28. " SSSL1_28 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 27. " SSSL1_27 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 26. " SSSL1_26 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 25. " SSSL1_25 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 24. " SSSL1_24 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 23. " SSSL1_23 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 22. " SSSL1_22 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 21. " SSSL1_21 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 20. " SSSL1_20 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 19. " SSSL1_19 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 18. " SSSL1_18 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 17. " SSSL1_17 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 16. " SSSL1_16 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 15. " SSSL1_15 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 14. " SSSL1_14 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 13. " SSSL1_13 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 12. " SSSL1_12 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 11. " SSSL1_11 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 10. " SSSL1_10 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 9. " SSSL1_9 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 8. " SSSL1_8 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 7. " SSSL1_7 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 6. " SSSL1_6 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 5. " SSSL1_5 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 4. " SSSL1_4 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 3. " SSSL1_3 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 2. " SSSL1_2 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0 1. " SSSL1_1 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0 0. " SSSL1_0 ,Snooping Segment Status Low 1" "Not occurred,Occurred"
|
|
line.long 0x04 "SSRH1,Snooping Status Register High"
|
|
eventfld.long 0x4 31. " SSSH1_63 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 30. " SSSH1_62 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 29. " SSSH1_61 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 28. " SSSH1_60 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 27. " SSSH1_59 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 26. " SSSH1_58 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 25. " SSSH1_57 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 24. " SSSH1_56 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 23. " SSSH1_55 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 22. " SSSH1_54 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 21. " SSSH1_53 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 20. " SSSH1_52 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 19. " SSSH1_51 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 18. " SSSH1_50 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 17. " SSSH1_49 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 16. " SSSH1_48 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 15. " SSSH1_47 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 14. " SSSH1_46 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 13. " SSSH1_45 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 12. " SSSH1_44 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 11. " SSSH1_43 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 10. " SSSH1_42 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 9. " SSSH1_41 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 8. " SSSH1_40 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 7. " SSSH1_39 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 6. " SSSH1_38 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 5. " SSSH1_37 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 4. " SSSH1_36 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 3. " SSSH1_35 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 2. " SSSH1_34 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x4 1. " SSSH1_33 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
eventfld.long 0x4 0. " SSSH1_32 ,Snooping Segment Status High 1" "Not occurred,Occurred"
|
|
group.long 0x74++0xb
|
|
line.long 0x00 "I2ULA,I2 Unit Level Arbitration Register"
|
|
bitfld.long 0x00 18.--20. " I2L5 ,Internal 2 Mem Level 5" "100% priority to B,25% to A,Single 50%,Double 50%,75% to A,100% to A,?..."
|
|
bitfld.long 0x00 15.--17. " I2L4M47 ,Internal 2 Mem Level 4 (m47)" "100% priority to B,25% to A,Single 50%,Double 50%,75% to A,100% to A,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " I2L4M03 ,Internal 2 Mem Level 4 (m03)" "100% priority to B,25% to A,Single 50%,Double 50%,75% to A,100% to A,?..."
|
|
bitfld.long 0x00 9.--11. " I2L3M67 ,Internal 2 Mem Level 3 (m67)" "100% priority to B,25% to A,Single 50%,Double 50%,75% to A,100% to A,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " I2L3M45 ,Internal 2 Mem Level 3 (m45)" "100% priority to B,25% to A,Single 50%,Double 50%,75% to A,100% to A,?..."
|
|
bitfld.long 0x00 3.--5. " I2L3M23 ,Internal 2 Mem Level 3 (m23)" "100% priority to B,25% to A,Single 50%,Double 50%,75% to A,100% to A,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " I2L3M01 ,Internal 2 Mem Level 3 (m01)" "100% priority to B,25% to A,Single 50%,Double 50%,75% to A,100% to A,?..."
|
|
line.long 0x04 "I2ACR,I2 Memory Arbitration Control Register"
|
|
bitfld.long 0x04 8. " I2RDT ,Read Through bit" "Store and forward,Read through"
|
|
line.long 0x08 "RINT2,M4IF Internal 2 Control Register"
|
|
bitfld.long 0x08 13. " I2DVACK ,Intr 2 DVFS acknowledge" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 12. " I2LPACK ,Intr 2 low-power acknowledge" "Not asserted,Asserted"
|
|
bitfld.long 0x08 11. " I2PSS ,Intr 2 Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
hexmask.long.byte 0x08 3.--10. 1. " I2PST ,Internal 2 memory Power Saving Timer"
|
|
bitfld.long 0x08 2. " I2DVFS ,Internal memory 2 DVFS request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x08 1. " I2LPMD ,Internal memory 2 LPMD request" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " DI2PS ,Disable Internal 2 memory Power Saving mode" "No,Yes"
|
|
rgroup.long 0x84++0x07
|
|
line.long 0x00 "SBS0,Step By Step Address 0 Register"
|
|
line.long 0x04 "SBS1,Step By Step Address 1 Register"
|
|
bitfld.long 0x04 29. " SBS_VLD ,Step By Step Valid" "Not valid,Valid"
|
|
bitfld.long 0x04 28. " SBS_TYPE ,Step By Step Request Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x04 25.--27. " SBS_LEN ,Step By Step Length" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x04 23.--24. " SBS_SIZE ,Step By Step Size" "8,16,32,64"
|
|
textline " "
|
|
bitfld.long 0x04 21.--22. " SBS_BURST ,Step By Step Burst" "Reserved,INCR,WRAP,?..."
|
|
bitfld.long 0x04 18.--20. " SBS_PROT ,Step By Step Protection" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " SBS_LOCK ,Step By Step Lock" "0,1,2,3"
|
|
bitfld.long 0x04 12.--15. " SBS_CACHE ,Step By Step Cache" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " SBS_AXI_ID ,Step By Step AXI ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " SBS_MASTER_ID ,Step By Step Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " SBS_END ,Step By Step Endianness" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x8c++7
|
|
line.long 0x00 "MCR0,M4IF Control Register 0"
|
|
bitfld.long 0x00 31. " SW_RST ,Software reset" "Reset,No reset"
|
|
bitfld.long 0x00 27. " FDVACK ,Fast DVFS acknowledge" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SDVACK ,Slow DVFS acknowledge" "Not asserted,Asserted"
|
|
bitfld.long 0x00 25. " IDVACK ,Intr DVFS acknowledge" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DVACK ,General DVFS acknowledge" "Not asserted,Asserted"
|
|
bitfld.long 0x00 23. " FLPACK ,Fast low-power acknowledge" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SLPACK ,Slow low-power acknowledge" "Not asserted,Asserted"
|
|
bitfld.long 0x00 21. " ILPACK ,Intr low-power acknowledge" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 20. " LPACK ,General low-power acknowledge" "Not asserted,Asserted"
|
|
bitfld.long 0x00 18. " FPSS ,Fast Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SPSS ,Slow Power Saving Status" "No power saving,Power saving"
|
|
bitfld.long 0x00 16. " IPSS ,Intr Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EAS3 ,Enable Stop Retortion M3" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EAS2 ,Enable Stop Retortion M2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EAS1 ,Enable Stop Retortion M1" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EAS0 ,Enable Stop Retortion M0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FDVFS ,Fast DVFS request" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " SDVFS ,Slow DVFS request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDVFS ,Internal mem. DVFS request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " DVFS ,General DVFS request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FLPMD ,Fast LPMD request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " SLPMD ,Slow LPMD request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ILPMD ,Internal mem. LPMD request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " LPMD ,General LPMD request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DFPS ,Disable Fast arb. Power Saving mode" "No,Yes"
|
|
bitfld.long 0x00 1. " DSPS ,Disable Slow arb. Power Saving mode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DIPS ,Disable Internal memory Power Saving mode" "No,Yes"
|
|
line.long 0x04 "MCR1,M4IF Control Register 1"
|
|
bitfld.long 0x04 31. " EAS7 ,Enable Stop Arbitration M7" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " EAS6 ,Enable Stop Arbitration M6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " EAS5 ,Enable Stop Arbitration M5" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " EAS4 ,Enable Stop Arbitration M4" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x04 18.--25. 1. " IPST ,Internal 1 memory arbitration Power Saving Timer"
|
|
hexmask.long.byte 0x04 9.--16. 1. " SPST ,Slow arbitration Power Saving Timer"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " FPST ,Fast arbitration Power Saving Timer"
|
|
group.long 0x94++0xb
|
|
line.long 0x00 "MDCR,M4IF Debug Control Register"
|
|
bitfld.long 0x0 31. " DBG_EN ,Debug Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " DBG_RST ,Debug Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 23. " I2SBS_EN ,Step By Step Enable int2" "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " I1SBS_EN ,Step By Step Enable slow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DDPT ,Debug Dynamic Priority Type" "Write,Read"
|
|
bitfld.long 0x00 17.--19. " DDPM ,Debug Dynamic Priority Master" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SBS_EN ,Step By Step Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FSBS ,Fast Step By Step" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SSBS ,Slow Step By Step" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " I1SBS ,Int1 Step By Step" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 11. " I2SBS ,Int2 Step By Step" "Not requested,Requested"
|
|
bitfld.long 0x00 8.--9. " RARB ,Read Arbitration" "Fast,Slow,Internal 1 mem.,Internal 2 mem."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " VARB ,Visibility Arbitration" "Fast,Slow,Internal 1 mem.,Internal 2 mem."
|
|
line.long 0x04 "FACR,Fast Arbitration Control Register"
|
|
bitfld.long 0x04 8. " FRDT ,Read Through bit" "Store and forward,Read"
|
|
bitfld.long 0x04 4.--7. " FDPUR ,Dynamic Priority Update Resolution" "Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,15"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FDPE ,Dynamic Priority Enable" "Disabled,Enabled"
|
|
line.long 0x08 "FPWC,F_Priority Weighting Configuration Register"
|
|
bitfld.long 0x08 20.--22. " FAHR ,Access Hit Rate" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 16.--19. " FPHR ,Page Hit Rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " FPCR ,FPCR" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 5.--6. " FAPR ,Access Penalty Rate" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " FDPM ,Dynamic Priority Maximum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xa0++0xf
|
|
line.long 0x00 "SACR,Slow Arbitration Control Register"
|
|
bitfld.long 0x00 8. " SRDT ,Read Through bit" "Store and forward,Read"
|
|
line.long 0x04 "PSM2,Power saving masters 2 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " M5_PST ,Master #5 power saving timer"
|
|
bitfld.long 0x04 22. " M5_WIS ,Master #5 Write Idle Status" "Idle,Not idle"
|
|
textline " "
|
|
bitfld.long 0x04 21. " M5_RIS ,Master #5 Read Idle Status" "Idle,Not idle"
|
|
bitfld.long 0x04 20. " M5_PSS ,Master #5 Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
bitfld.long 0x04 17.--19. " M5_ROC ,Master #5 ready off cycles" "Reserved,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16. " M5_PSD ,Master #5 power saving disable" "No,Yes"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " M4_PST ,Master #4 power saving timer"
|
|
bitfld.long 0x04 6. " M4_WIS ,Master #4 Write Idle Status" "Idle,Not idle"
|
|
textline " "
|
|
bitfld.long 0x04 5. " M4_RIS ,Master #4 Read Idle Status" "Idle,Not idle"
|
|
bitfld.long 0x04 4. " M4_PSS ,Master #4 Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
bitfld.long 0x04 1.--3. " M4_ROC ,Master #4 ready off cycles" "Reserved,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0. " M4_PSD ,Master #4 power saving disable" "No,Yes"
|
|
line.long 0x08 "IACR,Int. Memory Arbitration Control Register"
|
|
bitfld.long 0x08 8. " IRDT ,Read Through bit" "Store and forward,Read"
|
|
line.long 0x0c "PSM3,Power saving masters 3 Register"
|
|
hexmask.long.byte 0x0c 24.--31. 1. " M7_PST ,Master #7 power saving timer"
|
|
bitfld.long 0x0c 22. " M7_WIS ,Master #7 Write Idle Status" "Idle,Not idle"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " M7_RIS ,Master #7 Read Idle Status" "Idle,Not idle"
|
|
bitfld.long 0x0c 20. " M7_PSS , Master #7 Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
bitfld.long 0x0c 17.--19. " M7_ROC ,Master #7 ready off cycles" "Reserved,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 16. " M7_PSD ,Master #7 power saving disable" "No,Yes"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 8.--15. 1. " M6_PST ,Master #6 power saving timer"
|
|
bitfld.long 0x0c 6. " M6_WIS ,Master #6 Write Idle Status" "Idle,Not idle"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " M6_RIS ,Master #6 Read Idle Status" "Idle,Not idle"
|
|
bitfld.long 0x0c 4. " M6_PSS ,Master #6 Power Saving Status" "No power saving,Power saving"
|
|
textline " "
|
|
bitfld.long 0x0c 1.--3. " M6_ROC ,Master #6 ready off cycles" "Reserved,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0c 0. " M6_PSD ,Master #6 power saving disable" "No,Yes"
|
|
group.long 0xb0++0xb
|
|
line.long 0x00 "FULA,F_Unit_Level_Arbitration Register"
|
|
bitfld.long 0x00 18.--20. " FL5 ,Fast Level 5" "100% to B,25% to A,Single 50%,Double 50%,75% to A,100% to A,?..."
|
|
bitfld.long 0x00 15.--17. " FL4M47 ,Fast Level 4 (m47)" "100% to B,25% to A,single 50%,double 50%,75% to A,100% to A,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " FL4M03 ,Fast Level 4 (m03)" "100% to B,25% to A,single 50%,double 50%,75% to A,100% to A,?..."
|
|
bitfld.long 0x00 9.--11. " FL3M67 ,Fast Level 3 (m67)" "100% to B,25% to A,single 50%,double 50%,75% to A,100% to A,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " FL3M45 ,Fast Level 3 (m45)" "100% to B,25% to A,single 50%,double 50%,75% to A,100% to A,?..."
|
|
bitfld.long 0x00 3.--5. " FL3M23 ,Fast Level 3 (m23)" "100% to B,25% to A,single 50%,double 50%,75% to A,100% to A,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " FL3M01 ,Fast Level 3 (m01)" "100% to B,25% to A,single 50%,double 50%,75% to A,100% to A,?..."
|
|
line.long 0x04 "SULA,S_Unit_Level_Arbitration_ Register"
|
|
bitfld.long 0x04 18.--20. " SL5 ,Slow Level 5" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
bitfld.long 0x04 15.--17. " SL4M47 ,Slow Level 4 (m47)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " SL4M03 ,Slow Level 4 (m03)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
bitfld.long 0x04 9.--11. " SL3M67 ,Slow Level 3 (m67)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SL3M45 ,Slow Level 3 (m45)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
bitfld.long 0x04 3.--5. " SL3M23 ,Slow Level 3 (m23)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " SL3M01 ,Slow Level 3 (m01)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
line.long 0x08 "IULA,I_Unit_Level_Arbitration_ Register"
|
|
bitfld.long 0x08 18.--20. " IL5 ,Internal Level 5" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
bitfld.long 0x08 15.--17. " IL4M47 ,Internal Level 4 (m47)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " IL4M03 ,Internal Level 4 (m03)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
bitfld.long 0x08 9.--11. " IL3M67 ,Internal Level 3 (m67)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
textline " "
|
|
bitfld.long 0x08 6.--8. " IL3M45 ,Internal Level 3 (m45)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
bitfld.long 0x08 3.--5. " IL3M23 ,Internal Level 3 (m23)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " IL3M01 ,Internal Level 3 (m01)" "100% to B,12.5% to A,25% to A,37.5% to A,50% - 50%,62.5% A,75% to A,100% to A"
|
|
rgroup.long 0xbc++3
|
|
line.long 0x0 "FDPS,Fast_Dynamic_Priority_Status Register"
|
|
bitfld.long 0x0 16.--19. " FDP4 ,Fast Dynamic Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 12.--15. " FDP3 ,Fast Dynamic Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 8.--11. " FDP2 ,Fast Dynamic Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 4.--7. " FDP1 ,Fast Dynamic Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " FDP0 ,Fast Dynamic Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xc0++0xb
|
|
line.long 0x00 "FDPC,Fast_Dynamic_Priority_Control Register"
|
|
bitfld.long 0x00 22.--24. " FD4_MAS ,Fast Dynamic 4 master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. " FD4_RW ,Fast Dynamic 4 read/write" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " FD3_MAS ,Fast Dynamic 3 master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " FD3_RW ,Fast Dynamic 3 read/write" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " FD2_MAS ,Fast Dynamic 2 master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 11. " FD2_RW ,Fast Dynamic 2 read/write" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 7.--9. " FD1_MAS ,Fast Dynamic 1 master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6. " FD1_RW ,Fast Dynamic 1 read/write" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " FD0_MAS ,Fast Dynamic 0 master" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 1. " FD0_RW ,Fast Dynamic 0 read/write" "Write,Read"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MLEN,Master Len Interrupt"
|
|
eventfld.long 0x00 15. " FB816 ,Burst of 16 bit or 8 bit was handled in the fast arbitration" "Not occurred,Occurred"
|
|
eventfld.long 0x00 14. " SB816 ,Burst of 16 bit or 8 bit was handled in the slow arbitration" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 13. " I1B816 ,Burst of 16 bit or 8 bit was handled in the int1 arbitration" "Not occurred,Occurred"
|
|
eventfld.long 0x00 12. " I2B816 ,Burst of 16 bit or 8 bit was handled in the int2 arbitration" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " M7LEN ,Master 7 burst length value bigger then 8 status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " M6LEN ,Master 6 burst length value bigger then 8 status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " M5LEN ,Master 5 burst length value bigger then 8 status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " M4LEN ,Master 4 burst length value bigger then 8 status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " M3LEN ,Master 3 burst length value bigger then 8 status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " M2LEN ,Master 2 burst length value bigger then 8 status" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " M1LEN ,Master 1 burst length value bigger then 8 status" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " M0LEN ,Master 0 burst length value bigger then 8 status" "Not occurred,Occurred"
|
|
group.long 0xd4++0x23
|
|
line.long 0x0 "WMSA0_0,Watermark Start ADDR_0 Register Region 0"
|
|
bitfld.long 0x0 31. " WE0_0 ,WaterMark Region 0 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. " WMS0_0 ,Watermark Start Addr space 0"
|
|
line.long 0x4 "WMSA0_1,Watermark Start ADDR_0 Register Region 1"
|
|
bitfld.long 0x4 31. " WE0_1 ,WaterMark Region 1 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x4 0.--15. 1. " WMS0_1 ,Watermark Start Addr space 0"
|
|
line.long 0x8 "WMSA0_2,Watermark Start ADDR_0 Register Region 2"
|
|
bitfld.long 0x8 31. " WE0_2 ,WaterMark Region 2 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x8 0.--15. 1. " WMS0_2 ,Watermark Start Addr space 0"
|
|
line.long 0xC "WMSA0_3,Watermark Start ADDR_0 Register Region 3"
|
|
bitfld.long 0xC 31. " WE0_3 ,WaterMark Region 3 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0xC 0.--15. 1. " WMS0_3 ,Watermark Start Addr space 0"
|
|
line.long 0x10 "WMSA0_4,Watermark Start ADDR_0 Register Region 4"
|
|
bitfld.long 0x10 31. " WE0_4 ,WaterMark Region 4 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x10 0.--15. 1. " WMS0_4 ,Watermark Start Addr space 0"
|
|
line.long 0x14 "WMSA0_5,Watermark Start ADDR_0 Register Region 5"
|
|
bitfld.long 0x14 31. " WE0_5 ,WaterMark Region 5 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 0.--15. 1. " WMS0_5 ,Watermark Start Addr space 0"
|
|
line.long 0x18 "WMSA0_6,Watermark Start ADDR_0 Register Region 6"
|
|
bitfld.long 0x18 31. " WE0_6 ,WaterMark Region 6 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x18 0.--15. 1. " WMS0_6 ,Watermark Start Addr space 0"
|
|
line.long 0x1C "WMSA0_7,Watermark Start ADDR_0 Register Region 7"
|
|
bitfld.long 0x1C 31. " WE0_7 ,WaterMark Region 7 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x1C 0.--15. 1. " WMS0_7 ,Watermark Start Addr space 0"
|
|
group.long 0xf4++0x1f
|
|
line.long 0x0 "WMEA0_0,Watermark End ADDR_0 Register Region 0"
|
|
hexmask.long.word 0x0 0.--15. 1. " WME0_0 ,Watermark End Addr space 0"
|
|
line.long 0x4 "WMEA0_1,Watermark End ADDR_0 Register Region 1"
|
|
hexmask.long.word 0x4 0.--15. 1. " WME0_1 ,Watermark End Addr space 0"
|
|
line.long 0x8 "WMEA0_2,Watermark End ADDR_0 Register Region 2"
|
|
hexmask.long.word 0x8 0.--15. 1. " WME0_2 ,Watermark End Addr space 0"
|
|
line.long 0xC "WMEA0_3,Watermark End ADDR_0 Register Region 3"
|
|
hexmask.long.word 0xC 0.--15. 1. " WME0_3 ,Watermark End Addr space 0"
|
|
line.long 0x10 "WMEA0_4,Watermark End ADDR_0 Register Region 4"
|
|
hexmask.long.word 0x10 0.--15. 1. " WME0_4 ,Watermark End Addr space 0"
|
|
line.long 0x14 "WMEA0_5,Watermark End ADDR_0 Register Region 5"
|
|
hexmask.long.word 0x14 0.--15. 1. " WME0_5 ,Watermark End Addr space 0"
|
|
line.long 0x18 "WMEA0_6,Watermark End ADDR_0 Register Region 6"
|
|
hexmask.long.word 0x18 0.--15. 1. " WME0_6 ,Watermark End Addr space 0"
|
|
line.long 0x1C "WMEA0_7,Watermark End ADDR_0 Register Region 7"
|
|
hexmask.long.word 0x1C 0.--15. 1. " WME0_7 ,Watermark End Addr space 0"
|
|
group.long 0x114++0x3
|
|
line.long 0x00 "WMIS0,Watermark Interrupt and Status 0 Register"
|
|
bitfld.long 0x00 31. " WIE0 ,WaterMark Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 19.--29. 1. " FVMID0 ,Fast Violation Master ID"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--18. 1. " SVMID0 ,Slow Violation Master ID"
|
|
eventfld.long 0x00 7. " WS0_7 ,WaterMark Status0_7" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WS0_6 ,WaterMark Status0_6" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " WS0_5 ,WaterMark Status0_5" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WS0_4 ,WaterMark Status0_4" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " WS0_3 ,WaterMark Status0_3" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " WS0_2 ,WaterMark Status0_2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " WS0_1 ,WaterMark Status0_1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WS0_0 ,WaterMark Status0_0" "Not occurred,Occurred"
|
|
rgroup.long 0x118++0x7
|
|
line.long 0x0 "FWMVA0,Fast Watermark Violation Address 0 Register"
|
|
line.long 0x04 "SWMVA0,Slow Watermark Violation Address 0 register"
|
|
group.long 0x120++0x1f
|
|
line.long 0x0 "WMSA1_0,Watermark Start ADDR_1 Register Region 0"
|
|
bitfld.long 0x0 31. " WE1_0 ,WaterMark Region 0 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x0 0.--15. 1. " WMS1_0 ,Watermark Start Addr space 1"
|
|
line.long 0x4 "WMSA1_1,Watermark Start ADDR_1 Register Region 1"
|
|
bitfld.long 0x4 31. " WE1_1 ,WaterMark Region 1 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x4 0.--15. 1. " WMS1_1 ,Watermark Start Addr space 1"
|
|
line.long 0x8 "WMSA1_2,Watermark Start ADDR_1 Register Region 2"
|
|
bitfld.long 0x8 31. " WE1_2 ,WaterMark Region 2 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x8 0.--15. 1. " WMS1_2 ,Watermark Start Addr space 1"
|
|
line.long 0xC "WMSA1_3,Watermark Start ADDR_1 Register Region 3"
|
|
bitfld.long 0xC 31. " WE1_3 ,WaterMark Region 3 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0xC 0.--15. 1. " WMS1_3 ,Watermark Start Addr space 1"
|
|
line.long 0x10 "WMSA1_4,Watermark Start ADDR_1 Register Region 4"
|
|
bitfld.long 0x10 31. " WE1_4 ,WaterMark Region 4 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x10 0.--15. 1. " WMS1_4 ,Watermark Start Addr space 1"
|
|
line.long 0x14 "WMSA1_5,Watermark Start ADDR_1 Register Region 5"
|
|
bitfld.long 0x14 31. " WE1_5 ,WaterMark Region 5 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x14 0.--15. 1. " WMS1_5 ,Watermark Start Addr space 1"
|
|
line.long 0x18 "WMSA1_6,Watermark Start ADDR_1 Register Region 6"
|
|
bitfld.long 0x18 31. " WE1_6 ,WaterMark Region 6 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x18 0.--15. 1. " WMS1_6 ,Watermark Start Addr space 1"
|
|
line.long 0x1C "WMSA1_7,Watermark Start ADDR_1 Register Region 7"
|
|
bitfld.long 0x1C 31. " WE1_7 ,WaterMark Region 7 Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x1C 0.--15. 1. " WMS1_7 ,Watermark Start Addr space 1"
|
|
group.long 0x140++0x1f
|
|
line.long 0x0 "WMEA1_0,Watermark End ADDR_1 Register Region 0"
|
|
hexmask.long.word 0x0 0.--15. 1. " WME1_0 ,Watermark End Addr space 1"
|
|
line.long 0x4 "WMEA1_1,Watermark End ADDR_1 Register Region 1"
|
|
hexmask.long.word 0x4 0.--15. 1. " WME1_1 ,Watermark End Addr space 1"
|
|
line.long 0x8 "WMEA1_2,Watermark End ADDR_1 Register Region 2"
|
|
hexmask.long.word 0x8 0.--15. 1. " WME1_2 ,Watermark End Addr space 1"
|
|
line.long 0xC "WMEA1_3,Watermark End ADDR_1 Register Region 3"
|
|
hexmask.long.word 0xC 0.--15. 1. " WME1_3 ,Watermark End Addr space 1"
|
|
line.long 0x10 "WMEA1_4,Watermark End ADDR_1 Register Region 4"
|
|
hexmask.long.word 0x10 0.--15. 1. " WME1_4 ,Watermark End Addr space 1"
|
|
line.long 0x14 "WMEA1_5,Watermark End ADDR_1 Register Region 5"
|
|
hexmask.long.word 0x14 0.--15. 1. " WME1_5 ,Watermark End Addr space 1"
|
|
line.long 0x18 "WMEA1_6,Watermark End ADDR_1 Register Region 6"
|
|
hexmask.long.word 0x18 0.--15. 1. " WME1_6 ,Watermark End Addr space 1"
|
|
line.long 0x1C "WMEA1_7,Watermark End ADDR_1 Register Region 7"
|
|
hexmask.long.word 0x1C 0.--15. 1. " WME1_7 ,Watermark End Addr space 1"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "WMIS1,Watermark Interrupt and Status 1 Register"
|
|
bitfld.long 0x00 31. " WIE1 ,WaterMark Enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 19.--29. 1. " FVMID1 ,Fast Violation Master ID"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--18. 1. " SVMID1 ,Slow Violation Master ID"
|
|
eventfld.long 0x00 7. " WS1_7 ,WaterMark Status1_7" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " WS1_6 ,WaterMark Status1_6" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " WS1_5 ,WaterMark Status1_5" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WS1_4 ,WaterMark Status1_4" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " WS1_3 ,WaterMark Status1_3" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " WS1_2 ,WaterMark Status1_2" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " WS1_1 ,WaterMark Status1_1" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WS1_0 ,WaterMark Status1_0" "Not occurred,Occurred"
|
|
rgroup.long 0x164++0x07
|
|
line.long 0x00 "FWMVA1,Fast Watermark Violation Address 1 Register"
|
|
line.long 0x04 "SWMVA1,Slow Watermark Violation Address 1 register"
|
|
width 0xb
|
|
tree.end
|
|
tree "NFC (NAND Flash Controller)"
|
|
base ad:0x83fdb000
|
|
width 20.
|
|
tree "NFC AXI"
|
|
group.long 0x1e00++0x33
|
|
line.long 0x00 "NAND_CMD,Nand Flash Command"
|
|
hexmask.long.byte 0x00 24.--31. 1. " NAND_CMD3 ,NAND Flash Command3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NAND_CMD2 ,NAND Flash Command2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " NAND_CMD1 ,NAND Flash Command1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " NAND_CMD0 ,NAND Flash Command0"
|
|
line.long 0x4 "NAND_ADD0,Nand Flash Address 0"
|
|
line.long 0x8 "NAND_ADD1,Nand Flash Address 1"
|
|
line.long 0xC "NAND_ADD2,Nand Flash Address 2"
|
|
line.long 0x10 "NAND_ADD3,Nand Flash Address 3"
|
|
line.long 0x14 "NAND_ADD4,Nand Flash Address 4"
|
|
line.long 0x18 "NAND_ADD5,Nand Flash Address 5"
|
|
line.long 0x1C "NAND_ADD6,Nand Flash Address 6"
|
|
line.long 0x20 "NAND_ADD7,Nand Flash Address 7"
|
|
line.long 0x24 "NAND_ADD8,Nand Flash Address 8"
|
|
line.long 0x28 "NAND_ADD9,Nand Flash Address 9"
|
|
line.long 0x2C "NAND_ADD10,Nand Flash Address 10"
|
|
line.long 0x30 "NAND_ADD11,Nand Flash Address 11"
|
|
if ((per.l(ad:0x83fdb000+0x3024)&0x3)==0x0)
|
|
; NFC_CONFIGURATION2[PS]==00 --> page size = 1/2KB
|
|
group.long 0x1e34++0x3
|
|
line.long 0x0 "NFC_CONFIGURATION1,NFC configuration"
|
|
hexmask.long.byte 0x0 16.--23. 1. " NF_STATUS ,Nand Flash Status"
|
|
bitfld.long 0x0 12.--14. " ACTIVE_CS ,Active CS" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7"
|
|
textline " "
|
|
bitfld.long 0x0 8.--11. " NUM_OF_ITERATIONS ,Num Of Iterations" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 4.--6. " RBA ,Ram Buffer Address" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x0 2. " NFC_RST ,NFC Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " NF_CE ,NAND Flash Force CE" "Normal,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0 0. " SP_EN ,NAND Flash Spare Enable" "Main/spare,Spare only"
|
|
elif ((per.l(ad:0x83fdb000+0x3024)&0x3)==0x1)
|
|
; NFC_CONFIGURATION2[PS]==01 --> page size = 2KB
|
|
group.long 0x1e34++0x3
|
|
line.long 0x0 "NFC_CONFIGURATION1,NFC configuration"
|
|
hexmask.long.byte 0x0 16.--23. 1. " NF_STATUS ,Nand Flash Status"
|
|
bitfld.long 0x0 12.--14. " ACTIVE_CS ,Active CS" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7"
|
|
textline " "
|
|
bitfld.long 0x0 8.--11. " NUM_OF_ITERATIONS ,Num Of Iterations" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 4.--6. " RBA ,Ram Buffer Address" "1,Not allowed,Not allowed,4,Not allowed,Not allowed,Not allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x0 2. " NFC_RST ,NFC Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " NF_CE ,NAND Flash Force CE" "Normal,Asserted"
|
|
else
|
|
; NFC_CONFIGURATION2[PS]== 10 || 11 --> page size = 4KB
|
|
group.long 0x1e34++0x3
|
|
line.long 0x0 "NFC_CONFIGURATION1,NFC configuration"
|
|
hexmask.long.byte 0x0 16.--23. 1. " NF_STATUS ,Nand Flash Status"
|
|
bitfld.long 0x0 12.--14. " ACTIVE_CS ,Active CS" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7"
|
|
textline " "
|
|
bitfld.long 0x0 8.--11. " NUM_OF_ITERATIONS ,Num Of Iterations" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 4.--6. " RBA ,Ram Buffer Address" "1,Not allowed,Not allowed,Not allowed,Not allowed,Not allowed,Not allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x0 2. " NFC_RST ,NFC Reset" "No reset,Reset"
|
|
bitfld.long 0x0 1. " NF_CE ,NAND Flash Force CE" "Normal,Asserted"
|
|
endif
|
|
rgroup.long 0x1e38++0x07
|
|
line.long 0x00 "ECC_STATUS_RESULT,ECC Status and Result of Flash Operation"
|
|
bitfld.long 0x00 28.--31. " NOBER8 ,Number Of 9 bit Symbol ECC Errors for eight 528/538 bytes" "No error,1-Symbol Error,2-Symbol Error,3-Symbol Error,4-Symbol Error,5-Symbol Error,6-Symbol Error,7-Symbol Error,8-Symbol Error,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Uncorrectable error"
|
|
bitfld.long 0x00 24.--27. " NOBER7 ,Number Of 9 bit Symbol ECC Errors for seventh 528/538 bytes" "No error,1-Symbol Error,2-Symbol Error,3-Symbol Error,4-Symbol Error,5-Symbol Error,6-Symbol Error,7-Symbol Error,8-Symbol Error,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Uncorrectable error"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " NOBER6 ,Number Of 9 bit Symbol ECC Errors for sixth 528/538 bytes" "No error,1-Symbol Error,2-Symbol Error,3-Symbol Error,4-Symbol Error,5-Symbol Error,6-Symbol Error,7-Symbol Error,8-Symbol Error,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Uncorrectable error"
|
|
bitfld.long 0x00 16.--19. " NOBER5 ,Number Of 9 bit Symbol ECC Errors for fifth 528/538 bytes" "No error,1-Symbol Error,2-Symbol Error,3-Symbol Error,4-Symbol Error,5-Symbol Error,6-Symbol Error,7-Symbol Error,8-Symbol Error,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Uncorrectable error"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " NOBER4 ,Number Of 9 bit Symbol ECC Errors for fourth 528/538 bytes" "No error,1-Symbol Error,2-Symbol Error,3-Symbol Error,4-Symbol Error,5-Symbol Error,6-Symbol Error,7-Symbol Error,8-Symbol Error,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Uncorrectable error"
|
|
bitfld.long 0x00 8.--11. " NOBER3 ,Number Of 9 bit Symbol ECC Errors for third 528/538 bytes" "No error,1-Symbol Error,2-Symbol Error,3-Symbol Error,4-Symbol Error,5-Symbol Error,6-Symbol Error,7-Symbol Error,8-Symbol Error,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Uncorrectable error"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " NOBER2 ,Number Of 9 bit Symbol ECC Errors for second 528/538 bytes" "No error,1-Symbol Error,2-Symbol Error,3-Symbol Error,4-Symbol Error,5-Symbol Error,6-Symbol Error,7-Symbol Error,8-Symbol Error,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Uncorrectable error"
|
|
bitfld.long 0x00 0.--3. " NOBER1 ,Number Of 9 bit Symbol ECC Errors for first 528 bytes" "No error,1-Symbol Error,2-Symbol Error,3-Symbol Error,4-Symbol Error,5-Symbol Error,6-Symbol Error,7-Symbol Error,8-Symbol Error,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Uncorrectable error"
|
|
line.long 0x04 "STATUS_SUM,Status summary"
|
|
hexmask.long.byte 0x04 8.--15. 1. " ECC_SUM ,Ecc Summary report"
|
|
hexmask.long.byte 0x04 0.--7. 1. " NAND_STATUS_SUM ,Nand Status Summary"
|
|
group.long 0x1e40++0x03
|
|
line.long 0x00 "LAUNCH NFC,Initiate a Nand transaction"
|
|
bitfld.long 0x00 12. " AUTO_STAT ,Automatic Status Read operation" "Not executed,Executed"
|
|
bitfld.long 0x00 11. " AUTO_COPY_BACK1 ,Auto copy back sequence for all Nand devices" "Not executed,Executed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " AUTO_COPY_BACK0 ,Auto copy back sequence" "Not executed,Executed"
|
|
bitfld.long 0x00 9. " AUTO_ERASE ,Auto erase sequence" "Not executed,Executed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AUTO_READ ,Auto read sequence" "Not executed,Executed"
|
|
bitfld.long 0x00 6. " AUTO_PROG ,Auto program sequence" "Not executed,Executed"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " FDO ,NAND Flash atomic Data Output" "Reserved,One page,NAND Flash ID,Reserved,NAND Flash Status Register,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " FDI ,NAND Flash atomic Data Input" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FADD ,NAND Flash atomic Address Input" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FCMD ,NAND Flash atomic Command Input" "Not allowed,Allowed"
|
|
tree.end
|
|
tree "NFC IP"
|
|
group.long 0x3000++0x37
|
|
line.long 0x00 "NF_WR_PROT,NAND Flash Write Protection"
|
|
bitfld.long 0x00 31. " US7 ,Unlocked Status for CS7" "No unlocked,Unlocked"
|
|
bitfld.long 0x00 30. " LS7 ,Locked Status for CS7" "Not all locked,Unlocked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " LTS7 ,Lock-tight Status for CS7" "Not lock-tight,Lock-tight"
|
|
bitfld.long 0x00 28. " US6 ,Unlocked Status for CS6" "No unlocked,Unlocked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LS6 ,Locked Status for CS6" "Not all locked,Unlocked"
|
|
bitfld.long 0x00 26. " LTS6 ,Lock-tight Status for CS6" "Not lock-tight,Lock-tight"
|
|
textline " "
|
|
bitfld.long 0x00 25. " US5 ,Unlocked Status for CS5" "No unlocked,Unlocked"
|
|
bitfld.long 0x00 24. " LS5 ,Locked Status for CS5" "Not all locked,Unlocked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " LTS5 ,Lock-tight Status for CS5" "Not lock-tight,Lock-tight"
|
|
bitfld.long 0x00 22. " US4 ,Unlocked Status for CS4" "No unlocked,Unlocked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " LS4 ,Locked Status for CS4" "Not all locked,Unlocked"
|
|
bitfld.long 0x00 20. " LTS4 ,Lock-tight Status for CS4" "Not lock-tight,Lock-tight"
|
|
textline " "
|
|
bitfld.long 0x00 19. " US3 ,Unlocked Status for CS3" "No unlocked,Unlocked"
|
|
bitfld.long 0x00 18. " LS3 ,Locked Status for CS3" "Not all locked,Unlocked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " LTS3 ,Lock-tight Status for CS3" "Not lock-tight,Lock-tight"
|
|
bitfld.long 0x00 16. " US2 ,Unlocked Status for CS2" "No unlocked,Unlocked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " LS2 ,Locked Status for CS2" "Not all locked,Unlocked"
|
|
bitfld.long 0x00 14. " LTS2 ,Lock-tight Status for CS2" "Not lock-tight,Lock-tight"
|
|
textline " "
|
|
bitfld.long 0x00 13. " US1 ,Unlocked Status for CS1" "No unlocked,Unlocked"
|
|
bitfld.long 0x00 12. " LS1 ,Locked Status for CS1" "Not all locked,Unlocked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " LTS1 ,Lock-tight Status for CS1" "Not lock-tight,Lock-tight"
|
|
bitfld.long 0x00 10. " US0 ,Unlocked Status for CS0" "No unlocked,Unlocked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " LS0 ,Locked Status for CS0" "Not all locked,Unlocked"
|
|
bitfld.long 0x00 8. " LTS0 ,Lock-tight Status for CS0" "Not lock-tight,Lock-tight"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BLS ,Buffer Lock Set" "Locked,Locked,Unlocked,Locked"
|
|
bitfld.long 0x00 3.--5. " CS2L ,Chip Select to Lock" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WPC ,Write Protection Command" "Reserved,Locked-tight,Locked,Reserved,Unlocked,Unlocked,Unlocked,?..."
|
|
line.long 0x4 "UNLOCK_BLK_ADD0,Address to Unlock in Write Protection Mode for CS0"
|
|
hexmask.long.word 0x4 16.--31. 1. " UEBA0 ,Unlock end Block Address"
|
|
hexmask.long.word 0x4 0.--15. 1. " USBA0 ,Unlock Start Block Address"
|
|
line.long 0x8 "UNLOCK_BLK_ADD1,Address to Unlock in Write Protection Mode for CS1"
|
|
hexmask.long.word 0x8 16.--31. 1. " UEBA1 ,Unlock end Block Address"
|
|
hexmask.long.word 0x8 0.--15. 1. " USBA1 ,Unlock Start Block Address"
|
|
line.long 0xC "UNLOCK_BLK_ADD2,Address to Unlock in Write Protection Mode for CS2"
|
|
hexmask.long.word 0xC 16.--31. 1. " UEBA2 ,Unlock end Block Address"
|
|
hexmask.long.word 0xC 0.--15. 1. " USBA2 ,Unlock Start Block Address"
|
|
line.long 0x10 "UNLOCK_BLK_ADD3,Address to Unlock in Write Protection Mode for CS3"
|
|
hexmask.long.word 0x10 16.--31. 1. " UEBA3 ,Unlock end Block Address"
|
|
hexmask.long.word 0x10 0.--15. 1. " USBA3 ,Unlock Start Block Address"
|
|
line.long 0x14 "UNLOCK_BLK_ADD4,Address to Unlock in Write Protection Mode for CS4"
|
|
hexmask.long.word 0x14 16.--31. 1. " UEBA4 ,Unlock end Block Address"
|
|
hexmask.long.word 0x14 0.--15. 1. " USBA4 ,Unlock Start Block Address"
|
|
line.long 0x18 "UNLOCK_BLK_ADD5,Address to Unlock in Write Protection Mode for CS5"
|
|
hexmask.long.word 0x18 16.--31. 1. " UEBA5 ,Unlock end Block Address"
|
|
hexmask.long.word 0x18 0.--15. 1. " USBA5 ,Unlock Start Block Address"
|
|
line.long 0x1C "UNLOCK_BLK_ADD6,Address to Unlock in Write Protection Mode for CS6"
|
|
hexmask.long.word 0x1C 16.--31. 1. " UEBA6 ,Unlock end Block Address"
|
|
hexmask.long.word 0x1C 0.--15. 1. " USBA6 ,Unlock Start Block Address"
|
|
line.long 0x20 "UNLOCK_BLK_ADD7,Address to Unlock in Write Protection Mode for CS7"
|
|
hexmask.long.word 0x20 16.--31. 1. " UEBA7 ,Unlock end Block Address"
|
|
hexmask.long.word 0x20 0.--15. 1. " USBA7 ,Unlock Start Block Address"
|
|
line.long 0x24 "NFC_CONFIGURATION2,NFC Operation Configuration"
|
|
hexmask.long.byte 0x24 24.--31. 1. " ST_CMD ,Status Command"
|
|
hexmask.long.byte 0x24 16.--23. 1. " SPAS ,Spare Area Size"
|
|
textline " "
|
|
bitfld.long 0x24 15. " INT_MSK ,Mask interrupt Bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 14. " AUTO_PROG_DONE_MSK ,Auto Program Done Mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 12.--13. " NUM_ADR_PHASES1 ,Number Of Address Phases1" "3,4,5,6"
|
|
bitfld.long 0x24 9.--11. " EDC ,Extra dead cycles" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 7.--8. " PPB ,Pages Per Block" "32,64,128,256"
|
|
bitfld.long 0x24 6. " ECC_MODE ,Selects the error correction capabilities" "4bit,8bit"
|
|
textline " "
|
|
bitfld.long 0x24 5. " NUM_ADR_PHASES0 ,Number Of Address Phases0" "1,2"
|
|
bitfld.long 0x24 4. " NUM_CMD_PHASES ,Number Of Command Phases" "1,2"
|
|
textline " "
|
|
bitfld.long 0x24 3. " ECC_EN ,ECC operation Enable" "Bypassed,Executed"
|
|
bitfld.long 0x24 2. " SYM ,Symmetric mode" "2,1"
|
|
textline " "
|
|
bitfld.long 0x24 0.--1. " PS ,Page Size" "1/2KB,2KB,4KB,4KB"
|
|
line.long 0x28 "NFC_CONFIGURATION3,NAND Flash Operation Configuration3"
|
|
bitfld.long 0x28 20. " NO_SDMA ,NO_SDMA" "Responsible for data transfer,Not used"
|
|
textline " "
|
|
bitfld.long 0x28 16.--19. " FMP ,Fifo Mode Protect" "Disabled,64B,128B,256B,512B,1KB,2KB,4KB,?..."
|
|
bitfld.long 0x28 15. " RBB_MODE ,Ready-Busy mode" "Status-read command,Ipp_nfc_rbbX"
|
|
textline " "
|
|
bitfld.long 0x28 12.--14. " NUM_OF_DEVICES ,Num Of Devices" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x28 11. " DMA_MODE ,Dma Mode" "2 dma request,1 dma signal(log. OR of 2dma requests)"
|
|
textline " "
|
|
bitfld.long 0x28 8.--10. " SBB ,Status Busy Bit" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 4.--6. " Sb2R ,Status bit to Record" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 3. " FW ,Flash Width" "x16,x8"
|
|
textline " "
|
|
bitfld.long 0x28 2. " TOO ,Two On One" "Only 1,2"
|
|
textline " "
|
|
bitfld.long 0x28 0.--1. " ADD_OP ,Addressing Options" "Address_group0,Address_group0 and one Nand device,All address groups,All address groups"
|
|
line.long 0x2c "NFC_IPC,NAND Flash IP control"
|
|
bitfld.long 0x2C 31. " INT ,Interrupt" "Not finished,Finished"
|
|
bitfld.long 0x2C 30. " AUTO_PROG_DONE ,Automatic Program Done" "Not finished,Finished"
|
|
textline " "
|
|
bitfld.long 0x2C 29. " LPS ,Low Power Status" "Not low power,Low power"
|
|
bitfld.long 0x2C 28. " RB_B ,RB_B Status" "Busy,Idle"
|
|
textline " "
|
|
bitfld.long 0x2C 26.--27. " DMA_STATUS ,Dma Status" "Deasserted,Dma_wr_req,Dma_rd_req,Both"
|
|
bitfld.long 0x2C 1. " CACK ,IP configuration acknowledge" "Forbidden,Permitted"
|
|
textline " "
|
|
bitfld.long 0x2C 0. " CREQ ,IP request to configure NFC" "Not valid,Valid"
|
|
line.long 0x30 "AXI_ERR_ADD,AXI Error Address"
|
|
hexmask.long.word 0x30 0.--12. 1. " AXI_ERR_ADD ,AXI Error Address"
|
|
line.long 0x34 "NFC_DELAY_LINE,Delay-line"
|
|
hexmask.long.byte 0x34 8.--15. 1. " NFC_OFF_DEL ,NFC Delay-line Offset delay"
|
|
hexmask.long.byte 0x34 0.--7. 1. " NFC_ABS_DEL ,NFC Delay-line Absolute delay"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "EMIv2 (External Memory Interface Version II)"
|
|
base ad:0x83fdbf00
|
|
width 0x7
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IPLCK,IP Lock Register"
|
|
bitfld.long 0x0 5. " XFR_ERR_EN ,EMIv2's ips_xfr_err enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " LOCK_ALL ,Lock all EMIv2 registers from being configured by non privilidge masters" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " M4IF_LOCK ,Lock M4IF registers from being configured by non privilege masters" "Unlocked,Locked"
|
|
bitfld.long 0x00 2. " ESDC_LOCK ,Lock ESDCTL registers from being configured by non privilege masters" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WEIM_LOCK ,Lock WEIM registers from being configured by non privilege masters" "Unlocked,Locked"
|
|
bitfld.long 0x00 0. " NFC_LOCK ,Lock NFC register from being configured by non privilege masters" "Unlocked,Locked"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EICS,EMI Interrupt Control and Status Register"
|
|
bitfld.long 0x00 31. " EAOIE ,EMIv2 AP_ORed Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " EBOIE ,EMIv2 BP_ORed Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BM4IF_AP_INT ,M4IF AP interrupt is included in the EMIv2 BP_ORed interrupt" "Not included,Included"
|
|
bitfld.long 0x00 10. " BM4IF_BP_INT ,M4IF BP interrupt is included in the EMIv2 BP_ORed interrupt" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BWEIM_INT ,WEIM interrupt is included in the EMIv2 BP_ORed interrupt" "Not included,Included"
|
|
bitfld.long 0x00 8. " BNFC_INT ,NFC interrupt is included in the EMIv2 BP_ORed interrupt" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MAIS ,M4IF AP interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " MBIS ,M4IF BP interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WIS ,WEIMv2 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " NIS ,NFC interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AM4IF_AP_INT ,M4IF AP interrupt is included in the EMIv2 AP_ORed interrupt" "Not included,Included"
|
|
bitfld.long 0x00 2. " AM4IF_BP_INT ,M4IF BP interrupt is included in the EMIv2 AP_ORed interrupt" "Not included,Included"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AWEIM_INT ,WEIM interrupt is included in the EMIv2 AP_ORed interrupt" "Not included,Included"
|
|
bitfld.long 0x00 0. " ANFC_INT ,NFC interrupt is included in the EMIv2 AP_ORed interrupt" "Not included,Included"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "eSDHC (Enhanced Secure Digital Host Controller)"
|
|
tree "eSDHC 1"
|
|
base ad:0x70004000
|
|
width 12.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "DSADDR,DMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DS_ADDR ,DMA System Address"
|
|
line.long 0x04 "BLKATTR,Block Attributes Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer"
|
|
hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size"
|
|
line.long 0x08 "CMDARG,Command Argument Register"
|
|
line.long 0x0C "XFERTYP,Transfer Type Register"
|
|
hexmask.long.byte 0x0C 24.--29. 1. " CMDINX ,Command Index"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " CMDTYP ,Command Type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present"
|
|
bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No Response,Length 136,Length 48,Length 48 check busy"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " MSBSEL ,Multi / Single Block Select" "Single,Multiple"
|
|
bitfld.long 0x0C 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
bitfld.long 0x0C 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " BCEN ,Block Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
if (((per.long(ad:0x70004000+0x0c))&0x30000)==0x00)
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CMDRSP0,Command Response 0"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
elif (((per.long(ad:0x70004000+0x0c))&0x30000)==0x10000)
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R2 response"
|
|
line.long 0x04 "CMDRSP1,Command Response 1"
|
|
hexmask.long 0x04 0.--31. 1. " CMDRSP1 ,R2 response"
|
|
line.long 0x08 "CMDRSP2,Command Response 2"
|
|
hexmask.long 0x08 0.--31. 1. " CMDRSP2 ,R2 response"
|
|
line.long 0x0C "CMDRSP3,Command Response 3"
|
|
hexmask.long.tbyte 0x0c 0.--23. 1. " CMDRSP3 ,R2[23:0] response"
|
|
elif (((per.long(ad:0x70004000+0x0c))&0x30000)==0x20000)
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1/R3/R4/R5/R6 response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1b/R5b response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "CMDRSP3,Command Response 3"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP3 ,R1b response"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DATPORT,Buffer Data Port Register"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "PRSSTAT,Present State Register"
|
|
bitfld.long 0x00 31. " DLSL[7] ,Line 7 Signal Level" "Low,High"
|
|
bitfld.long 0x00 30. " DLSL[6] ,Line 6 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DLSL[5] ,Line 5 Signal Level" "Low,High"
|
|
bitfld.long 0x00 28. " DLSL[4] ,Line 4 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DLSL[3] ,Line 3 Signal Level" "Low,High"
|
|
bitfld.long 0x00 26. " DLSL[2] ,Line 2 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DLSL[1] ,Line 1 Signal Level" "Low,High"
|
|
bitfld.long 0x00 24. " DLSL[0] ,Line 0 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "No card,Card present"
|
|
bitfld.long 0x00 16. " CINS ,Card Inserted" "No card/Reset/Power on,Card inserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RTA ,Read Transfer Active" "No data,Transferring"
|
|
bitfld.long 0x00 8. " WTA ,Write Transfer Active" "No data,Transferring"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Not stable,Stable"
|
|
bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Can issue,Cannot issue"
|
|
bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Can issue,Cannot issue"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "PROCTL,Protocol Control Register"
|
|
bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transfer,Stop"
|
|
bitfld.long 0x00 8.--9. " DMAS ,DMA Select" "No/Simple DMA,ADMA1,ADMA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Level,Test level"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "No card,Card present"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian,?..."
|
|
bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " DTW ,Data Transfer Width" "1-bit,4-bit,8-bit,?..."
|
|
bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx213,SDCLKx214,SDCLKx215,SDCLKx216,SDCLKx217,SDCLKx218,SDCLKx219,SDCLKx220,SDCLKx221,SDCLKx222,SDCLKx223,SDCLKx224,SDCLKx225,SDCLKx226,SDCLKx227,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,SD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx2^13,SDCLKx2^14,SDCLKx2^15,SDCLKx2^16,SDCLKx2^17,SDCLKx2^18,SDCLKx2^19,SDCLKx2^20,SDCLKx2^21,SDCLKx2^22,SDCLKx2^23,SDCLKx2^24,SDCLKx2^25,SDCLKx2^26,SDCLKx2^27,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,PSD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
endif
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "IRQSTAT,Interrupt Status Register"
|
|
eventfld.long 0x00 28. " DMAE ,DMA Error" "No error,Error"
|
|
eventfld.long 0x00 24. " AC12E ,Auto CMD12 Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 22. " DEBE ,Data End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 21. " DCE ,Data CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 20. " DTOE ,Data Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 19. " CIE ,Command Index Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " CEBE ,Command End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 17. " CCE ,Command CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CTOE ,Command Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 8. " CINT ,Card Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CRM ,Card Removal" "Unstable/Inserted,Removed"
|
|
eventfld.long 0x00 6. " CINS ,Card Insertion" "Unstable/Removed,Inserted"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BRR ,Buffer Read Ready" "Not ready,Ready"
|
|
eventfld.long 0x00 4. " BWR ,Buffer Write Ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " BGE ,Block Gap Event" "No event,Event occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TC ,Transfer Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " CC ,Command Complete" "Not completed,Completed"
|
|
width 12.
|
|
line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " CINSEN ,Card Insertion Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled"
|
|
line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CINTIEN ,Card Interrupt Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 6. " CINIEN ,Card Insertion Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled"
|
|
if (((per.long(ad:0x70004000+0x30))&0x1000000)==0x1000000)
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued"
|
|
bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error"
|
|
bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error"
|
|
bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x3C++0x3
|
|
hide.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 16.--18. " MBL ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..."
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "WML,Watermark Level Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " WR_BRST_LEN ,Write Burst Length"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WR_WML ,Write Watermark Level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--12. 1. " RD_BRST_LEN ,Read Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RD_WML ,Read Watermark Level"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "FEVT,Force Event Register"
|
|
bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "No effect,Force"
|
|
bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "No effect,Force"
|
|
bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "No effect,Force"
|
|
bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "No effect,Force"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error"
|
|
bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State" "ST_STOP,ST_FDS,ST_CADR,ST_TFR"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADSADDR,ADMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR ,ADMA System Address"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "VENDOR,Vendor Specific Register"
|
|
bitfld.long 0x00 24.--27. " DBG_SEL ,Debug Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 1. " EXACT_BLK_NUM ,Exact block number block read enable for SDIO CMD53" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MMCBOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT[15:0] ,Stop At Block Gap value of automatic mode"
|
|
bitfld.long 0x00 7. " AUTO_SABG_EN ,Auto stop at block gap function" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOOT_EN ,Fast boot" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MMC_BOOT_MODE ,Boot mode select" "Normal,Alternative"
|
|
bitfld.long 0x00 4. " BOOT_ACK ,Boot ack mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DTOCV_ACK[3:0] ,Boot ACK time out counter value" "SDCLK x 2^8,SDCLK x 2^9,SDCLK x 2^10,SDCLK x 2^11,SDCLK x 2^12,SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,?..."
|
|
endif
|
|
rgroup.long 0xfc++0x3
|
|
line.long 0x00 "HOSTVER,Host Controller Version"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VVN[7:0] ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SVN[7:0] ,Specification Version Number"
|
|
width 0xb
|
|
tree.end
|
|
tree "eSDHC 2"
|
|
base ad:0x70008000
|
|
width 12.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "DSADDR,DMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DS_ADDR ,DMA System Address"
|
|
line.long 0x04 "BLKATTR,Block Attributes Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer"
|
|
hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size"
|
|
line.long 0x08 "CMDARG,Command Argument Register"
|
|
line.long 0x0C "XFERTYP,Transfer Type Register"
|
|
hexmask.long.byte 0x0C 24.--29. 1. " CMDINX ,Command Index"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " CMDTYP ,Command Type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present"
|
|
bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No Response,Length 136,Length 48,Length 48 check busy"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " MSBSEL ,Multi / Single Block Select" "Single,Multiple"
|
|
bitfld.long 0x0C 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
bitfld.long 0x0C 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " BCEN ,Block Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
if (((per.long(ad:0x70008000+0x0c))&0x30000)==0x00)
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CMDRSP0,Command Response 0"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
elif (((per.long(ad:0x70008000+0x0c))&0x30000)==0x10000)
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R2 response"
|
|
line.long 0x04 "CMDRSP1,Command Response 1"
|
|
hexmask.long 0x04 0.--31. 1. " CMDRSP1 ,R2 response"
|
|
line.long 0x08 "CMDRSP2,Command Response 2"
|
|
hexmask.long 0x08 0.--31. 1. " CMDRSP2 ,R2 response"
|
|
line.long 0x0C "CMDRSP3,Command Response 3"
|
|
hexmask.long.tbyte 0x0c 0.--23. 1. " CMDRSP3 ,R2[23:0] response"
|
|
elif (((per.long(ad:0x70008000+0x0c))&0x30000)==0x20000)
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1/R3/R4/R5/R6 response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1b/R5b response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "CMDRSP3,Command Response 3"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP3 ,R1b response"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DATPORT,Buffer Data Port Register"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "PRSSTAT,Present State Register"
|
|
bitfld.long 0x00 31. " DLSL[7] ,Line 7 Signal Level" "Low,High"
|
|
bitfld.long 0x00 30. " DLSL[6] ,Line 6 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DLSL[5] ,Line 5 Signal Level" "Low,High"
|
|
bitfld.long 0x00 28. " DLSL[4] ,Line 4 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DLSL[3] ,Line 3 Signal Level" "Low,High"
|
|
bitfld.long 0x00 26. " DLSL[2] ,Line 2 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DLSL[1] ,Line 1 Signal Level" "Low,High"
|
|
bitfld.long 0x00 24. " DLSL[0] ,Line 0 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "No card,Card present"
|
|
bitfld.long 0x00 16. " CINS ,Card Inserted" "No card/Reset/Power on,Card inserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RTA ,Read Transfer Active" "No data,Transferring"
|
|
bitfld.long 0x00 8. " WTA ,Write Transfer Active" "No data,Transferring"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Not stable,Stable"
|
|
bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Can issue,Cannot issue"
|
|
bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Can issue,Cannot issue"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "PROCTL,Protocol Control Register"
|
|
bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transfer,Stop"
|
|
bitfld.long 0x00 8.--9. " DMAS ,DMA Select" "No/Simple DMA,ADMA1,ADMA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Level,Test level"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "No card,Card present"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian,?..."
|
|
bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " DTW ,Data Transfer Width" "1-bit,4-bit,8-bit,?..."
|
|
bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx213,SDCLKx214,SDCLKx215,SDCLKx216,SDCLKx217,SDCLKx218,SDCLKx219,SDCLKx220,SDCLKx221,SDCLKx222,SDCLKx223,SDCLKx224,SDCLKx225,SDCLKx226,SDCLKx227,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,SD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx2^13,SDCLKx2^14,SDCLKx2^15,SDCLKx2^16,SDCLKx2^17,SDCLKx2^18,SDCLKx2^19,SDCLKx2^20,SDCLKx2^21,SDCLKx2^22,SDCLKx2^23,SDCLKx2^24,SDCLKx2^25,SDCLKx2^26,SDCLKx2^27,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,PSD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
endif
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "IRQSTAT,Interrupt Status Register"
|
|
eventfld.long 0x00 28. " DMAE ,DMA Error" "No error,Error"
|
|
eventfld.long 0x00 24. " AC12E ,Auto CMD12 Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 22. " DEBE ,Data End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 21. " DCE ,Data CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 20. " DTOE ,Data Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 19. " CIE ,Command Index Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " CEBE ,Command End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 17. " CCE ,Command CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CTOE ,Command Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 8. " CINT ,Card Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CRM ,Card Removal" "Unstable/Inserted,Removed"
|
|
eventfld.long 0x00 6. " CINS ,Card Insertion" "Unstable/Removed,Inserted"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BRR ,Buffer Read Ready" "Not ready,Ready"
|
|
eventfld.long 0x00 4. " BWR ,Buffer Write Ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " BGE ,Block Gap Event" "No event,Event occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TC ,Transfer Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " CC ,Command Complete" "Not completed,Completed"
|
|
width 12.
|
|
line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " CINSEN ,Card Insertion Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled"
|
|
line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CINTIEN ,Card Interrupt Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 6. " CINIEN ,Card Insertion Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled"
|
|
if (((per.long(ad:0x70008000+0x30))&0x1000000)==0x1000000)
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued"
|
|
bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error"
|
|
bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error"
|
|
bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x3C++0x3
|
|
hide.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 16.--18. " MBL ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..."
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "WML,Watermark Level Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " WR_BRST_LEN ,Write Burst Length"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WR_WML ,Write Watermark Level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--12. 1. " RD_BRST_LEN ,Read Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RD_WML ,Read Watermark Level"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "FEVT,Force Event Register"
|
|
bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "No effect,Force"
|
|
bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "No effect,Force"
|
|
bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "No effect,Force"
|
|
bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "No effect,Force"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error"
|
|
bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State" "ST_STOP,ST_FDS,ST_CADR,ST_TFR"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADSADDR,ADMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR ,ADMA System Address"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "VENDOR,Vendor Specific Register"
|
|
bitfld.long 0x00 24.--27. " DBG_SEL ,Debug Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 1. " EXACT_BLK_NUM ,Exact block number block read enable for SDIO CMD53" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MMCBOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT[15:0] ,Stop At Block Gap value of automatic mode"
|
|
bitfld.long 0x00 7. " AUTO_SABG_EN ,Auto stop at block gap function" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOOT_EN ,Fast boot" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MMC_BOOT_MODE ,Boot mode select" "Normal,Alternative"
|
|
bitfld.long 0x00 4. " BOOT_ACK ,Boot ack mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DTOCV_ACK[3:0] ,Boot ACK time out counter value" "SDCLK x 2^8,SDCLK x 2^9,SDCLK x 2^10,SDCLK x 2^11,SDCLK x 2^12,SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,?..."
|
|
endif
|
|
rgroup.long 0xfc++0x3
|
|
line.long 0x00 "HOSTVER,Host Controller Version"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VVN[7:0] ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SVN[7:0] ,Specification Version Number"
|
|
width 0xb
|
|
tree.end
|
|
tree "eSDHC 3"
|
|
base ad:0x70020000
|
|
width 12.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "DSADDR,DMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DS_ADDR ,DMA System Address"
|
|
line.long 0x04 "BLKATTR,Block Attributes Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer"
|
|
hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size"
|
|
line.long 0x08 "CMDARG,Command Argument Register"
|
|
line.long 0x0C "XFERTYP,Transfer Type Register"
|
|
hexmask.long.byte 0x0C 24.--29. 1. " CMDINX ,Command Index"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " CMDTYP ,Command Type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present"
|
|
bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No Response,Length 136,Length 48,Length 48 check busy"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x0C 6. " NIBBLE_POS ,Nibble position" "odd high>even high>odd low>even low,odd high>odd low>even high>even low"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " MSBSEL ,Multi / Single Block Select" "Single,Multiple"
|
|
bitfld.long 0x0C 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x0C 3. " DDR_EN ,Dual Data Rate mode selection" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " BCEN ,Block Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
if (((per.long(ad:0x70020000+0x0c))&0x30000)==0x00)
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CMDRSP0,Command Response 0"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
elif (((per.long(ad:0x70020000+0x0c))&0x30000)==0x10000)
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R2 response"
|
|
line.long 0x04 "CMDRSP1,Command Response 1"
|
|
hexmask.long 0x04 0.--31. 1. " CMDRSP1 ,R2 response"
|
|
line.long 0x08 "CMDRSP2,Command Response 2"
|
|
hexmask.long 0x08 0.--31. 1. " CMDRSP2 ,R2 response"
|
|
line.long 0x0C "CMDRSP3,Command Response 3"
|
|
hexmask.long.tbyte 0x0c 0.--23. 1. " CMDRSP3 ,R2[23:0] response"
|
|
elif (((per.long(ad:0x70020000+0x0c))&0x30000)==0x20000)
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1/R3/R4/R5/R6 response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1b/R5b response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "CMDRSP3,Command Response 3"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP3 ,R1b response"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DATPORT,Buffer Data Port Register"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "PRSSTAT,Present State Register"
|
|
bitfld.long 0x00 31. " DLSL[7] ,Line 7 Signal Level" "Low,High"
|
|
bitfld.long 0x00 30. " DLSL[6] ,Line 6 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DLSL[5] ,Line 5 Signal Level" "Low,High"
|
|
bitfld.long 0x00 28. " DLSL[4] ,Line 4 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DLSL[3] ,Line 3 Signal Level" "Low,High"
|
|
bitfld.long 0x00 26. " DLSL[2] ,Line 2 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DLSL[1] ,Line 1 Signal Level" "Low,High"
|
|
bitfld.long 0x00 24. " DLSL[0] ,Line 0 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "No card,Card present"
|
|
bitfld.long 0x00 16. " CINS ,Card Inserted" "No card/Reset/Power on,Card inserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RTA ,Read Transfer Active" "No data,Transferring"
|
|
bitfld.long 0x00 8. " WTA ,Write Transfer Active" "No data,Transferring"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Not stable,Stable"
|
|
bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Can issue,Cannot issue"
|
|
bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Can issue,Cannot issue"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "PROCTL,Protocol Control Register"
|
|
bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transfer,Stop"
|
|
bitfld.long 0x00 8.--9. " DMAS ,DMA Select" "No/Simple DMA,ADMA1,ADMA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Level,Test level"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "No card,Card present"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian,?..."
|
|
bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " DTW ,Data Transfer Width" "1-bit,4-bit,8-bit,?..."
|
|
bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
if ((per.long(ad:0x70020000+0x0C)&0x8)==0x8)
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IPP_RST_N ,Output to the CARD through the pad for hardware reset" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx212,SDCLKx213,SDCLKx214,SDCLKx215,SDCLKx216,SDCLKx217,SDCLKx218,SDCLKx219,SDCLKx220,SDCLKx221,SDCLKx222,SDCLKx223,SDCLKx224,SDCLKx225,SDCLKx226,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,SD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IPP_RST_N ,Output to the CARD through the pad for hardware reset" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx213,SDCLKx214,SDCLKx215,SDCLKx216,SDCLKx217,SDCLKx218,SDCLKx219,SDCLKx220,SDCLKx221,SDCLKx222,SDCLKx223,SDCLKx224,SDCLKx225,SDCLKx226,SDCLKx227,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,SD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
endif
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx2^13,SDCLKx2^14,SDCLKx2^15,SDCLKx2^16,SDCLKx2^17,SDCLKx2^18,SDCLKx2^19,SDCLKx2^20,SDCLKx2^21,SDCLKx2^22,SDCLKx2^23,SDCLKx2^24,SDCLKx2^25,SDCLKx2^26,SDCLKx2^27,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,PSD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
endif
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "IRQSTAT,Interrupt Status Register"
|
|
eventfld.long 0x00 28. " DMAE ,DMA Error" "No error,Error"
|
|
eventfld.long 0x00 24. " AC12E ,Auto CMD12 Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 22. " DEBE ,Data End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 21. " DCE ,Data CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 20. " DTOE ,Data Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 19. " CIE ,Command Index Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " CEBE ,Command End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 17. " CCE ,Command CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CTOE ,Command Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 8. " CINT ,Card Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CRM ,Card Removal" "Unstable/Inserted,Removed"
|
|
eventfld.long 0x00 6. " CINS ,Card Insertion" "Unstable/Removed,Inserted"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BRR ,Buffer Read Ready" "Not ready,Ready"
|
|
eventfld.long 0x00 4. " BWR ,Buffer Write Ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " BGE ,Block Gap Event" "No event,Event occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TC ,Transfer Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " CC ,Command Complete" "Not completed,Completed"
|
|
width 12.
|
|
line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " CINSEN ,Card Insertion Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled"
|
|
line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CINTIEN ,Card Interrupt Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 6. " CINIEN ,Card Insertion Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled"
|
|
if (((per.long(ad:0x70020000+0x30))&0x1000000)==0x1000000)
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued"
|
|
bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error"
|
|
bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error"
|
|
bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x3C++0x3
|
|
hide.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 16.--18. " MBL ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..."
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "WML,Watermark Level Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " WR_BRST_LEN ,Write Burst Length"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WR_WML ,Write Watermark Level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--12. 1. " RD_BRST_LEN ,Read Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RD_WML ,Read Watermark Level"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "FEVT,Force Event Register"
|
|
bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "No effect,Force"
|
|
bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "No effect,Force"
|
|
bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "No effect,Force"
|
|
bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "No effect,Force"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error"
|
|
bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State" "ST_STOP,ST_FDS,ST_CADR,ST_TFR"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADSADDR,ADMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR ,ADMA System Address"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DLLCTRL,DLL (Delay Line) Control"
|
|
bitfld.long 0x00 28.--31. " DLL_CTRL_REF_UPDATE_INT[3:0] ,DLL control loop update interval" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 20.--27. 1. " DLL_CTRL_SLV_UPDATE_INT[7:0] ,Slave delay line update interval"
|
|
bitfld.long 0x00 10.--15. " DLL_CTRL_SLV_OVERRIDE_VAL[5:0] ,DLL_CTRL_SLV_ OVERRIDE_VAL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLL_CTRL_SLV_OVERRIDE ,Manual override" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DLL_CTRL_GATE_UPDATE ,DLL auto update" "Enabled,Disabled"
|
|
bitfld.long 0x00 3.--6. " DLL_CTRL_SLV_DLY_TARGET[3:0] ,Delay target for the ESDHC loopback read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DLL_CTRL_SLV_FORCE_UPD ,Force slave delay line update immediately" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DLL_CTRL_RESET ,DLL reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " DLL_CTRL_ENABLE ,DLL & delay chain" "Disabled,Enabled"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "DLLSTS,DLL Status"
|
|
bitfld.long 0x00 8.--13. " DLL_STS_REF_SEL[5:0] ,Reference delay line select taps" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 2.--7. " DLL_STS_SLV_SEL[5:0] ,Slave delay line select status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 1. " DLL_STS_REF_LOCK ,Reference DLL lock status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DLL_STS_SLV_LOCK ,Slave delay-line lock status" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "VENDOR,Vendor Specific Register"
|
|
bitfld.long 0x00 24.--27. " DBG_SEL ,Debug Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 1. " EXACT_BLK_NUM ,Exact block number block read enable for SDIO CMD53" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
if ((per.long(ad:0x70020000+0x0C)&0x8)==0x8)
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MMCBOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT[15:0] ,Stop At Block Gap value of automatic mode"
|
|
bitfld.long 0x00 7. " AUTO_SABG_EN ,Auto stop at block gap function" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOOT_EN ,Fast boot" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MMC_BOOT_MODE ,Boot mode select" "Normal,Alternative"
|
|
bitfld.long 0x00 4. " BOOT_ACK ,Boot ack mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DTOCV_ACK[3:0] ,Boot ACK time out counter value" "SDCLK x 2^7,SDCLK x 2^8,SDCLK x 2^9,SDCLK x 2^10,SDCLK x 2^11,SDCLK x 2^12,SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,?..."
|
|
else
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MMCBOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT[15:0] ,Stop At Block Gap value of automatic mode"
|
|
bitfld.long 0x00 7. " AUTO_SABG_EN ,Auto stop at block gap function" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOOT_EN ,Fast boot" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MMC_BOOT_MODE ,Boot mode select" "Normal,Alternative"
|
|
bitfld.long 0x00 4. " BOOT_ACK ,Boot ack mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DTOCV_ACK[3:0] ,Boot ACK time out counter value" "SDCLK x 2^8,SDCLK x 2^9,SDCLK x 2^10,SDCLK x 2^11,SDCLK x 2^12,SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0xfc++0x3
|
|
line.long 0x00 "HOSTVER,Host Controller Version"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VVN[7:0] ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SVN[7:0] ,Specification Version Number"
|
|
width 0xb
|
|
tree.end
|
|
tree "eSDHC 4"
|
|
base ad:0x70024000
|
|
width 12.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "DSADDR,DMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " DS_ADDR ,DMA System Address"
|
|
line.long 0x04 "BLKATTR,Block Attributes Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks Count For Current Transfer"
|
|
hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer Block Size"
|
|
line.long 0x08 "CMDARG,Command Argument Register"
|
|
line.long 0x0C "XFERTYP,Transfer Type Register"
|
|
hexmask.long.byte 0x0C 24.--29. 1. " CMDINX ,Command Index"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " CMDTYP ,Command Type" "Normal,Suspend,Resume,Abort"
|
|
bitfld.long 0x0C 21. " DPSEL ,Data Present Select" "No data,Data present"
|
|
bitfld.long 0x0C 20. " CICEN ,Command Index Check Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CCCEN ,Command CRC Check Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--17. " RSPTYP ,Response Type Select" "No Response,Length 136,Length 48,Length 48 check busy"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 5. " MSBSEL ,Multi / Single Block Select" "Single,Multiple"
|
|
bitfld.long 0x0C 4. " DTDSEL ,Data Transfer Direction Select" "Write,Read"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
bitfld.long 0x0C 2. " AC12EN ,Auto CMD12 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " BCEN ,Block Count Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " DMAEN ,DMA Enable" "Disabled,Enabled"
|
|
if (((per.long(ad:0x70024000+0x0c))&0x30000)==0x00)
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "CMDRSP0,Command Response 0"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
elif (((per.long(ad:0x70024000+0x0c))&0x30000)==0x10000)
|
|
rgroup.long 0x10++0xF
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R2 response"
|
|
line.long 0x04 "CMDRSP1,Command Response 1"
|
|
hexmask.long 0x04 0.--31. 1. " CMDRSP1 ,R2 response"
|
|
line.long 0x08 "CMDRSP2,Command Response 2"
|
|
hexmask.long 0x08 0.--31. 1. " CMDRSP2 ,R2 response"
|
|
line.long 0x0C "CMDRSP3,Command Response 3"
|
|
hexmask.long.tbyte 0x0c 0.--23. 1. " CMDRSP3 ,R2[23:0] response"
|
|
elif (((per.long(ad:0x70024000+0x0c))&0x30000)==0x20000)
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1/R3/R4/R5/R6 response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
hgroup.long 0x1c++0x03
|
|
hide.long 0x00 "CMDRSP3,Command Response 3"
|
|
else
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "CMDRSP0,Command Response 0"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP0 ,R1b/R5b response"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CMDRSP1,Command Response 1"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "CMDRSP2,Command Response 2"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "CMDRSP3,Command Response 3"
|
|
hexmask.long 0x00 0.--31. 1. " CMDRSP3 ,R1b response"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DATPORT,Buffer Data Port Register"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "PRSSTAT,Present State Register"
|
|
bitfld.long 0x00 31. " DLSL[7] ,Line 7 Signal Level" "Low,High"
|
|
bitfld.long 0x00 30. " DLSL[6] ,Line 6 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DLSL[5] ,Line 5 Signal Level" "Low,High"
|
|
bitfld.long 0x00 28. " DLSL[4] ,Line 4 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DLSL[3] ,Line 3 Signal Level" "Low,High"
|
|
bitfld.long 0x00 26. " DLSL[2] ,Line 2 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DLSL[1] ,Line 1 Signal Level" "Low,High"
|
|
bitfld.long 0x00 24. " DLSL[0] ,Line 0 Signal Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CLSL ,CMD Line Signal Level" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 19. " WPSPL ,Write Protect Switch Pin Level" "Protected,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CDPL ,Card Detect Pin Level" "No card,Card present"
|
|
bitfld.long 0x00 16. " CINS ,Card Inserted" "No card/Reset/Power on,Card inserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BREN ,Buffer Read Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BWEN ,Buffer Write Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RTA ,Read Transfer Active" "No data,Transferring"
|
|
bitfld.long 0x00 8. " WTA ,Write Transfer Active" "No data,Transferring"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SDOFF ,SD Clock Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 6. " PEROFF ,IPG_PERCLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HCKOFF ,HCLK Gated Off Internally" "Active,Gated off"
|
|
bitfld.long 0x00 4. " IPGOFF ,IPG_CLK Gated Off Internally" "Active,Gated off"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDSTB ,SD Clock Stable" "Not stable,Stable"
|
|
bitfld.long 0x00 2. " DLA ,Data Line Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CDIHB ,Command Inhibit (DAT)" "Can issue,Cannot issue"
|
|
bitfld.long 0x00 0. " CIHB ,Command Inhibit (CMD)" "Can issue,Cannot issue"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "PROCTL,Protocol Control Register"
|
|
bitfld.long 0x00 26. " WECRM ,Wakeup Event Enable On SD Card Removal" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " WECINS ,Wakeup Event Enable On SD Card Insertion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " WECINT ,Wakeup Event Enable On Card Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " IABG ,Interrupt At Block Gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWCTL ,Read Wait Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CREQ ,Continue Request" "No effect,Restart"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SABGREQ ,Stop At Block Gap Request" "Transfer,Stop"
|
|
bitfld.long 0x00 8.--9. " DMAS ,DMA Select" "No/Simple DMA,ADMA1,ADMA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDSS ,Card Detect Signal Selection" "Level,Test level"
|
|
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "No card,Card present"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " EMODE ,Endian Mode" "Big endian,Half word big endian,Little endian,?..."
|
|
bitfld.long 0x00 3. " D3CD ,DAT3 as Card Detection Pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " DTW ,Data Transfer Width" "1-bit,4-bit,8-bit,?..."
|
|
bitfld.long 0x00 0. " LCTL ,LED Control" "Off,On"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx213,SDCLKx214,SDCLKx215,SDCLKx216,SDCLKx217,SDCLKx218,SDCLKx219,SDCLKx220,SDCLKx221,SDCLKx222,SDCLKx223,SDCLKx224,SDCLKx225,SDCLKx226,SDCLKx227,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,SD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
else
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SYSCTL,System Control Register"
|
|
bitfld.long 0x00 27. " INITA ,Initialization Active" "No effect,Active"
|
|
bitfld.long 0x00 26. " RSTD ,Software Reset For DAT Line" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RSTC ,Software Reset For CMD Line" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RSTA ,Software Reset For ALL" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DTOCV ,Data Timeout Counter Value" "SDCLKx2^13,SDCLKx2^14,SDCLKx2^15,SDCLKx2^16,SDCLKx2^17,SDCLKx2^18,SDCLKx2^19,SDCLKx2^20,SDCLKx2^21,SDCLKx2^22,SDCLKx2^23,SDCLKx2^24,SDCLKx2^25,SDCLKx2^26,SDCLKx2^27,?..."
|
|
hexmask.long.byte 0x00 8.--15. 1. " SDCLKFS ,SDCLK Frequency Select"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DVS ,Divisor" "Divisor by 1,Divisor by 2,Divisor by 3,Divisor by 4,Divisor by 5,Divisor by 6,Divisor by 7,Divisor by 8,Divisor by 9,Divisor by 10,Divisor by 11,Divisor by 12,Divisor by 13,Divisor by 14,Divisor by 15,Divisor by 16"
|
|
bitfld.long 0x00 3. " SDCLKEN ,PSD Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PEREN ,Peripheral Clock Enable" "Internally gated off,No auto gated off"
|
|
bitfld.long 0x00 1. " HCKEN ,HCLK Enable" "Internally gated off,No auto gated off"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IPGEN ,IPG Clock Enable" "Internally gated off,No auto gated off"
|
|
endif
|
|
group.long 0x30++0xB
|
|
line.long 0x00 "IRQSTAT,Interrupt Status Register"
|
|
eventfld.long 0x00 28. " DMAE ,DMA Error" "No error,Error"
|
|
eventfld.long 0x00 24. " AC12E ,Auto CMD12 Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 22. " DEBE ,Data End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 21. " DCE ,Data CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 20. " DTOE ,Data Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 19. " CIE ,Command Index Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 18. " CEBE ,Command End Bit Error" "No error,Error"
|
|
eventfld.long 0x00 17. " CCE ,Command CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CTOE ,Command Timeout Error" "No error,Error"
|
|
eventfld.long 0x00 8. " CINT ,Card Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " CRM ,Card Removal" "Unstable/Inserted,Removed"
|
|
eventfld.long 0x00 6. " CINS ,Card Insertion" "Unstable/Removed,Inserted"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BRR ,Buffer Read Ready" "Not ready,Ready"
|
|
eventfld.long 0x00 4. " BWR ,Buffer Write Ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x00 3. " DINT ,DMA Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " BGE ,Block Gap Event" "No event,Event occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TC ,Transfer Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 0. " CC ,Command Complete" "Not completed,Completed"
|
|
width 12.
|
|
line.long 0x04 "IRQSTATEN,Interrupt Status Enable Register"
|
|
bitfld.long 0x04 28. " DMAESEN ,DMA Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 24. " AC12ESEN ,Auto CMD12 Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 22. " DEBESEN ,Data End Bit Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " DCESEN ,Data CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 20. " DTOESEN ,Data Timeout Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 19. " CIESEN ,Command Index Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " CEBESEN ,Command End Bit Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 17. " CCESEN ,Command CRC Error Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 16. " CTOESEN ,Command Timeout Error Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CINTSEN ,Card Interrupt Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 7. " CRMSEN ,Card Removal Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " CINSEN ,Card Insertion Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BRRSEN ,Buffer Read Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " BWRSEN ,Buffer Write Ready Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 3. " DINTSEN ,DMA Interrupt Status Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BGESEN ,Block Gap Event Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 1. " TCSEN ,Transfer Complete Status Enable" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CCSEN ,Command Complete Status Enable" "Masked,Enabled"
|
|
line.long 0x08 "IRQSIGEN,Interrupt Signal Enable Register"
|
|
bitfld.long 0x08 28. " DMAEIEN ,DMA Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 24. " AC12EIEN ,Auto CMD12 Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 22. " DEBEIEN ,Data End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DCEIEN ,Data CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 20. " DTOEIEN ,Data Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 19. " CIEIEN ,Command Index Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " CEBEIEN ,Command End Bit Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 17. " CCEIEN ,Command CRC Error Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 16. " CTOEIEN ,Command Timeout Error Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CINTIEN ,Card Interrupt Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 7. " CRMIEN ,Card Removal Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 6. " CINIEN ,Card Insertion Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BRRIEN ,Buffer Read Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 4. " BWRIEN ,Buffer Write Ready Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 3. " DINTIEN ,DMA Interrupt Enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " BGEIEN ,Block Gap Event Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 1. " TCIEN ,Transfer Complete Interrupt Enable" "Masked,Enabled"
|
|
bitfld.long 0x08 0. " CCIEN ,Command Complete Interrupt Enable" "Masked,Enabled"
|
|
if (((per.long(ad:0x70024000+0x30))&0x1000000)==0x1000000)
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNIBAC12E ,Command Not Issued By Auto CMD12 Error" "No error,Not Issued"
|
|
bitfld.long 0x00 4. " AC12IE ,Auto CMD12 Index Error" "No error,Error"
|
|
bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 End Bit Error" "No error,Error"
|
|
bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 Timeout Error" "No error,Error"
|
|
bitfld.long 0x00 0. " AC12NE ,Auto CMD12 Not Executed" "Executed,Not executed"
|
|
else
|
|
hgroup.long 0x3C++0x3
|
|
hide.long 0x00 "AUTOC12ERR,Auto CMD12 Error Status Register"
|
|
endif
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "HOSTCAPBLT,Host Controller Capabilities"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage Support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage Support 3.0V" "Not supported,Supported"
|
|
bitfld.long 0x00 24. " VS33 ,Voltage Support 3.3V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SRS ,Suspend / Resume Support" "Not supported,Supported"
|
|
bitfld.long 0x00 22. " DMAS ,DMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High Speed Support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ADMAS ,ADMA Support" "Not supported,Supported"
|
|
bitfld.long 0x00 16.--18. " MBL ,Max Block Length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..."
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "WML,Watermark Level Register"
|
|
hexmask.long.byte 0x00 24.--28. 1. " WR_BRST_LEN ,Write Burst Length"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WR_WML ,Write Watermark Level"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--12. 1. " RD_BRST_LEN ,Read Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RD_WML ,Read Watermark Level"
|
|
wgroup.long 0x50++0x3
|
|
line.long 0x00 "FEVT,Force Event Register"
|
|
bitfld.long 0x00 31. " FEVTCINT ,Force Event Card Interrupt" "No effect,Force"
|
|
bitfld.long 0x00 28. " FEVTDMAE ,Force Event DMA Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FEVTAC12E ,Force Event Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 22. " FEVTDEBE ,Force Event Data End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FEVTDCE ,Force Event Data CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 20. " FEVTDTOE ,Force Event Data Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FEVTCIE ,Force Event Command Index Error" "No effect,Force"
|
|
bitfld.long 0x00 18. " FEVTCEBE ,Force Event Command End Bit Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FEVTCCE ,Force Event Command CRC Error" "No effect,Force"
|
|
bitfld.long 0x00 16. " FEVTCTOE ,Force Event Command Time Out Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FEVTCNIBAC12E ,Force Event Command Not Executed By Auto Command 12 Error" "No effect,Force"
|
|
bitfld.long 0x00 4. " FEVTAC12IE ,Force Event Auto Command 12 Index Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FEVTAC12EBE ,Force Event Auto Command 12 End Bit Error" "No effect,Force"
|
|
bitfld.long 0x00 2. " FEVTAC12CE ,Force Event Auto Command 12 CRC Error" "No effect,Force"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FEVTAC12TOE ,Force Event Auto Command 12 Time Out Error" "No effect,Force"
|
|
bitfld.long 0x00 0. " FEVTAC12NE ,Force Event Auto Command 12 Not Executed" "No effect,Force"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "ADMAES,ADMA Error Status Register"
|
|
bitfld.long 0x00 3. " ADMADCE ,ADMA Descritor Error" "No error,Error"
|
|
bitfld.long 0x00 2. " ADMALME ,ADMA Length Mismatch Error" "No error,Error"
|
|
bitfld.long 0x00 0.--1. " ADMAES ,ADMA Error State" "ST_STOP,ST_FDS,ST_CADR,ST_TFR"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ADSADDR,ADMA System Address Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " ADS_ADDR ,ADMA System Address"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
endif
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "VENDOR,Vendor Specific Register"
|
|
bitfld.long 0x00 24.--27. " DBG_SEL ,Debug Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT_ST_VAL ,Internal State Value"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 1. " EXACT_BLK_NUM ,Exact block number block read enable for SDIO CMD53" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0. " EXT_DMA_EN ,External DMA Request Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX50*"))
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "MMCBOOT,MMC Boot Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BOOT_BLK_CNT[15:0] ,Stop At Block Gap value of automatic mode"
|
|
bitfld.long 0x00 7. " AUTO_SABG_EN ,Auto stop at block gap function" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOOT_EN ,Fast boot" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MMC_BOOT_MODE ,Boot mode select" "Normal,Alternative"
|
|
bitfld.long 0x00 4. " BOOT_ACK ,Boot ack mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DTOCV_ACK[3:0] ,Boot ACK time out counter value" "SDCLK x 2^8,SDCLK x 2^9,SDCLK x 2^10,SDCLK x 2^11,SDCLK x 2^12,SDCLK x 2^13,SDCLK x 2^14,SDCLK x 2^15,SDCLK x 2^16,SDCLK x 2^17,SDCLK x 2^18,SDCLK x 2^19,SDCLK x 2^20,SDCLK x 2^21,SDCLK x 2^22,?..."
|
|
endif
|
|
rgroup.long 0xfc++0x3
|
|
line.long 0x00 "HOSTVER,Host Controller Version"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VVN[7:0] ,Vendor Version Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SVN[7:0] ,Specification Version Number"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "FEC (Fast Ethernet Controller)"
|
|
base ad:0x83fec000
|
|
width 7.
|
|
tree "Control/Status Registers"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "EIR,Ethernet Interrupt Event Register"
|
|
eventfld.long 0x00 31. " HBERR ,Heartbeat error" "No error,Error"
|
|
eventfld.long 0x00 30. " BABR ,Babbling receive error" "No error,Error"
|
|
eventfld.long 0x00 29. " BABT ,Babbling transmit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 28. " GRA ,Graceful stop complete" "Not completed,Completed"
|
|
eventfld.long 0x00 27. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " RXF ,Receive frame interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " MII ,MII interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "No error,Error"
|
|
eventfld.long 0x00 21. " LC ,Late collision" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " RL ,Collision retry limit" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "Not empty,Empty"
|
|
line.long 0x04 "EIMR,Interrupt Mask Register"
|
|
bitfld.long 0x04 31. " HBERR ,Heartbeat error" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " BABR ,Babbling receive error" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " BABT ,Babbling transmit error" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 28. " GRA ,Graceful stop complete" "Masked,Not masked"
|
|
bitfld.long 0x04 27. " TXF ,Transmit frame interrupt" "Masked,Not masked"
|
|
bitfld.long 0x04 26. " TXB ,Transmit buffer interrupt" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 25. " RXF ,Receive frame interrupt" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " RXB ,Receive buffer interrupt" "Masked,Not masked"
|
|
bitfld.long 0x04 23. " MII ,MII interrupt" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 22. " EBERR ,Ethernet bus error" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " LC ,Late collision" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " RL ,Collision retry limit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " UN ,Transmit FIFO underrun" "Masked,Not masked"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "RDAR,Receive Descriptor Active Register"
|
|
bitfld.long 0x00 24. " R_DES_ACTIVE ,Receive descriptor ring update" "Not received,Received"
|
|
line.long 0x04 "TDAR,Transmit Descriptor Active Register"
|
|
bitfld.long 0x04 24. " X_DES_ACTIVE ,Transmit descriptor ring update" "Not transmitted,Transmitted"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ECR,Ethernet Control Register"
|
|
bitfld.long 0x00 1. " ETHER_EN ,Ethernet enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESET ,Reset" "No reset,Reset"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "MMFR,MII Management Frame Register"
|
|
bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " OP ,Operation code" "Write,Write for MII frame,Read for MII frame,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " TA ,Turn around" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data"
|
|
line.long 0x04 "MSCR,MII Speed Control Register"
|
|
bitfld.long 0x04 7. " DIS_PREAMBLE ,Preamble not to be prepended to the MII management frame" "Prepended,Not prepended"
|
|
bitfld.long 0x04 1.--6. " MII_SPEED ,Controls the frequency of the MII management interface clock" "Turned off,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "MIBC,MIB Control Register"
|
|
bitfld.long 0x00 31. " MIB_DISABLE ,A read/write control" "Not halted,Halted"
|
|
rbitfld.long 0x00 30. " MB_IDLE ,A read-only status" "Updated,Not updated"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RCR,Receive Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " MAX_FL ,Maximum frame length"
|
|
bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected"
|
|
bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" "7-wire,MII"
|
|
bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LOOP ,Internal loopback" "Not looped,Looped"
|
|
group.long 0xc4++0x03
|
|
line.long 0x00 "TCR,Transmit Control Register"
|
|
bitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not received,Recived"
|
|
bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HBC ,Heartbeat control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped"
|
|
group.long 0xE4++0xb
|
|
line.long 0x00 "PALR,Physical Address Low Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PADDR1_0 ,Byte 0 of the 6 byte destination address"
|
|
hexmask.long.byte 0x00 16.--23. 1. " PADDR1_1 ,Byte 1 of the 6 byte destination address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " PADDR1_2 ,Byte 2 of the 6 byte destination address"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PADDR1_3 ,Byte 3 of the 6 byte destination address"
|
|
line.long 0x04 "PAUR,Physical Address High Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " PADDR2_4 ,Byte 4 of the 6 byte destination address"
|
|
hexmask.long.byte 0x04 16.--23. 1. " PADDR2_5 ,Byte 5 of the 6 byte destination address"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames"
|
|
line.long 0x08 "OPD,Opcode/Pause Duration Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field used in PAUSE frames"
|
|
hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause Duration field used in PAUSE frames"
|
|
group.long 0x118++0xF
|
|
line.long 0x00 "IAUR,Descriptor Individual Upper Address Registers"
|
|
line.long 0x04 "IALR,Descriptor Individual Lower Address Register"
|
|
line.long 0x08 "GAUR,Descriptor Group Upper Address Register"
|
|
line.long 0x0C "GALR,Descriptor Group Lower Address Register"
|
|
group.long 0x144++0x3
|
|
line.long 0x00 "TFWR,Transmit FIFO Watermark Register"
|
|
bitfld.long 0x00 0.--1. " X_WMRK ,Number of bytes written to transmit FIFO before transmission of a frame begins" "64 bytes,64 bytes,128 bytes,192 bytes"
|
|
rgroup.long 0x14c++0x03
|
|
line.long 0x00 "FRBR,FIFO Receive Bound Register"
|
|
hexmask.long.word 0x00 2.--9. 0x4 " R_BOUND ,Highest valid FIFO RAM address"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "FRSR,FIFO Receive Start Register"
|
|
hexmask.long.word 0x00 2.--9. 0x04 " R_FSTART ,Address of first receive FIFO location"
|
|
group.long 0x180++0x0b
|
|
line.long 0x00 "ERDSR,Receive Buffer Descriptor Ring Start Register"
|
|
hexmask.long 0x00 2.--31. 0x4 " R_DES_START ,Pointer to start of receive buffer descriptor queue"
|
|
line.long 0x04 "ETDSR,Transmit Buffer Descriptor Ring Start Register"
|
|
hexmask.long 0x04 2.--31. 0x4 " X_DES_START ,Pointer to start of transmit buffer descriptor queue"
|
|
line.long 0x08 "EMRBR,Receive Buffer Size Register"
|
|
hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size"
|
|
tree.end
|
|
tree "MIB Block Counters"
|
|
width 20.
|
|
group.long 0x200++0x77
|
|
line.long 0x00 "RMON_T_DROP,Count of frames not counted correctly"
|
|
line.long 0x04 "RMON_T_PACKETS,RMON Tx packet count"
|
|
line.long 0x08 "RMON_T_BC_PKT,RMON Tx Broadcast Packets"
|
|
line.long 0x0c "RMON_T_MC_PKT,RMON Tx Multicast Packets"
|
|
line.long 0x10 "RMON_T_CRC_ALIGN,RMON Tx Packets w CRC/Align error"
|
|
line.long 0x14 "RMON_T_UNDERSIZE,RMON Tx Packets < 64 bytes"
|
|
line.long 0x18 "RMON_T_OVERSIZE,RMON Tx Packets > MAX_FL bytes"
|
|
line.long 0x1c "RMON_T_FRAG,RMON Tx Packets < 64 bytes"
|
|
line.long 0x20 "RMON_T_JAB,RMON Tx Packets > MAX_FL bytes"
|
|
line.long 0x24 "RMON_T_COL,RMON Tx collision count"
|
|
line.long 0x28 "RMON_T_P64,RMON Tx 64 byte packets"
|
|
line.long 0x2c "RMON_T_P65TO127,RMON Tx 65 to 127 byte packets"
|
|
line.long 0x30 "RMON_T_P128TO255,RMON Tx 128 to 255 byte packets"
|
|
line.long 0x34 "RMON_T_P256TO511,RMON Tx 256 to 511 byte packets"
|
|
line.long 0x38 "RMON_T_P512TO1023,RMON Tx 512 to 1023 byte packets"
|
|
line.long 0x3c "RMON_T_P1024TO2047,RMON Tx 1024 to 2047 byte packets"
|
|
line.long 0x40 "RMON_T_P_GTE2048,RMON Tx packets w > 2048 bytes"
|
|
line.long 0x44 "RMON_T_OCTETS,RMON Tx Octets"
|
|
line.long 0x48 "IEEE_T_DROP,Count of frames not counted correctly"
|
|
line.long 0x4c "IEEE_T_FRAME_OK,Frames Transmitted OK"
|
|
line.long 0x50 "IEEE_T_1COL,Frames Transmitted with Single Collision"
|
|
line.long 0x54 "IEEE_T_MCOL,Frames Transmitted with Multiple Collisions"
|
|
line.long 0x58 "EEE_T_DEF,Frames Transmitted after Deferral Delay"
|
|
line.long 0x5c "IEEE_T_LCOL,Frames Transmitted with Late Collision"
|
|
line.long 0x60 "IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions"
|
|
line.long 0x64 "IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun"
|
|
line.long 0x68 "IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error"
|
|
line.long 0x6c "IEEE_T_SQE,Frames Transmitted with SQE Error"
|
|
line.long 0x70 "IEEE_T_FDXFC,Flow Control Pause frames transmitted"
|
|
line.long 0x74 "IEEE_T_OCTETS_OK,Octet count for Frames Transmitted w/o Error"
|
|
group.long 0x284++0x5f
|
|
line.long 0x00 "RMON_R_PACKETS,RMON Rx packet count"
|
|
line.long 0x04 "RMON_R_BC_PKT,RMON Rx Broadcast Packets"
|
|
line.long 0x08 "RMON_R_MC_PKT,RMON Rx Multicast Packets"
|
|
line.long 0x0c "RMON_R_CRC_ALIGN,RMON Rx Packets w CRC/Align error"
|
|
line.long 0x10 "RMON_R_UNDERSIZE,RMON Rx Packets < 64 bytes"
|
|
line.long 0x14 "RMON_R_OVERSIZE,RMON Rx Packets > MAX_FL bytes"
|
|
line.long 0x18 "RMON_R_FRAG,RMON Rx Packets < 64 bytes"
|
|
line.long 0x1c "RMON_R_JAB,RMON Rx Packets > MAX_FL bytes"
|
|
line.long 0x20 "RMON_R_RESVD_0,RMON_R_RESVD_0"
|
|
line.long 0x24 "RMON_R_P64,RMON Rx 64 byte packets"
|
|
line.long 0x28 "RMON_R_P65TO127,RMON Rx 65 to 127 byte packets"
|
|
line.long 0x2c "RMON_R_P128TO255,RMON Rx 128 to 255 byte packets"
|
|
line.long 0x30 "RMON_R_P256TO511,RMON Rx 256 to 511 byte packets"
|
|
line.long 0x34 "RMON_R_P512TO1023,RMON Rx 512 to 1023 byte packets"
|
|
line.long 0x38 "RMON_R_P1024TO2047,RMON Rx 1024 to 2047 byte packets"
|
|
line.long 0x3c "RMON_R_P_GTE2048,RMON Rx packets w > 2048 bytes"
|
|
line.long 0x40 "RMON_R_OCTETS,RMON Rx Octets"
|
|
line.long 0x44 "IEEE_R_DROP,Count of frames not counted correctly"
|
|
line.long 0x48 "IEEE_R_FRAME_OK,Frames Received OK"
|
|
line.long 0x4c "IEEE_R_CRC,Frames Received with CRC Error"
|
|
line.long 0x50 "IEEE_R_ALIGN,Frames Received with Alignment Error"
|
|
line.long 0x54 "IEEE_R_MACERR,Receive Fifo Overflow count"
|
|
line.long 0x58 "IEEE_R_FDXFC,Flow Control Pause frames received"
|
|
line.long 0x5c "IEEE_R_OCTETS_OK,Octet count for Frames Rcvd w/o Error"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "FIRI (Fast Infrared Interface)"
|
|
base ad:0x83fa8000
|
|
width 9.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "FIRITCR,FIRI Transmit Control Register"
|
|
bitfld.long 0x00 24. " HAG ,Hardware Address Generator" "Tx FIFO packet,TPA"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TPA ,Transmit Packet Address Transmit Packet Address"
|
|
bitfld.long 0x00 13.--14. " SRF ,Start Field Repeat Factor" "16PA/2STA,32PA/4STA,64PA/8STA,128PA/16STA"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " TDT ,Transmitter DMA request Trigger level" "Empty,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes"
|
|
bitfld.long 0x00 9. " TCIE ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TPEIE ,Transmitter Packet End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TFUIE ,Transmitter FIFO Underrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PCF ,Packet Complete by FIFO" "CRC/STO,Packet abort"
|
|
bitfld.long 0x00 5. " PC ,Packet Complete" "CRC/STO,Packet abort"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SIP ,Transmit Enable of SIP" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TPP ,Transmitter Pulse Polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " TM ,Transmitter Mode" "4 Mbps FIR,0.576 Mbps MIR,1.152 Mbps MIR,Software packet assembling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TE ,Transmitter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "FIRITCTR,FIRI Transmitter Count Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " TPL ,Transmit Packet Length"
|
|
line.long 0x08 "FIRIRCR,FIRI Receiver Control Register"
|
|
bitfld.long 0x08 24.--25. " RAM ,Address Match" "Not matched,RA,Broadcast,RA/Broadcast"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RA ,Receiver Address"
|
|
bitfld.long 0x08 11. " RPEDE ,Receiver Packet End DMA request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8.--10. " RDT ,Receiver DMA request Trigger level" "Reserved,16 bytes,32 bytes,48 bytes,64 bytes,80 bytes,96 bytes,112 bytes"
|
|
bitfld.long 0x08 7. " RPA ,Receiver Packet Abort" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " RPEIE ,Receiver Packet End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " PAIE ,Packet Abort Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " RFOIE ,Receiver FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " RPP ,Receiver Pulse Polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 1.--2. " RM ,Receiver Mode" "FIR,0.576 Mbps MIR,1.152 Mbps MIR,Software packet assembling"
|
|
textline " "
|
|
bitfld.long 0x08 0. " RE ,Receiver Enable" "Disabled,Enabled"
|
|
line.long 0x0c "FIRITSR,FIRI Transmit Status Register"
|
|
hexmask.long.byte 0x0c 8.--15. 1. " TFP ,Transmitter FIFO Pointer"
|
|
eventfld.long 0x0c 3. " TC ,Transmit Complete" "Not completed,Completed"
|
|
eventfld.long 0x0c 2. " SIPE ,SIP End" "Not ended,Ended"
|
|
textline " "
|
|
eventfld.long 0x0c 1. " TPE ,Transmitter Packet End" "Not ended,Ended"
|
|
eventfld.long 0x0c 0. " TXU ,Transmitter FIFO Underrun" "No underrun,Underrun"
|
|
line.long 0x10 "FIRIRSR,FIRI Receive Status Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " RFP ,Receiver FIFO Pointer"
|
|
bitfld.long 0x10 5. " PAS ,Preamble Search" "Not searching,Searching"
|
|
eventfld.long 0x10 4. " RPE ,Receiver Packet End" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x10 3. " RFO ,Receiver FIFO Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x10 2. " BAM ,Broadcast Address Match" "No broadcast,Broadcast"
|
|
eventfld.long 0x10 1. " CRCE ,CRC Error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x10 0. " DDE ,Address control or data field error" "No error,Error"
|
|
sif (cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x00 "TXFIFO,Transmitter FIFO"
|
|
hgroup.long 0x18++0x3
|
|
hide.long 0x00 "RXFIFO,Receiver FIFO"
|
|
in
|
|
endif
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "FIRICR,FIRI Control Register"
|
|
hexmask.long.byte 0x00 5.--11. 1. " BL ,Burst Length"
|
|
bitfld.long 0x00 0.--3. " OSF ,Over Sampling Factor" "No oversample,By 2,By 3,By 4,By 5,By 6,By 7,By 8,By 9,By 10,By 11,By 12,By 13,By 14,By 15,By 16"
|
|
width 0xb
|
|
tree.end
|
|
tree.open "GPIO (General Purpose Input/Output)"
|
|
tree "Common Register"
|
|
base ad:0x73f84000
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EDGE_SEL,GPIO Edge Select Register"
|
|
bitfld.long 0x00 31. " EDGE_SEL31 ,Edge Selection 31" "ICR_2_31,Any edge"
|
|
bitfld.long 0x00 30. " EDGE_SEL30 ,Edge Selection 30" "ICR_2_30,Any edge"
|
|
bitfld.long 0x00 29. " EDGE_SEL29 ,Edge Selection 29" "ICR_2_29,Any edge"
|
|
bitfld.long 0x00 28. " EDGE_SEL28 ,Edge Selection 28" "ICR_2_28,Any edge"
|
|
bitfld.long 0x00 27. " EDGE_SEL27 ,Edge Selection 27" "ICR_2_27,Any edge"
|
|
bitfld.long 0x00 26. " EDGE_SEL26 ,Edge Selection 26" "ICR_2_26,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EDGE_SEL25 ,Edge Selection 25" "ICR_2_25,Any edge"
|
|
bitfld.long 0x00 24. " EDGE_SEL24 ,Edge Selection 24" "ICR_2_24,Any edge"
|
|
bitfld.long 0x00 23. " EDGE_SEL23 ,Edge Selection 23" "ICR_2_23,Any edge"
|
|
bitfld.long 0x00 22. " EDGE_SEL22 ,Edge Selection 22" "ICR_2_22,Any edge"
|
|
bitfld.long 0x00 21. " EDGE_SEL21 ,Edge Selection 21" "ICR_2_21,Any edge"
|
|
bitfld.long 0x00 20. " EDGE_SEL20 ,Edge Selection 20" "ICR_2_20,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EDGE_SEL19 ,Edge Selection 19" "ICR_2_19,Any edge"
|
|
bitfld.long 0x00 18. " EDGE_SEL18 ,Edge Selection 18" "ICR_2_18,Any edge"
|
|
bitfld.long 0x00 17. " EDGE_SEL17 ,Edge Selection 17" "ICR_2_17,Any edge"
|
|
bitfld.long 0x00 16. " EDGE_SEL16 ,Edge Selection 16" "ICR_2_16,Any edge"
|
|
bitfld.long 0x00 15. " EDGE_SEL15 ,Edge Selection 15" "ICR_1_15,Any edge"
|
|
bitfld.long 0x00 14. " EDGE_SEL14 ,Edge Selection 14" "ICR_1_14,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EDGE_SEL13 ,Edge Selection 13" "ICR_1_13,Any edge"
|
|
bitfld.long 0x00 12. " EDGE_SEL12 ,Edge Selection 12" "ICR_1_12,Any edge"
|
|
bitfld.long 0x00 11. " EDGE_SEL11 ,Edge Selection 11" "ICR_1_11,Any edge"
|
|
bitfld.long 0x00 10. " EDGE_SEL10 ,Edge Selection 10" "ICR_1_10,Any edge"
|
|
bitfld.long 0x00 9. " EDGE_SEL9 ,Edge Selection 9" "ICR_1_9,Any edge"
|
|
bitfld.long 0x00 8. " EDGE_SEL8 ,Edge Selection 8" "ICR_1_8,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EDGE_SEL7 ,Edge Selection 7" "ICR_1_7,Any edge"
|
|
bitfld.long 0x00 6. " EDGE_SEL6 ,Edge Selection 6" "ICR_1_6,Any edge"
|
|
bitfld.long 0x00 5. " EDGE_SEL5 ,Edge Selection 5" "ICR_1_5,Any edge"
|
|
bitfld.long 0x00 4. " EDGE_SEL4 ,Edge Selection 4" "ICR_1_4,Any edge"
|
|
bitfld.long 0x00 3. " EDGE_SEL3 ,Edge Selection 3" "ICR_1_3,Any edge"
|
|
bitfld.long 0x00 2. " EDGE_SEL2 ,Edge Selection 2" "ICR_1_2,Any edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EDGE_SEL1 ,Edge Selection 1" "ICR_1_1,Any edge"
|
|
bitfld.long 0x00 0. " EDGE_SEL0 ,Edge Selection 0" "ICR_1_0,Any edge"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO 1"
|
|
base ad:0x73f84000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,GPIO Data Register"
|
|
bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High"
|
|
line.long 0x04 "GDIR,GPIO Direction Register"
|
|
bitfld.long 0x04 31. " GDIR31 ,GPIO Direction 31 bit" "Input,Output"
|
|
bitfld.long 0x04 30. " GDIR30 ,GPIO Direction 30 bit" "Input,Output"
|
|
bitfld.long 0x04 29. " GDIR29 ,GPIO Direction 29 bit" "Input,Output"
|
|
bitfld.long 0x04 28. " GDIR28 ,GPIO Direction 28 bit" "Input,Output"
|
|
bitfld.long 0x04 27. " GDIR27 ,GPIO Direction 27 bit" "Input,Output"
|
|
bitfld.long 0x04 26. " GDIR26 ,GPIO Direction 26 bit" "Input,Output"
|
|
bitfld.long 0x04 25. " GDIR25 ,GPIO Direction 25 bit" "Input,Output"
|
|
bitfld.long 0x04 24. " GDIR24 ,GPIO Direction 24 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GDIR23 ,GPIO Direction 23 bit" "Input,Output"
|
|
bitfld.long 0x04 22. " GDIR22 ,GPIO Direction 22 bit" "Input,Output"
|
|
bitfld.long 0x04 21. " GDIR21 ,GPIO Direction 21 bit" "Input,Output"
|
|
bitfld.long 0x04 20. " GDIR20 ,GPIO Direction 20 bit" "Input,Output"
|
|
bitfld.long 0x04 19. " GDIR19 ,GPIO Direction 19 bit" "Input,Output"
|
|
bitfld.long 0x04 18. " GDIR18 ,GPIO Direction 18 bit" "Input,Output"
|
|
bitfld.long 0x04 17. " GDIR17 ,GPIO Direction 17 bit" "Input,Output"
|
|
bitfld.long 0x04 16. " GDIR16 ,GPIO Direction 16 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GDIR15 ,GPIO Direction 15 bit" "Input,Output"
|
|
bitfld.long 0x04 14. " GDIR14 ,GPIO Direction 14 bit" "Input,Output"
|
|
bitfld.long 0x04 13. " GDIR13 ,GPIO Direction 13 bit" "Input,Output"
|
|
bitfld.long 0x04 12. " GDIR12 ,GPIO Direction 12 bit" "Input,Output"
|
|
bitfld.long 0x04 11. " GDIR11 ,GPIO Direction 11 bit" "Input,Output"
|
|
bitfld.long 0x04 10. " GDIR10 ,GPIO Direction 10 bit" "Input,Output"
|
|
bitfld.long 0x04 9. " GDIR9 ,GPIO Direction 9 bit" "Input,Output"
|
|
bitfld.long 0x04 8. " GDIR8 ,GPIO Direction 8 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " GDIR7 ,GPIO Direction 7 bit" "Input,Output"
|
|
bitfld.long 0x04 6. " GDIR6 ,GPIO Direction 6 bit" "Input,Output"
|
|
bitfld.long 0x04 5. " GDIR5 ,GPIO Direction 5 bit" "Input,Output"
|
|
bitfld.long 0x04 4. " GDIR4 ,GPIO Direction 4 bit" "Input,Output"
|
|
bitfld.long 0x04 3. " GDIR3 ,GPIO Direction 3 bit" "Input,Output"
|
|
bitfld.long 0x04 2. " GDIR2 ,GPIO Direction 2 bit" "Input,Output"
|
|
bitfld.long 0x04 1. " GDIR1 ,GPIO Direction 1 bit" "Input,Output"
|
|
bitfld.long 0x04 0. " GDIR0 ,GPIO Direction 0 bit" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "PSR,GPIO Pad Status Register"
|
|
bitfld.long 0x00 31. " PSR31 ,GPIO Pad Status bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PSR30 ,GPIO Pad Status bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PSR29 ,GPIO Pad Status bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " PSR28 ,GPIO Pad Status bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PSR27 ,GPIO Pad Status bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PSR26 ,GPIO Pad Status bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " PSR25 ,GPIO Pad Status bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PSR24 ,GPIO Pad Status bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PSR23 ,GPIO Pad Status bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " PSR22 ,GPIO Pad Status bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PSR21 ,GPIO Pad Status bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PSR20 ,GPIO Pad Status bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " PSR19 ,GPIO Pad Status bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PSR18 ,GPIO Pad Status bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PSR17 ,GPIO Pad Status bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " PSR16 ,GPIO Pad Status bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PSR15 ,GPIO Pad Status bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PSR14 ,GPIO Pad Status bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " PSR13 ,GPIO Pad Status bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PSR12 ,GPIO Pad Status bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PSR11 ,GPIO Pad Status bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " PSR10 ,GPIO Pad Status bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PSR9 ,GPIO Pad Status bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PSR8 ,GPIO Pad Status bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSR7 ,GPIO Pad Status bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PSR6 ,GPIO Pad Status bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PSR5 ,GPIO Pad Status bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " PSR4 ,GPIO Pad Status bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PSR3 ,GPIO Pad Status bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PSR2 ,GPIO Pad Status bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " PSR1 ,GPIO Pad Status bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PSR0 ,GPIO Pad Status bit 0" "Low,High"
|
|
tree "GPIO Interrupt Registers"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 30.--31. " ICR1_15 ,Interrupt 15 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 28.--29. " ICR1_14 ,Interrupt 14 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 26.--27. " ICR1_13 ,Interrupt 13 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 24.--25. " ICR1_12 ,Interrupt 12 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 22.--23. " ICR1_11 ,Interrupt 11 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 20.--21. " ICR1_10 ,Interrupt 10 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ICR1_9 ,Interrupt 9 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 16.--17. " ICR1_8 ,Interrupt 8 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 14.--15. " ICR1_7 ,Interrupt 7 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 12.--13. " ICR1_6 ,Interrupt 6 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 10.--11. " ICR1_5 ,Interrupt 5 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 8.--9. " ICR1_4 ,Interrupt 4 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICR1_3 ,Interrupt 3 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 4.--5. " ICR1_2 ,Interrupt 2 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 2.--3. " ICR1_1 ,Interrupt 1 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 0.--1. " ICR1_0 ,Interrupt 0 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 30.--31. " ICR2_31 ,Interrupt 31 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 28.--29. " ICR2_30 ,Interrupt 30 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 26.--27. " ICR2_29 ,Interrupt 29 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 24.--25. " ICR2_28 ,Interrupt 28 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 22.--23. " ICR2_27 ,Interrupt 27 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 20.--21. " ICR2_26 ,Interrupt 26 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " ICR2_25 ,Interrupt 25 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 16.--17. " ICR2_24 ,Interrupt 24 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 14.--15. " ICR2_23 ,Interrupt 23 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 12.--13. " ICR2_22 ,Interrupt 22 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 10.--11. " ICR2_21 ,Interrupt 21 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 8.--9. " ICR2_20 ,Interrupt 20 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " ICR2_19 ,Interrupt 19 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 4.--5. " ICR2_18 ,Interrupt 18 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 2.--3. " ICR2_17 ,Interrupt 17 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 0.--1. " ICR2_16 ,Interrupt 16 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x08 "IMR,GPIO Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " IMR31 ,Interrupt 31 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " IMR30 ,Interrupt 30 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " IMR29 ,Interrupt 29 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " IMR28 ,Interrupt 28 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 27. " IMR27 ,Interrupt 27 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " IMR26 ,Interrupt 26 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IMR25 ,Interrupt 25 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " IMR24 ,Interrupt 24 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " IMR23 ,Interrupt 23 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " IMR22 ,Interrupt 22 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " IMR21 ,Interrupt 21 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " IMR20 ,Interrupt 20 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IMR19 ,Interrupt 19 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " IMR18 ,Interrupt 18 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " IMR17 ,Interrupt 17 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " IMR16 ,Interrupt 16 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " IMR15 ,Interrupt 15 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " IMR14 ,Interrupt 14 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IMR13 ,Interrupt 13 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " IMR12 ,Interrupt 12 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 11. " IMR11 ,Interrupt 11 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " IMR10 ,Interrupt 10 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " IMR9 ,Interrupt 9 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " IMR8 ,Interrupt 8 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IMR7 ,Interrupt 7 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " IMR6 ,Interrupt 6 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " IMR5 ,Interrupt 5 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " IMR4 ,Interrupt 4 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " IMR3 ,Interrupt 3 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " IMR2 ,Interrupt 2 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IMR1 ,Interrupt 1 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " IMR0 ,Interrupt 0 Mask bit" "Masked,Not masked"
|
|
line.long 0x0C "ISR,GPIO Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " ISR31 ,Interrupt 31 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " ISR30 ,Interrupt 30 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " ISR29 ,Interrupt 29 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " ISR28 ,Interrupt 28 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " ISR27 ,Interrupt 27 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " ISR26 ,Interrupt 26 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " ISR25 ,Interrupt 25 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " ISR24 ,Interrupt 24 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " ISR23 ,Interrupt 23 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " ISR22 ,Interrupt 22 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " ISR21 ,Interrupt 21 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " ISR20 ,Interrupt 20 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " ISR19 ,Interrupt 19 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " ISR18 ,Interrupt 18 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " ISR17 ,Interrupt 17 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " ISR16 ,Interrupt 16 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " ISR15 ,Interrupt 15 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " ISR14 ,Interrupt 14 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " ISR13 ,Interrupt 13 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " ISR12 ,Interrupt 12 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " ISR11 ,Interrupt 11 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " ISR10 ,Interrupt 10 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " ISR9 ,Interrupt 9 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " ISR8 ,Interrupt 8 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " ISR7 ,Interrupt 7 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " ISR6 ,Interrupt 6 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " ISR5 ,Interrupt 5 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " ISR4 ,Interrupt 4 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " ISR3 ,Interrupt 3 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " ISR2 ,Interrupt 2 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ISR1 ,Interrupt 1 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " ISR0 ,Interrupt 0 Status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO 2"
|
|
base ad:0x73f88000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,GPIO Data Register"
|
|
bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High"
|
|
line.long 0x04 "GDIR,GPIO Direction Register"
|
|
bitfld.long 0x04 31. " GDIR31 ,GPIO Direction 31 bit" "Input,Output"
|
|
bitfld.long 0x04 30. " GDIR30 ,GPIO Direction 30 bit" "Input,Output"
|
|
bitfld.long 0x04 29. " GDIR29 ,GPIO Direction 29 bit" "Input,Output"
|
|
bitfld.long 0x04 28. " GDIR28 ,GPIO Direction 28 bit" "Input,Output"
|
|
bitfld.long 0x04 27. " GDIR27 ,GPIO Direction 27 bit" "Input,Output"
|
|
bitfld.long 0x04 26. " GDIR26 ,GPIO Direction 26 bit" "Input,Output"
|
|
bitfld.long 0x04 25. " GDIR25 ,GPIO Direction 25 bit" "Input,Output"
|
|
bitfld.long 0x04 24. " GDIR24 ,GPIO Direction 24 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GDIR23 ,GPIO Direction 23 bit" "Input,Output"
|
|
bitfld.long 0x04 22. " GDIR22 ,GPIO Direction 22 bit" "Input,Output"
|
|
bitfld.long 0x04 21. " GDIR21 ,GPIO Direction 21 bit" "Input,Output"
|
|
bitfld.long 0x04 20. " GDIR20 ,GPIO Direction 20 bit" "Input,Output"
|
|
bitfld.long 0x04 19. " GDIR19 ,GPIO Direction 19 bit" "Input,Output"
|
|
bitfld.long 0x04 18. " GDIR18 ,GPIO Direction 18 bit" "Input,Output"
|
|
bitfld.long 0x04 17. " GDIR17 ,GPIO Direction 17 bit" "Input,Output"
|
|
bitfld.long 0x04 16. " GDIR16 ,GPIO Direction 16 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GDIR15 ,GPIO Direction 15 bit" "Input,Output"
|
|
bitfld.long 0x04 14. " GDIR14 ,GPIO Direction 14 bit" "Input,Output"
|
|
bitfld.long 0x04 13. " GDIR13 ,GPIO Direction 13 bit" "Input,Output"
|
|
bitfld.long 0x04 12. " GDIR12 ,GPIO Direction 12 bit" "Input,Output"
|
|
bitfld.long 0x04 11. " GDIR11 ,GPIO Direction 11 bit" "Input,Output"
|
|
bitfld.long 0x04 10. " GDIR10 ,GPIO Direction 10 bit" "Input,Output"
|
|
bitfld.long 0x04 9. " GDIR9 ,GPIO Direction 9 bit" "Input,Output"
|
|
bitfld.long 0x04 8. " GDIR8 ,GPIO Direction 8 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " GDIR7 ,GPIO Direction 7 bit" "Input,Output"
|
|
bitfld.long 0x04 6. " GDIR6 ,GPIO Direction 6 bit" "Input,Output"
|
|
bitfld.long 0x04 5. " GDIR5 ,GPIO Direction 5 bit" "Input,Output"
|
|
bitfld.long 0x04 4. " GDIR4 ,GPIO Direction 4 bit" "Input,Output"
|
|
bitfld.long 0x04 3. " GDIR3 ,GPIO Direction 3 bit" "Input,Output"
|
|
bitfld.long 0x04 2. " GDIR2 ,GPIO Direction 2 bit" "Input,Output"
|
|
bitfld.long 0x04 1. " GDIR1 ,GPIO Direction 1 bit" "Input,Output"
|
|
bitfld.long 0x04 0. " GDIR0 ,GPIO Direction 0 bit" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "PSR,GPIO Pad Status Register"
|
|
bitfld.long 0x00 31. " PSR31 ,GPIO Pad Status bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PSR30 ,GPIO Pad Status bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PSR29 ,GPIO Pad Status bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " PSR28 ,GPIO Pad Status bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PSR27 ,GPIO Pad Status bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PSR26 ,GPIO Pad Status bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " PSR25 ,GPIO Pad Status bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PSR24 ,GPIO Pad Status bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PSR23 ,GPIO Pad Status bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " PSR22 ,GPIO Pad Status bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PSR21 ,GPIO Pad Status bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PSR20 ,GPIO Pad Status bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " PSR19 ,GPIO Pad Status bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PSR18 ,GPIO Pad Status bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PSR17 ,GPIO Pad Status bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " PSR16 ,GPIO Pad Status bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PSR15 ,GPIO Pad Status bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PSR14 ,GPIO Pad Status bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " PSR13 ,GPIO Pad Status bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PSR12 ,GPIO Pad Status bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PSR11 ,GPIO Pad Status bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " PSR10 ,GPIO Pad Status bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PSR9 ,GPIO Pad Status bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PSR8 ,GPIO Pad Status bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSR7 ,GPIO Pad Status bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PSR6 ,GPIO Pad Status bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PSR5 ,GPIO Pad Status bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " PSR4 ,GPIO Pad Status bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PSR3 ,GPIO Pad Status bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PSR2 ,GPIO Pad Status bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " PSR1 ,GPIO Pad Status bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PSR0 ,GPIO Pad Status bit 0" "Low,High"
|
|
tree "GPIO Interrupt Registers"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 30.--31. " ICR1_15 ,Interrupt 15 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 28.--29. " ICR1_14 ,Interrupt 14 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 26.--27. " ICR1_13 ,Interrupt 13 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 24.--25. " ICR1_12 ,Interrupt 12 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 22.--23. " ICR1_11 ,Interrupt 11 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 20.--21. " ICR1_10 ,Interrupt 10 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ICR1_9 ,Interrupt 9 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 16.--17. " ICR1_8 ,Interrupt 8 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 14.--15. " ICR1_7 ,Interrupt 7 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 12.--13. " ICR1_6 ,Interrupt 6 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 10.--11. " ICR1_5 ,Interrupt 5 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 8.--9. " ICR1_4 ,Interrupt 4 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICR1_3 ,Interrupt 3 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 4.--5. " ICR1_2 ,Interrupt 2 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 2.--3. " ICR1_1 ,Interrupt 1 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 0.--1. " ICR1_0 ,Interrupt 0 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 30.--31. " ICR2_31 ,Interrupt 31 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 28.--29. " ICR2_30 ,Interrupt 30 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 26.--27. " ICR2_29 ,Interrupt 29 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 24.--25. " ICR2_28 ,Interrupt 28 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 22.--23. " ICR2_27 ,Interrupt 27 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 20.--21. " ICR2_26 ,Interrupt 26 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " ICR2_25 ,Interrupt 25 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 16.--17. " ICR2_24 ,Interrupt 24 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 14.--15. " ICR2_23 ,Interrupt 23 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 12.--13. " ICR2_22 ,Interrupt 22 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 10.--11. " ICR2_21 ,Interrupt 21 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 8.--9. " ICR2_20 ,Interrupt 20 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " ICR2_19 ,Interrupt 19 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 4.--5. " ICR2_18 ,Interrupt 18 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 2.--3. " ICR2_17 ,Interrupt 17 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 0.--1. " ICR2_16 ,Interrupt 16 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x08 "IMR,GPIO Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " IMR31 ,Interrupt 31 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " IMR30 ,Interrupt 30 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " IMR29 ,Interrupt 29 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " IMR28 ,Interrupt 28 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 27. " IMR27 ,Interrupt 27 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " IMR26 ,Interrupt 26 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IMR25 ,Interrupt 25 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " IMR24 ,Interrupt 24 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " IMR23 ,Interrupt 23 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " IMR22 ,Interrupt 22 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " IMR21 ,Interrupt 21 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " IMR20 ,Interrupt 20 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IMR19 ,Interrupt 19 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " IMR18 ,Interrupt 18 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " IMR17 ,Interrupt 17 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " IMR16 ,Interrupt 16 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " IMR15 ,Interrupt 15 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " IMR14 ,Interrupt 14 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IMR13 ,Interrupt 13 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " IMR12 ,Interrupt 12 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 11. " IMR11 ,Interrupt 11 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " IMR10 ,Interrupt 10 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " IMR9 ,Interrupt 9 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " IMR8 ,Interrupt 8 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IMR7 ,Interrupt 7 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " IMR6 ,Interrupt 6 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " IMR5 ,Interrupt 5 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " IMR4 ,Interrupt 4 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " IMR3 ,Interrupt 3 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " IMR2 ,Interrupt 2 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IMR1 ,Interrupt 1 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " IMR0 ,Interrupt 0 Mask bit" "Masked,Not masked"
|
|
line.long 0x0C "ISR,GPIO Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " ISR31 ,Interrupt 31 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " ISR30 ,Interrupt 30 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " ISR29 ,Interrupt 29 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " ISR28 ,Interrupt 28 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " ISR27 ,Interrupt 27 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " ISR26 ,Interrupt 26 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " ISR25 ,Interrupt 25 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " ISR24 ,Interrupt 24 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " ISR23 ,Interrupt 23 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " ISR22 ,Interrupt 22 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " ISR21 ,Interrupt 21 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " ISR20 ,Interrupt 20 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " ISR19 ,Interrupt 19 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " ISR18 ,Interrupt 18 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " ISR17 ,Interrupt 17 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " ISR16 ,Interrupt 16 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " ISR15 ,Interrupt 15 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " ISR14 ,Interrupt 14 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " ISR13 ,Interrupt 13 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " ISR12 ,Interrupt 12 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " ISR11 ,Interrupt 11 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " ISR10 ,Interrupt 10 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " ISR9 ,Interrupt 9 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " ISR8 ,Interrupt 8 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " ISR7 ,Interrupt 7 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " ISR6 ,Interrupt 6 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " ISR5 ,Interrupt 5 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " ISR4 ,Interrupt 4 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " ISR3 ,Interrupt 3 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " ISR2 ,Interrupt 2 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ISR1 ,Interrupt 1 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " ISR0 ,Interrupt 0 Status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO 3"
|
|
base ad:0x73f8c000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,GPIO Data Register"
|
|
bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High"
|
|
line.long 0x04 "GDIR,GPIO Direction Register"
|
|
bitfld.long 0x04 31. " GDIR31 ,GPIO Direction 31 bit" "Input,Output"
|
|
bitfld.long 0x04 30. " GDIR30 ,GPIO Direction 30 bit" "Input,Output"
|
|
bitfld.long 0x04 29. " GDIR29 ,GPIO Direction 29 bit" "Input,Output"
|
|
bitfld.long 0x04 28. " GDIR28 ,GPIO Direction 28 bit" "Input,Output"
|
|
bitfld.long 0x04 27. " GDIR27 ,GPIO Direction 27 bit" "Input,Output"
|
|
bitfld.long 0x04 26. " GDIR26 ,GPIO Direction 26 bit" "Input,Output"
|
|
bitfld.long 0x04 25. " GDIR25 ,GPIO Direction 25 bit" "Input,Output"
|
|
bitfld.long 0x04 24. " GDIR24 ,GPIO Direction 24 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GDIR23 ,GPIO Direction 23 bit" "Input,Output"
|
|
bitfld.long 0x04 22. " GDIR22 ,GPIO Direction 22 bit" "Input,Output"
|
|
bitfld.long 0x04 21. " GDIR21 ,GPIO Direction 21 bit" "Input,Output"
|
|
bitfld.long 0x04 20. " GDIR20 ,GPIO Direction 20 bit" "Input,Output"
|
|
bitfld.long 0x04 19. " GDIR19 ,GPIO Direction 19 bit" "Input,Output"
|
|
bitfld.long 0x04 18. " GDIR18 ,GPIO Direction 18 bit" "Input,Output"
|
|
bitfld.long 0x04 17. " GDIR17 ,GPIO Direction 17 bit" "Input,Output"
|
|
bitfld.long 0x04 16. " GDIR16 ,GPIO Direction 16 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GDIR15 ,GPIO Direction 15 bit" "Input,Output"
|
|
bitfld.long 0x04 14. " GDIR14 ,GPIO Direction 14 bit" "Input,Output"
|
|
bitfld.long 0x04 13. " GDIR13 ,GPIO Direction 13 bit" "Input,Output"
|
|
bitfld.long 0x04 12. " GDIR12 ,GPIO Direction 12 bit" "Input,Output"
|
|
bitfld.long 0x04 11. " GDIR11 ,GPIO Direction 11 bit" "Input,Output"
|
|
bitfld.long 0x04 10. " GDIR10 ,GPIO Direction 10 bit" "Input,Output"
|
|
bitfld.long 0x04 9. " GDIR9 ,GPIO Direction 9 bit" "Input,Output"
|
|
bitfld.long 0x04 8. " GDIR8 ,GPIO Direction 8 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " GDIR7 ,GPIO Direction 7 bit" "Input,Output"
|
|
bitfld.long 0x04 6. " GDIR6 ,GPIO Direction 6 bit" "Input,Output"
|
|
bitfld.long 0x04 5. " GDIR5 ,GPIO Direction 5 bit" "Input,Output"
|
|
bitfld.long 0x04 4. " GDIR4 ,GPIO Direction 4 bit" "Input,Output"
|
|
bitfld.long 0x04 3. " GDIR3 ,GPIO Direction 3 bit" "Input,Output"
|
|
bitfld.long 0x04 2. " GDIR2 ,GPIO Direction 2 bit" "Input,Output"
|
|
bitfld.long 0x04 1. " GDIR1 ,GPIO Direction 1 bit" "Input,Output"
|
|
bitfld.long 0x04 0. " GDIR0 ,GPIO Direction 0 bit" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "PSR,GPIO Pad Status Register"
|
|
bitfld.long 0x00 31. " PSR31 ,GPIO Pad Status bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PSR30 ,GPIO Pad Status bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PSR29 ,GPIO Pad Status bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " PSR28 ,GPIO Pad Status bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PSR27 ,GPIO Pad Status bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PSR26 ,GPIO Pad Status bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " PSR25 ,GPIO Pad Status bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PSR24 ,GPIO Pad Status bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PSR23 ,GPIO Pad Status bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " PSR22 ,GPIO Pad Status bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PSR21 ,GPIO Pad Status bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PSR20 ,GPIO Pad Status bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " PSR19 ,GPIO Pad Status bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PSR18 ,GPIO Pad Status bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PSR17 ,GPIO Pad Status bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " PSR16 ,GPIO Pad Status bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PSR15 ,GPIO Pad Status bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PSR14 ,GPIO Pad Status bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " PSR13 ,GPIO Pad Status bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PSR12 ,GPIO Pad Status bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PSR11 ,GPIO Pad Status bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " PSR10 ,GPIO Pad Status bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PSR9 ,GPIO Pad Status bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PSR8 ,GPIO Pad Status bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSR7 ,GPIO Pad Status bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PSR6 ,GPIO Pad Status bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PSR5 ,GPIO Pad Status bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " PSR4 ,GPIO Pad Status bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PSR3 ,GPIO Pad Status bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PSR2 ,GPIO Pad Status bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " PSR1 ,GPIO Pad Status bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PSR0 ,GPIO Pad Status bit 0" "Low,High"
|
|
tree "GPIO Interrupt Registers"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 30.--31. " ICR1_15 ,Interrupt 15 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 28.--29. " ICR1_14 ,Interrupt 14 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 26.--27. " ICR1_13 ,Interrupt 13 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 24.--25. " ICR1_12 ,Interrupt 12 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 22.--23. " ICR1_11 ,Interrupt 11 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 20.--21. " ICR1_10 ,Interrupt 10 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ICR1_9 ,Interrupt 9 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 16.--17. " ICR1_8 ,Interrupt 8 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 14.--15. " ICR1_7 ,Interrupt 7 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 12.--13. " ICR1_6 ,Interrupt 6 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 10.--11. " ICR1_5 ,Interrupt 5 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 8.--9. " ICR1_4 ,Interrupt 4 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICR1_3 ,Interrupt 3 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 4.--5. " ICR1_2 ,Interrupt 2 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 2.--3. " ICR1_1 ,Interrupt 1 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 0.--1. " ICR1_0 ,Interrupt 0 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 30.--31. " ICR2_31 ,Interrupt 31 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 28.--29. " ICR2_30 ,Interrupt 30 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 26.--27. " ICR2_29 ,Interrupt 29 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 24.--25. " ICR2_28 ,Interrupt 28 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 22.--23. " ICR2_27 ,Interrupt 27 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 20.--21. " ICR2_26 ,Interrupt 26 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " ICR2_25 ,Interrupt 25 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 16.--17. " ICR2_24 ,Interrupt 24 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 14.--15. " ICR2_23 ,Interrupt 23 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 12.--13. " ICR2_22 ,Interrupt 22 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 10.--11. " ICR2_21 ,Interrupt 21 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 8.--9. " ICR2_20 ,Interrupt 20 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " ICR2_19 ,Interrupt 19 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 4.--5. " ICR2_18 ,Interrupt 18 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 2.--3. " ICR2_17 ,Interrupt 17 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 0.--1. " ICR2_16 ,Interrupt 16 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x08 "IMR,GPIO Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " IMR31 ,Interrupt 31 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " IMR30 ,Interrupt 30 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " IMR29 ,Interrupt 29 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " IMR28 ,Interrupt 28 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 27. " IMR27 ,Interrupt 27 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " IMR26 ,Interrupt 26 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IMR25 ,Interrupt 25 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " IMR24 ,Interrupt 24 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " IMR23 ,Interrupt 23 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " IMR22 ,Interrupt 22 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " IMR21 ,Interrupt 21 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " IMR20 ,Interrupt 20 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IMR19 ,Interrupt 19 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " IMR18 ,Interrupt 18 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " IMR17 ,Interrupt 17 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " IMR16 ,Interrupt 16 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " IMR15 ,Interrupt 15 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " IMR14 ,Interrupt 14 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IMR13 ,Interrupt 13 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " IMR12 ,Interrupt 12 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 11. " IMR11 ,Interrupt 11 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " IMR10 ,Interrupt 10 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " IMR9 ,Interrupt 9 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " IMR8 ,Interrupt 8 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IMR7 ,Interrupt 7 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " IMR6 ,Interrupt 6 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " IMR5 ,Interrupt 5 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " IMR4 ,Interrupt 4 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " IMR3 ,Interrupt 3 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " IMR2 ,Interrupt 2 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IMR1 ,Interrupt 1 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " IMR0 ,Interrupt 0 Mask bit" "Masked,Not masked"
|
|
line.long 0x0C "ISR,GPIO Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " ISR31 ,Interrupt 31 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " ISR30 ,Interrupt 30 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " ISR29 ,Interrupt 29 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " ISR28 ,Interrupt 28 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " ISR27 ,Interrupt 27 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " ISR26 ,Interrupt 26 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " ISR25 ,Interrupt 25 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " ISR24 ,Interrupt 24 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " ISR23 ,Interrupt 23 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " ISR22 ,Interrupt 22 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " ISR21 ,Interrupt 21 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " ISR20 ,Interrupt 20 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " ISR19 ,Interrupt 19 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " ISR18 ,Interrupt 18 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " ISR17 ,Interrupt 17 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " ISR16 ,Interrupt 16 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " ISR15 ,Interrupt 15 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " ISR14 ,Interrupt 14 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " ISR13 ,Interrupt 13 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " ISR12 ,Interrupt 12 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " ISR11 ,Interrupt 11 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " ISR10 ,Interrupt 10 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " ISR9 ,Interrupt 9 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " ISR8 ,Interrupt 8 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " ISR7 ,Interrupt 7 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " ISR6 ,Interrupt 6 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " ISR5 ,Interrupt 5 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " ISR4 ,Interrupt 4 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " ISR3 ,Interrupt 3 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " ISR2 ,Interrupt 2 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ISR1 ,Interrupt 1 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " ISR0 ,Interrupt 0 Status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO 4"
|
|
base ad:0x73f90000
|
|
width 6.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "DR,GPIO Data Register"
|
|
bitfld.long 0x00 31. " DR31 ,Data bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " DR30 ,Data bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " DR29 ,Data bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " DR28 ,Data bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " DR27 ,Data bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " DR26 ,Data bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " DR25 ,Data bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " DR24 ,Data bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DR23 ,Data bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " DR22 ,Data bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " DR21 ,Data bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " DR20 ,Data bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " DR19 ,Data bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " DR18 ,Data bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " DR17 ,Data bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " DR16 ,Data bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DR15 ,Data bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " DR14 ,Data bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " DR13 ,Data bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " DR12 ,Data bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " DR11 ,Data bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " DR10 ,Data bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " DR9 ,Data bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " DR8 ,Data bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DR7 ,Data bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " DR6 ,Data bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " DR5 ,Data bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " DR4 ,Data bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " DR3 ,Data bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " DR2 ,Data bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " DR1 ,Data bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " DR0 ,Data bit 0" "Low,High"
|
|
line.long 0x04 "GDIR,GPIO Direction Register"
|
|
bitfld.long 0x04 31. " GDIR31 ,GPIO Direction 31 bit" "Input,Output"
|
|
bitfld.long 0x04 30. " GDIR30 ,GPIO Direction 30 bit" "Input,Output"
|
|
bitfld.long 0x04 29. " GDIR29 ,GPIO Direction 29 bit" "Input,Output"
|
|
bitfld.long 0x04 28. " GDIR28 ,GPIO Direction 28 bit" "Input,Output"
|
|
bitfld.long 0x04 27. " GDIR27 ,GPIO Direction 27 bit" "Input,Output"
|
|
bitfld.long 0x04 26. " GDIR26 ,GPIO Direction 26 bit" "Input,Output"
|
|
bitfld.long 0x04 25. " GDIR25 ,GPIO Direction 25 bit" "Input,Output"
|
|
bitfld.long 0x04 24. " GDIR24 ,GPIO Direction 24 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GDIR23 ,GPIO Direction 23 bit" "Input,Output"
|
|
bitfld.long 0x04 22. " GDIR22 ,GPIO Direction 22 bit" "Input,Output"
|
|
bitfld.long 0x04 21. " GDIR21 ,GPIO Direction 21 bit" "Input,Output"
|
|
bitfld.long 0x04 20. " GDIR20 ,GPIO Direction 20 bit" "Input,Output"
|
|
bitfld.long 0x04 19. " GDIR19 ,GPIO Direction 19 bit" "Input,Output"
|
|
bitfld.long 0x04 18. " GDIR18 ,GPIO Direction 18 bit" "Input,Output"
|
|
bitfld.long 0x04 17. " GDIR17 ,GPIO Direction 17 bit" "Input,Output"
|
|
bitfld.long 0x04 16. " GDIR16 ,GPIO Direction 16 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GDIR15 ,GPIO Direction 15 bit" "Input,Output"
|
|
bitfld.long 0x04 14. " GDIR14 ,GPIO Direction 14 bit" "Input,Output"
|
|
bitfld.long 0x04 13. " GDIR13 ,GPIO Direction 13 bit" "Input,Output"
|
|
bitfld.long 0x04 12. " GDIR12 ,GPIO Direction 12 bit" "Input,Output"
|
|
bitfld.long 0x04 11. " GDIR11 ,GPIO Direction 11 bit" "Input,Output"
|
|
bitfld.long 0x04 10. " GDIR10 ,GPIO Direction 10 bit" "Input,Output"
|
|
bitfld.long 0x04 9. " GDIR9 ,GPIO Direction 9 bit" "Input,Output"
|
|
bitfld.long 0x04 8. " GDIR8 ,GPIO Direction 8 bit" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " GDIR7 ,GPIO Direction 7 bit" "Input,Output"
|
|
bitfld.long 0x04 6. " GDIR6 ,GPIO Direction 6 bit" "Input,Output"
|
|
bitfld.long 0x04 5. " GDIR5 ,GPIO Direction 5 bit" "Input,Output"
|
|
bitfld.long 0x04 4. " GDIR4 ,GPIO Direction 4 bit" "Input,Output"
|
|
bitfld.long 0x04 3. " GDIR3 ,GPIO Direction 3 bit" "Input,Output"
|
|
bitfld.long 0x04 2. " GDIR2 ,GPIO Direction 2 bit" "Input,Output"
|
|
bitfld.long 0x04 1. " GDIR1 ,GPIO Direction 1 bit" "Input,Output"
|
|
bitfld.long 0x04 0. " GDIR0 ,GPIO Direction 0 bit" "Input,Output"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "PSR,GPIO Pad Status Register"
|
|
bitfld.long 0x00 31. " PSR31 ,GPIO Pad Status bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " PSR30 ,GPIO Pad Status bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " PSR29 ,GPIO Pad Status bit 29" "Low,High"
|
|
bitfld.long 0x00 28. " PSR28 ,GPIO Pad Status bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " PSR27 ,GPIO Pad Status bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " PSR26 ,GPIO Pad Status bit 26" "Low,High"
|
|
bitfld.long 0x00 25. " PSR25 ,GPIO Pad Status bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " PSR24 ,GPIO Pad Status bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PSR23 ,GPIO Pad Status bit 23" "Low,High"
|
|
bitfld.long 0x00 22. " PSR22 ,GPIO Pad Status bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " PSR21 ,GPIO Pad Status bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " PSR20 ,GPIO Pad Status bit 20" "Low,High"
|
|
bitfld.long 0x00 19. " PSR19 ,GPIO Pad Status bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " PSR18 ,GPIO Pad Status bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " PSR17 ,GPIO Pad Status bit 17" "Low,High"
|
|
bitfld.long 0x00 16. " PSR16 ,GPIO Pad Status bit 16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PSR15 ,GPIO Pad Status bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " PSR14 ,GPIO Pad Status bit 14" "Low,High"
|
|
bitfld.long 0x00 13. " PSR13 ,GPIO Pad Status bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " PSR12 ,GPIO Pad Status bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " PSR11 ,GPIO Pad Status bit 11" "Low,High"
|
|
bitfld.long 0x00 10. " PSR10 ,GPIO Pad Status bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " PSR9 ,GPIO Pad Status bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " PSR8 ,GPIO Pad Status bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PSR7 ,GPIO Pad Status bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " PSR6 ,GPIO Pad Status bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " PSR5 ,GPIO Pad Status bit 5" "Low,High"
|
|
bitfld.long 0x00 4. " PSR4 ,GPIO Pad Status bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " PSR3 ,GPIO Pad Status bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " PSR2 ,GPIO Pad Status bit 2" "Low,High"
|
|
bitfld.long 0x00 1. " PSR1 ,GPIO Pad Status bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " PSR0 ,GPIO Pad Status bit 0" "Low,High"
|
|
tree "GPIO Interrupt Registers"
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "ICR1,GPIO Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 30.--31. " ICR1_15 ,Interrupt 15 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 28.--29. " ICR1_14 ,Interrupt 14 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 26.--27. " ICR1_13 ,Interrupt 13 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 24.--25. " ICR1_12 ,Interrupt 12 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 22.--23. " ICR1_11 ,Interrupt 11 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 20.--21. " ICR1_10 ,Interrupt 10 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ICR1_9 ,Interrupt 9 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 16.--17. " ICR1_8 ,Interrupt 8 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 14.--15. " ICR1_7 ,Interrupt 7 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 12.--13. " ICR1_6 ,Interrupt 6 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 10.--11. " ICR1_5 ,Interrupt 5 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 8.--9. " ICR1_4 ,Interrupt 4 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " ICR1_3 ,Interrupt 3 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 4.--5. " ICR1_2 ,Interrupt 2 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 2.--3. " ICR1_1 ,Interrupt 1 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x00 0.--1. " ICR1_0 ,Interrupt 0 Configuration 1 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x04 "ICR2,GPIO Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 30.--31. " ICR2_31 ,Interrupt 31 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 28.--29. " ICR2_30 ,Interrupt 30 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 26.--27. " ICR2_29 ,Interrupt 29 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 24.--25. " ICR2_28 ,Interrupt 28 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 22.--23. " ICR2_27 ,Interrupt 27 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 20.--21. " ICR2_26 ,Interrupt 26 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 18.--19. " ICR2_25 ,Interrupt 25 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 16.--17. " ICR2_24 ,Interrupt 24 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 14.--15. " ICR2_23 ,Interrupt 23 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 12.--13. " ICR2_22 ,Interrupt 22 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 10.--11. " ICR2_21 ,Interrupt 21 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 8.--9. " ICR2_20 ,Interrupt 20 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " ICR2_19 ,Interrupt 19 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 4.--5. " ICR2_18 ,Interrupt 18 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 2.--3. " ICR2_17 ,Interrupt 17 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
bitfld.long 0x04 0.--1. " ICR2_16 ,Interrupt 16 Configuration 2 bits" "Low-level,High-level,Rise-edge,Fall-edge"
|
|
line.long 0x08 "IMR,GPIO Interrupt Mask Register"
|
|
bitfld.long 0x08 31. " IMR31 ,Interrupt 31 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 30. " IMR30 ,Interrupt 30 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 29. " IMR29 ,Interrupt 29 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 28. " IMR28 ,Interrupt 28 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 27. " IMR27 ,Interrupt 27 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 26. " IMR26 ,Interrupt 26 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " IMR25 ,Interrupt 25 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 24. " IMR24 ,Interrupt 24 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 23. " IMR23 ,Interrupt 23 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 22. " IMR22 ,Interrupt 22 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 21. " IMR21 ,Interrupt 21 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 20. " IMR20 ,Interrupt 20 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IMR19 ,Interrupt 19 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 18. " IMR18 ,Interrupt 18 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 17. " IMR17 ,Interrupt 17 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 16. " IMR16 ,Interrupt 16 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 15. " IMR15 ,Interrupt 15 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 14. " IMR14 ,Interrupt 14 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " IMR13 ,Interrupt 13 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 12. " IMR12 ,Interrupt 12 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 11. " IMR11 ,Interrupt 11 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 10. " IMR10 ,Interrupt 10 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 9. " IMR9 ,Interrupt 9 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 8. " IMR8 ,Interrupt 8 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IMR7 ,Interrupt 7 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 6. " IMR6 ,Interrupt 6 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 5. " IMR5 ,Interrupt 5 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 4. " IMR4 ,Interrupt 4 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 3. " IMR3 ,Interrupt 3 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " IMR2 ,Interrupt 2 Mask bit" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IMR1 ,Interrupt 1 Mask bit" "Masked,Not masked"
|
|
bitfld.long 0x08 0. " IMR0 ,Interrupt 0 Mask bit" "Masked,Not masked"
|
|
line.long 0x0C "ISR,GPIO Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " ISR31 ,Interrupt 31 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " ISR30 ,Interrupt 30 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " ISR29 ,Interrupt 29 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " ISR28 ,Interrupt 28 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " ISR27 ,Interrupt 27 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 26. " ISR26 ,Interrupt 26 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " ISR25 ,Interrupt 25 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " ISR24 ,Interrupt 24 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " ISR23 ,Interrupt 23 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " ISR22 ,Interrupt 22 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " ISR21 ,Interrupt 21 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " ISR20 ,Interrupt 20 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " ISR19 ,Interrupt 19 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " ISR18 ,Interrupt 18 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " ISR17 ,Interrupt 17 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " ISR16 ,Interrupt 16 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " ISR15 ,Interrupt 15 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " ISR14 ,Interrupt 14 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " ISR13 ,Interrupt 13 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " ISR12 ,Interrupt 12 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " ISR11 ,Interrupt 11 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " ISR10 ,Interrupt 10 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " ISR9 ,Interrupt 9 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " ISR8 ,Interrupt 8 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " ISR7 ,Interrupt 7 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 6. " ISR6 ,Interrupt 6 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " ISR5 ,Interrupt 5 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " ISR4 ,Interrupt 4 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " ISR3 ,Interrupt 3 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " ISR2 ,Interrupt 2 Status bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " ISR1 ,Interrupt 1 Status bit" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " ISR0 ,Interrupt 0 Status bit" "No interrupt,Interrupt"
|
|
tree.end
|
|
textline " "
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "GPT (General Purpose Timer)"
|
|
base ad:0x73fa0000
|
|
width 9.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "GPTCR,GPT Control Register"
|
|
bitfld.long 0x00 31. " FO3 ,Force Output Compare Channel 3" "No effect,Compare"
|
|
bitfld.long 0x00 30. " FO2 ,Force Output Compare Channel 2" "No effect,Compare"
|
|
bitfld.long 0x00 29. " FO1 ,Force Output Compare Channel 1" "No effect,Compare"
|
|
textline " "
|
|
bitfld.long 0x00 26.--28. " OM3 ,Output Compare Channel 3 Operating Mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse"
|
|
bitfld.long 0x00 23.--25. " OM2 ,Output Compare Channel 2 Operating Mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse"
|
|
bitfld.long 0x00 20.--22. " OM1 ,Output Compare Channel 1 Operating Mode" "Disconnected,Toggled,Cleared,Set,Pulse,Pulse,Pulse,Pulse"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " IM2 ,Input Capture Channel 2 Operating Mode" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 16.--17. " IM1 ,Input Capture Channel 1 Operating Mode" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 15. " SWR ,Software Reset" "No reset,Reset"
|
|
textline " "
|
|
sif (cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6DUALLITE")
|
|
bitfld.long 0x00 10. " 24MEN ,Enable 24MHz clock input from crystal" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " FRR ,Freerun Or Restart Mode" "Restart,Freerun"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x00 6.--8. " CLKSRC ,Clock Source Select" "No clock,Peripheral Clock,High Frequency,External Clock,Low Frequency,Low Frequency,Low Frequency,Low Frequency"
|
|
elif (cpu()=="IMX6DUAL"||cpu()=="IMX6QUADLITE"||cpu()=="IMX6QUAD")
|
|
bitfld.long 0x00 6.--8. " CLKSRC ,Clock Source Select" "No clock,Peripheral Clock,High Frequency,External Clock,Low Frequency,Crystal oscillator/8,,Crystal oscillator"
|
|
elif (cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6DUALLITE"||cpuis("IMX50*"))
|
|
bitfld.long 0x00 6.--8. " CLKSRC ,Clock Source Select" "No clock,Peripheral Clock,High Frequency,External Clock,Low Frequency,Crystal oscillator,?..."
|
|
else
|
|
bitfld.long 0x00 6.--8. " CLKSRC ,Clock Source Select" "No clock,ipg_clk,ipg_clk_highfreq,ipp_ind_clkin,ipg_clk_32k,ipg_clk_32k,ipg_clk_32k,ipg_clk_32k"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPEN ,GPT Stop Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("IMX6*")||cpuis("IMX50*"))
|
|
bitfld.long 0x00 4. " DOZEEN ,GPT Doze Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " WAITEN ,GPT Wait Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DBGEN ,GPT Debug Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENMODE ,GPT Enable Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,GPT Enable" "Disabled,Enabled"
|
|
line.long 0x04 "GPTPR,GPT Prescaler Register"
|
|
sif (cpu()=="IMX6SOLO"||cpu()=="IMX6SOLOLITE"||cpu()=="IMX6DUALLITE")
|
|
bitfld.long 0x04 12.--15. " PRESCALER24M ,Prescaler bits" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
endif
|
|
hexmask.long.word 0x04 0.--11. 1. " PRESCALER ,Prescaler"
|
|
line.long 0x08 "GPTSR,GPT Status Register"
|
|
eventfld.long 0x08 5. " ROV ,Rollover Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " IF2 ,Input Capture 2 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " IF1 ,Input Capture 1 Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x08 2. " OF3 ,Output Compare 3 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 1. " OF2 ,Output Compare 2 Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x08 0. " OF1 ,Output Compare 1Flag" "Not occurred,Occurred"
|
|
line.long 0x0c "GPTIR,GPT Interrupt Register"
|
|
bitfld.long 0x0C 5. " ROVIE ,Rollover Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " IF2IE ,Input Capture 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " IF1IE ,Input Capture 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " OF3IE ,Output Compare 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " OF2IE ,Output Compare 2Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " OF1IE ,Output Compare 1Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x10 "GPTOCR1,GPT Output Compare Register 1"
|
|
line.long 0x14 "GPTOCR2,GPT Output Compare Register 2"
|
|
line.long 0x18 "GPTOCR3,GPT Output Compare Register 3"
|
|
rgroup.long 0x1C++0x0B
|
|
line.long 0x00 "GPTICR1,GPT Input Capture Register 1"
|
|
line.long 0x04 "GPTICR2,GPT Input Capture Register 2"
|
|
line.long 0x08 "GPTCNT,GPT Counter Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "HS_I2C (High Speed Inter IC)"
|
|
base ad:0x70038000
|
|
width 9.
|
|
if (((per.word(ad:0x70038000+0x08))&0x100)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "HISADR,HS_I2C Slave Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " ADR ,7 bit slave address"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "HIMADR,HS_I2C Master Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " ADR ,7 bit master address"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "HISADR,HS_I2C Slave Address Register"
|
|
hexmask.word 0x00 1.--10. 0x2 " ADR ,10 bit slave address"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "HIMADR,HS_I2C Master Address Register"
|
|
hexmask.word 0x00 1.--10. 0x2 " ADR ,10 bit master address"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "HICR,HS_I2C Control Register"
|
|
bitfld.word 0x00 15. " AUTO_RSTA ,Auto Restart" "Not generated,Generated"
|
|
bitfld.word 0x00 13.--14. " SAMC ,Slave Address Mode Control" "Both addressing,7bit addressing,10bit addressing,?..."
|
|
textline " "
|
|
bitfld.word 0x00 12. " HSM_EN ,High Speed Mode Enable" "Fast/Standard,High speed"
|
|
hexmask.word.byte 0x00 9.--11. 1. " HS_MST_CODE ,High Speed Master Code"
|
|
textline " "
|
|
bitfld.word 0x00 8. " ADDR_MODE ,Address Mode select" "7 bit,10 bit"
|
|
bitfld.word 0x00 7. " HIIEN ,HS_I2C interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " MSTA ,Master/slave mode select bit" "Slave,Master"
|
|
bitfld.word 0x00 5. " MTX ,Transmit/receive mode select bit" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.word 0x00 4. " TXAK ,Transmit acknowledge enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RSTA ,Repeat start" "No repeat,Repeat"
|
|
textline " "
|
|
bitfld.word 0x00 2. " DMA_EN_TX ,DMA Enable for TX" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DMA_EN_RX ,DMA Enable for RX" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " HIEN ,HS_I2C enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "HISR,HS_I2C Status Register"
|
|
bitfld.word 0x00 11. " SHS_MODE ,Slave high speed mode" "Fast/Standard,High speed"
|
|
bitfld.word 0x00 10. " SADDR_MODE ,Slave address mode" "7 bit,10 bit"
|
|
textline " "
|
|
bitfld.word 0x00 9. " SRW ,Slave read/write" "Receive,Transmit"
|
|
bitfld.word 0x00 8. " HIBB ,HS_I2C bus busy" "Idle,Busy"
|
|
textline " "
|
|
eventfld.word 0x00 7. " RXAK ,Received acknowledge" "Not received,Received"
|
|
eventfld.word 0x00 6. " TDC_ZERO ,Transmit Data Counter Zero" "Not zero,Zero"
|
|
textline " "
|
|
eventfld.word 0x00 5. " RDC_ZERO ,Receive Data Counter Zero" "Not zero,Zero"
|
|
eventfld.word 0x00 4. " BTD ,Byte transfer done" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.word 0x00 3. " HIAL ,HS_I2C Arbitration lost" "Not lost,Lost"
|
|
eventfld.word 0x00 2. " HIAAS ,HS_I2C addressed as a slave bit" "Not addressed,Addressed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TDE ,Transmit Data Empty" ">Transmit,<=Transmit"
|
|
bitfld.word 0x00 0. " RDF ,Receive Data Full" "Below,Reached"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "HIIMR,HS_I2C Interrupt Mask Register"
|
|
bitfld.word 0x00 7. " MASK_RXAK ,Mask Received Acknowledge Interrupt" "Not masked,Masked"
|
|
bitfld.word 0x00 6. " MASK_TDC ,Mask Transmit Data Count Zero Interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MASK_RDC ,Mask Receive Data Count Zero Interrupt" "Not masked,Masked"
|
|
bitfld.word 0x00 4. " MASK_BTD ,Mask Data Transfer Interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MASK_AL ,Mask Arbitration Lost Interrupt" "Not masked,Masked"
|
|
bitfld.word 0x00 2. " MASK_AAS ,Mask Addressed As Slave Interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " MASK_TDE ,Mask Transmit Data Empty Interrupt" "Not masked,Masked"
|
|
bitfld.word 0x00 0. " MASK_RDF ,Mask Receive Data Full Interrupt" "Not masked,Masked"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "HITDR,HS_I2C Tx Data Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TX_DATA ,TX Data Byte"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "HIRDR,HS_I2C Rx Data Register"
|
|
in
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "HIFSFDR,HS_I2C F/S-Mode Frequency Divide Register"
|
|
bitfld.word 0x00 0.--5. " FSICR ,F/S-Mode I2C clock rate" "26,28,30,32,40,44,48,52,72,80,88,96,128,144,160,176,256,288,320,352,512,576,640,704,1024,1152,1280,1408,2048,2304,2560,2816,34,36,38,40,56,60,64,68,104,112,120,128,192,208,224,240,384,416,448,480,768,832,896,960,1536,1664,1792,1920,3072,3328,3584,3840"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "HIHSFDR,HS_I2C HS-Mode Frequency Divider Register"
|
|
bitfld.word 0x00 0.--5. " HSICR ,HS-Mode I2C clock rate" "16,18,20,22,28,32,36,40,56,64,72,80,112,128,144,160,224,256,288,320,448,512,576,640,896,1024,1152,1280,1792,2048,2304,2560,24,26,28,30,44,48,52,56,88,96,104,112,176,192,208,224,352,384,416,448,704,768,832,896,1408,1536,1664,1792,2816,3072,3328,3584"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "HITFR,HS_I2C Tx FIFO Register"
|
|
bitfld.word 0x00 8.--11. " TFC ,Transmit FIFO Counter" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.word 0x00 2.--4. " TFWM ,Transmit FIFO Empty WaterMark" "0 dword,=< 1 byte,=< 2 bytes,=< 3 bytes,=< 4 bytes,=< 5 bytes,=< 6 bytes,=< 7 bytes"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TFLSH ,Transmit FIFO Flush" "No action,Reset"
|
|
bitfld.word 0x00 0. " TFEN ,Transmit FIFO Enable" "Disabled,Enabled"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "HIRFR,HS_I2C Rx FIFO Register"
|
|
bitfld.word 0x00 8.--11. " RFC ,Receive FIFO Counter" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
bitfld.word 0x00 2.--4. " RFWM ,Receive FIFO Full WaterMark" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RFLSH ,Receive FIFO Flush" "No effect,Reset"
|
|
bitfld.word 0x00 0. " RFEN ,Receive FIFO Enable" "Disabled,Enabled"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "HITDCR,HS_I2C Tx Data Count Register"
|
|
bitfld.word 0x00 9. " TDC_RSTA ,Transmit Data Count Repeat Start" "Not repeated,Repeated"
|
|
bitfld.word 0x00 8. " TDC_EN ,Transmit Data Counter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--7. 1. " TDC ,Transmit Data Counter"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "HIRDCR,HS_I2C Rx Data Count Register"
|
|
bitfld.word 0x00 9. " RDC_RSTA ,Receive Data Count Repeat Start" "Not repeated,Repeated"
|
|
bitfld.word 0x00 8. " RDC_EN ,Receive Data Counter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--7. 1. " RDC ,Receive Data Counter"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "I2C (Inter IC)"
|
|
tree "I2C1"
|
|
base ad:0x83fc8000
|
|
width 6.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "IADR,I2C Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " ADR ,Slave Address"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IFDR,I2C Frequency Divider Register"
|
|
bitfld.word 0x00 0.--5. " IC ,I2C Clock Rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2CR,I2C Control Register"
|
|
bitfld.word 0x00 7. " IEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IIEN ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MSTA ,Master/Slave Mode Select" "Slave,Master"
|
|
bitfld.word 0x00 4. " MTX ,Transmit/Receive Mode Select bit" "Receive,Transmit"
|
|
bitfld.word 0x00 3. " TXAK ,Transmit Acknowledge Enable" "ACK,NACK"
|
|
bitfld.word 0x00 2. " RSTA ,Repeat Start" "No effect,Repeat"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2SR,I2C Status Register"
|
|
rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed"
|
|
rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed"
|
|
rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy"
|
|
bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost"
|
|
rbitfld.word 0x00 2. " SRW ,Slave read/write" "Read,Write"
|
|
bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,NACK"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "I2DR,I2C Data I/O Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data Byte"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x83fc4000
|
|
width 6.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "IADR,I2C Address Register"
|
|
hexmask.word.byte 0x00 1.--7. 0x2 " ADR ,Slave Address"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "IFDR,I2C Frequency Divider Register"
|
|
bitfld.word 0x00 0.--5. " IC ,I2C Clock Rate" "30,32,36,42,48,52,60,72,80,88,104,128,144,160,192,240,288,320,384,480,576,640,768,960,1152,1280,1536,1920,2304,2560,3072,3840,22,24,26,28,32,36,40,44,48,56,64,72,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896,1024,1280,1536,1792,2048"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2CR,I2C Control Register"
|
|
bitfld.word 0x00 7. " IEN ,I2C Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " IIEN ,I2C Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " MSTA ,Master/Slave Mode Select" "Slave,Master"
|
|
bitfld.word 0x00 4. " MTX ,Transmit/Receive Mode Select bit" "Receive,Transmit"
|
|
bitfld.word 0x00 3. " TXAK ,Transmit Acknowledge Enable" "ACK,NACK"
|
|
bitfld.word 0x00 2. " RSTA ,Repeat Start" "No effect,Repeat"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "I2SR,I2C Status Register"
|
|
rbitfld.word 0x00 7. " ICF ,Data transferring bit" "In progress,Completed"
|
|
rbitfld.word 0x00 6. " IAAS ,I2C addressed as a slave bit" "Not addressed,Addressed"
|
|
rbitfld.word 0x00 5. " IBB ,I2C bus busy bit" "Idle,Busy"
|
|
bitfld.word 0x00 4. " IAL ,Arbitration lost" "Not lost,Lost"
|
|
rbitfld.word 0x00 2. " SRW ,Slave read/write" "Read,Write"
|
|
bitfld.word 0x00 1. " IIF ,I2C interrupt" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 0. " RXAK ,Received acknowledge" "ACK,NACK"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "I2DR,I2C Data I/O Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DATA ,Data Byte"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "IIM (IC Identification)"
|
|
base ad:0x83f98000
|
|
width 7.
|
|
tree "Common Registers"
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "STAT,Status Register"
|
|
bitfld.byte 0x00 7. " BUSY ,IIM busy" "Not busy,Busy"
|
|
eventfld.byte 0x00 1. " PRGD ,Program Done" "Not finished,Finished"
|
|
textline " "
|
|
eventfld.byte 0x00 0. " SNSD ,Explicit Sense Cycle Done" "Not finished,Finished"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "STATM,Status IRQ Mask Register"
|
|
bitfld.byte 0x00 1. " PRGD_M ,Program Done Mask" "Masked,Not masked"
|
|
bitfld.byte 0x00 0. " SNSD_M ,Explcitly Sense Cycle Mask" "Masked,Not masked"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "ERR,Module Errors Register"
|
|
eventfld.byte 0x00 7. " PRGE ,Program Error" "No error,Error"
|
|
eventfld.byte 0x00 6. " WPE ,Write Protect Error" "No error,Error"
|
|
textline " "
|
|
eventfld.byte 0x00 5. " OPE ,Override Protect Error" "No error,Error"
|
|
eventfld.byte 0x00 4. " RPE ,Read Protect Error" "No error,Error"
|
|
textline " "
|
|
eventfld.byte 0x00 3. " WLRE ,Write to Locked Register Error" "No error,Error"
|
|
eventfld.byte 0x00 2. " SNSE ,Explicit Sense Cycle Error" "No error,Error"
|
|
textline " "
|
|
eventfld.byte 0x00 1. " PARITYE ,Parity Error of cache" "No error,Error"
|
|
group.byte 0x0c++0x00
|
|
line.byte 0x00 "EMASK,Error IRQ Mask Register"
|
|
bitfld.byte 0x00 7. " PRGE_M ,Program Error Mask" "Masked,Not masked"
|
|
bitfld.byte 0x00 6. " WPE_M ,Write Protect Error Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " OPE_M ,Override Protect Error Mask" "Masked,Not masked"
|
|
bitfld.byte 0x00 4. " RPE_M ,Read Protect Error Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " WLRE_M ,Write to Locked Register Error Mask" "Masked,Not masked"
|
|
bitfld.byte 0x00 2. " SNSE_M ,Explicit Sense Cycle Error Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " PARITYE_M ,Parity Error of Cache Mask" "Masked,Not masked"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "FCTL,Fuse Control Register"
|
|
bitfld.byte 0x00 7. " DPC ,Delayed Program Cycle" "Not delayed,Delayed"
|
|
bitfld.byte 0x00 4.--6. " PRG_LENGTH ,Program Length" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ESNS_N ,Explicit Sense Normal" "Normal,Initiated"
|
|
bitfld.byte 0x00 2. " ESNS_0 ,Explicit Sense 0-stressed" "Normal,Initiated"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ESNS_1 ,Explicit Sense 1-stressed" "Normal,Initiated"
|
|
bitfld.byte 0x00 0. " PRG ,Program" "Normal,Initiated"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "UA,Upper Address"
|
|
hexmask.byte 0x00 0.--5. 1. " A[13:8] ,Top six bits of address"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "LA,Lower Address"
|
|
hexmask.byte 0x00 0.--7. 1. " A[7:0] ,Bottom bits of address"
|
|
rgroup.byte 0x1c++0x00
|
|
line.byte 0x00 "SDAT,Explicit Sense Data Register"
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "PREV,Product Revision Register"
|
|
hexmask.byte 0x00 3.--7. 1. " PROD_REV ,Product Revision"
|
|
hexmask.byte 0x00 0.--2. 1. " PROD_VT ,Product vendor or technology"
|
|
rgroup.byte 0x24++0x00
|
|
line.byte 0x00 "SREV,Silicon Revision Register"
|
|
hexmask.byte 0x00 0.--7. 1. " SILICON_REV ,Mask Set Revision"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "PRG_P,Program Protection Register"
|
|
group.byte 0x2c++0x00
|
|
line.byte 0x00 "SCS0,Software-Controllable Signals Register 0"
|
|
bitfld.byte 0x00 7. " LOCK ,Register Lock" "Not locked,Locked"
|
|
bitfld.byte 0x00 6. " HAB_JDE ,HAB JTAG Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.byte 0x00 0.--5. 1. " SCS[26:21] ,These bits may be used in an implementation-defined way"
|
|
sif ((cpu()!="IMX53")&&(cpu()!="IMX534")&&(cpu()!="IMX535")&&(cpu()!="IMX536")&&(cpu()!="IMX537")&&(cpu()!="IMX538"))
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "SCS1,Software-Controllable Signals Register 1"
|
|
bitfld.byte 0x00 7. " LOCK ,Register Lock" "Not locked,Locked"
|
|
hexmask.byte 0x00 1.--6. 1. " SCS[20:14] ,These bits may be used in an implementation-defined way"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " LPB_ENABLED_STATUS ,LPB Enabled Status" "No LPB,LPB"
|
|
endif
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "SCS2,Software-Controllable Signals Register 2"
|
|
bitfld.byte 0x00 7. " LOCK ,Register Lock" "Not locked,Locked"
|
|
sif ((cpu()=="IMX53")||(cpu()=="IMX534")||(cpu()=="IMX535")||(cpu()=="IMX536")||(cpu()=="IMX537")||(cpu()=="IMX538"))
|
|
bitfld.byte 0x00 4. " FBRL4 ,Read lock for fuse bank #4" "Not locked,Locked"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FBRL3 ,Read lock for fuse bank #3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FBRL2 ,Read lock for fuse bank #2" "Not locked,Locked"
|
|
bitfld.byte 0x00 1. " FBRL1 ,Read lock for fuse bank #1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FBRL0 ,Read lock for fuse bank #0" "Not locked,Locked"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "SCS3,Software-Controllable Signals Register 3"
|
|
bitfld.byte 0x00 7. " LOCK ,Register Lock" "Not locked,Locked"
|
|
sif ((cpu()=="IMX53")||(cpu()=="IMX534")||(cpu()=="IMX535")||(cpu()=="IMX536")||(cpu()=="IMX537")||(cpu()=="iMX538"))
|
|
bitfld.byte 0x00 4. " FBWL4 ,Write lock for fuse bank #4" "Not locked,Locked"
|
|
endif
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FBWL3 ,Write lock for fuse bank #3" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " FBWL2 ,Write lock for fuse bank #2" "Not locked,Locked"
|
|
bitfld.byte 0x00 1. " FBWL1 ,Write lock for fuse bank #1" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FBWL0 ,Write lock for fuse bank #0" "Not locked,Locked"
|
|
width 11.
|
|
group.byte 0x3c++0x00
|
|
line.byte 0x00 "SAHARAEN0,Sahara Enable 0"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "SAHARAEN1,Sahara Enable 1"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "SAHARAEN2,Sahara Enable 2"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "SAHARAEN3,Sahara Enable 3"
|
|
group.byte 0x4c++0x00
|
|
line.byte 0x00 "SAHARAEN4,Sahara Enable 4"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "SAHARAEN5,Sahara Enable 5"
|
|
tree.end
|
|
tree "Fuse Bank 0"
|
|
width 15.
|
|
group.byte 0x800++0x00
|
|
line.byte 0x00 "FBAC0,Fuse Bank 0 Access Protection Register"
|
|
bitfld.byte 0x00 7. " FBWP ,Fuse Bank Write Protect" "Not protected,Protected"
|
|
bitfld.byte 0x00 6. " FBOP ,Fuse Bank Override Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FBRP ,Fuse Bank Read Protect" "Not protected,Protected"
|
|
bitfld.byte 0x00 3. " FBESP ,Fuse Banks Explicit Sense Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " IMEI_LOCK ,Locking rows 0860-087c" "Unlocked,Locked"
|
|
bitfld.byte 0x00 0. " BOOT_LOCK ,Locking rows 0804/080C-0818/0840-0844/0854" "Unlocked,Locked"
|
|
group.byte 0x804++0x00
|
|
line.byte 0x00 "JAC,JTAG Access Control Register"
|
|
bitfld.byte 0x00 7. " OSC_FREQ_SEL[1] ,Oscillator frequency select [1]" "0,1"
|
|
bitfld.byte 0x00 5.--6. " JTAG_SMODE ,JTAG Security Mode" "JTAG enabled,Secure JTAG,Reserved,No debug"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " OSC_FREQ_SEL[0] ,Oscillator frequency select [0]" "0,1"
|
|
bitfld.byte 0x00 3. " JTAG_HEO ,JTAG HAB Enable Override" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " KTE ,Kill Trace Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SEC_JTAG_RE ,Secure JTAG Re-enable" "Not overridden,Overridden"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " JTAG_BP ,JTAG Debug Security Bypass" "Not active,Active"
|
|
if (((per.l(ad:0x83f98000+0x814)&0x6)==0x6)&&((per.l(ad:0x83f98000+0x814)&0x30)==0x0))
|
|
; BT_MEM_CTL[1:0] = Expansion Card && BT_MEM_TYPE = 00
|
|
group.byte 0x80c++0x00
|
|
line.byte 0x00 "BTMSEL0,Boot modes selection register 0"
|
|
bitfld.byte 0x00 6.--7. " BT_SRC[1:0] ,Chooses specific eSDHC controller for booting from" "eSDHC-1,eSDHC-2,eSDHC-3,eSDHC-4"
|
|
bitfld.byte 0x00 5. " BT_MLC_SEL ,FAST BOOT enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BT_SPARE_SIZE ,'Fast boot' mode indication for use with eSD 2.10 protocol devices" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " BT_DPLUS_BYPASS ,Bypassing a pullup on D+ line in case of LPB" "Pullup,No pullup"
|
|
bitfld.byte 0x00 0. " BT_USB_SRC ,USB boot source selection" "Internal PHY(UTMI),External PHY(ULPI)"
|
|
elif (((per.l(ad:0x83f98000+0x814)&0x6)==0x6)&&((per.l(ad:0x83f98000+0x814)&0x30)==0x20))
|
|
; BT_MEM_CTL[1:0] = Expansion Card && BT_MEM_TYPE = 10
|
|
group.byte 0x80c++0x00
|
|
line.byte 0x00 "BTMSEL0,Boot modes selection register 0"
|
|
bitfld.byte 0x00 6.--7. " BT_SRC[1:0] ,Chooses specific I2C controller for booting from" "I2C-1,I2C-2,HS-I2C,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BT_SPARE_SIZE ,'Fast boot' mode indication for use with eSD 2.10 protocol devices" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " BT_DPLUS_BYPASS ,Bypassing a pullup on D+ line in case of LPB" "Pullup,No pullup"
|
|
bitfld.byte 0x00 0. " BT_USB_SRC ,USB boot source selection" "Internal PHY(UTMI),External PHY(ULPI)"
|
|
elif (((per.l(ad:0x83f98000+0x814)&0x6)==0x6)&&((per.l(ad:0x83f98000+0x814)&0x30)==0x30))
|
|
; BT_MEM_CTL[1:0] = Expansion Card && BT_MEM_TYPE = 11
|
|
group.byte 0x80c++0x00
|
|
line.byte 0x00 "BTMSEL0,Boot modes selection register 0"
|
|
bitfld.byte 0x00 6.--7. " BT_SRC[1:0] ,Chooses specific eSDHC/CSPI/I2C controller for booting from" "eCSPI1,eCSPI2,CSPI,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BT_SPARE_SIZE ,'Fast boot' mode indication for use with eSD 2.10 protocol devices" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " BT_DPLUS_BYPASS ,Bypassing a pullup on D+ line in case of LPB" "Pullup,No pullup"
|
|
bitfld.byte 0x00 0. " BT_USB_SRC ,USB boot source selection" "Internal PHY(UTMI),External PHY(ULPI)"
|
|
elif (((per.l(ad:0x83f98000+0x814)&0x6)==0x6)&&((per.l(ad:0x83f98000+0x814)&0x30)==0x10))
|
|
; BT_MEM_CTL[1:0] = Expansion Card && BT_MEM_TYPE = 01
|
|
group.byte 0x80c++0x00
|
|
line.byte 0x00 "BTMSEL0,Boot modes selection register 0"
|
|
bitfld.byte 0x00 5. " BT_MLC_SEL ,FAST BOOT enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BT_SPARE_SIZE ,'Fast boot' mode indication for use with eSD 2.10 protocol devices" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " BT_DPLUS_BYPASS ,Bypassing a pullup on D+ line in case of LPB" "Pullup,No pullup"
|
|
bitfld.byte 0x00 0. " BT_USB_SRC ,USB boot source selection" "Internal PHY(UTMI),External PHY(ULPI)"
|
|
elif ((per.l(ad:0x83f98000+0x814)&0x6)==0x2)
|
|
; BT_MEM_CTL[1:0] = NAND
|
|
group.byte 0x80c++0x00
|
|
line.byte 0x00 "BTMSEL0,Boot modes selection register 0"
|
|
bitfld.byte 0x00 5. " BT_MLC_SEL ,SLC/MLC NAND device select" "SLC,MLC"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BT_SPARE_SIZE ,Size of spare bytes for 4Kbyte page size NAND Flash devices" "128 bytes spare(Samsung),218 bytes spare(Micron/Toshiba)"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " BT_DPLUS_BYPASS ,Bypassing a pullup on D+ line in case of LPB" "Pullup,No pullup"
|
|
bitfld.byte 0x00 0. " BT_USB_SRC ,USB boot source selection" "Internal PHY(UTMI),External PHY(ULPI)"
|
|
else
|
|
;elif ((per.l(ad:0x83f98000+0x814)&0x6)==0x0)
|
|
; BT_MEM_CTL[1:0] = WEIM
|
|
group.byte 0x80c++0x00
|
|
line.byte 0x00 "BTMSEL0,Boot modes selection register 0"
|
|
bitfld.byte 0x00 1. " BT_DPLUS_BYPASS ,Bypassing a pullup on D+ line in case of LPB" "Pullup,No pullup"
|
|
bitfld.byte 0x00 0. " BT_USB_SRC ,USB boot source selection" "Internal PHY(UTMI),External PHY(ULPI)"
|
|
endif
|
|
group.byte 0x810++0x00
|
|
line.byte 0x00 "BTMSEL1,Boot modes selection register 1"
|
|
bitfld.byte 0x00 7. " BT_UNPROGRAMMED ,Indicates that the boot area has not yet been burned" "Unprogrammed,Programmed"
|
|
bitfld.byte 0x00 5.--6. " BT_PAGE_SIZE[1:0] ,NAND Flash Page Size" "1/2K,2K,4K,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " BT_EEPROM_CFG ,EEPROM DCD boot" "Used,Not used"
|
|
bitfld.byte 0x00 3. " GPIO_BT_SEL ,GPIO Boot Select" "By GPIO,By IIM"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--2. " HAB_TYPE[2:0] ,Security Type " "On,Engineering,On,Off,On,On,On,On"
|
|
if ((per.l(ad:0x83f98000+0x814)&0x6)==0x0)
|
|
; BT_MEM_CTL[1:0] = WEIM
|
|
group.byte 0x814++0x00
|
|
line.byte 0x00 "BTMSEL2,Boot modes selection register 2"
|
|
bitfld.byte 0x00 6.--7. " BT_UART_SRC[1:0] ,Chooses specific UART controller for booting from" "UART1,UART2,UART3,?..."
|
|
bitfld.byte 0x00 4.--5. " BT_MEM_TYPE[1:0] ,Boot Memory Type" "NOR,Reserved,OneNand,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 3. " BT_BUS_WIDTH ,WEIM Bus Width" "16-bit,32-bit"
|
|
bitfld.byte 0x00 1.--2. " BT_MEM_CTL[1:0] ,Boot Memory Control Type" "WEIM,NAND Flash,Reserved,SD/MMC"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DIR_BT_DIS ,Direct External Memory Boot Disable" "No,Yes"
|
|
elif ((per.l(ad:0x83f98000+0x814)&0x6)==0x2)
|
|
; BT_MEM_CTL[1:0] = NAND
|
|
group.byte 0x814++0x00
|
|
line.byte 0x00 "BTMSEL2,Boot modes selection register 2"
|
|
bitfld.byte 0x00 6.--7. " BT_UART_SRC[1:0] ,Chooses specific UART controller for booting from" "UART1,UART2,UART3,?..."
|
|
bitfld.byte 0x00 4.--5. " BT_MEM_TYPE[1:0] ,Boot Memory Type" "3 address cycles,4 address cycles,5 address cycles,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 3. " BT_BUS_WIDTH ,NAND/NOR Bus Width" "8-bit,16-bit"
|
|
bitfld.byte 0x00 1.--2. " BT_MEM_CTL[1:0] ,Boot Memory Control Type" "WEIM,NAND Flash,Reserved,SD/MMC"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DIR_BT_DIS ,Direct External Memory Boot Disable" "No,Yes"
|
|
elif ((per.l(ad:0x83f98000+0x814)&0x6)==0x6)
|
|
; BT_MEM_CTL[1:0] = Expansion Device
|
|
group.byte 0x814++0x00
|
|
line.byte 0x00 "BTMSEL2,Boot modes selection register 2"
|
|
bitfld.byte 0x00 6.--7. " BT_UART_SRC[1:0] ,Chooses specific UART controller for booting from" "UART1,UART2,UART3,?..."
|
|
bitfld.byte 0x00 4.--5. " BT_MEM_TYPE[1:0] ,Boot Memory Type" "SD/MMC/eMMC/eSD,Reserved,Serial ROM via I2C,Serial ROM via SPI"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " BT_BUS_WIDTH ,SD/MMC Bus Width" "16-bit,24-bit"
|
|
bitfld.byte 0x00 1.--2. " BT_MEM_CTL[1:0] ,Boot Memory Control Type" "WEIM,NAND Flash,Reserved,SD/MMC"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DIR_BT_DIS ,Direct External Memory Boot Disable" "No,Yes"
|
|
else
|
|
group.byte 0x814++0x00
|
|
line.byte 0x00 "BTMSEL2,Boot modes selection register 2"
|
|
bitfld.byte 0x00 6.--7. " BT_UART_SRC[1:0] ,Chooses specific UART controller for booting from" "UART1,UART2,UART3,?..."
|
|
bitfld.byte 0x00 1.--2. " BT_MEM_CTL[1:0] ,Boot Memory Control Type" "WEIM,NAND Flash,Reserved,SD/MMC"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DIR_BT_DIS ,Direct External Memory Boot Disable" "No,Yes"
|
|
endif
|
|
group.byte 0x818++0x00
|
|
line.byte 0x00 "HAB_CUS,HAB Customer Code register"
|
|
group.byte 0x840++0x00
|
|
line.byte 0x00 "FB0REG0,Fuse Bank 0 Register 0"
|
|
bitfld.byte 0x00 5.--7. " SRTC_MCOUNT[2:0] ,SRTC counter mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " CMD_DEFAULT ,Default Command" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BT_LPB[1:0] ,Options for Low-Power Boot Mode" "LPBM disabled,Generic PMIC/one GPIO,Generic PMIC/two GPIO,Atlas AP PMIC"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " SRTC_SECMOD[1:0] ,Security Mode for Secure RTC" "Low,Medium,High,?..."
|
|
group.byte 0x844++0x00
|
|
line.byte 0x00 "FB0REG1,Fuse Bank 0 Register 1"
|
|
bitfld.byte 0x00 5.--7. " BT_LPB_FREQ[2:0] ,Low-Power Boot Mode ARM core frequency" "192 MHz,133 Mhz,55.33 MHz,200 MHz,220 MHz,166 MHz,266 MHz,400 MHz"
|
|
bitfld.byte 0x00 3.--4. " CSU_FA_OUT[1:0] ,CSU_FA_OUT[1:0]" "0,1,2,3"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--2. " CSU_AM_DIS[1:0] ,CSU_AM_DIS[1:0]" "0,1,2,3"
|
|
bitfld.byte 0x00 0. " CSU_FA_COUNT ,CSU_FA_COUNT" "0,1"
|
|
group.byte 0x848++0x00
|
|
line.byte 0x00 "AP_BI_VER1,AP_BI_VER Register 1"
|
|
hexmask.byte 0x00 0.--7. 1. " AP_BI_VER[15:8] ,AP_BI_VER[15:8]"
|
|
group.byte 0x84c++0x00
|
|
line.byte 0x00 "AP_BI_VER0,AP_BI_VER Register 0"
|
|
hexmask.byte 0x00 0.--7. 1. " AP_BI_VER[7:0] ,AP_BI_VER[7:0]"
|
|
group.byte 0x854++0x00
|
|
line.byte 0x00 "SJCDIS,Secure Controller Disable register"
|
|
bitfld.byte 0x00 6. " SJC_DISABLE ,SJC disable" "No,Yes"
|
|
group.byte 0x860++0x00
|
|
line.byte 0x00 "IMEI7,IMEI Register 7"
|
|
hexmask.byte 0x00 0.--7. 1. " IMEI[63:56] ,IMEI[63:56]"
|
|
group.byte 0x864++0x00
|
|
line.byte 0x00 "IMEI6,IMEI Register 6"
|
|
hexmask.byte 0x00 0.--7. 1. " IMEI[55:48] ,IMEI[55:48]"
|
|
group.byte 0x868++0x00
|
|
line.byte 0x00 "IMEI5,IMEI Register 5"
|
|
hexmask.byte 0x00 0.--7. 1. " IMEI[47:40] ,IMEI[47:40]"
|
|
group.byte 0x86C++0x00
|
|
line.byte 0x00 "IMEI4,IMEI Register 4"
|
|
hexmask.byte 0x00 0.--7. 1. " IMEI[39:32] ,IMEI[39:32]"
|
|
group.byte 0x870++0x00
|
|
line.byte 0x00 "IMEI3,IMEI Register 3"
|
|
hexmask.byte 0x00 0.--7. 1. " IMEI[31:24] ,IMEI[31:24]"
|
|
group.byte 0x874++0x00
|
|
line.byte 0x00 "IMEI2,IMEI Register 2"
|
|
hexmask.byte 0x00 0.--7. 1. " IMEI[23:16] ,IMEI[23:16]"
|
|
group.byte 0x878++0x00
|
|
line.byte 0x00 "IMEI1,IMEI Register 1"
|
|
hexmask.byte 0x00 0.--7. 1. " IMEI[15:8] ,IMEI[15:8]"
|
|
group.byte 0x87C++0x00
|
|
line.byte 0x00 "IMEI0,IMEI Register 0"
|
|
hexmask.byte 0x00 0.--7. 1. " IMEI[7:0] ,IMEI[7:0]"
|
|
tree "Freescale Internal Use Registers"
|
|
hgroup.byte 0x808++0x00
|
|
hide.byte 0x00 "FB0_INT_USE0,Fuse Bank 0 Freescale Internal Use 0"
|
|
hgroup.byte 0x81C++0x00
|
|
hide.byte 0x00 "FB0_INT_USE1,Fuse Bank 0 Freescale Internal Use 1"
|
|
hgroup.byte 0x820++0x00
|
|
hide.byte 0x00 "FB0_INT_USE2,Fuse Bank 0 Freescale Internal Use 2"
|
|
hgroup.byte 0x824++0x00
|
|
hide.byte 0x00 "FB0_INT_USE3,Fuse Bank 0 Freescale Internal Use 3"
|
|
hgroup.byte 0x828++0x00
|
|
hide.byte 0x00 "FB0_INT_USE4,Fuse Bank 0 Freescale Internal Use 4"
|
|
hgroup.byte 0x82C++0x00
|
|
hide.byte 0x00 "FB0_INT_USE5,Fuse Bank 0 Freescale Internal Use 5"
|
|
hgroup.byte 0x830++0x00
|
|
hide.byte 0x00 "FB0_INT_USE6,Fuse Bank 0 Freescale Internal Use 6"
|
|
hgroup.byte 0x834++0x00
|
|
hide.byte 0x00 "FB0_INT_USE7,Fuse Bank 0 Freescale Internal Use 7"
|
|
hgroup.byte 0x838++0x00
|
|
hide.byte 0x00 "FB0_INT_USE8,Fuse Bank 0 Freescale Internal Use 8"
|
|
hgroup.byte 0x83C++0x00
|
|
hide.byte 0x00 "FB0_INT_USE9,Fuse Bank 0 Freescale Internal Use 9"
|
|
hgroup.byte 0x850++0x00
|
|
hide.byte 0x00 "FB0_INT_USE10,Fuse Bank 0 Freescale Internal Use 10"
|
|
hgroup.byte 0x858++0x00
|
|
hide.byte 0x00 "FB0_INT_USE11,Fuse Bank 0 Freescale Internal Use 11"
|
|
hgroup.byte 0x85c++0x00
|
|
hide.byte 0x00 "FB0_INT_USE12,Fuse Bank 0 Freescale Internal Use 12"
|
|
tree.end
|
|
tree.end
|
|
tree "Fuse Bank 1"
|
|
width 19.
|
|
group.byte 0xc00++0x00
|
|
line.byte 0x00 "FBAC1,Fuse Bank Access Control 1"
|
|
bitfld.byte 0x00 7. " FBWP ,Fuse Bank Write Protect" "Not protected,Protected"
|
|
bitfld.byte 0x00 6. " FBOP ,Fuse Bank Override Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FBRP ,Fuse Bank Read Protect" "Not protected,Protected"
|
|
bitfld.byte 0x00 4. " FBSP ,Fuse Bank Scan Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FBESP ,Explicit sense by software" "Sensed,Not sensed"
|
|
bitfld.byte 0x00 2. " SRK_LOCK ,Locking row 0C04" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " SJC_RESP_LOCK ,Locking rows 0C08-0C20" "Unlocked,Locked"
|
|
bitfld.byte 0x00 0. " SCC_LOCK ,SCC lock" "Unlocked,Locked"
|
|
group.byte 0xc04++0x00
|
|
line.byte 0x00 "SRK_HASH31,SRK_HASH Register 31"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[255:248] ,Most significant byte of 256-bit hash value of super root key [255:248]"
|
|
group.byte 0xC08++0x00
|
|
line.byte 0x00 "SJC_RESP6,SJC_RESP Register 6"
|
|
hexmask.byte 0x00 0.--7. 1. " SJC_RESP[55:48] ,SJC_RESP[55:48]"
|
|
group.byte 0xC0C++0x00
|
|
line.byte 0x00 "SJC_RESP5,SJC_RESP Register 5"
|
|
hexmask.byte 0x00 0.--7. 1. " SJC_RESP[47:40] ,SJC_RESP[47:40]"
|
|
group.byte 0xC10++0x00
|
|
line.byte 0x00 "SJC_RESP4,SJC_RESP Register 4"
|
|
hexmask.byte 0x00 0.--7. 1. " SJC_RESP[39:32] ,SJC_RESP[39:32]"
|
|
group.byte 0xC14++0x00
|
|
line.byte 0x00 "SJC_RESP3,SJC_RESP Register 3"
|
|
hexmask.byte 0x00 0.--7. 1. " SJC_RESP[31:24] ,SJC_RESP[31:24]"
|
|
group.byte 0xC18++0x00
|
|
line.byte 0x00 "SJC_RESP2,SJC_RESP Register 2"
|
|
hexmask.byte 0x00 0.--7. 1. " SJC_RESP[23:16] ,SJC_RESP[23:16]"
|
|
group.byte 0xC1C++0x00
|
|
line.byte 0x00 "SJC_RESP1,SJC_RESP Register 1"
|
|
hexmask.byte 0x00 0.--7. 1. " SJC_RESP[15:8] ,SJC_RESP[15:8]"
|
|
group.byte 0xC20++0x00
|
|
line.byte 0x00 "SJC_RESP0,SJC_RESP Register 0"
|
|
hexmask.byte 0x00 0.--7. 1. " SJC_RESP[7:0] ,SJC_RESP[7:0]"
|
|
group.byte 0xC24++0x00
|
|
line.byte 0x00 "MAC_ADDR5,MAC_ADDR Register 5"
|
|
hexmask.byte 0x00 0.--7. 1. " MAC_ADDR[47:40] ,MAC_ADDR[47:40]"
|
|
group.byte 0xC28++0x00
|
|
line.byte 0x00 "MAC_ADDR4,MAC_ADDR Register 4"
|
|
hexmask.byte 0x00 0.--7. 1. " MAC_ADDR[39:32] ,MAC_ADDR[39:32]"
|
|
group.byte 0xC2C++0x00
|
|
line.byte 0x00 "MAC_ADDR3,MAC_ADDR Register 3"
|
|
hexmask.byte 0x00 0.--7. 1. " MAC_ADDR[31:24] ,MAC_ADDR[31:24]"
|
|
group.byte 0xC30++0x00
|
|
line.byte 0x00 "MAC_ADDR2,MAC_ADDR Register 2"
|
|
hexmask.byte 0x00 0.--7. 1. " MAC_ADDR[23:16] ,MAC_ADDR[23:16]"
|
|
group.byte 0xC34++0x00
|
|
line.byte 0x00 "MAC_ADDR1,MAC_ADDR Register 1"
|
|
hexmask.byte 0x00 0.--7. 1. " MAC_ADDR[15:8] ,MAC_ADDR[15:8]"
|
|
group.byte 0xC38++0x00
|
|
line.byte 0x00 "MAC_ADDR0,MAC_ADDR Register 0"
|
|
hexmask.byte 0x00 0.--7. 1. " MAC_ADDR[7:0] ,MAC_ADDR[7:0]"
|
|
group.byte 0xC3C++0x00
|
|
line.byte 0x00 "TVDAC_GAIN1,TVDAC_GAIN Register 1"
|
|
hexmask.byte 0x00 0.--5. 1. " TVDAC_GAIN1[5:0] ,TVDAC_GAIN1[5:0]"
|
|
group.byte 0xC40++0x00
|
|
line.byte 0x00 "TVDAC_GAIN2,TVDAC_GAIN Register 2"
|
|
hexmask.byte 0x00 0.--5. 1. " TVDAC_GAIN2[5:0] ,TVDAC_GAIN2[5:0]"
|
|
group.byte 0xC44++0x00
|
|
line.byte 0x00 "TVDAC_GAIN3,TVDAC_GAIN Register 3"
|
|
hexmask.byte 0x00 0.--5. 1. " TVDAC_GAIN3[5:0] ,TVDAC_GAIN3[5:0]"
|
|
group.byte 0xc48++0x00
|
|
line.byte 0x00 "PTCREG0,PTC Register 0"
|
|
bitfld.byte 0x00 5.--7. " PTC_VER[2:0] ,PTC version" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 4. " GDPTCV_VALID ,GDPTCV_VALID" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " GDPTCV[3:0] ,GDPTCV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xc4c++0x00
|
|
line.byte 0x00 "PTCREG1,PTC Register 1"
|
|
bitfld.byte 0x00 7. " MMU_EN ,Memory Management Unit enable" "Disable,Enable"
|
|
bitfld.byte 0x00 4. " LDPTCV_VALID ,LDPTCV_VALID" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " LDPTCV[3:0] ,LDPTCV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0xc50++0x00
|
|
line.byte 0x00 "DVFS_DELAY_ADJUST,DVFS Delay Adjustment Register"
|
|
hexmask.byte 0x00 0.--7. 1. " DVFS_DELAY_ADJUST[7:0] ,DVFS_DELAY_ADJUST[7:0]"
|
|
group.byte 0xc54++0x00
|
|
line.byte 0x00 "FB1REG0,Fuse Bank 1 Register 0"
|
|
bitfld.byte 0x00 3.--5. " l1d_tch[2:0] ,l1d_tch[2:0]" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--3. " l1d_tcs[2:0] ,l1d_tcs[2:0]" "0,1,2,3,4,5,6,7,?..."
|
|
group.byte 0xc54++0x00
|
|
line.byte 0x00 "FB1REG1,Fuse Bank 1 Register 1"
|
|
bitfld.byte 0x00 6.--7. " tlb_tc[1:0] ,tlb_tc[1:0]" "0,1,2,3"
|
|
bitfld.byte 0x00 3.--5. " l1i_tch[2:0] ,l1i_tch[2:0]" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--3. " l1i_tcs[2:0] ,l1i_tcs[2:0]" "0,1,2,3,4,5,6,7,?..."
|
|
tree "Freescale Internal Use Registers"
|
|
hgroup.byte 0xC5C++0x00
|
|
hide.byte 0x00 "FB1_INT_USE0,Fuse Bank 1 Freescale Internal Use 0"
|
|
hgroup.byte 0xC60++0x00
|
|
hide.byte 0x00 "FB1_INT_USE1,Fuse Bank 1 Freescale Internal Use 1"
|
|
hgroup.byte 0xC64++0x00
|
|
hide.byte 0x00 "FB1_INT_USE2,Fuse Bank 1 Freescale Internal Use 2"
|
|
hgroup.byte 0xC68++0x00
|
|
hide.byte 0x00 "FB1_INT_USE3,Fuse Bank 1 Freescale Internal Use 3"
|
|
hgroup.byte 0xC6C++0x00
|
|
hide.byte 0x00 "FB1_INT_USE4,Fuse Bank 1 Freescale Internal Use 4"
|
|
hgroup.byte 0xC70++0x00
|
|
hide.byte 0x00 "FB1_INT_USE5,Fuse Bank 1 Freescale Internal Use 5"
|
|
hgroup.byte 0xC74++0x00
|
|
hide.byte 0x00 "FB1_INT_USE6,Fuse Bank 1 Freescale Internal Use 6"
|
|
hgroup.byte 0xC78++0x00
|
|
hide.byte 0x00 "FB1_INT_USE7,Fuse Bank 1 Freescale Internal Use 7"
|
|
hgroup.byte 0xC7C++0x00
|
|
hide.byte 0x00 "FB1_INT_USE8,Fuse Bank 1 Freescale Internal Use 8"
|
|
tree.end
|
|
tree.end
|
|
tree "Fuse Bank 2"
|
|
width 15.
|
|
hgroup.byte 0x1000++0x00
|
|
hide.byte 0x00 "FB2_INT_USE1,Fuse Bank 2 Freescale Internal Use 1"
|
|
hgroup.byte 0x1004++0x00
|
|
hide.byte 0x00 "FB2_INT_USE2,Fuse Bank 2 Freescale Internal Use 2"
|
|
hgroup.byte 0x1008++0x00
|
|
hide.byte 0x00 "FB2_INT_USE3,Fuse Bank 2 Freescale Internal Use 3"
|
|
hgroup.byte 0x100C++0x00
|
|
hide.byte 0x00 "FB2_INT_USE4,Fuse Bank 2 Freescale Internal Use 4"
|
|
hgroup.byte 0x1010++0x00
|
|
hide.byte 0x00 "FB2_INT_USE5,Fuse Bank 2 Freescale Internal Use 5"
|
|
hgroup.byte 0x1014++0x00
|
|
hide.byte 0x00 "FB2_INT_USE6,Fuse Bank 2 Freescale Internal Use 6"
|
|
hgroup.byte 0x1018++0x00
|
|
hide.byte 0x00 "FB2_INT_USE7,Fuse Bank 2 Freescale Internal Use 7"
|
|
hgroup.byte 0x101C++0x00
|
|
hide.byte 0x00 "FB2_INT_USE8,Fuse Bank 2 Freescale Internal Use 8"
|
|
hgroup.byte 0x1020++0x00
|
|
hide.byte 0x00 "FB2_INT_USE9,Fuse Bank 2 Freescale Internal Use 9"
|
|
hgroup.byte 0x1024++0x00
|
|
hide.byte 0x00 "FB2_INT_USE10,Fuse Bank 2 Freescale Internal Use 10"
|
|
hgroup.byte 0x1028++0x00
|
|
hide.byte 0x00 "FB2_INT_USE11,Fuse Bank 2 Freescale Internal Use 11"
|
|
hgroup.byte 0x102C++0x00
|
|
hide.byte 0x00 "FB2_INT_USE12,Fuse Bank 2 Freescale Internal Use 12"
|
|
hgroup.byte 0x1030++0x00
|
|
hide.byte 0x00 "FB2_INT_USE13,Fuse Bank 2 Freescale Internal Use 13"
|
|
hgroup.byte 0x1034++0x00
|
|
hide.byte 0x00 "FB2_INT_USE14,Fuse Bank 2 Freescale Internal Use 14"
|
|
hgroup.byte 0x1038++0x00
|
|
hide.byte 0x00 "FB2_INT_USE15,Fuse Bank 2 Freescale Internal Use 15"
|
|
hgroup.byte 0x103C++0x00
|
|
hide.byte 0x00 "FB2_INT_USE16,Fuse Bank 2 Freescale Internal Use 16"
|
|
hgroup.byte 0x1040++0x00
|
|
hide.byte 0x00 "FB2_INT_USE17,Fuse Bank 2 Freescale Internal Use 17"
|
|
hgroup.byte 0x1044++0x00
|
|
hide.byte 0x00 "FB2_INT_USE18,Fuse Bank 2 Freescale Internal Use 18"
|
|
hgroup.byte 0x1048++0x00
|
|
hide.byte 0x00 "FB2_INT_USE19,Fuse Bank 2 Freescale Internal Use 19"
|
|
hgroup.byte 0x104C++0x00
|
|
hide.byte 0x00 "FB2_INT_USE20,Fuse Bank 2 Freescale Internal Use 20"
|
|
hgroup.byte 0x1050++0x00
|
|
hide.byte 0x00 "FB2_INT_USE21,Fuse Bank 2 Freescale Internal Use 21"
|
|
hgroup.byte 0x1054++0x00
|
|
hide.byte 0x00 "FB2_INT_USE22,Fuse Bank 2 Freescale Internal Use 22"
|
|
hgroup.byte 0x1058++0x00
|
|
hide.byte 0x00 "FB2_INT_USE23,Fuse Bank 2 Freescale Internal Use 23"
|
|
hgroup.byte 0x105C++0x00
|
|
hide.byte 0x00 "FB2_INT_USE24,Fuse Bank 2 Freescale Internal Use 24"
|
|
hgroup.byte 0x1060++0x00
|
|
hide.byte 0x00 "FB2_INT_USE25,Fuse Bank 2 Freescale Internal Use 25"
|
|
hgroup.byte 0x1064++0x00
|
|
hide.byte 0x00 "FB2_INT_USE26,Fuse Bank 2 Freescale Internal Use 26"
|
|
hgroup.byte 0x1068++0x00
|
|
hide.byte 0x00 "FB2_INT_USE27,Fuse Bank 2 Freescale Internal Use 27"
|
|
hgroup.byte 0x106C++0x00
|
|
hide.byte 0x00 "FB2_INT_USE28,Fuse Bank 2 Freescale Internal Use 28"
|
|
hgroup.byte 0x1070++0x00
|
|
hide.byte 0x00 "FB2_INT_USE29,Fuse Bank 2 Freescale Internal Use 29"
|
|
hgroup.byte 0x1074++0x00
|
|
hide.byte 0x00 "FB2_INT_USE30,Fuse Bank 2 Freescale Internal Use 30"
|
|
hgroup.byte 0x1078++0x00
|
|
hide.byte 0x00 "FB2_INT_USE31,Fuse Bank 2 Freescale Internal Use 31"
|
|
hgroup.byte 0x107C++0x00
|
|
hide.byte 0x00 "FB2_INT_USE32,Fuse Bank 2 Freescale Internal Use 32"
|
|
tree.end
|
|
tree "Fuse Bank 3"
|
|
width 12.
|
|
group.byte 0x1400++0x00
|
|
line.byte 0x00 "FBAC3,Fuse Bank 3 Access Protection Register"
|
|
bitfld.byte 0x00 7. " FBWP ,Fuse Bank Write Protect" "Not protected,Protected"
|
|
bitfld.byte 0x00 6. " FBOP ,Fuse Bank Override Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FBRP ,Fuse Bank Read Protect" "Not protected,Protected"
|
|
bitfld.byte 0x00 4. " TRIM_LOCK ,Locking rows 0C24-0C7C" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " FBESP ,Explicit sense by software" "Sensed,Not sensed"
|
|
bitfld.byte 0x00 1. " SRK_LOCK88 ,Locking rows 1404-142C" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SRK_LOCK160 ,Locking rows 1430-147C" "Unlocked,Locked"
|
|
group.byte 0x1404++0x00
|
|
line.byte 0x00 "SRK_HASH30,SRK_HASH Register 30"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[247:240] ,SRK_HASH[247:240]"
|
|
group.byte 0x1408++0x00
|
|
line.byte 0x00 "SRK_HASH29,SRK_HASH Register 29"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[239:232] ,SRK_HASH[239:232]"
|
|
group.byte 0x140C++0x00
|
|
line.byte 0x00 "SRK_HASH28,SRK_HASH Register 28"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[231:224] ,SRK_HASH[231:224]"
|
|
group.byte 0x1410++0x00
|
|
line.byte 0x00 "SRK_HASH27,SRK_HASH Register 27"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[223:216] ,SRK_HASH[223:216]"
|
|
group.byte 0x1414++0x00
|
|
line.byte 0x00 "SRK_HASH26,SRK_HASH Register 26"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[215:208] ,SRK_HASH[215:208]"
|
|
group.byte 0x1418++0x00
|
|
line.byte 0x00 "SRK_HASH25,SRK_HASH Register 25"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[207:200] ,SRK_HASH[207:200]"
|
|
group.byte 0x141C++0x00
|
|
line.byte 0x00 "SRK_HASH24,SRK_HASH Register 24"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[199:192] ,SRK_HASH[199:192]"
|
|
group.byte 0x1420++0x00
|
|
line.byte 0x00 "SRK_HASH23,SRK_HASH Register 23"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[191:184] ,SRK_HASH[191:184]"
|
|
group.byte 0x1424++0x00
|
|
line.byte 0x00 "SRK_HASH22,SRK_HASH Register 22"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[183:176] ,SRK_HASH[183:176]"
|
|
group.byte 0x1428++0x00
|
|
line.byte 0x00 "SRK_HASH21,SRK_HASH Register 21"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[175:168] ,SRK_HASH[175:168]"
|
|
group.byte 0x142C++0x00
|
|
line.byte 0x00 "SRK_HASH20,SRK_HASH Register 20"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[167:160] ,SRK_HASH[167:160]"
|
|
group.byte 0x1430++0x00
|
|
line.byte 0x00 "SRK_HASH19,SRK_HASH Register 19"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[159:152] ,SRK_HASH[159:152]"
|
|
group.byte 0x1434++0x00
|
|
line.byte 0x00 "SRK_HASH18,SRK_HASH Register 18"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[151:144] ,SRK_HASH[151:144]"
|
|
group.byte 0x1438++0x00
|
|
line.byte 0x00 "SRK_HASH17,SRK_HASH Register 17"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[143:136] ,SRK_HASH[143:136]"
|
|
group.byte 0x143C++0x00
|
|
line.byte 0x00 "SRK_HASH16,SRK_HASH Register 16"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[135:128] ,SRK_HASH[135:128]"
|
|
group.byte 0x1440++0x00
|
|
line.byte 0x00 "SRK_HASH15,SRK_HASH Register 15"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[127:120] ,SRK_HASH[127:120]"
|
|
group.byte 0x1444++0x00
|
|
line.byte 0x00 "SRK_HASH14,SRK_HASH Register 14"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[119:112] ,SRK_HASH[119:112]"
|
|
group.byte 0x1448++0x00
|
|
line.byte 0x00 "SRK_HASH13,SRK_HASH Register 13"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[111:104] ,SRK_HASH[111:104]"
|
|
group.byte 0x144C++0x00
|
|
line.byte 0x00 "SRK_HASH12,SRK_HASH Register 12"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[103:96] ,SRK_HASH[103:96]"
|
|
group.byte 0x1450++0x00
|
|
line.byte 0x00 "SRK_HASH11,SRK_HASH Register 11"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[95:88] ,SRK_HASH[95:88]"
|
|
group.byte 0x1454++0x00
|
|
line.byte 0x00 "SRK_HASH10,SRK_HASH Register 10"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[87:80] ,SRK_HASH[87:80]"
|
|
group.byte 0x1458++0x00
|
|
line.byte 0x00 "SRK_HASH9,SRK_HASH Register 9"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[79:72] ,SRK_HASH[79:72]"
|
|
group.byte 0x145C++0x00
|
|
line.byte 0x00 "SRK_HASH8,SRK_HASH Register 8"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[71:64] ,SRK_HASH[71:64]"
|
|
group.byte 0x1460++0x00
|
|
line.byte 0x00 "SRK_HASH7,SRK_HASH Register 7"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[63:56] ,SRK_HASH[63:56]"
|
|
group.byte 0x1464++0x00
|
|
line.byte 0x00 "SRK_HASH6,SRK_HASH Register 6"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[55:48] ,SRK_HASH[55:48]"
|
|
group.byte 0x1468++0x00
|
|
line.byte 0x00 "SRK_HASH5,SRK_HASH Register 5"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[47:40] ,SRK_HASH[47:40]"
|
|
group.byte 0x146C++0x00
|
|
line.byte 0x00 "SRK_HASH4,SRK_HASH Register 4"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[39:32] ,SRK_HASH[39:32]"
|
|
group.byte 0x1470++0x00
|
|
line.byte 0x00 "SRK_HASH3,SRK_HASH Register 3"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[31:24] ,SRK_HASH[31:24]"
|
|
group.byte 0x1474++0x00
|
|
line.byte 0x00 "SRK_HASH2,SRK_HASH Register 2"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[23:16] ,SRK_HASH[23:16]"
|
|
group.byte 0x1478++0x00
|
|
line.byte 0x00 "SRK_HASH1,SRK_HASH Register 1"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[15:8] ,SRK_HASH[15:8]"
|
|
group.byte 0x147C++0x00
|
|
line.byte 0x00 "SRK_HASH0,SRK_HASH Register 0"
|
|
hexmask.byte 0x00 0.--7. 1. " SRK_HASH[7:0] ,SRK_HASH[7:0]"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "IOMUXC (IOMUX Controller)"
|
|
base ad:0x73fa8000
|
|
width 6.
|
|
tree "General Purpose Registers"
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "GPR0,General Purpose Register 0"
|
|
bitfld.long 0x00 10. " EMI_MUX ,EMI_MUX" "Access 1 request,Snooping 2 request to IPUv3EX"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TPIU_TRACE_EN ,Special enable for ALT6 for PADS EIM_D16 - EIM_D31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SDMA_SEL_EV20 ,SDMA Select Event 20" "ESDHCv2 1,I2C1"
|
|
bitfld.long 0x00 7. " SDMA_SEL_EV21 ,SDMA Select Event 21" "ESDHCv2 2,I2C2"
|
|
line.long 0x04 "GPR1,General Purpose Register 1"
|
|
tree.end
|
|
width 15.
|
|
tree "IOMUXC_OBSERVE_MUX Registers"
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "OBSERVE_MUX_0,OBSERVE_MUX_0 Register"
|
|
bitfld.long 0x00 0.--5. " OBSRV ,Instance Pin for Observability IOMUXC_OBSERVE_MUX_0" "ahbmax;Pin max_halted,ccm;Pin ccm_clk_switch_ack,ccm;Pin ccm_ipg_stop,ccm;Pin ccm_ipg_wait,ccm;Pin ccm_lpsr_ipu,ccm;Pin ccm_pdn_4all_req,ccm;Pin hndsk_current_state[0],ccm;Pin ipi_int_1,ccm;Pin ipi_int_2,ccm;Pin lpm_current_state[0],ccm;Pin shd_current_state[0],cspi;Pin ~ipi_int_cspi_b,csu;Pin ~ipi_int_csu_b,dpllip1;Pin dpllip_cpen,ecspi1;Pin ipd_req_cspi_rdma_b,ecspi1;Pin ipd_req_cspi_tdma_b,ecspi1;Pin ~ipi_int_cspi_b,ecspi2;Pin ipd_req_cspi_rdma_b,ecspi2;Pin ~ipi_int_cspi_b,emi;Pin chosen_data_master_fast[0],emi;Pin chosen_data_master_int2[0],emi;Pin chosen_data_master_int1[0],emi;Pin chosen_data_master_slow[0],emi;Pin dvfs_ack_fast,emi;Pin dvfs_ack_int1,emi;Pin ~ipi_emi_ap_int_b,emi;Pin ~ipi_int_nfc_b,emi;Pin ipp_obe_data_dir[3],emi;Pin ipp_obe_maddr_dir[1],emi;Pin lpack,emi;Pin lpmd_int1_s1_mem,epit1;Pin ipi_int_epit_oc,epit2;Pin ipi_int_epit_oc,esdhc1;Pin ~ipi_esdhcv2_irq_b,esdhc2;Pin ~ipi_esdhcv2_irq_b,esdhc3;Pin ~ipi_esdhcv2_irq_b,esdhc4;Pin ~ipi_esdhcv2_irq_b,fec;Pin fec_ipi_int,firi;Pin ~ipi_int_b,gpc;Pin gpc_cta8_pg[0],gpc;Pin gpc_cta8_pg[1],gpc;Pin gpc_cta8_pg[2],gpc;Pin gpc_cta8_pg[3],gpc;Pin gpc_cta8_pg[4],gpc;Pin gpc_emi_pg[0],gpc;Pin gpc_emi_short_b,gpc;Pin gpc_event,gpc;Pin gpc int,gpc;Pin gpc_int2,gpc;Pin gpc_neon_pg[0],pata;Pin ata_rcv_fifo_alarm,pata;Pin ata_tx_fifo_alarm,pata;Pin ata_txfer_end_alarm,slm;Pin ipd_tx_smc_req,src;Pin arm_por_rst,src;Pin warm_reset,tigerp_platform_ne_32k_256k;Pin dsm_request,tigerp_platform_ne_32k_256k;Pin ~nm_irq_b,tzic;Pin tzic_fiq_b,tzic;Pin tzic_irq_b,vpu;Pin ipi_int_vpu,?..."
|
|
line.long 0x04 "OBSERVE_MUX_1,OBSERVE_MUX_1 Register"
|
|
bitfld.long 0x04 0.--5. " OBSRV ,Instance Pin for Observability IOMUXC_OBSERVE_MUX_1" "ccm;Pin ahbmax_halt_req,ccm;Pin ccm_pdn_4arm_req,ccm;Pin ccm_pup_req,ccm;Pin ccm_system_in_stop_mode,ccm;Pin ccm_system_in_wait_mode,ccm;Pin dpll_en_dpllip,ccm;Pin emi_dvfs_req_fast,ccm;Pin emi_dvfs_req_int1,ccm;Pin emi_dvfs_req_slow,ccm;Pin emi_lpmd,ccm;Pin emi_lpmd_fast,ccm;Pin hndsk_current_state[1],ccm;Pin lpm_current_state[1],ccm;Pin shd_current_state[1],dpllip2;Pin dpllip_cpen,ecspi2;Pin ipd_req_cspi_tdma_b,emi;Pin chosen_data_master_fast[1],emi;Pin chosen_data_master_int2[1],emi;Pin chosen_data_master_int1[1],emi;Pin chosen_data_master_slow[1],emi;Pin dvfs_ack,emi;Pin ipp_obe_data_dir[2],emi;Pin ipp_obe_maddr_dir[0],emi;Pin lpack_fast,emi;Pin lpmd_int1_s0_mem,firi;Pin dma_req_b[0],firi;Pin dma_req_b[1],gpc;Pin gpc_cta8_clk_upd_req,gpc;Pin gpc_cta8_pg[5],gpc;Pin gpc_cta8_pg[6],gpc;Pin gpc_cta8_pg[7],gpc;Pin gpc_cta8_pg[8],gpc;Pin gpc_cta8_pg[9],gpc;Pin gpc_emi_pg[1],gpc;Pin gpc_ipu_switch_b,gpc;Pin gpc_l1bits_pwrdwn,gpc;Pin gpc_l2bits_pwrdwn,gpc;Pin gpc_neon_pg[1],gpio1;Pin ipi_gpio_int15_0,gpio1;Pin ipi_gpio_int31_16,gpio1;Pin ipi_gpio_int32[0],gpio1;Pin ipi_gpio_int32[1],gpio1;Pin ipi_gpio_int32[2],gpio1;Pin ipi_gpio_int32[3],gpio1;Pin ipi_gpio_int32[4],gpio1;Pin ipi_gpio_int32[5],gpio1;Pin ipi_gpio_int32[6],gpio1;Pin ipi gpio int32[7],gpio2;Pin ipi_gpio_int15_0,gpio2;Pin ipi_gpio_int31_16,gpio3;Pin ipi_gpio_int15_0,gpio3;Pin ipi_gpio_int31_16,gpio4;Pin ipi_gpio_int15_0,gpio4;Pin ipi_gpio_int31_16,gpt;Pin ipi_int_gpt,gpu3d;Pin ~gpu_int_b,src;Pin arm_soc_rst_b,tigerp_platform_ne_32k_256k;Pin dsm_request,uart1;Pin ipd_uart_rx_dmareq_b,uart1;Pin ipd_uart_tx_dmareq_b,uart2;Pin ipd_uart_rx_dmareq_b,uart2;Pin ipd_uart_tx_dmareq_b,?..."
|
|
line.long 0x08 "OBSERVE_MUX_2,OBSERVE_MUX_2 Register"
|
|
bitfld.long 0x08 0.--5. " OBSRV ,Instance Pin for Observability IOMUXC_OBSERVE_MUX_2" "ccm;Pin emi_freq_change_req,ccm;Pin emi_lpmd_int1,ccm;Pin hndsk_current_state[2],ccm;Pin ipu_clk_changed,ccm;Pin lpm_current_state[2],dpllip3;Pin dpllip_cpen,emi;Pin chosen_data_master_fast[2],emi;Pin chosen_data_master_int2[2],emi;Pin chosen_data_master_int1[2],emi;Pin chosen_data_master_slow[2],emi;Pin ipp_obe_weim_nfc_dir[0],emi;Pin lpack,emi;Pin lpack_fast,emi;Pin lpack_int1,emi;Pin lpack_slow,emi;Pin lpmd_int1_s1_mem,gpc;Pin gpc_core_pwrdwn,gpc;Pin gpc_cta8_clk_dvfs_operation,gpc;Pin gpc_cta8_pg[10],gpc;Pin gpc_cta8_pg[11],gpc;Pin gpc_cta8_pg[12],gpc;Pin gpc_cta8_pg[13],gpc;Pin gpc_cta8_pg[14],gpc;Pin gpc_emi_pg[2],gpc;Pin gpc_neon_pg[2],gpc;Pin gpc_neon_pwrdwn,gpc;Pin gpc_pdn_ack,gpc;Pin gpc_pup_ack,gpu3d;Pin ~gpu_idle,hsc_mipi_mix;Pin mcg_err_int,hsc_mipi_mix;Pin mcg_func_int,hsc_mipi_mix;Pin mcg_tmr_int,i2c1;Pin ~ipi_int_b,i2c2;Pin ~ipi_int_b,iim;Pin ~iim_irq_b,ipu;Pin ipi_int_ipu_err,ipu;Pin ipi_int_ipu_func,kpp;Pin ~ipi_int_kpp_b,owire;Pin ipi_owire_int,pata;Pin ipbus_int,pwm1;Pin ipi_int_pwm,pwm2;Pin ipi_int_pwm,rtic;Pin ipi_rtic_done_int,sahara;Pin ~ipi_int_sahara_host0_b,src;Pin sjc_por_rst_b,src;Pin system_rst_b,ssi1;Pin ipd_ssi_rx0_dmareq_b,ssi1;Pin ipd ssi rx1 dmareq b,ssi1;Pin ipd_ssi_tx1_dmareq_b,ssi2;Pin ipd_ssi_rx1_dmareq_b,?..."
|
|
line.long 0x0c "OBSERVE_MUX_3,OBSERVE_MUX_3 Register"
|
|
bitfld.long 0x0C 0.--5. " OBSRV ,Instance Pin for Observability IOMUXC_OBSERVE_MUX_3" "ccm;Pin emi_lpmd_slow,ccm;Pin rtic_ipg_stop_req,cspi;Pin ipd_req_cspi_rdma_b,cspi;Pin ipd_req_cspi_tdma_b,dpllip1;Pin dpllip_lrf_sticky,dpllip2;Pin dpllip_lrf_sticky,dpllip3;Pin dpllip_lrf_sticky,emi;Pin dvfs_ack_slow,emi;Pin ipp_obe_weim_nfc_dir[1],emi;Pin lpack_slow,emi;Pin nfc_dma_rd_req,emi;Pin nfc_dma_wr_req,emi;Pin weim_idle,epit2;Pin ipi_int_epit_oc,gpc;Pin gpc_cta8_pg[15],gpc;Pin gpc_cta8_pg[16],gpc;Pin gpc_cta8_pg[17],gpc;Pin gpc_cta8_pg[18],gpc;Pin gpc_cta8_pg[19],gpc;Pin gpc_emi_pg[3],gpc;Pin gpc_freq_change_mode,gpc;Pin gpc_neon_pg[3],gpc;Pin gpc_neon_short_b,gpu3d;Pin gpu_idle,ipu;Pin ipg_clk_change_ack,ipu;Pin ipu_sdma_event,ipu;Pin ipu_stby_ack,sahara;Pin ipg_stop_ack,scc;Pin ipg_stop_ack,scc;Pin scc_ipi_sctl_irq,scc;Pin scc_ipi_sctl_ns_irq,scc;Pin scc_ipi_smon_irq,sdma;Pin ipg_stop_ack,sdma;Pin ~ipi_host_intr_b,sim;Pin ipi_int_sim_data_irq,sim;Pin ipi_int_sim_ipb_int,slm;Pin ~ipi_slm_excep_int_b,slm;Pin ~ipi_slm_int_b,slm;Pin ~ipi_slm_rx_smc_int_b,spdif;Pin ~mirq_tx_b,src;Pin any_pu_rst_b,src;Pin emi_rst_b,src;Pin ipi_int_1,src;Pin system_early_rst_b,srtc;Pin ~ipi_srtc_int_b,srtc;Pin ~ipi_srtc_sec_int_b,ssi1;Pin ipd_ssi_tx0_dmareq_b,ssi1;Pin ~ipi int b,ssi2;Pin ~ipi_int_b,ssi3;Pin ~ipi_int_b,tigerp_platform_ne_32k_256k;Pin nm_irq_b,?..."
|
|
line.long 0x10 "OBSERVE_MUX_4,OBSERVE_MUX_4 Register"
|
|
bitfld.long 0x10 0.--5. " OBSRV ,Instance Pin for Observability IOMUXC_OBSERVE_MUX_4" "ccm;Pin emi_lpmd_garb,ccm;Pin ipu_freq_change_req,ccm;Pin ipu_stop_clk_at_stop_req,ccm;Pin pll_lvs,ccm;Pin sahara_ipg_stop_req,ccm;Pin scc_ipg_stop_req,ccm;Pin sdma_ipg_stop_req,ccm;Pin src_clock_ready,emi;Pin esdctl_idle,emi;Pin nfc_idle,esdhc3;Pin ipd_esdhcv2_dreq_b,esdhc4;Pin ipd_esdhcv2_dreq_b,gpc;Pin gpc_cta8_iso,gpc;Pin gpc_cta8_pg[20],gpc;Pin gpc_emi_pg[4],gpc;Pin gpc_ipu_pg_event,gpc;Pin gpc_ipu_stat_pg,gpc;Pin volt_chng,iim;Pin fuse_latched,ipu;Pin ipu_stby_ack,rtic;Pin ipg_stop_ack,sfp;Pin sfp_ready,slm;Pin ipd_tx_req_4,spdif;Pin drq1_spdif_b,src;Pin emi_dvfs_req,src;Pin en_system_clk,src;Pin memory_repair_mode,src;Pin power_gating_reset_done,tigerp_platform_ne_32k_256k;Pin cti1_trigout0,tigerp_platform_ne_32k_256k;Pin cti1_trigout1,tigerp_platform_ne_32k_256k;Pin cti1_trigout2,tigerp_platform_ne_32k_256k;Pin cti1_trigout3,tigerp_platform_ne_32k_256k;Pin ~cti_irq_b,tigerp_platform_ne_32k_256k;Pin dbgack,tigerp_platform_ne_32k_256k;Pin ~pmu_irq_b,tve;Pin ipi_tve_int,tzic;Pin tzic_wakeup_request,uart1;Pin ~ipi_uart_anded_b,uart2;Pin ~ipi_uart_anded_b,uart3;Pin ipd_uart_rx_dmareq_b,uart3;Pin ipd_uart_tx_dmareq_b,uart3;Pin ~ipi_uart_anded_b,usboh3;Pin ipi_int_uh1,usboh3;Pin ipi_int_uh2,usboh3;Pin ipi_int_uh3,usboh3;Pin ipi_int_uotg,vpu;Pin ipi_int_vpu,vpu;Pin vpu_idle,wdog1;Pin ~ipi_wdog_int_b,wdog2;Pin ~ipi_wdog_int_b,wdog2;Pin wdog_rst_b,hsi2c;Pin ~ipi_hsi2c_int_b,sahara;Pin ~ipi_int_sahara_host1_b,?..."
|
|
tree.end
|
|
width 32.
|
|
tree "SW_MUX_CTL_PAD Registers"
|
|
group.long 0x1c++0x3d3
|
|
line.long 0x00 "SW_MUX_CTL_PAD_EIM_DA0,SW_MUX_CTL_PAD_EIM_DA0 Register"
|
|
bitfld.long 0x00 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[0]:emi,TRACE[16]:tpiu"
|
|
line.long 0x04 "SW_MUX_CTL_PAD_EIM_DA1,SW_MUX_CTL_PAD_EIM_DA1 Register"
|
|
bitfld.long 0x04 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[1]:emi,TRACE[17]:tpiu"
|
|
line.long 0x08 "SW_MUX_CTL_PAD_EIM_DA2,SW_MUX_CTL_PAD_EIM_DA2 Register"
|
|
bitfld.long 0x08 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[2]:emi,TRACE[18]:tpiu"
|
|
line.long 0x0c "SW_MUX_CTL_PAD_EIM_DA3,SW_MUX_CTL_PAD_EIM_DA3 Register"
|
|
bitfld.long 0x0c 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[3]:emi,TRACE[19]:tpiu"
|
|
line.long 0x10 "SW_MUX_CTL_PAD_EIM_DA4,SW_MUX_CTL_PAD_EIM_DA4 Register"
|
|
bitfld.long 0x10 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[4]:emi,TRACE[20]:tpiu"
|
|
line.long 0x14 "SW_MUX_CTL_PAD_EIM_DA5,SW_MUX_CTL_PAD_EIM_DA5 Register"
|
|
bitfld.long 0x14 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[5]:emi,TRACE[21]:tpiu"
|
|
line.long 0x18 "SW_MUX_CTL_PAD_EIM_DA6,SW_MUX_CTL_PAD_EIM_DA6 Register"
|
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bitfld.long 0x18 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[6]:emi,TRACE[22]:tpiu"
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line.long 0x1c "SW_MUX_CTL_PAD_EIM_DA7,SW_MUX_CTL_PAD_EIM_DA7 Register"
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bitfld.long 0x1c 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[7]:emi,TRACE[23]:tpiu"
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line.long 0x20 "SW_MUX_CTL_PAD_EIM_DA8,SW_MUX_CTL_PAD_EIM_DA8 Register"
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bitfld.long 0x20 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[8]:emi,TRACE[24]:tpiu"
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line.long 0x24 "SW_MUX_CTL_PAD_EIM_DA9,SW_MUX_CTL_PAD_EIM_DA9 Register"
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bitfld.long 0x24 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[9]:emi,TRACE[25]:tpiu"
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line.long 0x28 "SW_MUX_CTL_PAD_EIM_DA10,SW_MUX_CTL_PAD_EIM_DA10 Register"
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bitfld.long 0x28 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[10]:emi,TRACE[26]:tpiu"
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line.long 0x2c "SW_MUX_CTL_PAD_EIM_DA11,SW_MUX_CTL_PAD_EIM_DA11 Register"
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bitfld.long 0x2c 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[11]:emi,TRACE[27]:tpiu"
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line.long 0x30 "SW_MUX_CTL_PAD_EIM_DA12,SW_MUX_CTL_PAD_EIM_DA12 Register"
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bitfld.long 0x30 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[12]:emi,TRACE[28]:tpiu"
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line.long 0x34 "SW_MUX_CTL_PAD_EIM_DA13,SW_MUX_CTL_PAD_EIM_DA13 Register"
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bitfld.long 0x34 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[13]:emi,TRACE[29]:tpiu"
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line.long 0x38 "SW_MUX_CTL_PAD_EIM_DA14,SW_MUX_CTL_PAD_EIM_DA14 Register"
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bitfld.long 0x38 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[14]:emi,TRACE[30]:tpiu"
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line.long 0x3c "SW_MUX_CTL_PAD_EIM_DA15,SW_MUX_CTL_PAD_EIM_DA15 Register"
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bitfld.long 0x3c 0. " MUX_MODE ,MUX Mode Select Field" "EIM_DA[15]:emi,TRACE[31]:tpiu"
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line.long 0x40 "SW_MUX_CTL_PAD_EIM_D16,SW_MUX_CTL_PAD_EIM_D16 Register"
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bitfld.long 0x40 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D16"
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textline " "
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bitfld.long 0x40 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[16]:emi,GPIO[0]:gpio2,USBH2_DATA0:usboh3,CTS:uart2,SDA:i2c1,AUD4_RXFS:audmux,TRACE[0]:tpiu,AUD5_TXD:audmux"
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line.long 0x44 "SW_MUX_CTL_PAD_EIM_D17,SW_MUX_CTL_PAD_EIM_D17 Register"
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bitfld.long 0x44 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D17"
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textline " "
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bitfld.long 0x44 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[17]:emi,GPIO[1]:gpio2,USBH2_DATA1:usboh3,RXD_MUX:uart2,CTS:uart3,SISG[4]:ipu,TRACE[1]:tpiu,AUD5_RXD:audmux"
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line.long 0x48 "SW_MUX_CTL_PAD_EIM_D18,SW_MUX_CTL_PAD_EIM_D18 Register"
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bitfld.long 0x48 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D18"
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textline " "
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bitfld.long 0x48 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[18]:emi,GPIO[2]:gpio2,USBH2_DATA2:usboh3,TXD_MUX:uart2,RTS:uart3,SISG[5]:ipu,TRACE[2]:tpiu,AUD5_TXC:audmux"
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line.long 0x4c "SW_MUX_CTL_PAD_EIM_D19,SW_MUX_CTL_PAD_EIM_D19 Register"
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bitfld.long 0x4c 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D19"
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textline " "
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bitfld.long 0x4c 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[19]:emi,GPIO[3]:gpio2,USBH2_DATA3:usboh3,RTS:uart2,SCL:i2c1,AUD4_RXC:audmux,TRACE[3]:tpiu,AUD5_TXFS:audmux"
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line.long 0x50 "SW_MUX_CTL_PAD_EIM_D20,SW_MUX_CTL_PAD_EIM_D20 Register"
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bitfld.long 0x50 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D20"
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textline " "
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bitfld.long 0x50 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[20]:emi,GPIO[4]:gpio2,USBH2_DATA4:usboh3,CSU_INT_DEB:csu,SRTC_ALARM_DEB:srtc,AUD4_TXD:audmux,TRACE[4]:tpiu,TXREADY:usbphy"
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line.long 0x54 "SW_MUX_CTL_PAD_EIM_D21,SW_MUX_CTL_PAD_EIM_D21 Register"
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bitfld.long 0x54 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D21"
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textline " "
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bitfld.long 0x54 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[21]:emi,GPIO[5]:gpio2,USBH2_DATA5:usboh3,SRTC_ALARM_DEB:srtc,Reserved,AUD4_RXD:audmux,TRACE[5]:tpiu,RXVALID:usbphy"
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line.long 0x58 "SW_MUX_CTL_PAD_EIM_D22,SW_MUX_CTL_PAD_EIM_D22 Register"
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bitfld.long 0x58 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D22"
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textline " "
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bitfld.long 0x58 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[22]:emi,GPIO[6]:gpio2,USBH2_DATA6:usboh3,FAIL_STATE:scc,Reserved,AUD4_TXC:audmux,TRACE[6]:tpiu,RXACTIVE:usbphy"
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line.long 0x5c "SW_MUX_CTL_PAD_EIM_D23,SW_MUX_CTL_PAD_EIM_D23 Register"
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bitfld.long 0x5c 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D23"
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textline " "
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bitfld.long 0x5c 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[23]:emi,GPIO[7]:gpio2,USBH2_DATA7:usboh3,SEC_STATE:scc,OUT1:spdif,AUD4_TXFS:audmux,TRACE[7]:tpiu,RXERROR:usbphy"
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line.long 0x60 "SW_MUX_CTL_PAD_EIM_D24,SW_MUX_CTL_PAD_EIM_D24 Register"
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bitfld.long 0x60 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D24"
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textline " "
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bitfld.long 0x60 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[24]:emi,GPIO[8]:gpio2,USBOTG_DATA0:usboh3,CTS:uart3,SDA:i2c2,AUD6_RXFS:audmux,TRACE[8]:tpiu,SIECLOCK:usbphy"
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line.long 0x64 "SW_MUX_CTL_PAD_EIM_D25,SW_MUX_CTL_PAD_EIM_D25 Register"
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bitfld.long 0x64 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D25"
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textline " "
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bitfld.long 0x64 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[25]:emi,COL[6]:kpp,USBOTG_DATA1:usboh3,RXD_MUX:uart3,CTS:uart2,CMPOUT1:gpt,TRACE[9]:tpiu,VBUSVALID:usbphy"
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line.long 0x68 "SW_MUX_CTL_PAD_EIM_D26,SW_MUX_CTL_PAD_EIM_D26 Register"
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bitfld.long 0x68 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D26"
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textline " "
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bitfld.long 0x68 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[26]:emi,COL[7]:kpp,USBOTG_DATA2:usboh3,TXD_MUX:uart3,RTS:uart2,CMPOUT2:gpt,TRACE[10]:tpiu,AVALID:usbphy"
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line.long 0x6c "SW_MUX_CTL_PAD_EIM_D27,SW_MUX_CTL_PAD_EIM_D27 Register"
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bitfld.long 0x6c 4. " SION ,Software Input On Field" "Regular,Force input path EIM_D27"
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textline " "
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bitfld.long 0x6c 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[27]:emi,GPIO[9]:gpio2,USBOTG_DATA3:usboh3,RTS:uart3,SCL:i2c2,AUD6_RXC:audmux,TRACE[11]:tpiu,BVALID:usbphy"
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line.long 0x70 "SW_MUX_CTL_PAD_EIM_D28,SW_MUX_CTL_PAD_EIM_D28 Register"
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bitfld.long 0x70 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[28]:emi,ROW[4]:kpp,USBOTG_DATA4:usboh3,OBSRV_INT_OUT0:elvis_observe_mux,SISG[0]:ipu,AUD6_TXD:audmux,TRACE[12]:tpiu,ENDSESSION:usbphy"
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line.long 0x74 "SW_MUX_CTL_PAD_EIM_D29,SW_MUX_CTL_PAD_EIM_D29 Register"
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bitfld.long 0x74 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[29]:emi,ROW[5]:kpp,USBOTG_DATA5:usboh3,OBSRV_INT_OUT1:elvis_observe_mux,SISG[1]:ipu,AUD6_RXD:audmux,TRACE[13]:tpiu,IDDIG:usbphy"
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line.long 0x78 "SW_MUX_CTL_PAD_EIM_D30,SW_MUX_CTL_PAD_EIM_D30 Register"
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bitfld.long 0x78 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[30]:emi,ROW[6]:kpp,USBOTG_DATA6:usboh3,OBSRV_INT_OUT2:elvis_observe_mux,SISG[2]:ipu,AUD6_TXC:audmux,TRACE[14]:tpiu,HOSTDISCONNECT:usbphy"
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line.long 0x7c "SW_MUX_CTL_PAD_EIM_D31,SW_MUX_CTL_PAD_EIM_D31 Register"
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bitfld.long 0x7c 0.--2. " MUX_MODE ,MUX Mode Select Field" "WEIM_D[31]:emi,ROW[7]:kpp,USBOTG_DATA7:usboh3,OBSRV_INT_OUT3:elvis_observe_mux,SISG[3]:ipu,AUD6_TXFS:audmux,TRACE[15]:tpiu,?..."
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line.long 0x80 "SW_MUX_CTL_PAD_EIM_A16,SW_MUX_CTL_PAD_EIM_A16 Register"
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bitfld.long 0x80 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A16"
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textline " "
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bitfld.long 0x80 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_A[16]:emi,GPIO[10]:gpio2,DATA_HS_OUT[0]:hsc_mipi_mix,Reserved,Reserved,Reserved,Reserved,OSC_FREQ_SEL[0]:src"
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line.long 0x84 "SW_MUX_CTL_PAD_EIM_A17,SW_MUX_CTL_PAD_EIM_A17 Register"
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bitfld.long 0x84 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A17"
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textline " "
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bitfld.long 0x84 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_A[17]:emi,GPIO[11]:gpio2,DATA_HS_OUT[1]:hsc_mipi_mix,Reserved,Reserved,Reserved,Reserved,OSC_FREQ_SEL[1]:src"
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line.long 0x88 "SW_MUX_CTL_PAD_EIM_A18,SW_MUX_CTL_PAD_EIM_A18 Register"
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bitfld.long 0x88 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A18"
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textline " "
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bitfld.long 0x88 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_A[18]:emi,GPIO[12]:gpio2,DATA_HS_OUT[2]:hsc_mipi_mix,Reserved,Reserved,Reserved,Reserved,BT_LPB[0]:src"
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line.long 0x8c "SW_MUX_CTL_PAD_EIM_A19,SW_MUX_CTL_PAD_EIM_A19 Register"
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bitfld.long 0x8c 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A19"
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textline " "
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bitfld.long 0x8c 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_A[19]:emi,GPIO[13]:gpio2,DATA_HS_OUT[3]:hsc_mipi_mix,Reserved,Reserved,Reserved,Reserved,BT_LPB[1]:src"
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line.long 0x90 "SW_MUX_CTL_PAD_EIM_A20,SW_MUX_CTL_PAD_EIM_A20 Register"
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bitfld.long 0x90 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A20"
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textline " "
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bitfld.long 0x90 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_A[20]:emi,GPIO[14]:gpio2,DATA_HS_OUT[4]:hsc_mipi_mix,Reserved,Reserved,Reserved,Reserved,BT_UART_SRC[0]:src"
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line.long 0x94 "SW_MUX_CTL_PAD_EIM_A21,SW_MUX_CTL_PAD_EIM_A21 Register"
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bitfld.long 0x94 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A21"
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textline " "
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bitfld.long 0x94 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_A[21]:emi,GPIO[15]:gpio2,DATA_HS_OUT[5]:hsc_mipi_mix,Reserved,Reserved,Reserved,Reserved,BT_UART_SRC[1]:src"
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line.long 0x98 "SW_MUX_CTL_PAD_EIM_A22,SW_MUX_CTL_PAD_EIM_A22 Register"
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bitfld.long 0x98 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A22"
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textline " "
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bitfld.long 0x98 0.--1. " MUX_MODE ,MUX Mode Select Field" "EIM_A[22]:emi,GPIO[16]:gpio2,DATA_HS_OUT[6]:hsc_mipi_mix,?..."
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line.long 0x9c "SW_MUX_CTL_PAD_EIM_A23,SW_MUX_CTL_PAD_EIM_A23 Register"
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bitfld.long 0x9c 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A23"
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textline " "
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bitfld.long 0x9c 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_A[23]:emi,GPIO[17]:gpio2,DATA_HS_OUT[7]:hsc_mipi_mix,Reserved,Reserved,Reserved,Reserved,BT_HPN_EN:src"
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line.long 0xa0 "SW_MUX_CTL_PAD_EIM_A24,SW_MUX_CTL_PAD_EIM_A24 Register"
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bitfld.long 0xa0 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A24"
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textline " "
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bitfld.long 0xa0 0.--1. " MUX_MODE ,MUX Mode Select Field" "EIM_A[24]:emi,GPIO[18]:gpio2,USBH2_CLK:usboh3,?..."
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line.long 0xa4 "SW_MUX_CTL_PAD_EIM_A25,SW_MUX_CTL_PAD_EIM_A25 Register"
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bitfld.long 0xa4 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A25"
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textline " "
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bitfld.long 0xa4 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_A[25]:emi,GPIO[19]:gpio2,USBH2_DIR:usboh3,Reserved,Reserved,Reserved,DI1_PIN4:ipu,?..."
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line.long 0xa8 "SW_MUX_CTL_PAD_EIM_A26,SW_MUX_CTL_PAD_EIM_A26 Register"
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bitfld.long 0xa8 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A26"
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textline " "
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bitfld.long 0xa8 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_A[26]:emi,GPIO[20]:gpio2,USBH2_STP:usboh3,Reserved,SISG[0]:ipu,CSI1_DATA_EN:hsc_mipi_mix,DI2_EXT_CLK:ccm,?..."
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line.long 0xac "SW_MUX_CTL_PAD_EIM_A27,SW_MUX_CTL_PAD_EIM_A27 Register"
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bitfld.long 0xac 4. " SION ,Software Input On Field" "Regular,Force input path EIM_A27"
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textline " "
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bitfld.long 0xac 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_A[27]:emi,GPIO[21]:gpio2,USBH2_NXT:usboh3,OBSRV_INT_OUT4:elvis_observe_mux,SISG[1]:ipu,CSI2_DATA_EN:hsc_mipi_mix,DI1_PIN1:hsc_mipi_mix,?..."
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line.long 0xb0 "SW_MUX_CTL_PAD_EIM_EB0,SW_MUX_CTL_PAD_EIM_EB0 Register"
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bitfld.long 0xb0 0.--1. " MUX_MODE ,MUX Mode Select Field" "EIM_EB[0]:emi,Reserved,DETECT_D:hsc_mipi_mix,?..."
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line.long 0xb4 "SW_MUX_CTL_PAD_EIM_EB1,SW_MUX_CTL_PAD_EIM_EB1 Register"
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bitfld.long 0xb4 0.--1. " MUX_MODE ,MUX Mode Select Field" "EIM_EB[1]:emi,Reserved,DELAY_D:hsc_mipi_mix,?..."
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line.long 0xb8 "SW_MUX_CTL_PAD_EIM_EB2,SW_MUX_CTL_PAD_EIM_EB2 Register"
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bitfld.long 0xb8 4. " SION ,Software Input On Field" "Regular,Force input path EIM_EB2"
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textline " "
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bitfld.long 0xb8 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_EB[2]:emi,GPIO[22]:gpio2,TRCTL:tpiu,MDIO:fec,SISG[2]:ipu,CSI1_D[2]:hsc_mipi_mix,AUD5_RXFS:audmux,CMPOUT1:gpt"
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line.long 0xbc "SW_MUX_CTL_PAD_EIM_EB3,SW_MUX_CTL_PAD_EIM_EB3 Register"
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bitfld.long 0xbc 4. " SION ,Software Input On Field" "Regular,Force input path EIM_EB3"
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textline " "
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bitfld.long 0xbc 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_EB[3]:emi,GPIO[23]:gpio2,TRCLK:tpiu,RDATA[1]:fec,SISG[3]:ipu,CSI1_D[3]:hsc_mipi_mix,AUD5_RXC:audmux,CMPOUT2:gpt"
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line.long 0xc0 "SW_MUX_CTL_PAD_EIM_OE,SW_MUX_CTL_PAD_EIM_OE Register"
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bitfld.long 0xc0 4. " SION ,Software Input On Field" "Regular,Force input path EIM_OE"
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textline " "
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bitfld.long 0xc0 0. " MUX_MODE ,MUX Mode Select Field" "EIM_OE:emi,GPIO[24]:gpio2"
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line.long 0xc4 "SW_MUX_CTL_PAD_EIM_CS0,SW_MUX_CTL_PAD_EIM_CS0 Register"
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bitfld.long 0xc4 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CS0"
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textline " "
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bitfld.long 0xc4 0. " MUX_MODE ,MUX Mode Select Field" "EIM_CS0:emi,GPIO[25]:gpio2"
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line.long 0xc8 "SW_MUX_CTL_PAD_EIM_CS1,SW_MUX_CTL_PAD_EIM_CS1 Register"
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bitfld.long 0xc8 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CS1"
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textline " "
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bitfld.long 0xc8 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_CS1:emi,GPIO[26]:gpio2,Reserved,Reserved,SISG[4]:ipu,?..."
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line.long 0xcc "SW_MUX_CTL_PAD_EIM_CS2,SW_MUX_CTL_PAD_EIM_CS2 Register"
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bitfld.long 0xcc 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CS2"
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textline " "
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bitfld.long 0xcc 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_CS2:emi,GPIO[27]:gpio2,USBOTG_STP:usboh3,RDATA[2]:fec,SISG[5]:ipu,CSI1_D[4]:hsc_mipi_mix,AUD5_TXD:audmux,?..."
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line.long 0xd0 "SW_MUX_CTL_PAD_EIM_CS3,SW_MUX_CTL_PAD_EIM_CS3 Register"
|
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bitfld.long 0xd0 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CS3"
|
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textline " "
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bitfld.long 0xd0 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_CS3:emi,GPIO[28]:gpio2,USBOTG_NXT:usboh3,RDATA[3]:fec,SSI_EXT2_CLK:ccm,CSI1_D[5]:hsc_mipi_mix,AUD5_RXD:audmux,?..."
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line.long 0xd4 "SW_MUX_CTL_PAD_EIM_CS4,SW_MUX_CTL_PAD_EIM_CS4 Register"
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bitfld.long 0xd4 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CS4"
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textline " "
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bitfld.long 0xd4 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_CS4:emi,GPIO[29]:gpio2,USBOTG_CLK:usboh3,RX_ER:fec,SSI_EXT1_CLK:ccm,CSI1_D[6]:hsc_mipi_mix,AUD5_TXC:audmux,?..."
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line.long 0xd8 "SW_MUX_CTL_PAD_EIM_CS5,SW_MUX_CTL_PAD_EIM_CS5 Register"
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bitfld.long 0xd8 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CS5"
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textline " "
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bitfld.long 0xd8 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_CS5:emi,GPIO[30]:gpio2,USBOTG_DIR:usboh3,CRS:fec,DI1_EXT_CLK:ccm,CSI1_D[7]:hsc_mipi_mix,AUD5_TXFS:audmux,?..."
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line.long 0xdc "SW_MUX_CTL_PAD_EIM_DTACK,SW_MUX_CTL_PAD_EIM_DTACK Register"
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bitfld.long 0xdc 4. " SION ,Software Input On Field" "Regular,Force input path EIM_DTACK"
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textline " "
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bitfld.long 0xdc 0. " MUX_MODE ,MUX Mode Select Field" "WEIM_DTACK_B:emi,GPIO[31]:gpio2"
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line.long 0xe0 "SW_MUX_CTL_PAD_EIM_LBA,SW_MUX_CTL_PAD_EIM_LBA Register"
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bitfld.long 0xe0 4. " SION ,Software Input On Field" "Regular,Force input path EIM_LBA"
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textline " "
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bitfld.long 0xe0 0. " MUX_MODE ,MUX Mode Select Field" "EIM_LBA:emi,GPIO[1]:gpio3"
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line.long 0xe4 "SW_MUX_CTL_PAD_EIM_CRE,SW_MUX_CTL_PAD_EIM_CRE Register"
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bitfld.long 0xe4 4. " SION ,Software Input On Field" "Regular,Force input path EIM_CRE"
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textline " "
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bitfld.long 0xe4 0. " MUX_MODE ,MUX Mode Select Field" "EIM_CRE:emi,GPIO[2]:gpio3"
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line.long 0xe8 "SW_MUX_CTL_PAD_DRAM_CS1,SW_MUX_CTL_PAD_DRAM_CS1 Register"
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bitfld.long 0xe8 0. " MUX_MODE ,MUX Mode Select Field" "DRAM_CS1:emi,CLKO:ccm"
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line.long 0xec "SW_MUX_CTL_PAD_NANDF_WE_B,SW_MUX_CTL_PAD_NANDF_WE_B Register"
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bitfld.long 0xec 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_WE_B"
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textline " "
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bitfld.long 0xec 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_WE_B:emi,DIOW:pata,DAT0:esdhc3,GPIO[3]:gpio3,DEBUG_EVT_CHN_LINES[0]:sdma,?..."
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line.long 0xf0 "SW_MUX_CTL_PAD_NANDF_RE_B,SW_MUX_CTL_PAD_NANDF_RE_B Register"
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bitfld.long 0xf0 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_RE_B"
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textline " "
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bitfld.long 0xf0 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_RE_B:emi,DIOR:pata,DAT1:esdhc3,GPIO[4]:gpio3,DEBUG_EVT_CHN_LINES[1]:sdma,?..."
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line.long 0xf4 "SW_MUX_CTL_PAD_NANDF_ALE,SW_MUX_CTL_PAD_NANDF_ALE Register"
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bitfld.long 0xf4 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_ALE"
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textline " "
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bitfld.long 0xf4 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_ALE:emi,BUFFER_EN:pata,Reserved,GPIO[5]:gpio3,DEBUG_EVT_CHN_LINES[2]:sdma,?..."
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line.long 0xf8 "SW_MUX_CTL_PAD_NANDF_CLE,SW_MUX_CTL_PAD_NANDF_CLE Register"
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bitfld.long 0xf8 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_CLE"
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textline " "
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bitfld.long 0xf8 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_CLE:emi,PATA_RESET_B:pata,Reserved,GPIO[6]:gpio3,DEBUG_EVT_CHN_LINES[3]:sdma,?..."
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line.long 0xfc "SW_MUX_CTL_PAD_NANDF_WP_B,SW_MUX_CTL_PAD_NANDF_WP_B Register"
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bitfld.long 0xfc 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_WP_B"
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textline " "
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bitfld.long 0xfc 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_WP_B:emi,DMACK:pata,DAT2:esdhc3,GPIO[7]:gpio3,DEBUG_EVT_CHN_LINES[4]:sdma,?..."
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line.long 0x100 "SW_MUX_CTL_PAD_NANDF_RB0,SW_MUX_CTL_PAD_NANDF_RB0 Register"
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bitfld.long 0x100 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_RB0"
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textline " "
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bitfld.long 0x100 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_RB0:emi,DMARQ:pata,DAT3:esdhc3,GPIO[8]:gpio3,DEBUG_EVENT_CHANNEL[4]:sdma,SS1:ecspi2,?..."
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line.long 0x104 "SW_MUX_CTL_PAD_NANDF_RB1,SW_MUX_CTL_PAD_NANDF_RB1 Register"
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bitfld.long 0x104 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_RB1"
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textline " "
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bitfld.long 0x104 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_RB1:emi,IORDY:pata,RDY:ecspi2,GPIO[9]:gpio3,CMPOUT2:gpt,CMD:esdhc4,MOSI:cspi,?..."
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line.long 0x108 "SW_MUX_CTL_PAD_NANDF_RB2,SW_MUX_CTL_PAD_NANDF_RB2 Register"
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bitfld.long 0x108 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_RB2"
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textline " "
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bitfld.long 0x108 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_RB2:emi,COL:fec,SCLK:ecspi2,GPIO[10]:gpio3,CMPOUT3:gpt,DI2_WAIT:hsc_mipi_mix,USBH3_NXT:usboh3,H3_DP:usboh3"
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line.long 0x10c "SW_MUX_CTL_PAD_NANDF_RB3,SW_MUX_CTL_PAD_NANDF_RB3 Register"
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bitfld.long 0x10c 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_RB3"
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textline " "
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bitfld.long 0x10c 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_RB3:emi,RX_CLK:fec,MISO:ecspi2,GPIO[11]:gpio3,TOG_EN:dpllip1,DI1_WAIT:hsc_mipi_mix,USBH3_CLK:usboh3,H3_DM:usboh3"
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line.long 0x110 "SW_MUX_CTL_PAD_GPIO_NAND,SW_MUX_CTL_PAD_GPIO_NAND Register"
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bitfld.long 0x110 4. " SION ,Software Input On Field" "Regular,Force input path GPIO_NAND"
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textline " "
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bitfld.long 0x110 0. " MUX_MODE ,MUX Mode Select Field" "GPIO[12]:gpio3,INTRQ:pata"
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line.long 0x114 "SW_MUX_CTL_PAD_NANDF_CS0,SW_MUX_CTL_PAD_NANDF_CS0 Register"
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bitfld.long 0x114 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_CS0"
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textline " "
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bitfld.long 0x114 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_CS0:emi,Reserved,Reserved,GPIO[16]:gpio3,?..."
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line.long 0x118 "SW_MUX_CTL_PAD_NANDF_CS1,SW_MUX_CTL_PAD_NANDF_CS1 Register"
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bitfld.long 0x118 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_CS1"
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textline " "
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bitfld.long 0x118 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_CS1:emi,Reserved,Reserved,GPIO[17]:gpio3,DEBUG_EVENT_CHANNEL[5]:sdma,?..."
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line.long 0x11c "SW_MUX_CTL_PAD_NANDF_CS2,SW_MUX_CTL_PAD_NANDF_CS2 Register"
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bitfld.long 0x11c 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_CS2"
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textline " "
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bitfld.long 0x11c 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_CS2:emi,CS_0:pata,TX_ER:fec,GPIO[18]:gpio3,DEBUG_EVT_CHN_LINES[5]:sdma,CLK:esdhc4,SCLK:cspi,H1_DP:usboh3"
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line.long 0x120 "SW_MUX_CTL_PAD_NANDF_CS3,SW_MUX_CTL_PAD_NANDF_CS3 Register"
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bitfld.long 0x120 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_CS3"
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textline " "
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bitfld.long 0x120 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_CS3:emi,CS_1:pata,MDC:fec,GPIO[19]:gpio3,DEBUG_EVT_CHN_LINES[6]:sdma,DAT0:esdhc4,PD0:sim,H1_DM:usboh3"
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line.long 0x124 "SW_MUX_CTL_PAD_NANDF_CS4,SW_MUX_CTL_PAD_NANDF_CS4 Register"
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bitfld.long 0x124 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_CS4"
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textline " "
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bitfld.long 0x124 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_CS4:emi,DA_0:pata,TDATA[1]:fec,GPIO[20]:gpio3,DEBUG_EVT_CHN_LINES[7]:sdma,DAT1:esdhc4,CLK0:sim,USBH3_STP:usboh3"
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line.long 0x128 "SW_MUX_CTL_PAD_NANDF_CS5,SW_MUX_CTL_PAD_NANDF_CS5 Register"
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bitfld.long 0x128 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_CS5"
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textline " "
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bitfld.long 0x128 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_CS5:emi,DA_1:pata,TDATA[2]:fec,GPIO[21]:gpio3,DEBUG_EVENT_CHANNEL[0]:sdma,DAT2:esdhc4,RST0:sim,USBH3_DIR:usboh3"
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line.long 0x12c "SW_MUX_CTL_PAD_NANDF_CS6,SW_MUX_CTL_PAD_NANDF_CS6 Register"
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bitfld.long 0x12c 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_CS6"
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textline " "
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bitfld.long 0x12c 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_CS6:emi,DA_2:pata,TDATA[3]:fec,GPIO[22]:gpio3,DEBUG_EVENT_CHANNEL[1]:sdma,DAT3:esdhc4,VEN0:sim,SS3:cspi"
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line.long 0x130 "SW_MUX_CTL_PAD_NANDF_CS7,SW_MUX_CTL_PAD_NANDF_CS7 Register"
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bitfld.long 0x130 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_CS7"
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textline " "
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bitfld.long 0x130 0.--2. " MUX_MODE ,MUX Mode Select Field" "NANDF_CS7:emi,TX_EN:fec,Reserved,GPIO[23]:gpio3,DEBUG_EVENT_CHANNEL[2]:sdma,CLK:esdhc3,TX0:sim,?..."
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line.long 0x134 "SW_MUX_CTL_PAD_NANDF_RDY_INT,SW_MUX_CTL_PAD_NANDF_RDY_INT Register"
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bitfld.long 0x134 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_RDY_INT"
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textline " "
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bitfld.long 0x134 0.--2. " MUX_MODE ,MUX Mode Select Field" "RDY:emi,TX_CLK:fec,SS0:ecspi2,GPIO[24]:gpio3,DEBUG_EVENT_CHANNEL[3]:sdma,CMD:esdhc3,RX0:sim,?..."
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line.long 0x138 "SW_MUX_CTL_PAD_NANDF_D15,SW_MUX_CTL_PAD_NANDF_D15 Register"
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bitfld.long 0x138 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D15"
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textline " "
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bitfld.long 0x138 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[15]:emi,PATA_DATA[15]:pata,MOSI:ecspi2,GPIO[25]:gpio3,DEBUG_PC[0]:sdma,DAT7:esdhc3,IPU_DIAG_BUS[0]:ipu,GPU_DEBUG_OUT[0]:gpu3d"
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line.long 0x13c "SW_MUX_CTL_PAD_NANDF_D14,SW_MUX_CTL_PAD_NANDF_D14 Register"
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bitfld.long 0x13c 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D14"
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textline " "
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bitfld.long 0x13c 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[14]:emi,PATA_DATA[14]:pata,SS3:ecspi2,GPIO[26]:gpio3,DEBUG_PC[1]:sdma,DAT6:esdhc3,IPU_DIAG_BUS[1]:ipu,GPU_DEBUG_OUT[1]:gpu3d"
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line.long 0x140 "SW_MUX_CTL_PAD_NANDF_D13,SW_MUX_CTL_PAD_NANDF_D13 Register"
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bitfld.long 0x140 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D13"
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textline " "
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bitfld.long 0x140 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[13]:emi,PATA_DATA[13]:pata,SS2:ecspi2,GPIO[27]:gpio3,DEBUG_PC[2]:sdma,DAT5:esdhc3,IPU_DIAG_BUS[2]:ipu,GPU_DEBUG_OUT[2]:gpu3d"
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line.long 0x144 "SW_MUX_CTL_PAD_NANDF_D12,SW_MUX_CTL_PAD_NANDF_D12 Register"
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bitfld.long 0x144 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D12"
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textline " "
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bitfld.long 0x144 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[12]:emi,PATA_DATA[12]:pata,SS1:ecspi2,GPIO[28]:gpio3,DEBUG_PC[3]:sdma,DAT4:esdhc3,IPU_DIAG_BUS[3]:ipu,GPU_DEBUG_OUT[3]:gpu3d"
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line.long 0x148 "SW_MUX_CTL_PAD_NANDF_D11,SW_MUX_CTL_PAD_NANDF_D11 Register"
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bitfld.long 0x148 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D11"
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textline " "
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bitfld.long 0x148 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[11]:emi,PATA_DATA[11]:pata,RX_DV:fec,GPIO[29]:gpio3,DEBUG_PC[4]:sdma,DAT3:esdhc3,IPU_DIAG_BUS[4]:ipu,GPU_DEBUG_OUT[4]:gpu3d"
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line.long 0x14c "SW_MUX_CTL_PAD_NANDF_D10,SW_MUX_CTL_PAD_NANDF_D10 Register"
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bitfld.long 0x14c 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D10"
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textline " "
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bitfld.long 0x14c 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[10]:emi,PATA_DATA[10]:pata,Reserved,GPIO[30]:gpio3,DEBUG_PC[5]:sdma,DAT2:esdhc3,IPU_DIAG_BUS[5]:ipu,GPU_DEBUG_OUT[5]:gpu3d"
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line.long 0x150 "SW_MUX_CTL_PAD_NANDF_D9,SW_MUX_CTL_PAD_NANDF_D9 Register"
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bitfld.long 0x150 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D9"
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textline " "
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bitfld.long 0x150 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[9]:emi,PATA_DATA[9]:pata,RDATA[0]:fec,GPIO[31]:gpio3,DEBUG_PC[6]:sdma,DAT1:esdhc3,IPU_DIAG_BUS[6]:ipu,GPU_DEBUG_OUT[6]:gpu3d"
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line.long 0x154 "SW_MUX_CTL_PAD_NANDF_D8,SW_MUX_CTL_PAD_NANDF_D8 Register"
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bitfld.long 0x154 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D8"
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textline " "
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bitfld.long 0x154 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[8]:emi,PATA_DATA[8]:pata,TDATA[0]:fec,GPIO[0]:gpio4,DEBUG_PC[7]:sdma,DAT0:esdhc3,IPU_DIAG_BUS[7]:ipu,GPU_DEBUG_OUT[7]:gpu3d"
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line.long 0x158 "SW_MUX_CTL_PAD_NANDF_D7,SW_MUX_CTL_PAD_NANDF_D7 Register"
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bitfld.long 0x158 4. " SION ,Software Input On Field" "Regular,Force input path ANDF_D7"
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textline " "
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bitfld.long 0x158 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[7]:emi,PATA_DATA[7]:pata,Reserved,GPIO[1]:gpio4,DEBUG_PC[8]:sdma,USBH3_DATA0:usboh3,IPU_DIAG_BUS[8]:ipu,GPU_DEBUG_OUT[8]:gpu3d"
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line.long 0x15c "SW_MUX_CTL_PAD_NANDF_D6,SW_MUX_CTL_PAD_NANDF_D6 Register"
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bitfld.long 0x15c 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D6"
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textline " "
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bitfld.long 0x15c 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[6]:emi,PATA_DATA[6]:pata,LCTL:esdhc4,GPIO[2]:gpio4,DEBUG_PC[9]:sdma,USBH3_DATA1:usboh3,IPU_DIAG_BUS[9]:ipu,GPU_DEBUG_OUT[9]:gpu3d"
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line.long 0x160 "SW_MUX_CTL_PAD_NANDF_D5,SW_MUX_CTL_PAD_NANDF_D5 Register"
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bitfld.long 0x160 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D5"
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textline " "
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bitfld.long 0x160 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[5]:emi,PATA_DATA[5]:pata,WP:esdhc4,GPIO[3]:gpio4,DEBUG_PC[10]:sdma,USBH3_DATA2:usboh3,IPU_DIAG_BUS[10]:ipu,GPU_DEBUG_OUT[10]:gpu3d"
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line.long 0x164 "SW_MUX_CTL_PAD_NANDF_D4,SW_MUX_CTL_PAD_NANDF_D4 Register"
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bitfld.long 0x164 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D4"
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textline " "
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bitfld.long 0x164 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[4]:emi,PATA_DATA[4]:pata,CD:esdhc4,GPIO[4]:gpio4,DEBUG_PC[11]:sdma,USBH3_DATA3:usboh3,IPU_DIAG_BUS[11]:ipu,GPU_DEBUG_OUT[11]:gpu3d"
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line.long 0x168 "SW_MUX_CTL_PAD_NANDF_D3,SW_MUX_CTL_PAD_NANDF_D3 Register"
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bitfld.long 0x168 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D3"
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textline " "
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bitfld.long 0x168 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[3]:emi,PATA_DATA[3]:pata,DAT4:esdhc4,GPIO[5]:gpio4,DEBUG_PC[12]:sdma,USBH3_DATA4:usboh3,IPU_DIAG_BUS[12]:ipu,GPU_DEBUG_OUT[12]:gpu3d"
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line.long 0x16c "SW_MUX_CTL_PAD_NANDF_D2,SW_MUX_CTL_PAD_NANDF_D2 Register"
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bitfld.long 0x16c 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D2"
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textline " "
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bitfld.long 0x16c 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[2]:emi,PATA_DATA[2]:pata,DAT5:esdhc4,GPIO[6]:gpio4,DEBUG_PC[13]:sdma,USBH3_DATA5:usboh3,IPU_DIAG_BUS[13]:ipu,GPU_DEBUG_OUT[13]:gpu3d"
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line.long 0x170 "SW_MUX_CTL_PAD_NANDF_D1,SW_MUX_CTL_PAD_NANDF_D1 Register"
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bitfld.long 0x170 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D1"
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textline " "
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bitfld.long 0x170 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[1]:emi,PATA_DATA[1]:pata,DAT6:esdhc4,GPIO[7]:gpio4,DEBUG_CORE_STATE[0]:sdma,USBH3_DATA6:usboh3,IPU_DIAG_BUS[14]:ipu,GPU_DEBUG_OUT[14]:gpu3d"
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line.long 0x174 "SW_MUX_CTL_PAD_NANDF_D0,SW_MUX_CTL_PAD_NANDF_D0 Register"
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bitfld.long 0x174 4. " SION ,Software Input On Field" "Regular,Force input path NANDF_D0"
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textline " "
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bitfld.long 0x174 0.--2. " MUX_MODE ,MUX Mode Select Field" "EIM_NFC_D[0]:emi,PATA_DATA[0]:pata,DAT7:esdhc4,GPIO[8]:gpio4,DEBUG_CORE_STATE[1]:sdma,USBH3_DATA7:usboh3,IPU_DIAG_BUS[15]:ipu,GPU_DEBUG_OUT[15]:gpu3d"
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line.long 0x178 "SW_MUX_CTL_PAD_CSI1_D8,SW_MUX_CTL_PAD_CSI1_D8 Register"
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bitfld.long 0x178 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D8"
|
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textline " "
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bitfld.long 0x178 0.--1. " MUX_MODE ,MUX Mode Select Field" "CSI1_D[8]:hsc_mipi_mix,DETECT_Z:hsc_mipi_mix,Reserved,GPIO[12]:gpio3"
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line.long 0x17c "SW_MUX_CTL_PAD_CSI1_D9,SW_MUX_CTL_PAD_CSI1_D9 Register"
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bitfld.long 0x17c 4. " SION ,Software Input On Field" "Regular,Force input path CSI_D9"
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textline " "
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bitfld.long 0x17c 0.--1. " MUX_MODE ,MUX Mode Select Field" "CSI1_D[9]:hsc_mipi_mix,DELAY_Z:hsc_mipi_mix,Reserved,GPIO[13]:gpio3"
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line.long 0x180 "SW_MUX_CTL_PAD_CSI1_D10,SW_MUX_CTL_PAD_CSI1_D10 Register"
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bitfld.long 0x180 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D10"
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line.long 0x184 "SW_MUX_CTL_PAD_CSI1_D11,SW_MUX_CTL_PAD_CSI1_D11 Register"
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bitfld.long 0x184 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D11"
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line.long 0x188 "SW_MUX_CTL_PAD_CSI1_D12,SW_MUX_CTL_PAD_CSI1_D12 Register"
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bitfld.long 0x188 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D12"
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line.long 0x18c "SW_MUX_CTL_PAD_CSI1_D13,SW_MUX_CTL_PAD_CSI1_D13 Register"
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bitfld.long 0x18c 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D13"
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line.long 0x190 "SW_MUX_CTL_PAD_CSI1_D14,SW_MUX_CTL_PAD_CSI1_D14 Register"
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bitfld.long 0x190 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D14"
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line.long 0x194 "SW_MUX_CTL_PAD_CSI1_D15,SW_MUX_CTL_PAD_CSI1_D15 Register"
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bitfld.long 0x194 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D15"
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line.long 0x198 "SW_MUX_CTL_PAD_CSI1_D16,SW_MUX_CTL_PAD_CSI1_D16 Register"
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|
bitfld.long 0x198 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D16"
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line.long 0x19c "SW_MUX_CTL_PAD_CSI1_D17,SW_MUX_CTL_PAD_CSI1_D17 Register"
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bitfld.long 0x19c 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D17"
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line.long 0x1a0 "SW_MUX_CTL_PAD_CSI1_D18,SW_MUX_CTL_PAD_CSI1_D18 Register"
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bitfld.long 0x1a0 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D18"
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line.long 0x1a4 "SW_MUX_CTL_PAD_CSI1_D19,SW_MUX_CTL_PAD_CSI1_D19 Register"
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bitfld.long 0x1a4 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_D19"
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line.long 0x1a8 "SW_MUX_CTL_PAD_CSI1_VSYNC,SW_MUX_CTL_PAD_CSI1_VSYNC Register"
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bitfld.long 0x1a8 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_VSYNC"
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|
textline " "
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bitfld.long 0x1a8 0.--1. " MUX_MODE ,MUX Mode Select Field" "CSI1_VSYNC:hsc_mipi_mix,TX_DDR_Q:mipi_dphy_trippi_1_slave,Reserved,GPIO[14]:gpio3"
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line.long 0x1ac "SW_MUX_CTL_PAD_CSI1_HSYNC,SW_MUX_CTL_PAD_CSI1_HSYNC Register"
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bitfld.long 0x1ac 4. " SION ,Software Input On Field" "Regular,Force input path CSI1_HSYNC"
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|
textline " "
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bitfld.long 0x1ac 0.--1. " MUX_MODE ,MUX Mode Select Field" "CSI1_HSYNC:hsc_mipi_mix,TX_DDR_I:mipi_dphy_trippi_1_slave,Reserved,GPIO[15]:gpio3"
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line.long 0x1b0 "SW_MUX_CTL_PAD_CSI2_D12,SW_MUX_CTL_PAD_CSI2_D12 Register"
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bitfld.long 0x1b0 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_D12"
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textline " "
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bitfld.long 0x1b0 0.--1. " MUX_MODE ,MUX Mode Select Field" "CSI2_D[12]:hsc_mipi_mix,LP_RX_E:hsc_mipi_mix,Reserved,GPIO[9]:gpio4"
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line.long 0x1b4 "SW_MUX_CTL_PAD_CSI2_D13,SW_MUX_CTL_PAD_CSI2_D13 Register"
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bitfld.long 0x1b4 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_D13"
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textline " "
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bitfld.long 0x1b4 0.--1. " MUX_MODE ,MUX Mode Select Field" "CSI2_D[13]:hsc_mipi_mix,RX_VALID_ESC_OUT:hsc_mipi_mix,GPIO[10]:gpio4,EMI_DEBUG[45]:emi"
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line.long 0x1b8 "SW_MUX_CTL_PAD_CSI2_D14,SW_MUX_CTL_PAD_CSI2_D14 Register"
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bitfld.long 0x1b8 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_D14"
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line.long 0x1bc "SW_MUX_CTL_PAD_CSI2_D15,SW_MUX_CTL_PAD_CSI2_D15 Register"
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bitfld.long 0x1bc 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_D15"
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line.long 0x1c0 "SW_MUX_CTL_PAD_CSI2_D16,SW_MUX_CTL_PAD_CSI2_D16 Register"
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bitfld.long 0x1c0 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_D16"
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line.long 0x1c4 "SW_MUX_CTL_PAD_CSI2_D17,SW_MUX_CTL_PAD_CSI2_D17 Register"
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bitfld.long 0x1c4 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_D17"
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line.long 0x1c8 "SW_MUX_CTL_PAD_CSI2_D18,SW_MUX_CTL_PAD_CSI2_D18 Register"
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bitfld.long 0x1c8 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_D18"
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textline " "
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bitfld.long 0x1c8 0.--2. " MUX_MODE ,MUX Mode Select Field" "CSI2_D[18]:hsc_mipi_mix,HS_TX_E:hsc_mipi_mix,OBSRV_INT_OUT0:elvis_observe_mux,GPIO[11]:gpio4,DEBUG_RTBUFFER_WRITE:sdma,Reserved,EMI_DEBUG[46]:emi,?..."
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line.long 0x1cc "SW_MUX_CTL_PAD_CSI2_D19,SW_MUX_CTL_PAD_CSI2_D19 Register"
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bitfld.long 0x1cc 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_D19"
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textline " "
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bitfld.long 0x1cc 0.--2. " MUX_MODE ,MUX Mode Select Field" "CSI2_D[19]:hsc_mipi_mix,LP_TX_E:hsc_mipi_mix,OBSRV_INT_OUT1:elvis_observe_mux,GPIO[12]:gpio4,DEBUG_YIELD:sdma,Reserved,EMI_DEBUG[47]:emi,?..."
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line.long 0x1d0 "SW_MUX_CTL_PAD_CSI2_VSYNC,SW_MUX_CTL_PAD_CSI2_VSYNC Register"
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bitfld.long 0x1d0 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_VSYNC"
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textline " "
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bitfld.long 0x1d0 0.--2. " MUX_MODE ,MUX Mode Select Field" "CSI2_VSYNC:hsc_mipi_mix,HS_RX_E:hsc_mipi_mix,OBSRV_INT_OUT2:elvis_observe_mux,GPIO[13]:gpio4,DEBUG_BUS_ERROR:sdma,Reserved,EMI_DEBUG[48]:emi,?..."
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line.long 0x1d4 "SW_MUX_CTL_PAD_CSI2_HSYNC,SW_MUX_CTL_PAD_CSI2_HSYNC Register"
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bitfld.long 0x1d4 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_HSYNC"
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textline " "
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bitfld.long 0x1d4 0.--2. " MUX_MODE ,MUX Mode Select Field" "CSI2_HSYNC:hsc_mipi_mix,TX_BYTE_CLK_HS_OUT:hsc_mipi_mix,OBSRV_INT_OUT3:elvis_observe_mux,GPIO[14]:gpio4,Reserved,Reserved,EMI_DEBUG[49]:emi,?..."
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line.long 0x1d8 "SW_MUX_CTL_PAD_CSI2_PIXCLK,SW_MUX_CTL_PAD_CSI2_PIXCLK Register"
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bitfld.long 0x1d8 4. " SION ,Software Input On Field" "Regular,Force input path CSI2_PIXCLK"
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textline " "
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bitfld.long 0x1d8 0.--2. " MUX_MODE ,MUX Mode Select Field" "CSI2_PIXCLK:hsc_mipi_mix,RX_BYTE_CLK_HS_OUT:hsc_mipi_mix,OBSRV_INT_OUT4:elvis_observe_mux,GPIO[15]:gpio4,Reserved,Reserved,EMI_DEBUG[50]:emi,?..."
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line.long 0x1dc "SW_MUX_CTL_PAD_I2C1_CLK,SW_MUX_CTL_PAD_I2C1_CLK Register"
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bitfld.long 0x1dc 4. " SION ,Software Input On Field" "Regular,Force input path I2C1_CLK"
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textline " "
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bitfld.long 0x1dc 0.--1. " MUX_MODE ,MUX Mode Select Field" "SCL:hsi2c,Reserved,Reserved,GPIO[16]:gpio4"
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line.long 0x1e0 "SW_MUX_CTL_PAD_I2C1_DAT,SW_MUX_CTL_PAD_I2C1_DAT Register"
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bitfld.long 0x1e0 4. " SION ,Software Input On Field" "Regular,Force input path I2C1_DAT"
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textline " "
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bitfld.long 0x1e0 0.--1. " MUX_MODE ,MUX Mode Select Field" "SDA:hsi2c,Reserved,Reserved,GPIO[17]:gpio4"
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line.long 0x1e4 "SW_MUX_CTL_PAD_AUD3_BB_TXD,SW_MUX_CTL_PAD_AUD3_BB_TXD Register"
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bitfld.long 0x1e4 4. " SION ,Software Input On Field" "Regular,Force input path AUD3_BB_TXD"
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textline " "
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bitfld.long 0x1e4 0.--2. " MUX_MODE ,MUX Mode Select Field" "AUD3_TXD:audmux,DATA:slm,Reserved,GPIO[18]:gpio4,Reserved,Reserved,Reserved,DATAOUT[0]:usbphy"
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line.long 0x1e8 "SW_MUX_CTL_PAD_AUD3_BB_RXD,SW_MUX_CTL_PAD_AUD3_BB_RXD Register"
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bitfld.long 0x1e8 4. " SION ,Software Input On Field" "Regular,Force input path AUD3_BB_RXD"
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textline " "
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bitfld.long 0x1e8 0.--2. " MUX_MODE ,MUX Mode Select Field" "AUD3_RXD:audmux,RXD_MUX:uart3,Reserved,GPIO[19]:gpio4,Reserved,Reserved,Reserved,DATAOUT[1]:usbphy"
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line.long 0x1ec "SW_MUX_CTL_PAD_AUD3_BB_CK,SW_MUX_CTL_PAD_AUD3_BB_CK Register"
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bitfld.long 0x1ec 4. " SION ,Software Input On Field" "Regular,Force input path AUD3_BB_CK"
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textline " "
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bitfld.long 0x1ec 0.--2. " MUX_MODE ,MUX Mode Select Field" "AUD3_TXC:audmux,CLK:slm,Reserved,GPIO[20]:gpio4,Reserved,Reserved,Reserved,DATAOUT[2]:usbphy"
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line.long 0x1f0 "SW_MUX_CTL_PAD_AUD3_BB_FS,SW_MUX_CTL_PAD_AUD3_BB_FS Register"
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bitfld.long 0x1f0 4. " SION ,Software Input On Field" "Regular,Force input path AUD3_BB_FS"
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textline " "
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bitfld.long 0x1f0 0.--2. " MUX_MODE ,MUX Mode Select Field" "AUD3_TXFS:audmux,TXD_MUX:uart3,Reserved,GPIO[21]:gpio4,Reserved,Reserved,Reserved,DATAOUT[3]:usbphy"
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line.long 0x1f4 "SW_MUX_CTL_PAD_CSPI1_MOSI,SW_MUX_CTL_PAD_CSPI1_MOSI Register"
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bitfld.long 0x1f4 4. " SION ,Software Input On Field" "Regular,Force input path CSPI1_MOSI"
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textline " "
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bitfld.long 0x1f4 0.--2. " MUX_MODE ,MUX Mode Select Field" "MOSI:ecspi1,SDA:i2c1,Reserved,GPIO[22]:gpio4,Reserved,Reserved,Reserved,DATAOUT[4]:usbphy"
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line.long 0x1f8 "SW_MUX_CTL_PAD_CSPI1_MISO,SW_MUX_CTL_PAD_CSPI1_MISO Register"
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bitfld.long 0x1f8 4. " SION ,Software Input On Field" "Regular,Force input path CSPI1_MISO"
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textline " "
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bitfld.long 0x1f8 0.--2. " MUX_MODE ,MUX Mode Select Field" "MISO:ecspi1,AUD4_RXD:audmux,Reserved,GPIO[23]:gpio4,Reserved,Reserved,Reserved,DATAOUT[5]:usbphy"
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line.long 0x1fc "SW_MUX_CTL_PAD_CSPI1_SS0,SW_MUX_CTL_PAD__CSPI1_SS0 Register"
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bitfld.long 0x1fc 4. " SION ,Software Input On Field" "Regular,Force input path CSPI1_SS0"
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textline " "
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bitfld.long 0x1fc 0.--2. " MUX_MODE ,MUX Mode Select Field" "SS0:ecspi1,AUD4_TXC:audmux,Reserved,GPIO[24]:gpio4,Reserved,Reserved,Reserved,DATAOUT[6]:usbphy"
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line.long 0x200 "SW_MUX_CTL_PAD_CSPI1_SS1,SW_MUX_CTL_PAD_CSPI1_SS1 Register"
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bitfld.long 0x200 4. " SION ,Software Input On Field" "Regular,Force input path CSPI1_SS1"
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textline " "
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bitfld.long 0x200 0.--2. " MUX_MODE ,MUX Mode Select Field" "SS1:ecspi1,AUD4_TXD:audmux,Reserved,GPIO[25]:gpio4,Reserved,Reserved,Reserved,DATAOUT[7]:usbphy"
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line.long 0x204 "SW_MUX_CTL_PAD_CSPI1_RDY,SW_MUX_CTL_PAD_CSPI1_RDY Register"
|
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bitfld.long 0x204 4. " SION ,Software Input On Field" "Regular,Force input path CSPI1_RDY"
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textline " "
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bitfld.long 0x204 0.--2. " MUX_MODE ,MUX Mode Select Field" "RDY:ecspi1,AUD4_TXFS:audmux,Reserved,GPIO[26]:gpio4,Reserved,Reserved,Reserved,DATAOUT[8]:usbphy"
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line.long 0x208 "SW_MUX_CTL_PAD_CSPI1_SCLK,SW_MUX_CTL_PAD_CSPI1_SCLK Register"
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bitfld.long 0x208 4. " SION ,Software Input On Field" "Regular,Force input path CSPI1_SCLK"
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textline " "
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bitfld.long 0x208 0.--2. " MUX_MODE ,MUX Mode Select Field" "SCLK:ecspi1,SCL:i2c1,Reserved,GPIO[27]:gpio4,Reserved,Reserved,Reserved,DATAOUT[9]:usbphy"
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line.long 0x20c "SW_MUX_CTL_PAD_UART1_RXD,SW_MUX_CTL_PAD_UART1_RXD Register"
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bitfld.long 0x20c 4. " SION ,Software Input On Field" "Regular,Force input path UART1_RXD"
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textline " "
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bitfld.long 0x20c 0.--2. " MUX_MODE ,MUX Mode Select Field" "RXD_MUX:uart1,Reserved,Reserved,GPIO[28]:gpio4,Reserved,READY_ESC_OUT:hsc_mipi_mix,EMI_DEBUG[12]:emi,DATAOUT[10]:usbphy"
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line.long 0x210 "SW_MUX_CTL_PAD_UART1_TXD,SW_MUX_CTL_PAD_UART1_TXD Register"
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bitfld.long 0x210 4. " SION ,Software Input On Field" "Regular,Force input path UART1_TXD"
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textline " "
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bitfld.long 0x210 0.--2. " MUX_MODE ,MUX Mode Select Field" "TXD_MUX:uart1,PWMO:pwm2,Reserved,GPIO[29]:gpio4,Reserved,REQUEST_ESC_OUT:hsc_mipi_mix,EMI_DEBUG[13]:emi,DATAOUT[11]:usbphy"
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line.long 0x214 "SW_MUX_CTL_PAD_UART1_RTS,SW_MUX_CTL_PAD_UART1_RTS Register"
|
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bitfld.long 0x214 4. " SION ,Software Input On Field" "Regular,Force input path UART1_RTS"
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textline " "
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bitfld.long 0x214 0.--2. " MUX_MODE ,MUX Mode Select Field" "RTS:uart1,Reserved,Reserved,GPIO[30]:gpio4,Reserved,CLK_ESC_OUT:hsc_mipi_mix,EMI_DEBUG[14]:emi,DATAOUT[12]:usbphy"
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line.long 0x218 "SW_MUX_CTL_PAD_UART1_CTS,SW_MUX_CTL_PAD_UART1_CTS Register"
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bitfld.long 0x218 4. " SION ,Software Input On Field" "Regular,Force input path UART1_CTS"
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textline " "
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bitfld.long 0x218 0.--2. " MUX_MODE ,MUX Mode Select Field" "CTS:uart1,Reserved,Reserved,GPIO[31]:gpio4,Reserved,READY_HS_OUT:hsc_mipi_mix,EMI_DEBUG[15]:emi,DATAOUT[13]:usbphy"
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line.long 0x21c "SW_MUX_CTL_PAD_UART2_RXD,SW_MUX_CTL_PAD_UART2_RXD Register"
|
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bitfld.long 0x21c 4. " SION ,Software Input On Field" "Regular,Force input path UART2_RXD"
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textline " "
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bitfld.long 0x21c 0.--2. " MUX_MODE ,MUX Mode Select Field" "RXD_MUX:uart2,TXD:firi,Reserved,GPIO[20]:gpio1,Reserved,VALID_HS_OUT:hsc_mipi_mix,EMI_DEBUG[16]:emi,DATAOUT[14]:usbphy"
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line.long 0x220 "SW_MUX_CTL_PAD_UART2_TXD,SW_MUX_CTL_PAD_UART2_TXD Register"
|
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bitfld.long 0x220 4. " SION ,Software Input On Field" "Regular,Force input path UART2_TXD"
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textline " "
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bitfld.long 0x220 0.--2. " MUX_MODE ,MUX Mode Select Field" "TXD_MUX:uart2,RXD:firi,Reserved,GPIO[21]:gpio1,Reserved,VALID_ESC_OUT:hsc_mipi_mix,EMI_DEBUG[17]:emi,DATAOUT[15]:usbphy"
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line.long 0x224 "SW_MUX_CTL_PAD_UART3_RXD,SW_MUX_CTL_PAD_UART3_RXD Register"
|
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bitfld.long 0x224 4. " SION ,Software Input On Field" "Regular,Force input path UART3_RXD"
|
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textline " "
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bitfld.long 0x224 0.--2. " MUX_MODE ,MUX Mode Select Field" "DTR:uart1,RXD_MUX:uart3,CSI1_D[0]:hsc_mipi_mix,GPIO[22]:gpio1,Reserved,SYNC_HS_OUT:hsc_mipi_mix,EMI_DEBUG[18]:emi,LINESTATE[0]:usbphy"
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line.long 0x228 "SW_MUX_CTL_PAD_UART3_TXD,SW_MUX_CTL_PAD_UART3_TXD Register"
|
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bitfld.long 0x228 4. " SION ,Software Input On Field" "Regular,Force input path UART3_TXD"
|
|
textline " "
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bitfld.long 0x228 0.--2. " MUX_MODE ,MUX Mode Select Field" "DSR:uart1,TXD_MUX:uart3,CSI1_D[1]:hsc_mipi_mix,GPIO[23]:gpio1,Reserved,REQUEST_HS_OUT:hsc_mipi_mix,EMI_DEBUG[19]:emi,LINESTATE[1]:usbphy"
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line.long 0x22c "SW_MUX_CTL_PAD_OWIRE_LINE,SW_MUX_CTL_PAD_OWIRE_LINE Register"
|
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bitfld.long 0x22c 4. " SION ,Software Input On Field" "Regular,Force input path OWIRE_LINE"
|
|
textline " "
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bitfld.long 0x22c 0.--2. " MUX_MODE ,MUX Mode Select Field" "LINE:owire,Reserved,Reserved,GPIO[24]:gpio1,Reserved,CTI_TRIGOUT6:tigerp_platform_ne_32k_256k,OUT1:spdif,SYSTEM_RST:src"
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line.long 0x230 "SW_MUX_CTL_PAD_KEY_ROW0,SW_MUX_CTL_PAD_KEY_ROW0 Register"
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bitfld.long 0x230 0.--2. " MUX_MODE ,MUX Mode Select Field" "ROW[0]:kpp,DSTROBE:emi,TX_DDR_Q:mipi_dphy_trippi_2_master,Reserved,Reserved,RANDOM_V:scc,EMI_DEBUG[20]:emi,?..."
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line.long 0x234 "SW_MUX_CTL_PAD_KEY_ROW1,SW_MUX_CTL_PAD_KEY_ROW1 Register"
|
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bitfld.long 0x234 0.--2. " MUX_MODE ,MUX Mode Select Field" "ROW[1]:kpp,RTIC_SEC_VIO:rtic,TX_DDR_I:mipi_dphy_trippi_2_master,Reserved,Reserved,RANDOM:scc,EMI_DEBUG[21]:emi,?..."
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line.long 0x238 "SW_MUX_CTL_PAD_KEY_ROW2,SW_MUX_CTL_PAD_KEY_ROW2 Register"
|
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bitfld.long 0x238 0.--2. " MUX_MODE ,MUX Mode Select Field" "ROW[2]:kpp,RTIC_DONE_INT:rtic,TX_DDR_Q:mipi_dphy_trippi_1_master,Reserved,Reserved,DONE:sjc,EMI_DEBUG[22]:emi,?..."
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line.long 0x23c "SW_MUX_CTL_PAD_KEY_ROW3,SW_MUX_CTL_PAD_KEY_ROW3 Register"
|
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bitfld.long 0x23c 0.--2. " MUX_MODE ,MUX Mode Select Field" "ROW[3]:kpp,CSU_ALARM_AUT[0]:csu,TX_DDR_I:mipi_dphy_trippi_1_master,Reserved,Reserved,FAIL:sjc,EMI_DEBUG[23]:emi,?..."
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line.long 0x240 "SW_MUX_CTL_PAD_KEY_COL0,SW_MUX_CTL_PAD_KEY_COL0 Register"
|
|
bitfld.long 0x240 0.--2. " MUX_MODE ,MUX Mode Select Field" "COL[0]:kpp,CSU_ALARM_AUT[1]:csu,HS_TX_E0:hsc_mipi_mix,Reserved,Reserved,Reserved,Reserved,PLL1_BYP:ccm"
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line.long 0x244 "SW_MUX_CTL_PAD_KEY_COL1,SW_MUX_CTL_PAD_KEY_COL1 Register"
|
|
bitfld.long 0x244 0.--2. " MUX_MODE ,MUX Mode Select Field" "COL[1]:kpp,CSU_ALARM_AUT[2]:csu,HS_TX_E1:hsc_mipi_mix,Reserved,Reserved,Reserved,Reserved,PLL2_BYP:ccm"
|
|
line.long 0x248 "SW_MUX_CTL_PAD_KEY_COL2,SW_MUX_CTL_PAD_KEY_COL2 Register"
|
|
bitfld.long 0x248 0.--2. " MUX_MODE ,MUX Mode Select Field" "COL[2]:kpp,SNOOP2:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,PLL3_BYP:ccm"
|
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line.long 0x24c "SW_MUX_CTL_PAD_KEY_COL3,SW_MUX_CTL_PAD_KEY_COL3 Register"
|
|
bitfld.long 0x24c 0.--2. " MUX_MODE ,MUX Mode Select Field" "COL[3]:kpp,Reserved,Reserved,Reserved,Reserved,CTI_TRIGOUT7:tigerp_platform_ne_32k_256k,Reserved,INT_BOOT:src"
|
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line.long 0x250 "SW_MUX_CTL_PAD_KEY_COL4,SW_MUX_CTL_PAD_KEY_COL4 Register"
|
|
bitfld.long 0x250 4. " SION ,Software Input On Field" "Regular,Force input path KEY_COL4"
|
|
textline " "
|
|
bitfld.long 0x250 0.--2. " MUX_MODE ,MUX Mode Select Field" "COL[4]:kpp,RI:uart1,RTS:uart3,SCL:i2c2,SSI_EXT2_CLK:ccm,CTI_TRIGIN_ACK7:tigerp_platform_ne_32k_256k,OUT1:spdif,ANY_PU_RST:src"
|
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line.long 0x254 "SW_MUX_CTL_PAD_KEY_COL5,SW_MUX_CTL_PAD_KEY_COL5 Register"
|
|
bitfld.long 0x254 4. " SION ,Software Input On Field" "Regular,Force input path KEY_COL5"
|
|
textline " "
|
|
bitfld.long 0x254 0.--2. " MUX_MODE ,MUX Mode Select Field" "COL[5]:kpp,DCD:uart1,CTS:uart3,SDA:i2c2,SSI_EXT1_CLK:ccm,CTI_TRIGIN7:tigerp_platform_ne_32k_256k,MCT_EXT_ACT_TRIG:hsc_mipi_mix,JTAG_ACT:sjc"
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line.long 0x258 "SW_MUX_CTL_PAD_JTAG_DE_B,SW_MUX_CTL_PAD_JTAG_DE_B Register"
|
|
bitfld.long 0x258 4. " SION ,Software Input On Field" "Regular,Force input path JTAG_DE_B"
|
|
line.long 0x25c "SW_MUX_CTL_PAD_USBH1_CLK,SW_MUX_CTL_PAD_USBH1_CLK Register"
|
|
bitfld.long 0x25c 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_CLK"
|
|
textline " "
|
|
bitfld.long 0x25c 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_CLK:usboh3,SCLK:cspi,GPIO[25]:gpio1,LPDT_ESC_OUT:hsc_mipi_mix,DEBUG_CORE_RUN:sdma,SCL:i2c2,EMI_DEBUG[0]:emi,CTS:uart3"
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|
line.long 0x260 "SW_MUX_CTL_PAD_USBH1_DIR,SW_MUX_CTL_PAD_USBH1_DIR Register"
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|
bitfld.long 0x260 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_DIR"
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|
textline " "
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bitfld.long 0x260 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_DIR:usboh3,MOSI:cspi,GPIO[26]:gpio1,HS_RX_Z:hsc_mipi_mix,DEBUG_MODE:sdma,SDA:i2c2,EMI_DEBUG[1]:emi,RTS:uart3"
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width 32.
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|
line.long 0x264 "SW_MUX_CTL_PAD_USBH1_STP,SW_MUX_CTL_PAD_USBH1_STP Register"
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bitfld.long 0x264 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_STP"
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|
textline " "
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bitfld.long 0x264 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_STP:usboh3,RDY:cspi,GPIO[27]:gpio1,ACTIVE_HS_OUT:hsc_mipi_mix,DEBUG_EVENT_CHANNEL_SEL:sdma,RXD_MUX:uart3,EMI_DEBUG[2]:emi,BISTOK:usbphy"
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|
line.long 0x268 "SW_MUX_CTL_PAD_USBH1_NXT,SW_MUX_CTL_PAD_USBH1_NXT Register"
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bitfld.long 0x268 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_NXT"
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|
textline " "
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bitfld.long 0x268 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_NXT:usboh3,MISO:cspi,GPIO[28]:gpio1,RX_TERM_E:hsc_mipi_mix,DEBUG_BUS_RWB:sdma,TXD_MUX:uart3,EMI_DEBUG[3]:emi,ONBIST:usbphy"
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line.long 0x26c "SW_MUX_CTL_PAD_USBH1_DATA0,SW_MUX_CTL_PAD_USBH1_DATA0 Register"
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bitfld.long 0x26c 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_DATA0"
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|
textline " "
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bitfld.long 0x26c 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_DATA0:usboh3,CTS:uart2,GPIO[11]:gpio1,DATA_ESC_OUT[0]:hsc_mipi_mix,DEBUG_CORE_STATE[2]:sdma,Reserved,EMI_DEBUG[4]:emi,VSTATUS[0]:usbphy"
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line.long 0x270 "SW_MUX_CTL_PAD_USBH1_DATA1,SW_MUX_CTL_PAD_USBH1_DATA1 Register"
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bitfld.long 0x270 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_DATA1"
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textline " "
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bitfld.long 0x270 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_DATA1:usboh3,RXD_MUX:uart2,GPIO[12]:gpio1,DATA_ESC_OUT[1]:hsc_mipi_mix,DEBUG_CORE_STATE[3]:sdma,Reserved,EMI_DEBUG[5]:emi,VSTATUS[1]:usbphy"
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line.long 0x274 "SW_MUX_CTL_PAD_USBH1_DATA2,SW_MUX_CTL_PAD_USBH1_DATA2 Register"
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bitfld.long 0x274 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_DATA2"
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|
textline " "
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bitfld.long 0x274 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_DATA2:usboh3,TXD_MUX:uart2,GPIO[13]:gpio1,DATA_ESC_OUT[2]:hsc_mipi_mix,DEBUG_MATCHED_DMBUS:sdma,Reserved,EMI_DEBUG[6]:emi,VSTATUS[2]:usbphy"
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line.long 0x278 "SW_MUX_CTL_PAD_USBH1_DATA3,SW_MUX_CTL_PAD_USBH1_DATA3 Register"
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bitfld.long 0x278 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_DATA3"
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textline " "
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bitfld.long 0x278 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_DATA3:usboh3,RTS:uart2,GPIO[14]:gpio1,DATA_ESC_OUT[3]:hsc_mipi_mix,DEBUG_BUS_DEVICE[0]:sdma,Reserved,EMI_DEBUG[7]:emi,VSTATUS[3]:usbphy"
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line.long 0x27c "SW_MUX_CTL_PAD_USBH1_DATA4,SW_MUX_CTL_PAD_USBH1_DATA4 Register"
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bitfld.long 0x27c 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_DATA4"
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textline " "
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bitfld.long 0x27c 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_DATA4:usboh3,SS0:cspi,GPIO[15]:gpio1,DATA_ESC_OUT[4]:hsc_mipi_mix,DEBUG_BUS_DEVICE[1]:sdma,Reserved,EMI_DEBUG[8]:emi,VSTATUS[4]:usbphy"
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line.long 0x280 "SW_MUX_CTL_PAD_USBH1_DATA5,SW_MUX_CTL_PAD_USBH1_DATA5 Register"
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bitfld.long 0x280 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_DATA5"
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textline " "
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bitfld.long 0x280 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_DATA5:usboh3,SS1:cspi,GPIO[16]:gpio1,DATA_ESC_OUT[5]:hsc_mipi_mix,DEBUG_BUS_DEVICE[2]:sdma,Reserved,EMI_DEBUG[9]:emi,VSTATUS[5]:usbphy"
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line.long 0x284 "SW_MUX_CTL_PAD_USBH1_DATA6,SW_MUX_CTL_PAD_USBH1_DATA6 Register"
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bitfld.long 0x284 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_DATA6"
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textline " "
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bitfld.long 0x284 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_DATA6:usboh3,SS3:cspi,GPIO[17]:gpio1,DATA_ESC_OUT[6]:hsc_mipi_mix,DEBUG_BUS_DEVICE[3]:sdma,Reserved,EMI_DEBUG[10]:emi,VSTATUS[6]:usbphy"
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line.long 0x288 "SW_MUX_CTL_PAD_USBH1_DATA7,SW_MUX_CTL_PAD_USBH1_DATA7 Register"
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bitfld.long 0x288 4. " SION ,Software Input On Field" "Regular,Force input path USBH1_DATA7"
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textline " "
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bitfld.long 0x288 0.--2. " MUX_MODE ,MUX Mode Select Field" "USBH1_DATA7:usboh3,SS3:ecspi1,GPIO[18]:gpio1,DATA_ESC_OUT[7]:hsc_mipi_mix,DEBUG_BUS_DEVICE[4]:sdma,SS3:ecspi2,EMI_DEBUG[11]:emi,VSTATUS[7]:usbphy"
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line.long 0x28c "SW_MUX_CTL_PAD_DI1_PIN11,SW_MUX_CTL_PAD_DI1_PIN11 Register"
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bitfld.long 0x28c 4. " SION ,Software Input On Field" "Regular,Force input path DI1_PIN11"
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textline " "
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bitfld.long 0x28c 0.--2. " MUX_MODE ,MUX Mode Select Field" "DI1_PIN11:ipu,READY_ESC_IN:hsc_mipi_mix,Reserved,Reserved,GPIO[0]:gpio3,Reserved,Reserved,SS2:ecspi1"
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line.long 0x290 "SW_MUX_CTL_PAD_DI1_PIN12,SW_MUX_CTL_PAD_DI1_PIN12 Register"
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bitfld.long 0x290 4. " SION ,Software Input On Field" "Regular,Force input path DI1_PIN12"
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textline " "
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bitfld.long 0x290 0.--2. " MUX_MODE ,MUX Mode Select Field" "DI1_PIN12:ipu,REQUEST_ESC_IN:hsc_mipi_mix,Reserved,Reserved,GPIO[1]:gpio3,?..."
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line.long 0x294 "SW_MUX_CTL_PAD_DI1_PIN13,SW_MUX_CTL_PAD_USBH1_DATA7 Register"
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bitfld.long 0x294 4. " SION ,Software Input On Field" "Regular,Force input path DI1_PIN13"
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textline " "
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bitfld.long 0x294 0.--2. " MUX_MODE ,MUX Mode Select Field" "DI1_PIN13:ipu,CLK_ESC_IN:hsc_mipi_mix,Reserved,Reserved,GPIO[2]:gpio3,?..."
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line.long 0x298 "SW_MUX_CTL_PAD_DI1_D0_CS,SW_MUX_CTL_PAD_DI1_D0_CS Register"
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bitfld.long 0x298 4. " SION ,Software Input On Field" "Regular,Force input path DI1_D0_CS"
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|
textline " "
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bitfld.long 0x298 0.--2. " MUX_MODE ,MUX Mode Select Field" "DI1_D0_CS:ipu,LPDT_ESC_IN:hsc_mipi_mix,Reserved,Reserved,GPIO[3]:gpio3,?..."
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line.long 0x29c "SW_MUX_CTL_PAD_DI1_D1_CS,SW_MUX_CTL_PAD_DI1_D1_CS Register"
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bitfld.long 0x29c 4. " SION ,Software Input On Field" "Regular,Force input path DI1_D1_CS"
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textline " "
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bitfld.long 0x29c 0.--2. " MUX_MODE ,MUX Mode Select Field" "DI1_D1_CS:ipu,READY_HS_IN:hsc_mipi_mix,DI1_PIN14:ipu,DI1_PIN5:ipu,GPIO[4]:gpio3,?..."
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line.long 0x2a0 "SW_MUX_CTL_PAD_DISPB2_SER_DIN,SW_MUX_CTL_PAD_DISPB2_SER Register"
|
|
bitfld.long 0x2a0 4. " SION ,Software Input On Field" "Regular,Force input path DISPB2_SER_DIN"
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textline " "
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bitfld.long 0x2a0 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISPB2_SER_DIN:ipu,VALID_HS_IN:hsc_mipi_mix,DI1_PIN1:hsc_mipi_mix,Reserved,GPIO[5]:gpio3,?..."
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line.long 0x2a4 "SW_MUX_CTL_PAD_DISPB2_SER_DI0,SW_MUX_CTL_PAD_DISPB2_SER_DI0 Register"
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bitfld.long 0x2a4 4. " SION ,Software Input On Field" "Regular,Force input path DISPB2_SER_DIO"
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textline " "
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bitfld.long 0x2a4 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISPB2_SER_DIO:ipu,ACTIVE_HS_IN:hsc_mipi_mix,Reserved,DI1_PIN6:ipu,GPIO[6]:gpio3,Reserved,WDOG_RST_B_DEB:wdog1,?..."
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line.long 0x2a8 "SW_MUX_CTL_PAD_DISPB2_SER_CLK,SW_MUX_CTL_PAD_DISPB2_SER_CLK Register"
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bitfld.long 0x2a8 4. " SION ,Software Input On Field" "Regular,Force input path DISPB2_SER_CLK"
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textline " "
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bitfld.long 0x2a8 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISPB2_SER_CLK:ipu,BYTE_CLK_HS_IN:hsc_mipi_mix,DI1_PIN17:ipu,DI1_PIN7:ipu,GPIO[7]:gpio3,Reserved,WDOG_RST_B_DEB:wdog2,?..."
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line.long 0x2ac "SW_MUX_CTL_PAD_DISPB2_SER_RS,SW_MUX_CTL_PAD_DISPB2_SER_RS Register"
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bitfld.long 0x2ac 4. " SION ,Software Input On Field" "Regular,Force input path DISPB2_SER_RS"
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textline " "
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bitfld.long 0x2ac 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISPB2_SER_RS:ipu,VALID_ESC_IN:hsc_mipi_mix,DI1_PIN16:ipu,DI1_PIN8:ipu,GPIO[8]:gpio3,?..."
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width 28.
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line.long 0x2b0 "SW_MUX_CTL_PAD_DISP1_DATO,SW_MUX_CTL_PAD_DISP1_DATO Register"
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bitfld.long 0x2b0 4. " SION ,Software Input On Field" "Regular,Force input path DISP1_DAT0"
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line.long 0x2b4 "SW_MUX_CTL_PAD_DISP1_DAT1,SW_MUX_CTL_PAD_DISP1_DAT1 Register"
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bitfld.long 0x2b4 4. " SION ,Software Input On Field" "Regular,Force input path DISP1_DAT1"
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line.long 0x2b8 "SW_MUX_CTL_PAD_DISP1_DAT2,SW_MUX_CTL_PAD_DISPB2_SER_RS Register"
|
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bitfld.long 0x2b8 4. " SION ,Software Input On Field" "Regular,Force input path DISP1_DAT2"
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line.long 0x2bc "SW_MUX_CTL_PAD_DISP1_DAT3,SW_MUX_CTL_PAD_DISP1_DAT3 Register"
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bitfld.long 0x2bc 4. " SION ,Software Input On Field" "Regular,Force input path DISP1_DAT3"
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line.long 0x2c0 "SW_MUX_CTL_PAD_DISP1_DAT4,SW_MUX_CTL_PAD_DISP1_DAT4 Register"
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bitfld.long 0x2c0 4. " SION ,Software Input On Field" "Regular,Force input path DISP1_DAT4"
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line.long 0x2c4 "SW_MUX_CTL_PAD_DISP1_DAT5,SW_MUX_CTL_PAD_DISP1_DAT5 Register"
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bitfld.long 0x2c4 4. " SION ,Software Input On Field" "Regular,Force input path DISP1_DAT5"
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line.long 0x2c8 "SW_MUX_CTL_PAD_DISP1_DAT6,SW_MUX_CTL_PAD_DISP1_DAT6 Register"
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bitfld.long 0x2c8 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[6]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_USB_SRC:src"
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line.long 0x2cc "SW_MUX_CTL_PAD_DISP1_DAT7,SW_MUX_CTL_PAD_DISP1_DAT7 Register"
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bitfld.long 0x2cc 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[7]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_EEPROM_CFG:src"
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line.long 0x2d0 "SW_MUX_CTL_PAD_DISP1_DAT8,SW_MUX_CTL_PAD_DISP1_DAT8 Register"
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bitfld.long 0x2d0 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[8]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_SRC[0]:src"
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line.long 0x2d4 "SW_MUX_CTL_PAD_DISP1_DAT9,SW_MUX_CTL_PAD_DISP1_DAT9 Register"
|
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bitfld.long 0x2d4 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[9]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_SRC[1]:src"
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line.long 0x2d8 "SW_MUX_CTL_PAD_DISP1_DAT10,SW_MUX_CTL_PAD_DISP1_DAT10 Register"
|
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bitfld.long 0x2d8 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[10]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_SPARE_SIZE:src"
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line.long 0x2dc "SW_MUX_CTL_PAD_DISP1_DAT11,SW_MUX_CTL_PAD_DISP1_DAT11 Register"
|
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bitfld.long 0x2dc 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[11]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_LPB_FREQ[2]:src"
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line.long 0x2e0 "SW_MUX_CTL_PAD_DISP1_DAT12,SW_MUX_CTL_PAD_DISP1_DAT12 Register"
|
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bitfld.long 0x2e0 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[12]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_MLC_SEL:src"
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line.long 0x2e4 "SW_MUX_CTL_PAD_DISP1_DAT13,SW_MUX_CTL_PAD_DISP1_DAT13 Register"
|
|
bitfld.long 0x2e4 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[13]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_MEM_CTL[0]:src"
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line.long 0x2e8 "SW_MUX_CTL_PAD_DISP1_DAT14,SW_MUX_CTL_PAD_DISP1_DAT14 Register"
|
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bitfld.long 0x2e8 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[14]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_MEM_CTL[1]:src"
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line.long 0x2ec "SW_MUX_CTL_PAD_DISP1_DAT15,SW_MUX_CTL_PAD_DISP1_DAT15 Register"
|
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bitfld.long 0x2ec 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[15]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_BUS_WIDTH:src"
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line.long 0x2f0 "SW_MUX_CTL_PAD_DISP1_DAT16,SW_MUX_CTL_PAD_DISP1_DAT16 Register"
|
|
bitfld.long 0x2f0 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[16]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_PAGE_SIZE[0]:src"
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line.long 0x2f4 "SW_MUX_CTL_PAD_DISP1_DAT17,SW_MUX_CTL_PAD_DISP1_DAT17 Register"
|
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bitfld.long 0x2f4 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[17]:ipu,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BT_PAGE_SIZE[1]:src"
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line.long 0x2f8 "SW_MUX_CTL_PAD_DISP1_DAT18,SW_MUX_CTL_PAD_DISP1_DAT18 Register"
|
|
bitfld.long 0x2f8 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[18]:ipu,Reserved,Reserved,Reserved,DI2_PIN5:ipu,DI2_PIN11:ipu,Reserved,BT_WEIM_MUXED[0]:src"
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line.long 0x2fc "SW_MUX_CTL_PAD_DISP1_DAT19,SW_MUX_CTL_PAD_DISP1_DAT19 Register"
|
|
bitfld.long 0x2fc 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[19]:ipu,Reserved,Reserved,Reserved,DI2_PIN6:ipu,DI2_PIN12:ipu,Reserved,BT_WEIM_MUXED[1]:src"
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line.long 0x300 "SW_MUX_CTL_PAD_DISP1_DAT20,SW_MUX_CTL_PAD_DISP1_DAT20 Register"
|
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bitfld.long 0x300 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[20]:ipu,Reserved,Reserved,Reserved,DI2_PIN7:ipu,DI2_PIN13:ipu,Reserved,BT_MEM_TYPE[0]:src"
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line.long 0x304 "SW_MUX_CTL_PAD_DISP1_DAT21,SW_MUX_CTL_PAD_DISP1_DAT21 Register"
|
|
bitfld.long 0x304 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[21]:ipu,Reserved,Reserved,Reserved,DI2_PIN8:ipu,DI2_PIN14:ipu,Reserved,BT_MEM_TYPE[1]:src"
|
|
line.long 0x308 "SW_MUX_CTL_PAD_DISP1_DAT22,SW_MUX_CTL_PAD_DISP1_DAT22 Register"
|
|
bitfld.long 0x308 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[22]:ipu,Reserved,Reserved,CTI_TRIGOUT_ACK6:tigerp_platform_ne_32k_256k,Reserved,DISP2_DAT[16]:ipu,DI2_D0_CS:ipu,BT_LPB_FREQ[0]:src"
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|
line.long 0x30c "SW_MUX_CTL_PAD_DISP1_DAT23,SW_MUX_CTL_PAD_DISP1_DAT23 Register"
|
|
bitfld.long 0x30c 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP1_DAT[23]:ipu,Reserved,Reserved,CTI_TRIGOUT_ACK7:tigerp_platform_ne_32k_256k,SER_DISP2_CS:ipu,DISP2_DAT[17]:ipu,DI2_D1_CS:ipu,BT_LPB_FREQ[1]:src"
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line.long 0x310 "SW_MUX_CTL_PAD_DI1_PIN3,SW_MUX_CTL_PAD_DI1_PIN3 Register"
|
|
bitfld.long 0x310 0.--2. " MUX_MODE ,MUX Mode Select Field" "DI1_PIN3:ipu,TX_DDR_Q:mipi_dphy_trippi_4_slave,Reserved,Reserved,Reserved,Reserved,EMI_DEBUG[24]:emi,SIM_TX_CLK_TEST:sim"
|
|
line.long 0x314 "SW_MUX_CTL_PAD_DI1_PIN2,SW_MUX_CTL_PAD_DI1_PIN2 Register"
|
|
bitfld.long 0x314 0.--2. " MUX_MODE ,MUX Mode Select Field" "DI1_PIN2:ipu,TX_DDR_I:mipi_dphy_trippi_4_slave,Reserved,Reserved,Reserved,Reserved,EMI_DEBUG[25]:emi,SIM_RCV_CLK_TEST:sim"
|
|
line.long 0x318 "SW_MUX_CTL_PAD_DI_GP1,SW_MUX_CTL_PAD_DI_GP1 Register"
|
|
bitfld.long 0x318 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISPB1_SER_RS:ipu,RX_VALID_ESC_IN:hsc_mipi_mix,DI1_EXT_CLK:ccm,Reserved,Reserved,Reserved,EMI_DEBUG[26]:emi,?..."
|
|
line.long 0x31c "SW_MUX_CTL_PAD_DI_GP,SW_MUX_CTL_PAD_DI_GP2 Register"
|
|
bitfld.long 0x31c 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISPB1_SER_CLK:ipu,SYNC_HS_IN:hsc_mipi_mix,DI2_WAIT:hsc_mipi_mix,Reserved,Reserved,Reserved,EMI_DEBUG[27]:emi,?..."
|
|
line.long 0x320 "SW_MUX_CTL_PAD_DI_GP3,SW_MUX_CTL_PAD_DI_GP3 Register"
|
|
bitfld.long 0x320 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISPB1_SER_DIO:ipu,REQUEST_HS_IN:hsc_mipi_mix,TX_ER:fec,CSI1_DATA_EN:hsc_mipi_mix,Reserved,Reserved,EMI_DEBUG[28]:emi,?..."
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|
line.long 0x324 "SW_MUX_CTL_PAD_DI2_PIN4,SW_MUX_CTL_PAD_DI2_PIN4 Register"
|
|
bitfld.long 0x324 0.--2. " MUX_MODE ,MUX Mode Select Field" "DI2_PIN4:ipu,DATA_HS_IN[0]:hsc_mipi_mix,CRS:fec,CSI2_DATA_EN:hsc_mipi_mix,Reserved,Reserved,EMI_DEBUG[29]:emi,?..."
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|
line.long 0x328 "SW_MUX_CTL_PAD_DI2_PIN2,SW_MUX_CTL_PAD_DI2_PIN2 Register"
|
|
bitfld.long 0x328 0.--2. " MUX_MODE ,MUX Mode Select Field" "DI2_PIN2:ipu,DATA_HS_IN[1]:hsc_mipi_mix,MDC:fec,Reserved,Reserved,Reserved,EMI_DEBUG[30]:emi,?..."
|
|
line.long 0x32c "SW_MUX_CTL_PAD_DI2_PIN3,SW_MUX_CTL_PAD_DI2_PIN3 Register"
|
|
bitfld.long 0x32c 0.--2. " MUX_MODE ,MUX Mode Select Field" "DI2_PIN3:ipu,DATA_HS_IN[2]:hsc_mipi_mix,MDIO:fec,Reserved,Reserved,Reserved,EMI_DEBUG[31]:emi,?..."
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|
line.long 0x330 "SW_MUX_CTL_PAD_DI2_DISP_CLK,SW_MUX_CTL_PAD_DI2_DISP_CLK Register"
|
|
bitfld.long 0x330 0.--1. " MUX_MODE ,MUX Mode Select Field" "DI2_DISP_CLK:ipu,Reserved,RDATA[1]:fec,?..."
|
|
line.long 0x334 "SW_MUX_CTL_PAD_DI_GP4,SW_MUX_CTL_PAD_DI_GP4 Register"
|
|
bitfld.long 0x334 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISPB1_SER_DIN:ipu,DATA_HS_IN[3]:hsc_mipi_mix,RDATA[2]:fec,DI2_PIN1:hsc_mipi_mix,DI2_PIN15:ipu,Reserved,EMI_DEBUG[32]:emi,?..."
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|
line.long 0x338 "SW_MUX_CTL_PAD_DISP2_DAT0,SW_MUX_CTL_PAD_DISP2_DAT0 Register"
|
|
bitfld.long 0x338 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[0]:ipu,DATA_HS_IN[4]:hsc_mipi_mix,RDATA[3]:fec,USBH3_CLK:usboh3,COL[6]:kpp,RXD_MUX:uart3,EMI_DEBUG[33]:emi,?..."
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|
line.long 0x33c "SW_MUX_CTL_PAD_DISP2_DAT1,SW_MUX_CTL_PAD_DISP2_DAT1 Register"
|
|
bitfld.long 0x33c 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[1]:ipu,DATA_HS_IN[5]:hsc_mipi_mix,RX_ER:fec,USBH3_DIR:usboh3,COL[7]:kpp,TXD_MUX:uart3,EMI_DEBUG[34]:emi,?..."
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|
line.long 0x340 "SW_MUX_CTL_PAD_DISP2_DAT2,SW_MUX_CTL_PAD_DISP2_DAT2 Register"
|
|
bitfld.long 0x340 4. " SION ,Software Input On Field" "Regular,Force input path DISP2_DAT2"
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|
line.long 0x344 "SW_MUX_CTL_PAD_DISP2_DAT3,SW_MUX_CTL_PAD_DISP2_DAT3 Register"
|
|
bitfld.long 0x344 4. " SION ,Software Input On Field" "Regular,Force input path DISP2_DAT3"
|
|
line.long 0x348 "SW_MUX_CTL_PAD_DISP2_DAT4,SW_MUX_CTL_PAD_DISP2_DAT4 Register"
|
|
bitfld.long 0x348 4. " SION ,Software Input On Field" "Regular,Force input path DISP2_DAT4"
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|
line.long 0x34c "SW_MUX_CTL_PAD_DISP2_DAT5,SW_MUX_CTL_PAD_DISP2_DAT5 Register"
|
|
bitfld.long 0x34c 4. " SION ,Software Input On Field" "Regular,Force input path DISP2_DAT5"
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|
line.long 0x350 "SW_MUX_CTL_PAD_DISP2_DAT6,SW_MUX_CTL_PAD_DISP2_DAT6 Register"
|
|
bitfld.long 0x350 4. " SION ,Software Input On Field" "Regular,Force input path DISP2_DAT6"
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|
textline " "
|
|
bitfld.long 0x350 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[6]:ipu,DATA_HS_IN[6]:hsc_mipi_mix,TDATA[1]:fec,USBH3_STP:usboh3,ROW[4]:kpp,GPIO[19]:gpio1,EMI_DEBUG[35]:emi,?..."
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|
line.long 0x354 "SW_MUX_CTL_PAD_DISP2_DAT7,SW_MUX_CTL_PAD_DISP2_DAT7 Register"
|
|
bitfld.long 0x354 4. " SION ,Software Input On Field" "Regular,Force input path DISP2_DAT7"
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|
textline " "
|
|
bitfld.long 0x354 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[7]:ipu,DATA_HS_IN[7]:hsc_mipi_mix,TDATA[2]:fec,USBH3_NXT:usboh3,ROW[5]:kpp,GPIO[29]:gpio1,EMI_DEBUG[36]:emi,?..."
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|
line.long 0x358 "SW_MUX_CTL_PAD_DISP2_DAT8,SW_MUX_CTL_PAD_DISP2_DAT8 Register"
|
|
bitfld.long 0x358 4. " SION ,Software Input On Field" "Regular,Force input path DISP2_DAT8"
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|
textline " "
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bitfld.long 0x358 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[8]:ipu,DATA_ESC_IN[0]:hsc_mipi_mix,TDATA[3]:fec,USBH3_DATA0:usboh3,ROW[6]:kpp,GPIO[30]:gpio1,EMI_DEBUG[37]:emi,?..."
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line.long 0x35c "SW_MUX_CTL_PAD_DISP2_DAT9,SW_MUX_CTL_PAD_DISP2_DAT9 Register"
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bitfld.long 0x35c 4. " SION ,Software Input On Field" "Regular,Force input path DISP2_DAT9"
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|
textline " "
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bitfld.long 0x35c 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[9]:ipu,DATA_ESC_IN[1]:hsc_mipi_mix,TX_EN:fec,USBH3_DATA1:usboh3,AUD6_RXC:audmux,GPIO[31]:gpio1,EMI_DEBUG[38]:emi,?..."
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line.long 0x360 "SW_MUX_CTL_PAD_DISP2_DAT10,SW_MUX_CTL_PAD_DISP2_DAT10 Register"
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bitfld.long 0x360 4. " SION ,Software Input On Field" "Regular,Force input path DISP2_DAT10"
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textline " "
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bitfld.long 0x360 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[10]:ipu,DATA_ESC_IN[2]:hsc_mipi_mix,COL:fec,USBH3_DATA2:usboh3,ROW[7]:kpp,SER_DISP2_CS:ipu,EMI_DEBUG[39]:emi,?..."
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|
line.long 0x364 "SW_MUX_CTL_PAD_DISP2_DAT11,SW_MUX_CTL_PAD_DISP2_DAT11 Register"
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bitfld.long 0x364 4. " SION ,Software Input On Field" "Regular,Force input path DISP2_DAT11"
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textline " "
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bitfld.long 0x364 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[11]:ipu,DATA_ESC_IN[3]:hsc_mipi_mix,RX_CLK:fec,USBH3_DATA3:usboh3,AUD6_TXD:audmux,Reserved,EMI_DEBUG[40]:emi,?..."
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|
line.long 0x368 "SW_MUX_CTL_PAD_DISP2_DAT12,SW_MUX_CTL_PAD_DISP2_DAT12 Register"
|
|
bitfld.long 0x368 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[12]:ipu,DATA_ESC_IN[4]:hsc_mipi_mix,RX_DV:fec,USBH3_DATA4:usboh3,AUD6_RXD:audmux,Reserved,EMI_DEBUG[41]:emi,?..."
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line.long 0x36c "SW_MUX_CTL_PAD_DISP2_DAT13,SW_MUX_CTL_PAD_DISP2_DAT13 Register"
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bitfld.long 0x36c 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[13]:ipu,DATA_ESC_IN[5]:hsc_mipi_mix,TX_CLK:fec,USBH3_DATA5:usboh3,AUD6_TXC:audmux,Reserved,EMI_DEBUG[42]:emi,?..."
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|
line.long 0x370 "SW_MUX_CTL_PAD_DISP2_DAT14,SW_MUX_CTL_PAD_DISP2_DAT14 Register"
|
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bitfld.long 0x370 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[14]:ipu,DATA_ESC_IN[6]:hsc_mipi_mix,RDATA[0]:fec,USBH3_DATA6:usboh3,AUD6_TXFS:audmux,Reserved,EMI_DEBUG[43]:emi,?..."
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|
line.long 0x374 "SW_MUX_CTL_PAD_DISP2_DAT15,SW_MUX_CTL_PAD_DISP2_DAT15 Register"
|
|
bitfld.long 0x374 0.--2. " MUX_MODE ,MUX Mode Select Field" "DISP2_DAT[15]:ipu,DATA_ESC_IN[7]:hsc_mipi_mix,TDATA[0]:fec,USBH3_DATA7:usboh3,AUD6_RXFS:audmux,SER_DISP1_CS:ipu,EMI_DEBUG[44]:emi,?..."
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|
line.long 0x378 "SW_MUX_CTL_PAD_SD1_CMD,SW_MUX_CTL_PAD_SD1_CMD Register"
|
|
bitfld.long 0x378 4. " SION ,Software Input On Field" "Regular,Force input path SD1_CMD"
|
|
textline " "
|
|
bitfld.long 0x378 0.--1. " MUX_MODE ,MUX Mode Select Field" "CMD:esdhc1,AUD5_RXFS:audmux,MOSI:cspi,?..."
|
|
line.long 0x37c "SW_MUX_CTL_PAD_SD1_CLK,SW_MUX_CTL_PAD_SD1_CLK Register"
|
|
bitfld.long 0x37c 0.--1. " MUX_MODE ,MUX Mode Select Field" "CLK:esdhc1,AUD5_RXC:audmux,SCLK:cspi,?..."
|
|
line.long 0x380 "SW_MUX_CTL_PAD_SD1_DATA0,SW_MUX_CTL_PAD_SD1_DATA0 Register"
|
|
bitfld.long 0x380 4. " SION ,Software Input On Field" "Regular,Force input path SD1_DATA0"
|
|
textline " "
|
|
bitfld.long 0x380 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT0:esdhc1,AUD5_TXD:audmux,MISO:cspi,?..."
|
|
line.long 0x384 "SW_MUX_CTL_PAD_SD1_DATA1,SW_MUX_CTL_PAD_SD1_DATA1 Register"
|
|
bitfld.long 0x384 4. " SION ,Software Input On Field" "Regular,Force input path SD1_DATA1"
|
|
textline " "
|
|
bitfld.long 0x384 0. " MUX_MODE ,MUX Mode Select Field" "DAT1:esdhc1,AUD5_RXD:audmux"
|
|
line.long 0x388 "SW_MUX_CTL_PAD_SD1_DATA2,SW_MUX_CTL_PAD_SD1_DATA2 Register"
|
|
bitfld.long 0x388 4. " SION ,Software Input On Field" "Regular,Force input path SD1_DATA2"
|
|
textline " "
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|
bitfld.long 0x388 0. " MUX_MODE ,MUX Mode Select Field" "DAT2:esdhc1,AUD5_TXC:audmux"
|
|
line.long 0x38c "SW_MUX_CTL_PAD_SD1_DATA3,SW_MUX_CTL_PAD_SD1_DATA3 Register"
|
|
bitfld.long 0x38c 4. " SION ,Software Input On Field" "Regular,Force input path SD1_DATA3"
|
|
textline " "
|
|
bitfld.long 0x38c 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT3:esdhc1,AUD5_TXFS:audmux,SS1:cspi,?..."
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|
line.long 0x390 "SW_MUX_CTL_PAD_GPIO1_0,SW_MUX_CTL_PAD_GPIO1_0 Register"
|
|
bitfld.long 0x390 4. " SION ,Software Input On Field" "Regular,Force input path GPIO1_0"
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|
textline " "
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bitfld.long 0x390 0.--2. " MUX_MODE ,MUX Mode Select Field" "CD:esdhc1,GPIO[0]:gpio1,SS2:cspi,?..."
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line.long 0x394 "SW_MUX_CTL_PAD_GPIO1_1,SW_MUX_CTL_PAD_GPIO1_1 Register"
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bitfld.long 0x394 4. " SION ,Software Input On Field" "Regular,Force input path GPIO1_1"
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textline " "
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bitfld.long 0x394 0.--2. " MUX_MODE ,MUX Mode Select Field" "WP:esdhc1,GPIO[1]:gpio1,MISO:cspi,?..."
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line.long 0x398 "SW_MUX_CTL_PAD_SD2_CMD,SW_MUX_CTL_PAD_SD2_CMD Register"
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bitfld.long 0x398 4. " SION ,Software Input On Field" "Regular,Force input path SD2_CMD"
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textline " "
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bitfld.long 0x398 0.--1. " MUX_MODE ,MUX Mode Select Field" "CMD:esdhc2,SCL:i2c1,MOSI:cspi,?..."
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line.long 0x39c "SW_MUX_CTL_PAD_SD2_CLK,SW_MUX_CTL_PAD_SD2_CLK Register"
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bitfld.long 0x39c 4. " SION ,Software Input On Field" "Regular,Force input path SD2_CLK"
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|
textline " "
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bitfld.long 0x39c 0.--1. " MUX_MODE ,MUX Mode Select Field" "CLK:esdhc2,SDA:i2c1,SCLK:cspi,?..."
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line.long 0x3a0 "SW_MUX_CTL_PAD_SD2_DATA0,SW_MUX_CTL_PAD_SD2_DATA0 Register"
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bitfld.long 0x3a0 4. " SION ,Software Input On Field" "Regular,Force input path SD2_DATA0"
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|
textline " "
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bitfld.long 0x3a0 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT0:esdhc2,DAT4:esdhc1,MISO:cspi,?..."
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line.long 0x3a4 "SW_MUX_CTL_PAD_SD2_DATA1,SW_MUX_CTL_PAD_SD2_DATA1 Register"
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bitfld.long 0x3a4 4. " SION ,Software Input On Field" "Regular,Force input path SD2_DATA1"
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textline " "
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|
bitfld.long 0x3a4 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT1:esdhc2,DAT5:esdhc1,H2_DP:usboh3,?..."
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line.long 0x3a8 "SW_MUX_CTL_PAD_SD2_DATA2,SW_MUX_CTL_PAD_SD2_DATA2 Register"
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bitfld.long 0x3a8 4. " SION ,Software Input On Field" "Regular,Force input path SD2_DATA2"
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|
textline " "
|
|
bitfld.long 0x3a8 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT2:esdhc2,DAT6:esdhc1,H2_DM:usboh3,?..."
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|
line.long 0x3ac "SW_MUX_CTL_PAD_SD2_DATA3,SW_MUX_CTL_PAD_SD2_DATA3 Register"
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bitfld.long 0x3ac 4. " SION ,Software Input On Field" "Regular,Force input path SD2_DATA3"
|
|
textline " "
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bitfld.long 0x3ac 0.--1. " MUX_MODE ,MUX Mode Select Field" "DAT3:esdhc2,DAT7:esdhc1,SS2:cspi,?..."
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line.long 0x3b0 "SW_MUX_CTL_PAD_GPIO1_2,SW_MUX_CTL_PAD_GPIO1_2 Register"
|
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bitfld.long 0x3b0 4. " SION ,Software Input On Field" "Regular,Force input path GPIO1_2"
|
|
textline " "
|
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bitfld.long 0x3b0 0.--2. " MUX_MODE ,MUX Mode Select Field" "GPIO[2]:gpio1,PWMO:pwm1,SCL:i2c2,Reserved,Reserved,CCM_OUT_2:ccm,TOG_EN:dpllip1,PLL1_BYP:ccm"
|
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line.long 0x3b4 "SW_MUX_CTL_PAD_GPIO1_3,SW_MUX_CTL_PAD_GPIO1_3 Register"
|
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bitfld.long 0x3b4 4. " SION ,Software Input On Field" "Regular,Force input path GPIO1_3"
|
|
textline " "
|
|
bitfld.long 0x3b4 0.--2. " MUX_MODE ,MUX Mode Select Field" "GPIO[3]:gpio1,PWMO:pwm2,SDA:i2c2,Reserved,Reserved,CLKO2:ccm,CLKIN:gpt,PLL2_BYP:ccm"
|
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line.long 0x3b8 "SW_MUX_CTL_PAD_PMIC_INT_REQ,SW_MUX_CTL_PAD_PMIC_INT_REQ Register"
|
|
bitfld.long 0x3b8 0. " MUX_MODE ,MUX Mode Select Field" "PWRFAIL_INT:tzic,PMU_IRQ_B:tigerp_platform_ne_32k_256k"
|
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line.long 0x3bc "SW_MUX_CTL_PAD_GPIO1_4,SW_MUX_CTL_PAD_GPIO1_4 Register"
|
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bitfld.long 0x3bc 4. " SION ,Software Input On Field" "Regular,Force input path GPIO1_4"
|
|
textline " "
|
|
bitfld.long 0x3bc 0.--2. " MUX_MODE ,MUX Mode Select Field" "GPIO[4]:gpio1,SDMA_EXT_EVENT[0]:sdma,WDOG_B:wdog1,RDY:emi,DI2_EXT_CLK:ipu,Reserved,CAPIN1:gpt,TOG_EN:dpllip1"
|
|
line.long 0x3c0 "SW_MUX_CTL_PAD_GPIO1_5,SW_MUX_CTL_PAD_GPIO1_5 Register"
|
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bitfld.long 0x3c0 4. " SION ,Software Input On Field" "Regular,Force input path GPIO1_5"
|
|
textline " "
|
|
bitfld.long 0x3c0 0.--2. " MUX_MODE ,MUX Mode Select Field" "GPIO[5]:gpio1,SDMA_EXT_EVENT[1]:sdma,WDOG_B:wdog2,DI2_PIN16:ipu,Reserved,CLKO:ccm,CSI2_MCLK:ccm,?..."
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line.long 0x3c4 "SW_MUX_CTL_PAD_GPIO1_6,SW_MUX_CTL_PAD_GPIO1_6 Register"
|
|
bitfld.long 0x3c4 4. " SION ,Software Input On Field" "Regular,Force input path GPIO1_6"
|
|
textline " "
|
|
bitfld.long 0x3c4 0.--2. " MUX_MODE ,MUX Mode Select Field" "GPIO[6]:gpio1,SSI_EXT2_CLK:ccm,MCT_EXT_ACT_TRIG:hsc_mipi_mix,REF_EN_B:ccm,DI2_PIN17:ipu,EPITO:epit2,CAPIN2:gpt,TD:csu"
|
|
line.long 0x3c8 "SW_MUX_CTL_PAD_GPIO1_7,SW_MUX_CTL_PAD_GPIO1_7 Register"
|
|
bitfld.long 0x3c8 4. " SION ,Software Input On Field" "Regular,Force input path GPIO1_7"
|
|
textline " "
|
|
bitfld.long 0x3c8 0.--2. " MUX_MODE ,MUX Mode Select Field" "GPIO[7]:gpio1,SSI_EXT1_CLK:ccm,OUT1:spdif,CCM_OUT_0:ccm,Reserved,EPITO:epit1,WP:esdhc2,TOG_EN:dpllip1"
|
|
line.long 0x3cc "SW_MUX_CTL_PAD_GPIO1_8,SW_MUX_CTL_PAD_GPIO1_8 Register"
|
|
bitfld.long 0x3cc 4. " SION ,Software Input On Field" "Regular,Force input path GPIO1_8"
|
|
textline " "
|
|
bitfld.long 0x3cc 0.--2. " MUX_MODE ,MUX Mode Select Field" "GPIO[8]:gpio1,USB_PWR:usboh3,CSI2_DATA_EN:hsc_mipi_mix,Reserved,CLKO2:ccm,Reserved,CD:esdhc2,TESTER_ACK:src"
|
|
line.long 0x3d0 "SW_MUX_CTL_PAD_GPIO1_9,SW_MUX_CTL_PAD_GPIO1_9 Register"
|
|
bitfld.long 0x3d0 4. " SION ,Software Input On Field" "Regular,Force input path GPIO1_9"
|
|
textline " "
|
|
bitfld.long 0x3d0 0.--2. " MUX_MODE ,MUX Mode Select Field" "GPIO[9]:gpio1,USB_OC:usboh3,DI2_D1_CS:ipu,CCM_OUT_1:ccm,CLKO:ccm,Reserved,LCTL:esdhc2,SER_DISP2_CS:ipu"
|
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tree.end
|
|
width 32.
|
|
tree "SW_PAD_CTL_PAD Registers"
|
|
group.long 0x3f0--0x81b
|
|
line.long 0x0 "SW_PAD_CTL_PAD_EIM_D16,SW_PAD_CTL_EIM_D16 Register"
|
|
bitfld.long 0x0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x0 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x4 "SW_PAD_CTL_PAD_EIM_D17,SW_PAD_CTL_EIM_D17 Register"
|
|
bitfld.long 0x4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x8 "SW_PAD_CTL_PAD_EIM_D18,SW_PAD_CTL_EIM_D18 Register"
|
|
bitfld.long 0x8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xC "SW_PAD_CTL_PAD_EIM_D19,SW_PAD_CTL_EIM_D19 Register"
|
|
bitfld.long 0xC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x10 "SW_PAD_CTL_PAD_EIM_D20,SW_PAD_CTL_EIM_D20 Register"
|
|
bitfld.long 0x10 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x10 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x10 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x14 "SW_PAD_CTL_PAD_EIM_D21,SW_PAD_CTL_EIM_D21 Register"
|
|
bitfld.long 0x14 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x14 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x14 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x18 "SW_PAD_CTL_PAD_EIM_D22,SW_PAD_CTL_EIM_D22 Register"
|
|
bitfld.long 0x18 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x18 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x18 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1C "SW_PAD_CTL_PAD_EIM_D23,SW_PAD_CTL_EIM_D23 Register"
|
|
bitfld.long 0x1C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x1C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x20 "SW_PAD_CTL_PAD_EIM_D24,SW_PAD_CTL_EIM_D24 Register"
|
|
bitfld.long 0x20 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x20 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x20 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x24 "SW_PAD_CTL_PAD_EIM_D25,SW_PAD_CTL_EIM_D25 Register"
|
|
bitfld.long 0x24 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x24 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x24 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x28 "SW_PAD_CTL_PAD_EIM_D26,SW_PAD_CTL_EIM_D26 Register"
|
|
bitfld.long 0x28 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x28 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x28 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2C "SW_PAD_CTL_PAD_EIM_D27,SW_PAD_CTL_EIM_D27 Register"
|
|
bitfld.long 0x2C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x30 "SW_PAD_CTL_PAD_EIM_D28,SW_PAD_CTL_EIM_D28 Register"
|
|
bitfld.long 0x30 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x30 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x30 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x30 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x34 "SW_PAD_CTL_PAD_EIM_D29,SW_PAD_CTL_EIM_D29 Register"
|
|
bitfld.long 0x34 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x34 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x34 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x34 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x38 "SW_PAD_CTL_PAD_EIM_D30,SW_PAD_CTL_EIM_D30 Register"
|
|
bitfld.long 0x38 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x38 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x38 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x38 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x3C "SW_PAD_CTL_PAD_EIM_D31,SW_PAD_CTL_EIM_D31 Register"
|
|
bitfld.long 0x3C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x3C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x3C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x3C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x40 "SW_PAD_CTL_PAD_EIM_A16,SW_PAD_CTL_EIM_A16 Register"
|
|
bitfld.long 0x40 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x44 "SW_PAD_CTL_PAD_EIM_A17,SW_PAD_CTL_EIM_A17 Register"
|
|
bitfld.long 0x44 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x48 "SW_PAD_CTL_PAD_EIM_A18,SW_PAD_CTL_EIM_A18 Register"
|
|
bitfld.long 0x48 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x4C "SW_PAD_CTL_PAD_EIM_A19,SW_PAD_CTL_EIM_A19 Register"
|
|
bitfld.long 0x4C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x50 "SW_PAD_CTL_PAD_EIM_A20,SW_PAD_CTL_EIM_A20 Register"
|
|
bitfld.long 0x50 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x54 "SW_PAD_CTL_PAD_EIM_A21,SW_PAD_CTL_EIM_A21 Register"
|
|
bitfld.long 0x54 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x58 "SW_PAD_CTL_PAD_EIM_A22,SW_PAD_CTL_EIM_A22 Register"
|
|
bitfld.long 0x58 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x5C "SW_PAD_CTL_PAD_EIM_A23,SW_PAD_CTL_EIM_A23 Register"
|
|
bitfld.long 0x5C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x60 "SW_PAD_CTL_PAD_EIM_A24,SW_PAD_CTL_EIM_A24 Register"
|
|
bitfld.long 0x60 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x64 "SW_PAD_CTL_PAD_EIM_A25,SW_PAD_CTL_EIM_A25 Register"
|
|
bitfld.long 0x64 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x68 "SW_PAD_CTL_PAD_EIM_A26,SW_PAD_CTL_EIM_A26 Register"
|
|
bitfld.long 0x68 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x6C "SW_PAD_CTL_PAD_EIM_A27,SW_PAD_CTL_EIM_A27 Register"
|
|
bitfld.long 0x6C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
line.long 0x70 "SW_PAD_CTL_PAD_EIM_EB0,SW_PAD_CTL_EIM_EB0 Register"
|
|
bitfld.long 0x70 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x70 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x74 "SW_PAD_CTL_PAD_EIM_EB1,SW_PAD_CTL_EIM_EB1 Register"
|
|
bitfld.long 0x74 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x74 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x78 "SW_PAD_CTL_PAD_EIM_EB2,SW_PAD_CTL_EIM_EB2 Register"
|
|
bitfld.long 0x78 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x78 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x78 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x78 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x7C "SW_PAD_CTL_PAD_EIM_EB3,SW_PAD_CTL_EIM_EB3 Register"
|
|
bitfld.long 0x7C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x7C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x7C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x80 "SW_PAD_CTL_PAD_EIM_OE,SW_PAD_CTL_EIM_OE Register"
|
|
bitfld.long 0x80 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x80 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x84 "SW_PAD_CTL_PAD_EIM_CS0,SW_PAD_CTL_EIM_CS0 Register"
|
|
bitfld.long 0x84 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x84 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x88 "SW_PAD_CTL_PAD_EIM_CS1,SW_PAD_CTL_EIM_CS1 Register"
|
|
bitfld.long 0x88 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x88 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x8C "SW_PAD_CTL_PAD_EIM_CS2,SW_PAD_CTL_EIM_CS2 Register"
|
|
bitfld.long 0x8C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x8C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x8C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x90 "SW_PAD_CTL_PAD_EIM_CS3,SW_PAD_CTL_EIM_CS3 Register"
|
|
bitfld.long 0x90 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x90 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x90 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x94 "SW_PAD_CTL_PAD_EIM_CS4,SW_PAD_CTL_EIM_CS4 Register"
|
|
bitfld.long 0x94 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x94 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x94 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x98 "SW_PAD_CTL_PAD_EIM_CS5,SW_PAD_CTL_EIM_CS5 Register"
|
|
bitfld.long 0x98 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x98 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x98 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x9C "SW_PAD_CTL_PAD_EIM_DTACK,SW_PAD_CTL_EIM_DTACK Register"
|
|
bitfld.long 0x9C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x9C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xA0 "SW_PAD_CTL_PAD_EIM_WAIT,SW_PAD_CTL_EIM_WAIT Register"
|
|
bitfld.long 0xA0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xA4 "SW_PAD_CTL_PAD_EIM_LBA,SW_PAD_CTL_EIM_LBA Register"
|
|
bitfld.long 0xA4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xA4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xA8 "SW_PAD_CTL_PAD_EIM_BCLK,SW_PAD_CTL_EIM_BCLK Register"
|
|
bitfld.long 0xA8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xA8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xAC "SW_PAD_CTL_PAD_EIM_RW,SW_PAD_CTL_EIM_RW Register"
|
|
bitfld.long 0xAC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xAC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xB0 "SW_PAD_CTL_PAD_EIM_CRE,SW_PAD_CTL_EIM_CRE Register"
|
|
bitfld.long 0xB0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xB0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xB4 "SW_PAD_CTL_PAD_DRAM_RAS,SW_PAD_CTL_DRAM_RAS Register"
|
|
bitfld.long 0xB4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xB4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xB8 "SW_PAD_CTL_PAD_DRAM_CAS,SW_PAD_CTL_DRAM_CAS Register"
|
|
bitfld.long 0xB8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xB8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xBC "SW_PAD_CTL_PAD_DRAM_SDWE,SW_PAD_CTL_DRAM_SDWE Register"
|
|
bitfld.long 0xBC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xBC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xBC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xBC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xC0 "SW_PAD_CTL_PAD_DRAM_SDCKE0,SW_PAD_CTL_DRAM_SDCKE0 Register"
|
|
bitfld.long 0xC0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xC0 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xC0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xC0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xC4 "SW_PAD_CTL_PAD_DRAM_SDCKE1,SW_PAD_CTL_DRAM_SDCKE1 Register"
|
|
bitfld.long 0xC4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xC4 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xC4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xC4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xC8 "SW_PAD_CTL_PAD_DRAM_SDCLK,SW_PAD_CTL_DRAM_SDCLK Register"
|
|
bitfld.long 0xC8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xC8 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xC8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xC8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xCC "SW_PAD_CTL_PAD_DRAM_SDQS0,SW_PAD_CTL_DRAM_SDQS0 Register"
|
|
bitfld.long 0xCC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xCC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xCC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xCC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xCC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xCC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xD0 "SW_PAD_CTL_PAD_DRAM_SDQS1,SW_PAD_CTL_DRAM_SDQS1 Register"
|
|
bitfld.long 0xD0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xD0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xD0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xD0 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xD0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xD0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xD4 "SW_PAD_CTL_PAD_DRAM_SDQS2,SW_PAD_CTL_DRAM_SDQS2 Register"
|
|
bitfld.long 0xD4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xD4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xD4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xD4 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xD4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xD4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xD8 "SW_PAD_CTL_PAD_DRAM_SDQS3,SW_PAD_CTL_DRAM_SDQS3 Register"
|
|
bitfld.long 0xD8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xD8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xD8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xD8 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xD8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xD8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xDC "SW_PAD_CTL_PAD_DRAM_CS0,SW_PAD_CTL_DRAM_CS0 Register"
|
|
bitfld.long 0xDC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xDC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xDC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xDC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xDC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xE0 "SW_PAD_CTL_PAD_DRAM_CS1,SW_PAD_CTL_DRAM_CS1 Register"
|
|
bitfld.long 0xE0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xE0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xE0 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xE0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xE0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xE4 "SW_PAD_CTL_PAD_DRAM_DQM0,SW_PAD_CTL_DRAM_DQM0 Register"
|
|
bitfld.long 0xE4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xE4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xE4 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xE4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xE4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xE8 "SW_PAD_CTL_PAD_DRAM_DQM1,SW_PAD_CTL_DRAM_DQM1 Register"
|
|
bitfld.long 0xE8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xE8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xE8 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xE8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xE8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xEC "SW_PAD_CTL_PAD_DRAM_DQM2,SW_PAD_CTL_DRAM_DQM2 Register"
|
|
bitfld.long 0xEC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xEC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xEC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xEC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xEC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xF0 "SW_PAD_CTL_PAD_DRAM_DQM3,SW_PAD_CTL_DRAM_DQM3 Register"
|
|
bitfld.long 0xF0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xF0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0xF0 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xF0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0xF0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xF4 "SW_PAD_CTL_PAD_NANDF_WE_B,SW_PAD_CTL_NANDF_WE_B Register"
|
|
bitfld.long 0xF4 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0xF4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xF4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xF4 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xF4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0xF8 "SW_PAD_CTL_PAD_NANDF_RE_B,SW_PAD_CTL_NANDF_RE_B Register"
|
|
bitfld.long 0xF8 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0xF8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xF8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xF8 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0xF8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0xFC "SW_PAD_CTL_PAD_NANDF_ALE,SW_PAD_CTL_NANDF_ALE Register"
|
|
bitfld.long 0xFC 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0xFC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xFC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x100 "SW_PAD_CTL_PAD_NANDF_CLE,SW_PAD_CTL_NANDF_CLE Register"
|
|
bitfld.long 0x100 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x100 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x100 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x104 "SW_PAD_CTL_PAD_NANDF_WP_B,SW_PAD_CTL_NANDF_WP_B Register"
|
|
bitfld.long 0x104 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x104 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x104 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x104 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x104 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x108 "SW_PAD_CTL_PAD_NANDF_RB0,SW_PAD_CTL_NANDF_RB0 Register"
|
|
bitfld.long 0x108 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x108 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x108 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x108 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x108 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x108 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x10C "SW_PAD_CTL_PAD_NANDF_RB1,SW_PAD_CTL_NANDF_RB1 Register"
|
|
bitfld.long 0x10C 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x10C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x10C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x10C 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x110 "SW_PAD_CTL_PAD_NANDF_RB2,SW_PAD_CTL_NANDF_RB2 Register"
|
|
bitfld.long 0x110 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x110 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x110 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x110 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x110 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x110 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x110 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x114 "SW_PAD_CTL_PAD_NANDF_RB3,SW_PAD_CTL_NANDF_RB3 Register"
|
|
bitfld.long 0x114 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x114 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x114 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x114 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x114 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x114 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x114 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x118 "SW_PAD_CTL_PAD_EIM_SDBA2,SW_PAD_CTL_EIM_SDBA2 Register"
|
|
bitfld.long 0x118 9. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,DDR2"
|
|
textline " "
|
|
bitfld.long 0x118 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x118 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x118 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x118 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
line.long 0x11C "SW_PAD_CTL_PAD_EIM_SDODT1,SW_PAD_CTL_EIM_SDODT1 Register"
|
|
bitfld.long 0x11C 9. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,DDR2"
|
|
textline " "
|
|
bitfld.long 0x11C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x11C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x11C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x11C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x11C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x11C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x120 "SW_PAD_CTL_PAD_EIM_SDODT0,SW_PAD_CTL_EIM_SDODT0 Register"
|
|
bitfld.long 0x120 9. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,DDR2"
|
|
textline " "
|
|
bitfld.long 0x120 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x120 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x120 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x120 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x120 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x120 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x124 "SW_PAD_CTL_PAD_GPIO_NAND,SW_PAD_CTL_GPIO_NAND Register"
|
|
bitfld.long 0x124 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x124 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x124 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x128 "SW_PAD_CTL_PAD_NANDF_CS0,SW_PAD_CTL_NANDF_CS0 Register"
|
|
bitfld.long 0x128 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x128 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x12C "SW_PAD_CTL_PAD_NANDF_CS1,SW_PAD_CTL_NANDF_CS1 Register"
|
|
bitfld.long 0x12C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x12C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x130 "SW_PAD_CTL_PAD_NANDF_CS2,SW_PAD_CTL_NANDF_CS2 Register"
|
|
bitfld.long 0x130 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x130 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x130 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x130 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x130 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x130 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x130 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x134 "SW_PAD_CTL_PAD_NANDF_CS3,SW_PAD_CTL_NANDF_CS3 Register"
|
|
bitfld.long 0x134 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x134 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x134 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x134 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x134 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x134 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x134 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x138 "SW_PAD_CTL_PAD_NANDF_CS4,SW_PAD_CTL_NANDF_CS4 Register"
|
|
bitfld.long 0x138 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x138 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x138 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x138 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x138 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x138 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x13C "SW_PAD_CTL_PAD_NANDF_CS5,SW_PAD_CTL_NANDF_CS5 Register"
|
|
bitfld.long 0x13C 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x13C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x13C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x13C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x13C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x13C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x140 "SW_PAD_CTL_PAD_NANDF_CS6,SW_PAD_CTL_NANDF_CS6 Register"
|
|
bitfld.long 0x140 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x140 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x140 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x140 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x140 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x144 "SW_PAD_CTL_PAD_NANDF_CS7,SW_PAD_CTL_NANDF_CS7 Register"
|
|
bitfld.long 0x144 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x144 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x144 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x144 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x144 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x148 "SW_PAD_CTL_PAD_NANDF_RDY_INT,SW_PAD_CTL_NANDF_RDY_INT Register"
|
|
bitfld.long 0x148 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x148 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x148 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x148 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x148 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x148 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x148 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x14C "SW_PAD_CTL_PAD_NANDF_D15,SW_PAD_CTL_NANDF_D15 Register"
|
|
bitfld.long 0x14C 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x14C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x14C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x14C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x150 "SW_PAD_CTL_PAD_NANDF_D14,SW_PAD_CTL_NANDF_D14 Register"
|
|
bitfld.long 0x150 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x150 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x150 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x150 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x150 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x150 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x154 "SW_PAD_CTL_PAD_NANDF_D13,SW_PAD_CTL_NANDF_D13 Register"
|
|
bitfld.long 0x154 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x154 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x154 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x154 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x154 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x154 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x158 "SW_PAD_CTL_PAD_NANDF_D12,SW_PAD_CTL_NANDF_D12 Register"
|
|
bitfld.long 0x158 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x158 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x158 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x158 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x158 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x158 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x15C "SW_PAD_CTL_PAD_NANDF_D11,SW_PAD_CTL_NANDF_D11 Register"
|
|
bitfld.long 0x15C 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x15C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x15C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x15C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x15C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x15C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x160 "SW_PAD_CTL_PAD_NANDF_D10,SW_PAD_CTL_NANDF_D10 Register"
|
|
bitfld.long 0x160 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x160 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x160 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x160 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x160 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x160 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x164 "SW_PAD_CTL_PAD_NANDF_D9,SW_PAD_CTL_NANDF_D9 Register"
|
|
bitfld.long 0x164 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x164 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x164 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x164 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x164 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x164 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x168 "SW_PAD_CTL_PAD_NANDF_D8,SW_PAD_CTL_NANDF_D8 Register"
|
|
bitfld.long 0x168 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x168 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x168 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x168 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x168 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x168 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x16C "SW_PAD_CTL_PAD_NANDF_D7,SW_PAD_CTL_NANDF_D7 Register"
|
|
bitfld.long 0x16C 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x16C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x16C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x16C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x16C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x16C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x170 "SW_PAD_CTL_PAD_NANDF_D6,SW_PAD_CTL_NANDF_D6 Register"
|
|
bitfld.long 0x170 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x170 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x170 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x170 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x170 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x170 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x170 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x174 "SW_PAD_CTL_PAD_NANDF_D5,SW_PAD_CTL_NANDF_D5 Register"
|
|
bitfld.long 0x174 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x174 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x174 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x174 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x174 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x174 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x178 "SW_PAD_CTL_PAD_NANDF_D4,SW_PAD_CTL_NANDF_D4 Register"
|
|
bitfld.long 0x178 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x178 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x178 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x178 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x178 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x178 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x17C "SW_PAD_CTL_PAD_NANDF_D3,SW_PAD_CTL_NANDF_D3 Register"
|
|
bitfld.long 0x17C 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x17C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x17C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x17C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x17C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x17C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x180 "SW_PAD_CTL_PAD_NANDF_D2,SW_PAD_CTL_NANDF_D2 Register"
|
|
bitfld.long 0x180 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x180 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x180 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x180 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x180 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x180 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x184 "SW_PAD_CTL_PAD_NANDF_D1,SW_PAD_CTL_NANDF_D1 Register"
|
|
bitfld.long 0x184 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x184 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x184 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x184 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x184 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x184 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x188 "SW_PAD_CTL_PAD_NANDF_D0,SW_PAD_CTL_NANDF_D0 Register"
|
|
bitfld.long 0x188 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x188 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x188 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x188 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x188 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x188 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x18C "SW_PAD_CTL_PAD_CSI1_D8,SW_PAD_CTL_CSI1_D8 Register"
|
|
bitfld.long 0x18C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x18C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x190 "SW_PAD_CTL_PAD_CSI1_D9,SW_PAD_CTL_CSI1_D9 Register"
|
|
bitfld.long 0x190 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x190 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x190 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x190 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x194 "SW_PAD_CTL_PAD_CSI1_D10,SW_PAD_CTL_CSI1_D10 Register"
|
|
bitfld.long 0x194 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x198 "SW_PAD_CTL_PAD_CSI1_D11,SW_PAD_CTL_CSI1_D11 Register"
|
|
bitfld.long 0x198 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x19C "SW_PAD_CTL_PAD_CSI1_D12,SW_PAD_CTL_CSI1_D12 Register"
|
|
bitfld.long 0x19C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1A0 "SW_PAD_CTL_PAD_CSI1_D13,SW_PAD_CTL_CSI1_D13 Register"
|
|
bitfld.long 0x1A0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1A4 "SW_PAD_CTL_PAD_CSI1_D14,SW_PAD_CTL_CSI1_D14 Register"
|
|
bitfld.long 0x1A4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1A8 "SW_PAD_CTL_PAD_CSI1_D15,SW_PAD_CTL_CSI1_D15 Register"
|
|
bitfld.long 0x1A8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1AC "SW_PAD_CTL_PAD_CSI1_D16,SW_PAD_CTL_CSI1_D16 Register"
|
|
bitfld.long 0x1AC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1B0 "SW_PAD_CTL_PAD_CSI1_D17,SW_PAD_CTL_CSI1_D17 Register"
|
|
bitfld.long 0x1B0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1B4 "SW_PAD_CTL_PAD_CSI1_D18,SW_PAD_CTL_CSI1_D18 Register"
|
|
bitfld.long 0x1B4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1B8 "SW_PAD_CTL_PAD_CSI1_D19,SW_PAD_CTL_CSI1_D19 Register"
|
|
bitfld.long 0x1B8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1BC "SW_PAD_CTL_PAD_CSI1_VSYNC,SW_PAD_CTL_CSI1_VSYNC Register"
|
|
bitfld.long 0x1BC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1BC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1C0 "SW_PAD_CTL_PAD_CSI1_HSYNC,SW_PAD_CTL_CSI1_HSYNC Register"
|
|
bitfld.long 0x1C0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1C4 "SW_PAD_CTL_PAD_CSI1_PIXCLK,SW_PAD_CTL_CSI1_PIXCLK Register"
|
|
bitfld.long 0x1C4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1C8 "SW_PAD_CTL_PAD_CSI1_MCLK,SW_PAD_CTL_CSI1_MCLK Register"
|
|
bitfld.long 0x1C8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x1C8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1CC "SW_PAD_CTL_PAD_CSI2_D12,SW_PAD_CTL_CSI2_D12 Register"
|
|
bitfld.long 0x1CC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1CC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1CC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x1CC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1D0 "SW_PAD_CTL_PAD_CSI2_D13,SW_PAD_CTL_CSI2_D13 Register"
|
|
bitfld.long 0x1D0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1D0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1D0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x1D0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1D4 "SW_PAD_CTL_PAD_CSI2_D14,SW_PAD_CTL_CSI2_D14 Register"
|
|
bitfld.long 0x1D4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1D8 "SW_PAD_CTL_PAD_CSI2_D15,SW_PAD_CTL_CSI2_D15 Register"
|
|
bitfld.long 0x1D8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1DC "SW_PAD_CTL_PAD_CSI2_D16,SW_PAD_CTL_CSI2_D16 Register"
|
|
bitfld.long 0x1DC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1E0 "SW_PAD_CTL_PAD_CSI2_D17,SW_PAD_CTL_CSI2_D17 Register"
|
|
bitfld.long 0x1E0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x1E4 "SW_PAD_CTL_PAD_CSI2_D18,SW_PAD_CTL_CSI2_D18 Register"
|
|
bitfld.long 0x1E4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1E4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1E4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x1E4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1E8 "SW_PAD_CTL_PAD_CSI2_D19,SW_PAD_CTL_CSI2_D19 Register"
|
|
bitfld.long 0x1E8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1E8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1E8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x1E8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1EC "SW_PAD_CTL_PAD_CSI2_VSYNC,SW_PAD_CTL_CSI2_VSYNC Register"
|
|
bitfld.long 0x1EC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1EC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1EC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x1EC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1F0 "SW_PAD_CTL_PAD_CSI2_HSYNC,SW_PAD_CTL_CSI2_HSYNC Register"
|
|
bitfld.long 0x1F0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1F0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1F0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x1F0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1F4 "SW_PAD_CTL_PAD_CSI2_PIXCLK,SW_PAD_CTL_CSI2_PIXCLK Register"
|
|
bitfld.long 0x1F4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1F4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1F4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x1F4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1F8 "SW_PAD_CTL_PAD_I2C1_CLK,SW_PAD_CTL_I2C1_CLK Register"
|
|
bitfld.long 0x1F8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1F8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1F8 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x1F8 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1F8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x1FC "SW_PAD_CTL_PAD_I2C1_DAT,SW_PAD_CTL_I2C1_DAT Register"
|
|
bitfld.long 0x1FC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1FC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1FC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x1FC 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1FC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x200 "SW_PAD_CTL_PAD_AUD3_BB_TXD,SW_PAD_CTL_AUD3_BB_TXD Register"
|
|
bitfld.long 0x200 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x200 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x200 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x200 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x200 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x200 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x200 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x204 "SW_PAD_CTL_PAD_AUD3_BB_RXD,SW_PAD_CTL_AUD3_BB_RXD Register"
|
|
bitfld.long 0x204 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x204 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x204 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x204 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x204 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x208 "SW_PAD_CTL_PAD_AUD3_BB_CK,SW_PAD_CTL_AUD3_BB_CK Register"
|
|
bitfld.long 0x208 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x208 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x208 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x208 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x208 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x208 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x208 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x20C "SW_PAD_CTL_PAD_AUD3_BB_FS,SW_PAD_CTL_AUD3_BB_FS Register"
|
|
bitfld.long 0x20C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x20C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x20C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x210 "SW_PAD_CTL_PAD_CSPI1_MOSI,SW_PAD_CTL_CSPI1_MOSI Register"
|
|
bitfld.long 0x210 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x210 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x210 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x210 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x210 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x210 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x214 "SW_PAD_CTL_PAD_CSPI1_MISO,SW_PAD_CTL_CSPI1_MISO Register"
|
|
bitfld.long 0x214 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x214 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x214 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x214 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x218 "SW_PAD_CTL_PAD_CSPI1_SS0,SW_PAD_CTL_CSPI1_SS0 Register"
|
|
bitfld.long 0x218 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x218 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x218 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x218 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x21C "SW_PAD_CTL_PAD_CSPI1_SS1,SW_PAD_CTL_CSPI1_SS1 Register"
|
|
bitfld.long 0x21C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x21C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x21C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x21C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x220 "SW_PAD_CTL_PAD_CSPI1_RDY,SW_PAD_CTL_CSPI1_RDY Register"
|
|
bitfld.long 0x220 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x220 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x220 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x220 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x220 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x224 "SW_PAD_CTL_PAD_CSPI1_SCLK,SW_PAD_CTL_CSPI1_SCLK Register"
|
|
bitfld.long 0x224 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x224 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x224 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x224 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x224 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x224 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x228 "SW_PAD_CTL_PAD_UART1_RXD,SW_PAD_CTL_UART1_RXD Register"
|
|
bitfld.long 0x228 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x228 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x228 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x228 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x228 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x22C "SW_PAD_CTL_PAD_UART1_TXD,SW_PAD_CTL_UART1_TXD Register"
|
|
bitfld.long 0x22C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x22C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x22C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x22C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x22C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x230 "SW_PAD_CTL_PAD_UART1_RTS,SW_PAD_CTL_UART1_RTS Register"
|
|
bitfld.long 0x230 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x230 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x230 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x230 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x230 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x234 "SW_PAD_CTL_PAD_UART1_CTS,SW_PAD_CTL_UART1_CTS Register"
|
|
bitfld.long 0x234 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x234 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x234 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x234 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x234 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x238 "SW_PAD_CTL_PAD_UART2_RXD,SW_PAD_CTL_UART2_RXD Register"
|
|
bitfld.long 0x238 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x238 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x238 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x238 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x238 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x238 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x23C "SW_PAD_CTL_PAD_UART2_TXD,SW_PAD_CTL_UART2_TXD Register"
|
|
bitfld.long 0x23C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x23C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x23C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x23C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x23C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x23C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x240 "SW_PAD_CTL_PAD_UART3_RXD,SW_PAD_CTL_UART3_RXD Register"
|
|
bitfld.long 0x240 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x240 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x240 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x240 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x240 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x244 "SW_PAD_CTL_PAD_UART3_TXD,SW_PAD_CTL_UART3_TXD Register"
|
|
bitfld.long 0x244 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x244 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x244 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x244 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x244 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x248 "SW_PAD_CTL_PAD_OWIRE_LINE,SW_PAD_CTL_OWIRE_LINE Register"
|
|
bitfld.long 0x248 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x248 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x248 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x248 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x248 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x248 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x24C "SW_PAD_CTL_PAD_KEY_ROW0,SW_PAD_CTL_KEY_ROW0 Register"
|
|
bitfld.long 0x24C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x24C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x24C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x24C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x250 "SW_PAD_CTL_PAD_KEY_ROW1,SW_PAD_CTL_KEY_ROW1 Register"
|
|
bitfld.long 0x250 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x250 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x250 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x250 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x250 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x250 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x254 "SW_PAD_CTL_PAD_KEY_ROW2,SW_PAD_CTL_KEY_ROW2 Register"
|
|
bitfld.long 0x254 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x254 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x254 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x254 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x254 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x254 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x258 "SW_PAD_CTL_PAD_KEY_ROW3,SW_PAD_CTL_KEY_ROW3 Register"
|
|
bitfld.long 0x258 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x258 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x258 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x258 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x258 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x258 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x25C "SW_PAD_CTL_PAD_KEY_COL0,SW_PAD_CTL_KEY_COL0 Register"
|
|
bitfld.long 0x25C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x25C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x25C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x25C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x25C 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x25C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x25C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x260 "SW_PAD_CTL_PAD_KEY_COL1,SW_PAD_CTL_KEY_COL1 Register"
|
|
bitfld.long 0x260 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x260 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x260 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x260 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x260 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x260 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x260 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x264 "SW_PAD_CTL_PAD_KEY_COL2,SW_PAD_CTL_KEY_COL2 Register"
|
|
bitfld.long 0x264 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x264 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x264 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x264 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x264 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x264 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x264 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x268 "SW_PAD_CTL_PAD_KEY_COL3,SW_PAD_CTL_KEY_COL3 Register"
|
|
bitfld.long 0x268 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x268 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x268 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x268 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x268 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x268 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x268 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x26C "SW_PAD_CTL_PAD_KEY_COL4,SW_PAD_CTL_KEY_COL4 Register"
|
|
bitfld.long 0x26C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x26C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x26C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x26C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x26C 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x26C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x26C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x270 "SW_PAD_CTL_PAD_KEY_COL5,SW_PAD_CTL_KEY_COL5 Register"
|
|
bitfld.long 0x270 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x270 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x270 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x270 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x270 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x270 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x270 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x274 "SW_PAD_CTL_PAD_JTAG_TCK,SW_PAD_CTL_JTAG_TCK Register"
|
|
bitfld.long 0x274 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x278 "SW_PAD_CTL_PAD_JTAG_TMS,SW_PAD_CTL_JTAG_TMS Register"
|
|
bitfld.long 0x278 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x27C "SW_PAD_CTL_PAD_JTAG_TDI,SW_PAD_CTL_JTAG_TDI Register"
|
|
bitfld.long 0x27C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x280 "SW_PAD_CTL_PAD_JTAG_TRSTB,SW_PAD_CTL_JTAG_TRSTB Register"
|
|
bitfld.long 0x280 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x284 "SW_PAD_CTL_PAD_JTAG_MOD,SW_PAD_CTL_JTAG_MOD Register"
|
|
bitfld.long 0x284 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x288 "SW_PAD_CTL_PAD_USBH1_CLK,SW_PAD_CTL_USBH1_CLK Register"
|
|
bitfld.long 0x288 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x288 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x288 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x288 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x288 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x288 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x288 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x28C "SW_PAD_CTL_PAD_USBH1_DIR,SW_PAD_CTL_USBH1_DIR Register"
|
|
bitfld.long 0x28C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x28C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x28C 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x28C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x290 "SW_PAD_CTL_PAD_USBH1_STP,SW_PAD_CTL_USBH1_STP Register"
|
|
bitfld.long 0x290 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x290 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x290 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x290 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x290 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x294 "SW_PAD_CTL_PAD_USBH1_NXT,SW_PAD_CTL_USBH1_NXT Register"
|
|
bitfld.long 0x294 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x294 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x294 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x294 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x294 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x298 "SW_PAD_CTL_PAD_USBH1_DATA0,SW_PAD_CTL_USBH1_DATA0 Register"
|
|
bitfld.long 0x298 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x298 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x298 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x298 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x298 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x29C "SW_PAD_CTL_PAD_USBH1_DATA1,SW_PAD_CTL_USBH1_DATA1 Register"
|
|
bitfld.long 0x29C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x29C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x29C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x29C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x29C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2A0 "SW_PAD_CTL_PAD_USBH1_DATA2,SW_PAD_CTL_USBH1_DATA2 Register"
|
|
bitfld.long 0x2A0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2A0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2A0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2A0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2A0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2A4 "SW_PAD_CTL_PAD_USBH1_DATA3,SW_PAD_CTL_USBH1_DATA3 Register"
|
|
bitfld.long 0x2A4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2A4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2A4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2A4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2A4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2A8 "SW_PAD_CTL_PAD_USBH1_DATA4,SW_PAD_CTL_USBH1_DATA4 Register"
|
|
bitfld.long 0x2A8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2A8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2A8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2A8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2A8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2AC "SW_PAD_CTL_PAD_USBH1_DATA5,SW_PAD_CTL_USBH1_DATA5 Register"
|
|
bitfld.long 0x2AC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2AC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2AC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2AC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2AC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2B0 "SW_PAD_CTL_PAD_USBH1_DATA6,SW_PAD_CTL_USBH1_DATA6 Register"
|
|
bitfld.long 0x2B0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2B0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2B0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2B0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2B0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2B4 "SW_PAD_CTL_PAD_USBH1_DATA7,SW_PAD_CTL_USBH1_DATA7 Register"
|
|
bitfld.long 0x2B4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2B4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2B4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2B4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2B4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2B8 "SW_PAD_CTL_PAD_DI1_PIN11,SW_PAD_CTL_DI1_PIN11 Register"
|
|
bitfld.long 0x2B8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2B8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2B8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2B8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2B8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2BC "SW_PAD_CTL_PAD_DI1_PIN12,SW_PAD_CTL_DI1_PIN12 Register"
|
|
bitfld.long 0x2BC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2BC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2BC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2BC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2C0 "SW_PAD_CTL_PAD_DI1_PIN13,SW_PAD_CTL_DI1_PIN13 Register"
|
|
bitfld.long 0x2C0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2C0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2C0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2C4 "SW_PAD_CTL_PAD_DI1_D0_CS,SW_PAD_CTL_DI1_D0_CS Register"
|
|
bitfld.long 0x2C4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2C4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2C4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2C8 "SW_PAD_CTL_PAD_DI1_D1_CS,SW_PAD_CTL_DI1_D1_CS Register"
|
|
bitfld.long 0x2C8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2C8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2C8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2CC "SW_PAD_CTL_PAD_DISPB2_SER_DIN,SW_PAD_CTL_DISPB2_SER_DIN Register"
|
|
bitfld.long 0x2CC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2CC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2CC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2CC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2CC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2D0 "SW_PAD_CTL_PAD_DISPB2_SER_DIO,SW_PAD_CTL_DISPB2_SER_DIO Register"
|
|
bitfld.long 0x2D0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2D0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2D0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2D0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2D4 "SW_PAD_CTL_PAD_DISPB2_SER_CLK,SW_PAD_CTL_DISPB2_SER_CLK Register"
|
|
bitfld.long 0x2D4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2D4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2D4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2D4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2D8 "SW_PAD_CTL_PAD_DISPB2_SER_RS,SW_PAD_CTL_DISPB2_SER_RS Register"
|
|
bitfld.long 0x2D8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2D8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2D8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2D8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2DC "SW_PAD_CTL_PAD_DISP1_DAT0,SW_PAD_CTL_DISP1_DAT0 Register"
|
|
bitfld.long 0x2DC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2DC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2DC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2E0 "SW_PAD_CTL_PAD_DISP1_DAT1,SW_PAD_CTL_DISP1_DAT1 Register"
|
|
bitfld.long 0x2E0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2E0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2E0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2E4 "SW_PAD_CTL_PAD_DISP1_DAT2,SW_PAD_CTL_DISP1_DAT2 Register"
|
|
bitfld.long 0x2E4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2E4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2E4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2E8 "SW_PAD_CTL_PAD_DISP1_DAT3,SW_PAD_CTL_DISP1_DAT3 Register"
|
|
bitfld.long 0x2E8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2E8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2E8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2EC "SW_PAD_CTL_PAD_DISP1_DAT4,SW_PAD_CTL_DISP1_DAT4 Register"
|
|
bitfld.long 0x2EC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2EC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2EC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2F0 "SW_PAD_CTL_PAD_DISP1_DAT5,SW_PAD_CTL_DISP1_DAT5 Register"
|
|
bitfld.long 0x2F0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2F0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2F0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2F4 "SW_PAD_CTL_PAD_DISP1_DAT6,SW_PAD_CTL_DISP1_DAT6 Register"
|
|
bitfld.long 0x2F4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2F4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2F4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2F4 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2F4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2F4 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2F8 "SW_PAD_CTL_PAD_DISP1_DAT7,SW_PAD_CTL_DISP1_DAT7 Register"
|
|
bitfld.long 0x2F8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2F8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2F8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2F8 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2F8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2F8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2FC "SW_PAD_CTL_PAD_DISP1_DAT8,SW_PAD_CTL_DISP1_DAT8 Register"
|
|
bitfld.long 0x2FC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2FC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2FC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x2FC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x2FC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x2FC 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x300 "SW_PAD_CTL_PAD_DISP1_DAT9,SW_PAD_CTL_DISP1_DAT9 Register"
|
|
bitfld.long 0x300 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x300 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x300 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x300 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x300 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x300 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x304 "SW_PAD_CTL_PAD_DISP1_DAT10,SW_PAD_CTL_DISP1_DAT10 Register"
|
|
bitfld.long 0x304 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x304 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x304 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x304 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x304 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x304 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x308 "SW_PAD_CTL_PAD_DISP1_DAT11,SW_PAD_CTL_DISP1_DAT11 Register"
|
|
bitfld.long 0x308 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x308 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x308 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x308 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x308 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x308 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x30C "SW_PAD_CTL_PAD_DISP1_DAT12,SW_PAD_CTL_DISP1_DAT12 Register"
|
|
bitfld.long 0x30C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x30C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x30C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x30C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x310 "SW_PAD_CTL_PAD_DISP1_DAT13,SW_PAD_CTL_DISP1_DAT13 Register"
|
|
bitfld.long 0x310 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x310 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x310 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x310 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x310 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x310 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x314 "SW_PAD_CTL_PAD_DISP1_DAT14,SW_PAD_CTL_DISP1_DAT14 Register"
|
|
bitfld.long 0x314 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x314 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x314 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x314 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x314 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x314 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x318 "SW_PAD_CTL_PAD_DISP1_DAT15,SW_PAD_CTL_DISP1_DAT15 Register"
|
|
bitfld.long 0x318 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x318 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x318 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x318 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x318 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x318 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x31C "SW_PAD_CTL_PAD_DISP1_DAT16,SW_PAD_CTL_DISP1_DAT16 Register"
|
|
bitfld.long 0x31C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x31C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x31C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x31C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x31C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x31C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x320 "SW_PAD_CTL_PAD_DISP1_DAT17,SW_PAD_CTL_DISP1_DAT17 Register"
|
|
bitfld.long 0x320 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x320 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x320 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x320 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x320 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x320 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x324 "SW_PAD_CTL_PAD_DISP1_DAT18,SW_PAD_CTL_DISP1_DAT18 Register"
|
|
bitfld.long 0x324 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x324 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x324 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x324 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x324 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x324 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x328 "SW_PAD_CTL_PAD_DISP1_DAT19,SW_PAD_CTL_DISP1_DAT19 Register"
|
|
bitfld.long 0x328 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x328 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x328 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x328 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x328 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x328 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x32C "SW_PAD_CTL_PAD_DISP1_DAT20,SW_PAD_CTL_DISP1_DAT20 Register"
|
|
bitfld.long 0x32C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x32C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x32C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x32C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x32C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x32C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x330 "SW_PAD_CTL_PAD_DISP1_DAT21,SW_PAD_CTL_DISP1_DAT21 Register"
|
|
bitfld.long 0x330 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x330 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x330 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x330 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x330 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x330 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x334 "SW_PAD_CTL_PAD_DISP1_DAT22,SW_PAD_CTL_DISP1_DAT22 Register"
|
|
bitfld.long 0x334 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x334 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x334 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x334 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x334 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x334 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x338 "SW_PAD_CTL_PAD_DISP1_DAT23,SW_PAD_CTL_DISP1_DAT23 Register"
|
|
bitfld.long 0x338 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x338 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x338 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x338 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x338 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x338 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x33C "SW_PAD_CTL_PAD_DI1_PIN3,SW_PAD_CTL_DI1_PIN3 Register"
|
|
bitfld.long 0x33C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x33C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x33C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x33C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x33C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x340 "SW_PAD_CTL_PAD_DI1_DISP_CLK,SW_PAD_CTL_DI1_DISP_CLK Register"
|
|
bitfld.long 0x340 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x340 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x340 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x340 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x344 "SW_PAD_CTL_PAD_DI1_PIN2,SW_PAD_CTL_DI1_PIN2 Register"
|
|
bitfld.long 0x344 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x344 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x344 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x344 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x344 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x348 "SW_PAD_CTL_PAD_DI1_PIN15,SW_PAD_CTL_DI1_PIN15 Register"
|
|
bitfld.long 0x348 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x348 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x348 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x34C "SW_PAD_CTL_PAD_DI_GP1,SW_PAD_CTL_DI_GP1 Register"
|
|
bitfld.long 0x34C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x34C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x34C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x350 "SW_PAD_CTL_PAD_DI_GP2,SW_PAD_CTL_DI_GP2 Register"
|
|
bitfld.long 0x350 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x350 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x350 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x350 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x350 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x354 "SW_PAD_CTL_PAD_DI_GP3,SW_PAD_CTL_DI_GP3 Register"
|
|
bitfld.long 0x354 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x354 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x354 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x354 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x354 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x358 "SW_PAD_CTL_PAD_DI2_PIN4,SW_PAD_CTL_DI2_PIN4 Register"
|
|
bitfld.long 0x358 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x358 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x358 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x358 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x358 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x35C "SW_PAD_CTL_PAD_DI2_PIN2,SW_PAD_CTL_DI2_PIN2 Register"
|
|
bitfld.long 0x35C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x35C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x35C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x35C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x360 "SW_PAD_CTL_PAD_DI2_PIN3,SW_PAD_CTL_DI2_PIN3 Register"
|
|
bitfld.long 0x360 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x360 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x360 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x360 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x360 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x360 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x364 "SW_PAD_CTL_PAD_DI2_DISP_CLK,SW_PAD_CTL_DI2_DISP_CLK Register"
|
|
bitfld.long 0x364 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x364 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x364 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x364 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x364 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x368 "SW_PAD_CTL_PAD_DI_GP4,SW_PAD_CTL_DI_GP4 Register"
|
|
bitfld.long 0x368 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x368 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x368 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x368 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x368 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x36C "SW_PAD_CTL_PAD_DISP2_DAT0,SW_PAD_CTL_DISP2_DAT0 Register"
|
|
bitfld.long 0x36C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x36C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x36C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x36C 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x36C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x36C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x370 "SW_PAD_CTL_PAD_DISP2_DAT1,SW_PAD_CTL_DISP2_DAT1 Register"
|
|
bitfld.long 0x370 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x370 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x370 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x370 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x370 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x370 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x374 "SW_PAD_CTL_PAD_DISP2_DAT2,SW_PAD_CTL_DISP2_DAT2 Register"
|
|
bitfld.long 0x374 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x374 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x374 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x378 "SW_PAD_CTL_PAD_DISP2_DAT3,SW_PAD_CTL_DISP2_DAT3 Register"
|
|
bitfld.long 0x378 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x378 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x378 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x37C "SW_PAD_CTL_PAD_DISP2_DAT4,SW_PAD_CTL_DISP2_DAT4 Register"
|
|
bitfld.long 0x37C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x37C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x37C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x380 "SW_PAD_CTL_PAD_DISP2_DAT5,SW_PAD_CTL_DISP2_DAT5 Register"
|
|
bitfld.long 0x380 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x380 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x380 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x384 "SW_PAD_CTL_PAD_DISP2_DAT6,SW_PAD_CTL_DISP2_DAT6 Register"
|
|
bitfld.long 0x384 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x384 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x384 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x384 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x384 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x388 "SW_PAD_CTL_PAD_DISP2_DAT7,SW_PAD_CTL_DISP2_DAT7 Register"
|
|
bitfld.long 0x388 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x388 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x388 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x388 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x388 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x38C "SW_PAD_CTL_PAD_DISP2_DAT8,SW_PAD_CTL_DISP2_DAT8 Register"
|
|
bitfld.long 0x38C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x38C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x38C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x390 "SW_PAD_CTL_PAD_DISP2_DAT9,SW_PAD_CTL_DISP2_DAT9 Register"
|
|
bitfld.long 0x390 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x390 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x390 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x390 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x390 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x394 "SW_PAD_CTL_PAD_DISP2_DAT10,SW_PAD_CTL_DISP2_DAT10 Register"
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bitfld.long 0x394 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x394 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x394 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x394 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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textline " "
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bitfld.long 0x394 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x398 "SW_PAD_CTL_PAD_DISP2_DAT11,SW_PAD_CTL_DISP2_DAT11 Register"
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bitfld.long 0x398 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x398 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x398 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x398 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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textline " "
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bitfld.long 0x398 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x39C "SW_PAD_CTL_PAD_DISP2_DAT12,SW_PAD_CTL_DISP2_DAT12 Register"
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bitfld.long 0x39C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x39C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x39C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x39C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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textline " "
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bitfld.long 0x39C 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x3A0 "SW_PAD_CTL_PAD_DISP2_DAT13,SW_PAD_CTL_DISP2_DAT13 Register"
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bitfld.long 0x3A0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3A0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3A0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3A0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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textline " "
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bitfld.long 0x3A0 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x3A4 "SW_PAD_CTL_PAD_DISP2_DAT14,SW_PAD_CTL_DISP2_DAT14 Register"
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bitfld.long 0x3A4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3A4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3A4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3A4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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textline " "
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bitfld.long 0x3A4 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x3A8 "SW_PAD_CTL_PAD_DISP2_DAT15,SW_PAD_CTL_DISP2_DAT15 Register"
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bitfld.long 0x3A8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3A8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3A8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3A8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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textline " "
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bitfld.long 0x3A8 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x3AC "SW_PAD_CTL_PAD_SD1_CMD,SW_PAD_CTL_SD1_CMD Register"
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bitfld.long 0x3AC 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3AC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3AC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3AC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3AC 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3AC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3B0 "SW_PAD_CTL_PAD_SD1_CLK,SW_PAD_CTL_SD1_CLK Register"
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bitfld.long 0x3B0 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3B0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3B0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3B0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3B0 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3B0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3B4 "SW_PAD_CTL_PAD_SD1_DATA0,SW_PAD_CTL_SD1_DATA0 Register"
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bitfld.long 0x3B4 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3B4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3B4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3B4 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3B4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3B8 "SW_PAD_CTL_PAD_SD1_DATA1,SW_PAD_CTL_SD1_DATA1 Register"
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bitfld.long 0x3B8 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3B8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3B8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3B8 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3B8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3BC "SW_PAD_CTL_PAD_SD1_DATA2,SW_PAD_CTL_SD1_DATA2 Register"
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bitfld.long 0x3BC 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3BC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3BC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3BC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3BC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3C0 "SW_PAD_CTL_PAD_SD1_DATA3,SW_PAD_CTL_SD1_DATA3 Register"
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bitfld.long 0x3C0 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3C0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3C0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3C0 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3C0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3C4 "SW_PAD_CTL_PAD_GPIO1_0,SW_PAD_CTL_GPIO1_0 Register"
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bitfld.long 0x3C4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3C4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3C4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3C4 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3C4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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textline " "
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bitfld.long 0x3C4 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x3C8 "SW_PAD_CTL_PAD_GPIO1_1,SW_PAD_CTL_GPIO1_1 Register"
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bitfld.long 0x3C8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3C8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3C8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3C8 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3C8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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textline " "
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bitfld.long 0x3C8 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x3CC "SW_PAD_CTL_PAD_SD2_CMD,SW_PAD_CTL_SD2_CMD Register"
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bitfld.long 0x3CC 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3CC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3CC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3CC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3CC 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3CC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3D0 "SW_PAD_CTL_PAD_SD2_CLK,SW_PAD_CTL_SD2_CLK Register"
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bitfld.long 0x3D0 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3D0 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3D0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3D0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3D0 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3D0 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3D0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3D4 "SW_PAD_CTL_PAD_SD2_DATA0,SW_PAD_CTL_SD2_DATA0 Register"
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bitfld.long 0x3D4 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3D4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3D4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3D4 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3D4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3D8 "SW_PAD_CTL_PAD_SD2_DATA1,SW_PAD_CTL_SD2_DATA1 Register"
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bitfld.long 0x3D8 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3D8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3D8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3D8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3D8 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3D8 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3D8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3DC "SW_PAD_CTL_PAD_SD2_DATA2,SW_PAD_CTL_SD2_DATA2 Register"
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bitfld.long 0x3DC 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3DC 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3DC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3DC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3DC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3DC 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3DC 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3E0 "SW_PAD_CTL_PAD_SD2_DATA3,SW_PAD_CTL_SD2_DATA3 Register"
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bitfld.long 0x3E0 13. " HVE ,Low/high output voltage Field" "High,Low"
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textline " "
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bitfld.long 0x3E0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3E0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3E0 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3E0 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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line.long 0x3E4 "SW_PAD_CTL_PAD_GPIO1_2,SW_PAD_CTL_GPIO1_2 Register"
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bitfld.long 0x3E4 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3E4 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3E4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3E4 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3E4 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3E4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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textline " "
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bitfld.long 0x3E4 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x3E8 "SW_PAD_CTL_PAD_GPIO1_3,SW_PAD_CTL_GPIO1_3 Register"
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bitfld.long 0x3E8 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3E8 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3E8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3E8 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x3E8 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
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textline " "
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bitfld.long 0x3E8 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
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textline " "
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bitfld.long 0x3E8 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x3EC "SW_PAD_CTL_PAD_RESET_IN_B,SW_PAD_CTL_RESET_IN_B Register"
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bitfld.long 0x3EC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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line.long 0x3F0 "SW_PAD_CTL_PAD_POR_B,SW_PAD_CTL_POR_B Register"
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bitfld.long 0x3F0 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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line.long 0x3F4 "SW_PAD_CTL_PAD_BOOT_MODE1,SW_PAD_CTL_BOOT_MODE1 Register"
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bitfld.long 0x3F4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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line.long 0x3F8 "SW_PAD_CTL_PAD_BOOT_MODE0,SW_PAD_CTL_BOOT_MODE0 Register"
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bitfld.long 0x3F8 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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line.long 0x3FC "SW_PAD_CTL_PAD_PMIC_RDY,SW_PAD_CTL_PMIC_RDY Register"
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bitfld.long 0x3FC 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x3FC 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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line.long 0x400 "SW_PAD_CTL_PAD_CKIL,SW_PAD_CTL_CKIL Register"
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bitfld.long 0x400 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
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textline " "
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bitfld.long 0x400 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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line.long 0x404 "SW_PAD_CTL_PAD_PMIC_STBY_REQ,SW_PAD_CTL_PMIC_STBY_REQ Register"
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bitfld.long 0x404 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x404 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
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textline " "
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bitfld.long 0x404 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
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textline " "
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bitfld.long 0x404 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
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textline " "
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bitfld.long 0x404 0. " SRE ,Slew Rate Field" "Slow,Fast"
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line.long 0x408 "SW_PAD_CTL_PAD_PMIC_ON_REQ,SW_PAD_CTL_PMIC_ON_REQ Register"
|
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bitfld.long 0x408 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
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textline " "
|
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bitfld.long 0x408 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
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textline " "
|
|
bitfld.long 0x408 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x408 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
line.long 0x40C "SW_PAD_CTL_PAD_PMIC_INT_REQ,SW_PAD_CTL_PMIC_INT_REQ Register"
|
|
bitfld.long 0x40C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x40C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x40C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x40C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x410 "SW_PAD_CTL_PAD_CLK_SS,SW_PAD_CTL_CLK_SS Register"
|
|
bitfld.long 0x410 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x410 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
line.long 0x414 "SW_PAD_CTL_PAD_GPIO1_4,SW_PAD_CTL_GPIO1_4 Register"
|
|
bitfld.long 0x414 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x414 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x414 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x414 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x414 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x414 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x414 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x418 "SW_PAD_CTL_PAD_GPIO1_5,SW_PAD_CTL_GPIO1_5 Register"
|
|
bitfld.long 0x418 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x418 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x418 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x418 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x418 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x418 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x418 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x41C "SW_PAD_CTL_PAD_GPIO1_6,SW_PAD_CTL_GPIO1_6 Register"
|
|
bitfld.long 0x41C 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x41C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x41C 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x41C 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x41C 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x41C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x41C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x420 "SW_PAD_CTL_PAD_GPIO1_7,SW_PAD_CTL_GPIO1_7 Register"
|
|
bitfld.long 0x420 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x420 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x420 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x420 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x420 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x420 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x424 "SW_PAD_CTL_PAD_GPIO1_8,SW_PAD_CTL_GPIO1_8 Register"
|
|
bitfld.long 0x424 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x424 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x424 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x424 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x424 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x424 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x428 "SW_PAD_CTL_PAD_GPIO1_9,SW_PAD_CTL_GPIO1_9 Register"
|
|
bitfld.long 0x428 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x428 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x428 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
textline " "
|
|
bitfld.long 0x428 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
textline " "
|
|
bitfld.long 0x428 3. " ODE ,Open Drain Enable Field" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x428 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
textline " "
|
|
bitfld.long 0x428 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
tree.end
|
|
tree "SW_PAD_CTL_GRP Registers"
|
|
group.long 0x81c--0x8c3
|
|
line.long 0x0 "SW_PAD_CTL_GRP_CSI2_PKE0,SW_PAD_CTL_GRP_CSI2_PKE0 Register"
|
|
bitfld.long 0x0 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
line.long 0x4 "SW_PAD_CTL_GRP_DDRPKS,SW_PAD_CTL_GRP_DDRPKS Register"
|
|
bitfld.long 0x4 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x8 "SW_PAD_CTL_GRP_EIM_SR1,SW_PAD_CTL_GRP_EIM_SR1 Register"
|
|
bitfld.long 0x8 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xC "SW_PAD_CTL_GRP_DISP2_PKE0,SW_PAD_CTL_GRP_DISP2_PKE0 Register"
|
|
bitfld.long 0xC 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
line.long 0x10 "SW_PAD_CTL_GRP_DRAM_B4,SW_PAD_CTL_GRP_DRAM_B4 Register"
|
|
bitfld.long 0x10 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x14 "SW_PAD_CTL_GRP_INDDR,SW_PAD_CTL_GRP_INDDR Register"
|
|
bitfld.long 0x14 9. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,DDR2"
|
|
line.long 0x18 "SW_PAD_CTL_GRP_EIM_SR2,SW_PAD_CTL_GRP_EIM_SR2 Register"
|
|
bitfld.long 0x18 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x1C "SW_PAD_CTL_GRP_PKEDDR,SW_PAD_CTL_GRP_PKEDDR Register"
|
|
bitfld.long 0x1C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
line.long 0x20 "SW_PAD_CTL_GRP_DDR_A0,SW_PAD_CTL_GRP_DDR_A0 Register"
|
|
bitfld.long 0x20 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x24 "SW_PAD_CTL_GRP_EMI_PKE0,SW_PAD_CTL_GRP_EMI_PKE0 Register"
|
|
bitfld.long 0x24 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
line.long 0x28 "SW_PAD_CTL_GRP_EIM_SR3,SW_PAD_CTL_GRP_EIM_SR3 Register"
|
|
bitfld.long 0x28 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x2C "SW_PAD_CTL_GRP_DDR_A1,SW_PAD_CTL_GRP_DDR_A1 Register"
|
|
bitfld.long 0x2C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x30 "SW_PAD_CTL_GRP_DDRAPUS,SW_PAD_CTL_GRP_DDRAPUS Register"
|
|
bitfld.long 0x30 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
line.long 0x34 "SW_PAD_CTL_GRP_EIM_SR4,SW_PAD_CTL_GRP_EIM_SR4 Register"
|
|
bitfld.long 0x34 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x38 "SW_PAD_CTL_GRP_EMI_SR5,SW_PAD_CTL_GRP_EMI_SR5 Register"
|
|
bitfld.long 0x38 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x3C "SW_PAD_CTL_GRP_EMI_SR6,SW_PAD_CTL_GRP_EMI_SR6 Register"
|
|
bitfld.long 0x3C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x40 "SW_PAD_CTL_GRP_HYSDDR0,SW_PAD_CTL_GRP_HYSDDR0 Register"
|
|
bitfld.long 0x40 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x44 "SW_PAD_CTL_GRP_CSI1_PKE0,SW_PAD_CTL_GRP_CSI1_PKE0 Register"
|
|
bitfld.long 0x44 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
line.long 0x48 "SW_PAD_CTL_GRP_HYSDDR1,SW_PAD_CTL_GRP_HYSDDR1 Register"
|
|
bitfld.long 0x48 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x4C "SW_PAD_CTL_GRP_DISP1_PKE0,SW_PAD_CTL_GRP_DISP1_PKE0 Register"
|
|
bitfld.long 0x4C 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
line.long 0x50 "SW_PAD_CTL_GRP_HYSDDR2,SW_PAD_CTL_GRP_HYSDDR2 Register"
|
|
bitfld.long 0x50 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x54 "SW_PAD_CTL_GRP_HVDDR,SW_PAD_CTL_GRP_HVDDR Register"
|
|
bitfld.long 0x54 13. " HVE ,Low/high output voltage Field" "High,Low"
|
|
line.long 0x58 "SW_PAD_CTL_GRP_HYSDDR3,SW_PAD_CTL_GRP_HYSDDR3 Register"
|
|
bitfld.long 0x58 8. " HYS ,Hyst. Enable Field" "Disabled,Enabled"
|
|
line.long 0x5C "SW_PAD_CTL_GRP_DRAM_SR_B0,SW_PAD_CTL_GRP_DRAM_SR_B0 Register"
|
|
bitfld.long 0x5C 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x60 "SW_PAD_CTL_GRP_DDRAPKS,SW_PAD_CTL_GRP_DDRAPKS Register"
|
|
bitfld.long 0x60 6. " PUE ,Pull / Keep Select Field" "Keeper,Pull"
|
|
line.long 0x64 "SW_PAD_CTL_GRP_DRAM_SR_B1,SW_PAD_CTL_GRP_DRAM_SR_B1 Register"
|
|
bitfld.long 0x64 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x68 "SW_PAD_CTL_GRP_DDRPUS,SW_PAD_CTL_GRP_DDRPUS Register"
|
|
bitfld.long 0x68 4.--5. " PUS ,Pull Up / Down Config. Field" "100KOhm Pull Down,47KOhm Pull Up,100KOhm Pull Up,22KOhm Pull Up"
|
|
line.long 0x6C "SW_PAD_CTL_GRP_EIM_DS1,SW_PAD_CTL_GRP_EIM_DS1 Register"
|
|
bitfld.long 0x6C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x70 "SW_PAD_CTL_GRP_DRAM_SR_B2,SW_PAD_CTL_GRP_DRAM_SR_B2 Register"
|
|
bitfld.long 0x70 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x74 "SW_PAD_CTL_GRP_PKEADDR,SW_PAD_CTL_GRP_PKEADDR Register"
|
|
bitfld.long 0x74 7. " PKE ,Pull / Keep Enable Field" "Disabled,Enabled"
|
|
line.long 0x78 "SW_PAD_CTL_GRP_EIM_DS2,SW_PAD_CTL_GRP_EIM_DS2 Register"
|
|
bitfld.long 0x78 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x7C "SW_PAD_CTL_GRP_EIM_DS3,SW_PAD_CTL_GRP_EIM_DS3 Register"
|
|
bitfld.long 0x7C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x80 "SW_PAD_CTL_GRP_DRAM_SR_B4,SW_PAD_CTL_GRP_DRAM_SR_B4 Register"
|
|
bitfld.long 0x80 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x84 "SW_PAD_CTL_GRP_INMODE1,SW_PAD_CTL_GRP_INMODE1 Register"
|
|
bitfld.long 0x84 9. " DDR_INPUT ,DDR / CMOS Input Mode Field" "CMOS,DDR2"
|
|
line.long 0x88 "SW_PAD_CTL_GRP_DRAM_B0,SW_PAD_CTL_GRP_DRAM_B0 Register"
|
|
bitfld.long 0x88 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x8C "SW_PAD_CTL_GRP_EIM_DS4,SW_PAD_CTL_GRP_EIM_DS4 Register"
|
|
bitfld.long 0x8C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x90 "SW_PAD_CTL_GRP_DRAM_B1,SW_PAD_CTL_GRP_DRAM_B1 Register"
|
|
bitfld.long 0x90 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x94 "SW_PAD_CTL_GRP_DDR_SR_A0,SW_PAD_CTL_GRP_DDR_SR_A0 Register"
|
|
bitfld.long 0x94 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0x98 "SW_PAD_CTL_GRP_EMI_DS5,SW_PAD_CTL_GRP_EMI_DS5 Register"
|
|
bitfld.long 0x98 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0x9C "SW_PAD_CTL_GRP_DRAM_B2,SW_PAD_CTL_GRP_DRAM_B2 Register"
|
|
bitfld.long 0x9C 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
line.long 0xA0 "SW_PAD_CTL_GRP_DDR_SR_A1,SW_PAD_CTL_GRP_DDR_SR_A1 Register"
|
|
bitfld.long 0xA0 0. " SRE ,Slew Rate Field" "Slow,Fast"
|
|
line.long 0xA4 "SW_PAD_CTL_GRP_EMI_DS6,SW_PAD_CTL_GRP_EMI_DS6 Register"
|
|
bitfld.long 0xA4 1.--2. " DSE ,Drive Strength Field" "Low,Medium,High,Max"
|
|
tree.end
|
|
width 50.
|
|
tree "SELECT_INPUT Registers"
|
|
group.long 0x8c4--0xa27
|
|
line.long 0x00 "AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT,AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x00 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D21: ALT5,CSPI1_MISO: ALT1"
|
|
line.long 0x04 "AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT,AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x04 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D20: ALT5,CSPI1_SS1: ALT1"
|
|
line.long 0x08 "AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x08 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D22: ALT5,CSPI1_SS0: ALT1"
|
|
line.long 0x0c "AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x0c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D23: ALT5,CSPI1_RDY: ALT1"
|
|
line.long 0x10 "AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x10 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D17: ALT7,EIM_CS3: ALT6,SD1_DATA1: ALT1,?..."
|
|
line.long 0x14 "AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x14 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D16: ALT7,EIM_CS2: ALT6,SD1_DATA0: ALT1,?..."
|
|
line.long 0x18 "AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x18 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_EB3: ALT6,SD1_CLK: ALT1"
|
|
line.long 0x1c "AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x1c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_EB2: ALT6,SD1_CMD: ALT1"
|
|
line.long 0x20 "AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x20 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D18: ALT7,EIM_CS4: ALT6,SD1_DATA2: ALT1,?..."
|
|
line.long 0x24 "AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x24 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D19: ALT7,EIM_CS5: ALT6,SD1_DATA3: ALT1,?..."
|
|
line.long 0x28 "AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x28 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D29: ALT5,DISP2_DAT12: ALT4"
|
|
line.long 0x2c "AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x2c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D28: ALT5,DISP2_DAT11: ALT4"
|
|
line.long 0x30 "AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x30 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D27: ALT5,DISP2_DAT9: ALT4"
|
|
line.long 0x34 "AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x34 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D24: ALT5,DISP2_DAT15: ALT4"
|
|
line.long 0x38 "AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x38 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D30: ALT5,DISP2_DAT13: ALT4"
|
|
line.long 0x3c "AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT Register"
|
|
bitfld.long 0x3c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D31: ALT5,DISP2_DAT14: ALT4"
|
|
line.long 0x40 "CCM_IPP_DI0_CLK_SELECT_INPUT,CCM_IPP_DI0_CLK_SELECT_INPUT Register"
|
|
bitfld.long 0x40 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_CS5:ALT4,DI_GP1: ALT2"
|
|
line.long 0x44 "CCM_IPP_DI1_CLK_SELECT_INPUT,CCM_IPP_DI1_CLK_SELECT_INPUT Register"
|
|
bitfld.long 0x44 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_A26:ALT6,GPIO1_4:ALT4"
|
|
line.long 0x48 "CCM_PLL1_BYPASS_CLK_SELECT_INPUT,CCM_PLL1_BYPASS_CLK_SELECT_INPUT Register"
|
|
bitfld.long 0x48 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "KEY_COL0: ALT7,GPIO1_2: ALT7"
|
|
line.long 0x4c "CCM_PLL2_BYPASS_CLK_SELECT_INPUT,CCM_PLL2_BYPASS_CLK_SELECT_INPUT Register"
|
|
bitfld.long 0x4c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "KEY_COL1: ALT7,GPIO1_3: ALT7"
|
|
line.long 0x50 "CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT Register"
|
|
bitfld.long 0x50 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_CS2: ALT6,USBH1_CLK: ALT1,SD1_CLK: ALT2,SD2_CLK: ALT2"
|
|
line.long 0x54 "CSPI_IPP_IND_MISO_SELECT_INPUT,CSPI_IPP_IND_MISO_SELECT_INPUT Register"
|
|
bitfld.long 0x54 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "USBH1_NXT: ALT1,SD1_DATA0: ALT2,GPIO1_1: ALT2,SD2_DATA0: ALT2"
|
|
line.long 0x58 "CSPI_IPP_IND_MOSI_SELECT_INPUT,CSPI_IPP_IND_MOSI_SELECT_INPUT Register"
|
|
bitfld.long 0x58 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RB1: ALT6,USBH1_DIR: ALT1,SD1_CMD: ALT2,SD2_CMD: ALT2"
|
|
line.long 0x5c "CSPI_IPP_IND_SS1_B_SELECT_INPUT,CSPI_IPP_IND_SS1_B_SELECT_INPUT Register"
|
|
bitfld.long 0x5c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "USBH1_DATA5: ALT1,SD1_DATA3: ALT2"
|
|
line.long 0x60 "CSPI_IPP_IND_SS2_B_SELECT_INPUT,CSPI_IPP_IND_SS2_B_SELECT_INPUT Register"
|
|
bitfld.long 0x60 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "GPIO1_0: ALT2,SD2_DATA3: ALT2"
|
|
line.long 0x64 "CSPI_IPP_IND_SS3_B_SELECT_INPUT,CSPI_IPP_IND_SS3_B_SELECT_INPUT Register"
|
|
bitfld.long 0x64 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_CS6: ALT7,USBH1_DATA6: ALT1"
|
|
line.long 0x68 "DPLLIP1_L1T_TOG_EN_SELECT_INPUT,DPLLIP1_L1T_TOG_EN_SELECT_INPUT Register"
|
|
bitfld.long 0x68 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RB3: ALT4,GPIO1_2: ALT6,GPIO1_4: ALT7,GPIO1_7: ALT7"
|
|
line.long 0x6c "ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT Register"
|
|
bitfld.long 0x6c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RB0: ALT5,NANDF_D12: ALT2"
|
|
line.long 0x70 "ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT Register"
|
|
bitfld.long 0x70 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D14: ALT2,USBH1_DATA7: ALT5"
|
|
line.long 0x74 "EMI_IPP_IND_RDY_INT_SELECT_INPUT,EMI_IPP_IND_RDY_INT_SELECT_INPUT Register"
|
|
bitfld.long 0x74 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RDY_INT: ALT0,GPIO1_4: ALT3"
|
|
line.long 0x78 "ESDHC3_IPP_DAT0_IN_SELECT_INPUT,ESDHC3_IPP_DAT0_IN_SELECT_INPUT Register"
|
|
bitfld.long 0x78 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_WE_B: ALT2,NANDF_D8: ALT5"
|
|
line.long 0x7c "ESDHC3_IPP_DAT1_IN_SELECT_INPUT,ESDHC3_IPP_DAT1_IN_SELECT_INPUT Register"
|
|
bitfld.long 0x7c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RE_B: ALT2,NANDF_D9: ALT5"
|
|
line.long 0x80 "ESDHC3_IPP_DAT2_IN_SELECT_INPUT,ESDHC3_IPP_DAT2_IN_SELECT_INPUT Register"
|
|
bitfld.long 0x80 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_WP_B: ALT2,NANDF_D10: ALT5"
|
|
line.long 0x84 "ESDHC3_IPP_DAT3_IN_SELECT_INPUT,ESDHC3_IPP_DAT3_IN_SELECT_INPUT Register"
|
|
bitfld.long 0x84 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RB0: ALT2,NANDF_D11: ALT5"
|
|
line.long 0x88 "FEC_FEC_COL_SELECT_INPUT,FEC_FEC_COL_SELECT_INPUT Register"
|
|
bitfld.long 0x88 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RB2: ALT1,DISP2_DAT10: ALT2"
|
|
line.long 0x8c "FEC_FEC_CRS_SELECT_INPUT,FEC_FEC_CRS_SELECT_INPUT Register"
|
|
bitfld.long 0x8c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_CS5: ALT3,DI2_PIN4: ALT2"
|
|
line.long 0x90 "FEC_FEC_MDI_SELECT_INPUT,FEC_FEC_MDI_SELECT_INPUT Register"
|
|
bitfld.long 0x90 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_EB2: ALT3,DI2_PIN3: ALT2"
|
|
line.long 0x94 "FEC_FEC_RDATA_0_SELECT_INPUT,FEC_FEC_RDATA_0_SELECT_INPUT Register"
|
|
bitfld.long 0x94 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D9: ALT2,DISP2_DAT14: ALT2"
|
|
line.long 0x98 "FEC_FEC_RDATA_1_SELECT_INPUT,FEC_FEC_RDATA_1_SELECT_INPUT Register"
|
|
bitfld.long 0x98 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_EB3: ALT3,DI2_DISP_CLK: ALT2"
|
|
line.long 0x9c "FEC_FEC_RDATA_2_SELECT_INPUT,FEC_FEC_RDATA_2_SELECT_INPUT Register"
|
|
bitfld.long 0x9c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_CS2: ALT3,DI_GP4: ALT2"
|
|
line.long 0xa0 "FEC_FEC_RDATA_3_SELECT_INPUT,FEC_FEC_RDATA_3_SELECT_INPUT Register"
|
|
bitfld.long 0xa0 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_CS3: ALT3,DISP2_DAT0: ALT2"
|
|
line.long 0xa4 "FEC_FEC_RX_CLK_SELECT_INPUT,FEC_FEC_RX_CLK_SELECT_INPUT Register"
|
|
bitfld.long 0xa4 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RB3: ALT1,DISP2_DAT11: ALT2"
|
|
line.long 0xa8 "FEC_FEC_RX_DV_SELECT_INPUT,FEC_FEC_RX_DV_SELECT_INPUT Register"
|
|
bitfld.long 0xa8 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D11: ALT2,DISP2_DAT12: ALT2"
|
|
line.long 0xac "FEC_FEC_RX_ER_SELECT_INPUT,FEC_FEC_RX_ER_SELECT_INPUT Register"
|
|
bitfld.long 0xac 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_CS4: ALT3,DISP2_DAT1: ALT2"
|
|
line.long 0xb0 "FEC_FEC_TX_CLK_SELECT_INPUT,FEC_FEC_TX_CLK_SELECT_INPUT Register"
|
|
bitfld.long 0xb0 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RDY_INT: ALT1,DISP2_DAT13: ALT2"
|
|
line.long 0xb4 "GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,GPIO3_IPP_IND_G_IN_1_SELECT_INPUT Register"
|
|
bitfld.long 0xb4 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_LBA: ALT1,DI1_PIN12: ALT4"
|
|
line.long 0xb8 "GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,GPIO3_IPP_IND_G_IN_2_SELECT_INPUT Register"
|
|
bitfld.long 0xb8 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_CRE: ALT1,DI1_PIN13: ALT4"
|
|
line.long 0xbc "GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,GPIO3_IPP_IND_G_IN_3_SELECT_INPUT Register"
|
|
bitfld.long 0xbc 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_WE_B: ALT3,DI1_D0_CS: ALT4"
|
|
line.long 0xc0 "GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,GPIO3_IPP_IND_G_IN_4_SELECT_INPUT Register"
|
|
bitfld.long 0xc0 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RE_B: ALT3,DI1_D1_CS: ALT4"
|
|
line.long 0xc4 "GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,GPIO3_IPP_IND_G_IN_5_SELECT_INPUT Register"
|
|
bitfld.long 0xc4 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_ALE: ALT3,DISPB2_SER_DIN: ALT4"
|
|
line.long 0xc8 "GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,GPIO3_IPP_IND_G_IN_6_SELECT_INPUT Register"
|
|
bitfld.long 0xc8 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_CLE: ALT3,DISPB2_SER_DIO: ALT4"
|
|
line.long 0xcc "GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,GPIO3_IPP_IND_G_IN_7_SELECT_INPUT Register"
|
|
bitfld.long 0xcc 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_WP_B: ALT3,DISPB2_SER_CLK: ALT4"
|
|
line.long 0xd0 "GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,GPIO3_IPP_IND_G_IN_8_SELECT_INPUT Register"
|
|
bitfld.long 0xd0 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RB0: ALT3,DISPB2_SER_RS: ALT4"
|
|
line.long 0xd4 "GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,GPIO3_IPP_IND_G_IN_12_SELECT_INPUT Register"
|
|
bitfld.long 0xd4 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "GPIO_NAND: ALT0,CSI1_D8: ALT3"
|
|
line.long 0xd8 "HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT Register"
|
|
bitfld.long 0xd8 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_A27: ALT5,DI2_PIN4: ALT3,GPIO1_8: ALT2,?..."
|
|
line.long 0xdc "HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT Register"
|
|
bitfld.long 0xdc 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_A26: ALT5,DI_GP3: ALT3"
|
|
line.long 0xe0 "HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT,HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT Register"
|
|
bitfld.long 0xe0 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_A27: ALT6,DISPB2_SER_DIN: ALT2"
|
|
line.long 0xe4 "HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT,HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT Register"
|
|
bitfld.long 0xe4 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RB2: ALT5,DI_GP2: ALT2"
|
|
line.long 0xe8 "HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT Register"
|
|
bitfld.long 0xe8 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "KEY_COL5: ALT6,GPIO1_6: ALT2"
|
|
line.long 0xec "I2C1_IPP_SCL_IN_SELECT_INPUT,I2C1_IPP_SCL_IN_SELECT_INPUT Register"
|
|
bitfld.long 0xec 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D19: ALT4,CSPI1_SCLK: ALT1,SD2_CMD: ALT1,?..."
|
|
line.long 0xf0 "I2C1_IPP_SDA_IN_SELECT_INPUT,I2C1_IPP_SDA_IN_SELECT_INPUT Register"
|
|
bitfld.long 0xf0 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D16: ALT4,CSPI1_MOSI: ALT1,SD2_CLK: ALT1,?..."
|
|
line.long 0xf4 "I2C2_IPP_SCL_IN_SELECT_INPUT,I2C2_IPP_SCL_IN_SELECT_INPUT Register"
|
|
bitfld.long 0xf4 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D27: ALT4,KEY_COL4: ALT3,USBH1_CLK: ALT5,GPIO1_2: ALT2"
|
|
line.long 0xf8 "I2C2_IPP_SDA_IN_SELECT_INPUT,I2C2_IPP_SDA_IN_SELECT_INPUT Register"
|
|
bitfld.long 0xf8 0.--1. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D24: ALT4,KEY_COL5: ALT3,USBH1_DIR: ALT5,GPIO1_3: ALT2"
|
|
line.long 0xfc "IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT Register"
|
|
bitfld.long 0xfc 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DI_GP3: ALT0,DI_GP4: ALT0"
|
|
line.long 0x100 "IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT Register"
|
|
bitfld.long 0x100 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "DISPB2_SER_DIN: ALT0,DISPB2_SER_DIO: ALT0"
|
|
line.long 0x104 "KPP_IPP_IND_COL_6_SELECT_INPUT,KPP_IPP_IND_COL_6_SELECT_INPUT Register"
|
|
bitfld.long 0x104 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D25: ALT1,DISP2_DAT0: ALT4"
|
|
line.long 0x108 "KPP_IPP_IND_COL_7_SELECT_INPUT,KPP_IPP_IND_COL_7_SELECT_INPUT Register"
|
|
bitfld.long 0x108 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D26: ALT1,DISP2_DAT1: ALT4"
|
|
line.long 0x10c "KPP_IPP_IND_ROW_4_SELECT_INPUT,KPP_IPP_IND_ROW_4_SELECT_INPUT Register"
|
|
bitfld.long 0x10c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D28: ALT1,DISP2_DAT6: ALT4"
|
|
line.long 0x110 "KPP_IPP_IND_ROW_5_SELECT_INPUT,KPP_IPP_IND_ROW_5_SELECT_INPUT Register"
|
|
bitfld.long 0x110 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D29: ALT1,DISP2_DAT7: ALT4"
|
|
line.long 0x114 "KPP_IPP_IND_ROW_6_SELECT_INPUT,KPP_IPP_IND_ROW_6_SELECT_INPUT Register"
|
|
bitfld.long 0x114 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D30: ALT1,DISP2_DAT8: ALT4"
|
|
line.long 0x118 "KPP_IPP_IND_ROW_7_SELECT_INPUT,KPP_IPP_IND_ROW_7_SELECT_INPUT Register"
|
|
bitfld.long 0x118 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D31: ALT1,DISP2_DAT10: ALT4"
|
|
line.long 0x11c "UART1_IPP_UART_RTS_B_SELECT_INPUT,UART1_IPP_UART_RTS_B_SELECT_INPUT Register"
|
|
bitfld.long 0x11c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART1_RTS: ALT0,UART1_CTS: ALT0"
|
|
line.long 0x120 "UART1_IPP_UART_RXD_MUX_SELECT_INPUT,UART1_IPP_UART_RXD_MUX_SELECT_INPUT Register"
|
|
bitfld.long 0x120 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "UART1_RXD: ALT0,UART1_TXD: ALT0"
|
|
line.long 0x124 "UART2_IPP_UART_RTS_B_SELECT_INPUT,UART2_IPP_UART_RTS_B_SELECT_INPUT Register"
|
|
bitfld.long 0x124 0.--2. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D16: ALT3,EIM_D19: ALT3,EIM_D25: ALT4,EIM_D26: ALT4,USBH1_DATA0: ALT1,USBH1_DATA3: ALT1,?..."
|
|
line.long 0x128 "UART2_IPP_UART_RXD_MUX_SELECT_INPUT,UART2_IPP_UART_RXD_MUX_SELECT_INPUT Register"
|
|
bitfld.long 0x128 0.--2. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D17: ALT3,EIM_D18: ALT3,UART2_RXD: ALT0,UART2_TXD: ALT0,USBH1_DATA1: ALT1,USBH1_DATA2: ALT1,?..."
|
|
line.long 0x12c "UART3_IPP_UART_RTS_B_SELECT_INPUT,UART3_IPP_UART_RTS_B_SELECT_INPUT Register"
|
|
bitfld.long 0x12c 0.--2. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D17: ALT4,EIM_D18: ALT4,EIM_D24: ALT3,EIM_D27: ALT3,KEY_COL4: ALT2,KEY_COL5: ALT2,USBH1_CLK: ALT7,USBH1_DIR: ALT7"
|
|
line.long 0x130 "UART3_IPP_UART_RXD_MUX_SELECT_INPUT,UART3_IPP_UART_RXD_MUX_SELECT_INPUT Register"
|
|
bitfld.long 0x130 0.--3. " DAISY ,Selecting Pads Involved in Daisy Chain" "EIM_D25: ALT3,EIM_D26: ALT3,AUD3_BB_RXD: ALT1,AUD3_BB_FS: ALT1,UART3_RXD: ALT1,UART3_TXD: ALT1,USBH1_STP: ALT5,USBH1_NXT: ALT5,DISP2_DAT0: ALT5,DISP2_DAT1: ALT5,?..."
|
|
line.long 0x134 "USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT Register"
|
|
bitfld.long 0x134 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RB3: ALT6,DISP2_DAT0: ALT3"
|
|
line.long 0x138 "USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT Register"
|
|
bitfld.long 0x138 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D7: ALT5,DISP2_DAT8: ALT3"
|
|
line.long 0x13c "USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT Register"
|
|
bitfld.long 0x13c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D6: ALT5,DISP2_DAT9: ALT3"
|
|
line.long 0x140 "USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT Register"
|
|
bitfld.long 0x140 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D5: ALT5,DISP2_DAT10: ALT3"
|
|
line.long 0x144 "USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT Register"
|
|
bitfld.long 0x144 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D4: ALT5,DISP2_DAT11: ALT3"
|
|
line.long 0x148 "USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT Register"
|
|
bitfld.long 0x148 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D3: ALT5,DISP2_DAT12: ALT3"
|
|
line.long 0x14c "USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT Register"
|
|
bitfld.long 0x14c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D2: ALT5,DISP2_DAT13: ALT3"
|
|
line.long 0x150 "USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT Register"
|
|
bitfld.long 0x150 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D1: ALT5,DISP2_DAT14: ALT3"
|
|
line.long 0x154 "USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT Register"
|
|
bitfld.long 0x154 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_D0: ALT5,DISP2_DAT15: ALT3"
|
|
line.long 0x158 "USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT Register"
|
|
bitfld.long 0x158 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_CS5: ALT7,DISP2_DAT1: ALT3"
|
|
line.long 0x15c "USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT Register"
|
|
bitfld.long 0x15c 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_RB2: ALT6,DISP2_DAT7: ALT3"
|
|
line.long 0x160 "USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,USBOH3_IPP_IND_UH3_STP_SELECT_INPUT Register"
|
|
bitfld.long 0x160 0. " DAISY ,Selecting Pads Involved in Daisy Chain" "NANDF_CS4: ALT7,DISP2_DAT6: ALT3"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "IPUv3EX (Image Processing Unit 3)"
|
|
tree "Common registers"
|
|
base ad:0x5e000000
|
|
width 12.
|
|
group.long 0x00++0x3b
|
|
line.long 0x00 "IPU_CONF,IPU3E Configuration Register"
|
|
bitfld.long 0x00 31. " CSI_SEL ,CSI select bit" "CSI0,CSI1"
|
|
bitfld.long 0x00 30. " IC_INPUT ,IC Input select bit" "CSI0/1,VDI"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CSI1_DATA_SOURCE ,CSI1 data Source" "Parallel interface,MCT (MIPI)"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CSI0_DATA_SOURCE ,CSI0 data Source" "Parallel interface,MCT (MIPI)"
|
|
textline " "
|
|
bitfld.long 0x00 27. " VDI_DMFC_SYNC ,Direct path VDI -> IC_VF -> DMFC for sync flow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " IC_DMFC_SYNC ,IC to DMFC Sync flow" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 25. " IC_DMFC_SEL ,IC to DMFC select" "IDMAC,DMFC"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ISP_DOUBLE_FLOW ,ISP double flow" "2 flows,1 flow"
|
|
bitfld.long 0x00 22. " IDMAC_DISABLE ,Image DMA controller (IDMAC) disable bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IPU_DIAGBUS_ON ,IPU3E Diagnostics bus on" "Off,On"
|
|
bitfld.long 0x00 16.--20. " IPU_DIAGBUS_MODE ,IPU3E diagnostic bus mode" "Group 0,Group 1,Group 2,Group 3,Group 4,Group 5,Group 6,Group 7,Group 8,Group 9,Group 10,Group 11,Group 12,Group 13,Group 14,Group 15,Group 16,Group 17,?..."
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|
textline " "
|
|
bitfld.long 0x00 12. " VDI_EN ,VDI enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SISG_EN ,Still Image Synchronization Generator (SISG) Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DMFC_EN ,Display's Multi FIFO Controller Module (DMFC) Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DC_EN ,Display Controller Module (DC) Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SMFC_EN ,Sensor's Multi FIFO Controller Module (SMFC) Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DI1_EN ,Display Interface Module 1 Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DI0_EN ,Display interface Module 0 Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DP_EN ,Display processor Module Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ISP_EN ,Image Signal Processing Module Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRT_EN ,Image Rotation Module Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IC_EN ,Image Conversion Module Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSI1_EN ,Camera Sensor Interface 1 Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CSI0_EN ,Camera Sensor Interface 0 Enable bit" "Disabled,Enabled"
|
|
line.long 0x04 "SISG_CTRL0,SISG Control 0 Register"
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|
bitfld.long 0x04 30. " EXT_ACTV ,External Active" "Not active,Active"
|
|
hexmask.long 0x04 4.--28. 1. " VAL_STOP_SISG_COUNTER ,SISG Stop Counters value"
|
|
textline " "
|
|
bitfld.long 0x04 1.--3. " NO_VSYNC_2_STRT_CNT ,VSYCs to Start Counter" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VSYNC_RST_CNT ,VSYNC Resets counters" "VAL_STOP_SISG_COUNTER,VSYNC"
|
|
line.long 0x08 "SISG_CTRL1,SISG Control 1 Register"
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|
bitfld.long 0x08 13. " SISG_OUT_POL[5] ,Polarity of the SISG output signals" "Active low,Active high"
|
|
bitfld.long 0x08 12. " SISG_OUT_POL[4] ,Polarity of the SISG output signals" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SISG_OUT_POL[3] ,Polarity of the SISG output signals" "Active low,Active high"
|
|
bitfld.long 0x08 10. " SISG_OUT_POL[2] ,Polarity of the SISG output signals" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SISG_OUT_POL[1] ,Polarity of the SISG output signals" "Active low,Active high"
|
|
bitfld.long 0x08 8. " SISG_OUT_POL[0] ,Polarity of the SISG output signals" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x08 0.--4. " SISG_STROBE_CNT ,SISG Strobe Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0xC "SISG_SET_1,SISG set 1 Register"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. " SISG_SET ,Define the set value of the SISG counter #1"
|
|
line.long 0x10 "SISG_SET_2,SISG set 2 Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " SISG_SET ,Define the set value of the SISG counter #2"
|
|
line.long 0x14 "SISG_SET_3,SISG set 3 Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SISG_SET ,Define the set value of the SISG counter #3"
|
|
line.long 0x18 "SISG_SET_4,SISG set 4 Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " SISG_SET ,Define the set value of the SISG counter #4"
|
|
line.long 0x1C "SISG_SET_5,SISG set 5 Register"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. " SISG_SET ,Define the set value of the SISG counter #5"
|
|
line.long 0x20 "SISG_SET_6,SISG set 6 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " SISG_SET ,Define the set value of the SISG counter #6"
|
|
line.long 0x24 "SISG_CLR_1,SISG clear 1 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SISG_CLEAR ,Define the clear value of the SISG counter #1"
|
|
line.long 0x28 "SISG_CLR_2,SISG clear 2 Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " SISG_CLEAR ,Define the clear value of the SISG counter #2"
|
|
line.long 0x2C "SISG_CLR_3,SISG clear 3 Register"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " SISG_CLEAR ,Define the clear value of the SISG counter #3"
|
|
line.long 0x30 "SISG_CLR_4,SISG clear 4 Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " SISG_CLEAR ,Define the clear value of the SISG counter #4"
|
|
line.long 0x34 "SISG_CLR_5,SISG clear 5 Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SISG_CLEAR ,Define the clear value of the SISG counter #5"
|
|
line.long 0x38 "SISG_CLR_6,SISG clear 6 Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " SISG_CLEAR ,Define the clear value of the SISG counter #6"
|
|
width 19.
|
|
group.long 0x3c++0x23
|
|
line.long 0x0 "IPU_INT_CTRL_1,IPU3E Interrupt Control Register 1"
|
|
bitfld.long 0x0 31. " IDMAC_EOF_EN_31 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " IDMAC_EOF_EN_29 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " IDMAC_EOF_EN_28 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " IDMAC_EOF_EN_27 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " IDMAC_EOF_EN_24 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 23. " IDMAC_EOF_EN_23 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 22. " IDMAC_EOF_EN_22 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " IDMAC_EOF_EN_21 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " IDMAC_EOF_EN_20 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " IDMAC_EOF_EN_18 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 17. " IDMAC_EOF_EN_17 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 15. " IDMAC_EOF_EN_15 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " IDMAC_EOF_EN_14 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " IDMAC_EOF_EN_13 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " IDMAC_EOF_EN_12 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " IDMAC_EOF_EN_11 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " IDMAC_EOF_EN_10 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " IDMAC_EOF_EN_9 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " IDMAC_EOF_EN_8 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " IDMAC_EOF_EN_7 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IDMAC_EOF_EN_6 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " IDMAC_EOF_EN_5 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " IDMAC_EOF_EN_4 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " IDMAC_EOF_EN_3 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " IDMAC_EOF_EN_2 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " IDMAC_EOF_EN_1 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " IDMAC_EOF_EN_0 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "IPU_INT_CTRL_2,IPU3E Interrupt Control Register 2"
|
|
bitfld.long 0x04 20. " IDMAC_EOF_EN_52 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " IDMAC_EOF_EN_51 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " IDMAC_EOF_EN_50 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " IDMAC_EOF_EN_49 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " IDMAC_EOF_EN_48 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " IDMAC_EOF_EN_47 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " IDMAC_EOF_EN_46 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " IDMAC_EOF_EN_45 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " IDMAC_EOF_EN_44 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " IDMAC_EOF_EN_43 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " IDMAC_EOF_EN_42 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " IDMAC_EOF_EN_41 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " IDMAC_EOF_EN_40 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " IDMAC_EOF_EN_33 ,Enable End of Frame of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "IPU_INT_CTRL_3,IPU3E Interrupt Control Register 3"
|
|
bitfld.long 0x08 31. " IDMAC_NFACK_EN_31 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " IDMAC_NFACK_EN_29 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 28. " IDMAC_NFACK_EN_28 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " IDMAC_NFACK_EN_27 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " IDMAC_NFACK_EN_24 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " IDMAC_NFACK_EN_23 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " IDMAC_NFACK_EN_22 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " IDMAC_NFACK_EN_21 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " IDMAC_NFACK_EN_20 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IDMAC_NFACK_EN_18 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " IDMAC_NFACK_EN_17 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " IDMAC_NFACK_EN_15 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " IDMAC_NFACK_EN_14 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " IDMAC_NFACK_EN_13 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " IDMAC_NFACK_EN_12 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " IDMAC_NFACK_EN_11 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " IDMAC_NFACK_EN_10 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " IDMAC_NFACK_EN_9 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " IDMAC_NFACK_EN_8 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " IDMAC_NFACK_EN_7 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " IDMAC_NFACK_EN_6 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " IDMAC_NFACK_EN_5 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " IDMAC_NFACK_EN_4 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " IDMAC_NFACK_EN_3 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " IDMAC_NFACK_EN_2 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " IDMAC_NFACK_EN_1 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " IDMAC_NFACK_EN_0 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x0c "IPU_INT_CTRL_4,IPU3E Interrupt Control Register 4"
|
|
bitfld.long 0x0c 20. " IDMAC_NFACK_EN_52 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0c 19. " IDMAC_NFACK_EN_51 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 18. " IDMAC_NFACK_EN_50 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0c 17. " IDMAC_NFACK_EN_49 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " IDMAC_NFACK_EN_48 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0c 15. " IDMAC_NFACK_EN_47 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 14. " IDMAC_NFACK_EN_46 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0c 13. " IDMAC_NFACK_EN_45 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " IDMAC_NFACK_EN_44 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0c 11. " IDMAC_NFACK_EN_43 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " IDMAC_NFACK_EN_42 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " IDMAC_NFACK_EN_41 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " IDMAC_NFACK_EN_40 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0c 1. " IDMAC_NFACK_EN_33 ,Enable New Frame Ack of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x10 "IPU_INT_CTRL_5,IPU3E Interrupt Control Register 5"
|
|
bitfld.long 0x10 31. " IDMAC_NFB4EOF_EN_31 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " IDMAC_NFB4EOF_EN_29 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 28. " IDMAC_NFB4EOF_EN_28 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " IDMAC_NFB4EOF_EN_27 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " IDMAC_NFB4EOF_EN_24 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " IDMAC_NFB4EOF_EN_23 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 22. " IDMAC_NFB4EOF_EN_22 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " IDMAC_NFB4EOF_EN_21 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " IDMAC_NFB4EOF_EN_20 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " IDMAC_NFB4EOF_EN_18 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " IDMAC_NFB4EOF_EN_17 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " IDMAC_NFB4EOF_EN_15 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IDMAC_NFB4EOF_EN_14 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " IDMAC_NFB4EOF_EN_13 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 12. " IDMAC_NFB4EOF_EN_12 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " IDMAC_NFB4EOF_EN_11 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " IDMAC_NFB4EOF_EN_10 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " IDMAC_NFB4EOF_EN_9 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " IDMAC_NFB4EOF_EN_8 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " IDMAC_NFB4EOF_EN_7 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " IDMAC_NFB4EOF_EN_6 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " IDMAC_NFB4EOF_EN_5 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " IDMAC_NFB4EOF_EN_4 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " IDMAC_NFB4EOF_EN_3 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " IDMAC_NFB4EOF_EN_2 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " IDMAC_NFB4EOF_EN_1 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " IDMAC_NFB4EOF_EN_0 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x14 "IPU_INT_CTRL_6,IPU3E Interrupt Control Register 6"
|
|
bitfld.long 0x14 20. " IDMAC_NFB4EOF_EN_52 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 19. " IDMAC_NFB4EOF_EN_51 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 18. " IDMAC_NFB4EOF_EN_50 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " IDMAC_NFB4EOF_EN_49 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " IDMAC_NFB4EOF_EN_48 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " IDMAC_NFB4EOF_EN_47 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 14. " IDMAC_NFB4EOF_EN_46 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " IDMAC_NFB4EOF_EN_45 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 12. " IDMAC_NFB4EOF_EN_44 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " IDMAC_NFB4EOF_EN_43 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " IDMAC_NFB4EOF_EN_42 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " IDMAC_NFB4EOF_EN_41 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " IDMAC_NFB4EOF_EN_40 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " IDMAC_NFB4EOF_EN_33 ,New Frame before end-of-frame error indication of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x18 "IPU_INT_CTRL_7,IPU3E Interrupt Control Register 7"
|
|
bitfld.long 0x18 31. " IDMAC_EOS_EN_31 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " IDMAC_EOS_EN_29 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 28. " IDMAC_EOS_EN_28 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " IDMAC_EOS_EN_27 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " IDMAC_EOS_EN_24 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " IDMAC_EOS_EN_23 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x1c "IPU_INT_CTRL_8,IPU3E Interrupt Control Register 8"
|
|
bitfld.long 0x1c 20. " IDMAC_EOS_EN_52 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x1c 19. " IDMAC_EOS_EN_51 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 12. " IDMAC_EOS_EN_44 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x1c 11. " IDMAC_EOS_EN_43 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 10. " IDMAC_EOS_EN_42 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x1c 9. " IDMAC_EOS_EN_41 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 1. " IDMAC_EOS_EN_33 ,End of Scroll indication of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x20 "IPU_INT_CTRL_9,IPU3E Interrupt Control Register 9"
|
|
bitfld.long 0x20 31. " CSI1_PUPE_EN ,CSI1 parameters update error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " CSI0_PUPE_EN ,CSI0 parameters update error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 29. " ISP_PUPE_EN ,ISP parameters update error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 28. " IC_VF_BUF_OVF_EN ,Enables an interrupt that is a result of the IC Buffer overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 27. " IC_ENC_BUF_OVF_EN ,Enables an interrupt that is a result of the IC Buffer overflow" "Disabled,Enabled"
|
|
bitfld.long 0x20 26. " IC_BAYER_BUF_OVF_EN ,Enables an interrupt that is a result of the IC Buffer overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0. " VDI_FIFO1_OVF_EN ,FIFO1 overflow Interrupt1 Enable" "Disabled,Enabled"
|
|
group.long 0x60++0x3f
|
|
line.long 0x0 "IPU_INT_CTRL_10,IPU3E Interrupt Control Register 10"
|
|
bitfld.long 0x0 30. " AXIR_ERR_EN ,AXI read access interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " AXIW_ERR_EN ,AXI write access interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " NON_PRIVILEGED_ACC_ERR_EN ,Non Privileged Access Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " IC_BAYER_FRM_LOST_ERR_EN ,IC's Bayer frame lost interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " IC_ENC_FRM_LOST_ERR_EN ,IC's encoding frame lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " IC_VF_FRM_LOST_ERR_EN ,IC's view finder frame lost interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 22. " DI1_TIME_OUT_ERR_EN ,DI1 time out error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " DI0_TIME_OUT_ERR_EN ,DI0 time out error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " DI1_SYNC_DISP_ERR_EN ,DI1 Synchronous display error enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 19. " DI0_SYNC_DISP_ERR_EN ,DI0 Synchronous display error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 18. " DC_TEARING_ERR_6_EN ,Tearing Error #6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 17. " DC_TEARING_ERR_2_EN ,Tearing Error #2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " DC_TEARING_ERR_1_EN ,Tearing Error #1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " ISP_RAM_HIST_OF_EN ,Histogram RAM overflow/underun Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " ISP_RAM_ST_OF_EN ,Statistics RAM overflow/underun Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " SMFC3_FRM_LOST_EN ,Frame Lost of SMFC channel 3 interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SMFC2_FRM_LOST_EN ,Frame Lost of SMFC channel 2 interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " SMFC1_FRM_LOST_EN ,Frame Lost of SMFC channel 1 interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " SMFC0_FRM_LOST_EN ,Frame Lost of SMFC channel 0 interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x4 "IPU_INT_CTRL_11,IPU3E Interrupt Control Register 11"
|
|
bitfld.long 0x4 22. " IDMAC_EOBND_EN_22 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " IDMAC_EOBND_EN_21 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " IDMAC_EOBND_EN_20 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 12. " IDMAC_EOBND_EN_12 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " IDMAC_EOBND_EN_11 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " IDMAC_EOBND_EN_5 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " IDMAC_EOBND_EN_3 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " IDMAC_EOBND_EN_2 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " IDMAC_EOBND_EN_1 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " DMAC_EOBND_EN_0 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x8 "IPU_INT_CTRL_12,IPU3E Interrupt Control Register 12"
|
|
bitfld.long 0x8 18. " IDMAC_EOBND_EN_50 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x8 17. " IDMAC_EOBND_EN_49 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16. " IDMAC_EOBND_EN_48 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x8 15. " IDMAC_EOBND_EN_47 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 14. " IDMAC_EOBND_EN_46 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x8 13. " IDMAC_EOBND_EN_45 ,End-of-band indication of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0xc "IPU_INT_CTRL_13,IPU3E Interrupt Control Register 13"
|
|
bitfld.long 0xc 31. " IDMAC_TH_EN_31 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 29. " IDMAC_TH_EN_29 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 28. " IDMAC_TH_EN_28 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 27. " IDMAC_TH_EN_27 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 24. " IDMAC_TH_EN_24 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 23. " IDMAC_TH_EN_23 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 22. " IDMAC_TH_EN_22 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 21. " IDMAC_TH_EN_21 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 20. " IDMAC_TH_EN_20 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 18. " IDMAC_TH_EN_18 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 17. " IDMAC_TH_EN_17 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 15. " IDMAC_TH_EN_15 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 14. " IDMAC_TH_EN_14 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 13. " IDMAC_TH_EN_13 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 12. " IDMAC_TH_EN_12 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 11. " IDMAC_TH_EN_11 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 10. " IDMAC_TH_EN_10 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 9. " IDMAC_TH_EN_9 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 8. " IDMAC_TH_EN_8 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 7. " IDMAC_TH_EN_7 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 6. " IDMAC_TH_EN_6 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 5. " IDMAC_TH_EN_5 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 4. " IDMAC_TH_EN_4 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 3. " IDMAC_TH_EN_3 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 2. " IDMAC_TH_EN_2 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0xc 1. " IDMAC_TH_EN_1 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xc 0. " IDMAC_TH_EN_0 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x10 "IPU_INT_CTRL_14,IPU3E Interrupt Control Register 14"
|
|
bitfld.long 0x10 20. " IDMAC_TH_EN_52 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 19. " IDMAC_TH_EN_51 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 18. " IDMAC_TH_EN_50 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " IDMAC_TH_EN_49 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " IDMAC_TH_EN_48 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " IDMAC_TH_EN_47 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IDMAC_TH_EN_46 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " IDMAC_TH_EN_45 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 12. " IDMAC_TH_EN_44 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " IDMAC_TH_EN_43 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " IDMAC_TH_EN_42 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " IDMAC_TH_EN_41 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " IDMAC_TH_EN_40 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " IDMAC_TH_EN_33 ,Threshold crossing indication of Channel interrupt" "Disabled,Enabled"
|
|
line.long 0x14 "IPU_INT_CTRL_15,IPU3E Interrupt Control Register 15"
|
|
bitfld.long 0x14 31. " DI1_CNT_EN_PRE_8_EN ,Trigger generated by counter #8 of DI1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DI1_CNT_EN_PRE_3_EN ,Trigger generated by counter #3 of DI1 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DI1_DISP_CLK_EN_PRE_EN , DI1_DISP_CLK interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DI0_CNT_EN_PRE_10_EN ,Trigger generated by counter #10 of DI0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DI0_CNT_EN_PRE_9_EN ,Trigger generated by counter #9 of DI0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DI0_CNT_EN_PRE_8_EN ,Trigger generated by counter #8 of DI0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DI0_CNT_EN_PRE_7_EN ,Trigger generated by counter #7 of DI0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DI0_CNT_EN_PRE_6_EN ,Trigger generated by counter #6 of DI0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DI0_CNT_EN_PRE_5_EN ,Trigger generated by counter #5 of DI0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DI0_CNT_EN_PRE_4_EN ,Trigger generated by counter #4 of DI0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DI0_CNT_EN_PRE_3_EN ,Trigger generated by counter #3 of DI0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DI0_CNT_EN_PRE_2_EN ,Trigger generated by counter #2 of DI0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DI0_CNT_EN_PRE_1_EN ,Trigger generated by counter #1 of DI0 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DI0_CNT_EN_PRE_0_EN ,Trigger generated by counter #0 of DI0 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DC_ASYNC_STOP_EN ,DP stops an async flow and moves to a sync flow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DC_DP_START_EN ,DP start a new sync or async flow or when an async flow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DI_VSYNC_PRE_1_EN ,Enables the DI1 interrupt indicating of a VSYNC signal" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DI_VSYNC_PRE_0_EN ,Enables the DI0 interrupt indicating of a VSYNC signal" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DC_FC_6_EN ,Enables the DC Frame Complete on channel #6 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DC_FC_4_EN ,Enables the DC Frame Complete on channel #4 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DC_FC_3_EN ,Enables the DC Frame Complete on channel #3 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DC_FC_2_EN ,Enables the DC Frame Complete on channel #2 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DC_FC_1_EN ,Enables the DC Frame Complete on channel #1 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DC_FC_0_EN ,Enables the DC Frame Complete on channel #0 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DP_ASF_BRAKE_EN ,DP Async Flow Brake enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DP_SF_BRAKE_EN ,DP Sync Flow Brake enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DP_ASF_END_EN ,DP Async Flow End enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DP_ASF_START_EN ,DP Async Flow Start enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DP_SF_END_EN ,DP Sync Flow End enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DP_SF_START_EN ,DP Sync Flow Start enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " IPU_SNOOPING2_INT_EN ,IPU3E snooping 2 interrupt enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " IPU_SNOOPING1_INT_EN ,IPU3E snooping 1 interrupt enable bit" "Disabled,Enabled"
|
|
line.long 0x18 "IPU_SDMA_EVENT_1,IPU3E SDMA Event Control Register 1"
|
|
bitfld.long 0x18 31. " IDMAC_EOF_SDMA_EN_31 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " IDMAC_EOF_SDMA_EN_29 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 28. " IDMAC_EOF_SDMA_EN_28 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " IDMAC_EOF_SDMA_EN_27 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " IDMAC_EOF_SDMA_EN_24 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " IDMAC_EOF_SDMA_EN_23 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 22. " IDMAC_EOF_SDMA_EN_22 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " IDMAC_EOF_SDMA_EN_21 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " IDMAC_EOF_SDMA_EN_20 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " IDMAC_EOF_SDMA_EN_18 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 17. " IDMAC_EOF_SDMA_EN_17 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " IDMAC_EOF_SDMA_EN_15 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 14. " IDMAC_EOF_SDMA_EN_14 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 13. " IDMAC_EOF_SDMA_EN_13 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 12. " IDMAC_EOF_SDMA_EN_12 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " IDMAC_EOF_SDMA_EN_11 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 10. " IDMAC_EOF_SDMA_EN_10 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " IDMAC_EOF_SDMA_EN_9 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " IDMAC_EOF_SDMA_EN_8 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 7. " IDMAC_EOF_SDMA_EN_7 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 6. " IDMAC_EOF_SDMA_EN_6 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " IDMAC_EOF_SDMA_EN_5 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " IDMAC_EOF_SDMA_EN_4 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " IDMAC_EOF_SDMA_EN_3 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " IDMAC_EOF_SDMA_EN_2 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " IDMAC_EOF_SDMA_EN_1 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " IDMAC_EOF_SDMA_EN_0 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
line.long 0x1c "IPU_SDMA_EVENT_2,IPU3E SDMA Event Control Register 2"
|
|
bitfld.long 0x1c 20. " IDMAC_EOF_SDMA_EN_52 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x1c 19. " IDMAC_EOF_SDMA_EN_51 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 18. " IDMAC_EOF_SDMA_EN_50 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x1c 17. " IDMAC_EOF_SDMA_EN_49 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 16. " IDMAC_EOF_SDMA_EN_48 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x1c 15. " IDMAC_EOF_SDMA_EN_47 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 14. " IDMAC_EOF_SDMA_EN_46 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x1c 13. " IDMAC_EOF_SDMA_EN_45 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 12. " IDMAC_EOF_SDMA_EN_44 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x1c 11. " IDMAC_EOF_SDMA_EN_43 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 10. " IDMAC_EOF_SDMA_EN_42 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x1c 9. " IDMAC_EOF_SDMA_EN_41 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 8. " IDMAC_EOF_SDMA_EN_40 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x1c 1. " IDMAC_EOF_SDMA_EN_33 ,Enable End of Frame of Channel SDMA event" "Disabled,Enabled"
|
|
line.long 0x20 "IPU_SDMA_EVENT_3,IPU3E SDMA Event Control Register 3"
|
|
bitfld.long 0x20 31. " IDMAC_NFACK_SDMA_EN_31 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " IDMAC_NFACK_SDMA_EN_29 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 28. " IDMAC_NFACK_SDMA_EN_28 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 27. " IDMAC_NFACK_SDMA_EN_27 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 24. " IDMAC_NFACK_SDMA_EN_24 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 23. " IDMAC_NFACK_SDMA_EN_23 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 22. " IDMAC_NFACK_SDMA_EN_22 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 21. " IDMAC_NFACK_SDMA_EN_21 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " IDMAC_NFACK_SDMA_EN_20 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 18. " IDMAC_NFACK_SDMA_EN_18 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 17. " IDMAC_NFACK_SDMA_EN_17 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 15. " IDMAC_NFACK_SDMA_EN_15 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 14. " IDMAC_NFACK_SDMA_EN_14 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 13. " IDMAC_NFACK_SDMA_EN_13 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 12. " IDMAC_NFACK_SDMA_EN_12 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 11. " IDMAC_NFACK_SDMA_EN_11 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 10. " IDMAC_NFACK_SDMA_EN_10 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 9. " IDMAC_NFACK_SDMA_EN_9 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " IDMAC_NFACK_SDMA_EN_8 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 7. " IDMAC_NFACK_SDMA_EN_7 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 6. " IDMAC_NFACK_SDMA_EN_6 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " IDMAC_NFACK_SDMA_EN_5 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " IDMAC_NFACK_SDMA_EN_4 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 3. " IDMAC_NFACK_SDMA_EN_3 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 2. " IDMAC_NFACK_SDMA_EN_2 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x20 1. " IDMAC_NFACK_SDMA_EN_1 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0. " IDMAC_EOF_SDMA_EN_0 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
line.long 0x24 "IPU_SDMA_EVENT_4,IPU3E SDMA Event Control Register 4"
|
|
bitfld.long 0x24 20. " IDMAC_NFACK_SDMA_EN_52 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x24 19. " IDMAC_NFACK_SDMA_EN_51 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 18. " IDMAC_NFACK_SDMA_EN_50 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x24 17. " IDMAC_NFACK_SDMA_EN_49 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16. " IDMAC_NFACK_SDMA_EN_48 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x24 15. " IDMAC_NFACK_SDMA_EN_47 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 14. " IDMAC_NFACK_SDMA_EN_46 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x24 13. " IDMAC_NFACK_SDMA_EN_45 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 12. " IDMAC_NFACK_SDMA_EN_44 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x24 11. " IDMAC_NFACK_SDMA_EN_43 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 10. " IDMAC_NFACK_SDMA_EN_42 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x24 9. " IDMAC_NFACK_SDMA_EN_41 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 8. " IDMAC_NFACK_SDMA_EN_40 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x24 1. " IDMAC_NFACK_SDMA_EN_33 ,Enable New Frame Acknowledge of Channel SDMA event" "Disabled,Enabled"
|
|
line.long 0x28 "IPU_SDMA_EVENT_7,IPU3E SDMA Event Control Register 7"
|
|
bitfld.long 0x28 31. " IDMAC_EOS_SDMA_EN_31 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " IDMAC_EOS_SDMA_EN_29 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 28. " IDMAC_EOS_SDMA_EN_28 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x28 27. " IDMAC_EOS_SDMA_EN_27 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 24. " IDMAC_EOS_SDMA_EN_24 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x28 23. " IDMAC_EOS_SDMA_EN_23 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
line.long 0x2c "IPU_SDMA_EVENT_8,IPU3E SDMA Event Control Register 8"
|
|
bitfld.long 0x2c 20. " IDMAC_EOS_SDMA_EN_52 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x2c 19. " IDMAC_EOS_SDMA_EN_51 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2c 12. " IDMAC_EOS_SDMA_EN_44 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x2c 11. " IDMAC_EOS_SDMA_EN_43 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2c 10. " IDMAC_EOS_SDMA_EN_42 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x2c 9. " IDMAC_EOS_SDMA_EN_41 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2c 1. " IDMAC_EOS_SDMA_EN_32 ,Enable End of Scroll of Channel SDMA event" "Disabled,Enabled"
|
|
line.long 0x30 "IPU_SDMA_EVENT_11,IPU3E SDMA Event Control Register 11"
|
|
bitfld.long 0x30 22. " IDMAC_EOBND_SDMA_EN_22 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x30 21. " DMAC_EOBND_SDMA_EN_21 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 20. " IDMAC_EOBND_SDMA_EN_20 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x30 12. " IDMAC_EOBND_SDMA_EN_12 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 11. " IDMAC_EOBND_SDMA_EN_11 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " IDMAC_EOBND_SDMA_EN_5 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 3. " IDMAC_EOBND_SDMA_EN_3 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " IDMAC_EOBND_SDMA_EN_2 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 1. " IDMAC_EOBND_SDMA_EN_1 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " IDMAC_EOBND_SDMA_EN_0 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
line.long 0x34 "IPU_SDMA_EVENT_12,IPU3E SDMA Event Control Register 12"
|
|
bitfld.long 0x34 18. " IDMAC_EOBND_SDMA_EN_50 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x34 17. " IDMAC_EOBND_SDMA_EN_49 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 16. " IDMAC_EOBND_SDMA_EN_48 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x34 15. " IDMAC_EOBND_SDMA_EN_47 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 14. " IDMAC_EOBND_SDMA_EN_46 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x34 13. " IDMAC_EOBND_SDMA_EN_45 ,Enable End of Band of Channel SDMA event" "Disabled,Enabled"
|
|
line.long 0x38 "IPU_SDMA_EVENT_13,IPU3E SDMA Event Control Register 13"
|
|
bitfld.long 0x38 31. " IDMAC_TH_SDMA_EN_31 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " IDMAC_TH_SDMA_EN_29 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 28. " IDMAC_TH_SDMA_EN_28 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 27. " IDMAC_TH_SDMA_EN_27 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 24. " IDMAC_TH_SDMA_EN_24 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 23. " IDMAC_TH_SDMA_EN_23 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 22. " IDMAC_TH_SDMA_EN_22 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 21. " IDMAC_TH_SDMA_EN_21 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 20. " IDMAC_TH_SDMA_EN_20 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 18. " IDMAC_TH_SDMA_EN_18 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 17. " IDMAC_TH_SDMA_EN_17 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 15. " IDMAC_TH_SDMA_EN_15 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 14. " IDMAC_TH_SDMA_EN_14 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 13. " IDMAC_TH_SDMA_EN_13 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 12. " IDMAC_TH_SDMA_EN_12 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 11. " IDMAC_TH_SDMA_EN_11 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 10. " IDMAC_TH_SDMA_EN_10 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 9. " IDMAC_TH_SDMA_EN_9 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 8. " IDMAC_TH_SDMA_EN_8 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 7. " IDMAC_TH_SDMA_EN_7 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 6. " IDMAC_TH_SDMA_EN_6 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " IDMAC_TH_SDMA_EN_5 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " IDMAC_TH_SDMA_EN_4 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 3. " IDMAC_TH_SDMA_EN_3 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 2. " IDMAC_TH_SDMA_EN_2 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x38 1. " IDMAC_TH_SDMA_EN_1 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 0. " IDMAC_TH_SDMA_EN_0 ,Enable Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
line.long 0x3c "IPU_SDMA_EVENT_14,IPU3E SDMA Event Control Register 14"
|
|
bitfld.long 0x3c 20. " IDMAC_TH_SDMA_EN_52 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x3c 19. " IDMAC_TH_SDMA_EN_51 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 18. " IDMAC_TH_SDMA_EN_50 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x3c 17. " IDMAC_TH_SDMA_EN_49 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 16. " IDMAC_TH_SDMA_EN_48 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x3c 15. " IDMAC_TH_SDMA_EN_47 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 14. " IDMAC_TH_SDMA_EN_46 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x3c 13. " IDMAC_TH_SDMA_EN_45 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 12. " IDMAC_TH_SDMA_EN_44 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x3c 11. " IDMAC_TH_SDMA_EN_43 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 10. " IDMAC_TH_SDMA_EN_42 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x3c 9. " IDMAC_TH_SDMA_EN_41 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 8. " IDMAC_TH_SDMA_EN_40 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
bitfld.long 0x3c 1. " IDMAC_TH_SDMA_EN_33 ,Threshold of Channel SDMA event" "Disabled,Enabled"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "IPU_SRM_PRI1,IPUv3E Shadow Registers Memory Priority 1 Register"
|
|
bitfld.long 0x00 19.--20. " ISP_SRM_MODE ,ISP SRM Mode" "Disabled,Next frame,Frame by frame,Update now"
|
|
bitfld.long 0x00 16.--18. " ISP_SRM_PRI ,ISP SRM priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " CSI0_SRM_MODE ,CSI0 SRM Mode" "Disabled,Next frame,Frame by frame,Update now"
|
|
bitfld.long 0x00 8.--10. " CSI0_SRM_PRI ,CSI0 SRM priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " CSI1_SRM_MODE ,CSI1 SRM Mode" "Disabled,Next frame,Frame by frame,Update now"
|
|
bitfld.long 0x00 0.--2. " CSI1_SRM_PRI ,CSI1 SRM priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "IPU_SRM_PRI2,IPU3E Shadow Registers Memory Priority 2 Register"
|
|
bitfld.long 0x04 27.--28. " DI1_SRM_MODE ,DCI1 SRM Mode" "Disabled,Next frame,Frame by frame,Update now"
|
|
bitfld.long 0x04 24.--26. " DI1_SRM_PRI ,DI1 SRM priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 19.--20. " DI0_SRM_MCU_USE ,DI0 SRM is used by Disabled" "Not updated,Updated,..."
|
|
bitfld.long 0x04 16.--18. " DI0_SRM_PRI ,DI0 SRM priority" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " DC_6_SRM_MODE ,DC Group #6 SRM Mode" "Disabled,Next frame,Frame by frame,Update now"
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bitfld.long 0x04 12.--13. " DC_2_SRM_MODE ,DC Group #2 SRM Mode" "Disabled,Next frame,Frame by frame,Update now"
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textline " "
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bitfld.long 0x04 9.--11. " DC_SRM_PRI ,DC SRM priority" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 7.--8. " DP_A1_SRM_MODE ,DP Async flow #1 SRM Mode" "Disabled,Next frame,Frame by frame,Update now"
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textline " "
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bitfld.long 0x04 5.--6. " DP_A0_SRM_MODE ,DP Async flow #0 SRM Mode" "Disabled,Next frame,Frame by frame,Update now"
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bitfld.long 0x04 3.--4. " DP_S_SRM_MODE ,DP sync flow SRM Mode" "Disabled,Next frame,Reserved,Update now"
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textline " "
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bitfld.long 0x04 0.--2. " DP_SRM_PRI ,DC SRM priority" "0,1,2,3,4,5,6,7"
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line.long 0x08 "IPU_FS_PROC_FLOW1,IPU3E FSU Processing Flow 1 Register"
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bitfld.long 0x08 31. " VF_IN_VALID ,View-finder input valid" "Skipped,Used"
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textline " "
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bitfld.long 0x08 30. " ENC_IN_VALID ,Encoding input valid" "Skipped,Used"
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textline " "
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bitfld.long 0x08 28.--29. " VDI_SRC_SEL ,Source select for the VDI" "MCU,CSI direct (cb7),?..."
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textline " "
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bitfld.long 0x08 24.--27. " PRP_SRC_SEL ,Source select for the Pre Processing Task" "MCU,Capture0 (smfc0),Capture1 (smfco1),Capture2 (smfco2),Capture3 (smfco3),IC direct (cb7),IRT Encoding,IRT viewfinder,Reserved,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x08 20.--23. " ISP_SRC_SEL ,Source select for the ISP" "MCU,Capture0 (smfc0),Capture1 (smfc1),Capture2 (smfc2),Capture3 (smfc3),Reserved,IRT Encoding,IRT viewfinder,IRT playback,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x08 16.--19. " PP_ROT_SRC_SEL ,Source select for the pre processing task of the IRT" "MCU,Capture0 (smfc0),Reserved,Capture2 (smfc2),Reserved,Post-processing,Reserved,Reserved,Reserved,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x08 12.--15. " PP_SRC_SEL ,Source select for the pre processing task of the IC" "MCU,Capture0 (smfc0),Reserved,Capture2 (smfc2),Reserved,Reserved,Rotation,Reserved,Reserved,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x08 8.--11. " PRPVF_ROT_SRC_SEL ,Source select for the view finder task of the IRT" "MCU,Capture0 (smfc0),Capture1 (smfc1),Capture2 (smfc2),Capture3 (smfc3),IC direct (cb7),Reserved,Reserved,View-finder,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x08 4.--7. " ALT_ISP_SRC_SEL ,Alternate Source select for the ISP" "MCU,Capture0 (smfc0),Reserved,Capture2 (smfc2),Reserved,Reserved,IRT Encoding,IRT viewfinder,IRT playback,?..."
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textline " "
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bitfld.long 0x08 0.--3. " PRPENC_ROT_SRC_SEL ,Source select for the encoding task of the IRT" "MCU,Capture0 (smfc0),Capture1 (smfc1),Capture2 (smfc2),Capture3 (smfc3),IC direct (cb7),Reserved,Encoding,Reserved,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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line.long 0x0c "IPU_FS_PROC_FLOW2,IPU3E FSU Processing Flow 2 Register"
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bitfld.long 0x0c 28.--31. " PRP_ALT_DEST_SEL ,Pre processing alternate flow's destination select" "MCU,IC input buffer (ch12),PP (ch11),PP_ROT (ch47),DC1 (ch28),DC2 (ch41),DP_ASYNC1 (ch24),DP_ASYNC0 (ch29),DP_SYNC1 (ch27),DP_SYNC0 (ch23),Alt DC2 (ch41),Alt DP_ASYNC1 (ch24),Alt DP_ASYNC0 (ch29),?..."
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textline " "
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bitfld.long 0x0c 24.--27. " PRP_DEST_SEL ,Destination select for Rotation task coming from the Post Processing input" "MCU,IC input buffer (ch12),PP (ch11),PP_ROT (ch47),DC1 (ch28),DC2 (ch41),DP_ASYNC1 (ch24),DP_ASYNC0 (ch29),DP_SYNC1 (ch27),DP_SYNC0 (ch23),Alt DC2 (ch41),Alt DP_ASYNC1 (ch24),Alt DP_ASYNC0 (ch29),?..."
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textline " "
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bitfld.long 0x0c 20.--23. " PRPENC_ROT_DEST_SEL ,Destination select for Rotation task coming from the Encoding input" "MCU,Reserved,Reserved,Reserved,Reserved,IC Pre Processing,Reserved,DC1 (ch28),DC2 (ch41),DP_SYNC0 (ch23),DP_SYNC1 (ch27),DP_ASYNC1 (ch24),DP_ASYNC0 (ch29),Alt DC2 (ch41),Alt DP_ASYNC1 (ch24),Alt DP_ASYNC0 (ch29)"
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textline " "
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bitfld.long 0x0c 16.--19. " PP_ROT_DEST_SEL ,Destination select for Rotation task coming from the Post Processing input" "MCU,Reserved,Reserved,Reserved,IC Playback,Reserved,Reserved,DC1 (ch28),DC2 (ch41),DP_SYNC0 (ch23),DP_SYNC1 (ch27),DP_ASYNC1 (ch24),DP_ASYNC0 (ch29),Alt DC2 (ch41),Alt DP_ASYNC1 (ch24),Alt DP_ASYNC0 (ch29)"
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textline " "
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bitfld.long 0x0c 12.--15. " PP_DEST_SEL ,Destination select for post processing task" "MCU,Reserved,Reserved,IRT playback,Reserved,Reserved,Reserved,DC1 (ch28),DC2 (ch41),DP_SYNC0 (ch23),DP_SYNC1 (ch27),DP_ASYNC1 (ch24),DP_ASYNC0 (ch29),Alt DC2 (ch41),Alt DP_ASYNC1 (ch24),Alt DP_ASYNC0 (ch29)"
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textline " "
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bitfld.long 0x0c 8.--11. " PRPVF_ROT_DEST_SEL ,Destination select for Rotation task coming from the View finder input" "MCU,Reserved,Reserved,Reserved,Reserved,IC Pre Processing,Reserved,DC1 (ch28),DC2 (ch41),DP_SYNC0 (ch23),DP_SYNC1 (ch27),DP_ASYNC1 (ch24),DP_ASYNC0 (ch29),Alt DC2 (ch41),Alt DP_ASYNC1 (ch24),Alt DP_ASYNC0 (ch29)"
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textline " "
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bitfld.long 0x0c 4.--7. " PRPVF_DEST_SEL ,Destination select for View finder task" "MCU,IRT viewfinder,Reserved,Reserved,Reserved,Reserved,Reserved,DC1 (ch28),DC2 (ch41),DP_SYNC0 (ch23),DP_SYNC1 (ch27),DP_ASYNC1 (ch24),DP_ASYNC0 (ch29),Alt DC2 (ch41),Alt DP_ASYNC1 (ch24),Alt DP_ASYNC0 (ch29)"
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textline " "
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bitfld.long 0x0c 0.--3. " PRP_ENC_DEST_SEL ,Destination select for Encoding task" "MCU,IRT Encoding,Reserved,Reserved,Reserved,Reserved,Reserved,DC1 (ch28),DC2 (ch41),DP_SYNC0 (ch23),DP_SYNC1 (ch27),DP_ASYNC1 (ch24),DP_ASYNC0 (ch29),Alt DC2 (ch41),Alt DP_ASYNC1 (ch24),Alt DP_ASYNC0 (ch29)"
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line.long 0x10 "IPU_FS_PROC_FLOW3,IPU3E FSU Processing Flow 3 Register"
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bitfld.long 0x10 22.--23. " EXT_SRC2_DEST_SEL ,Destination select for External Source 2" "Disabled,DP_SYNC0 (ch23),DP_SYNC1 (ch27),DC1 (ch28)"
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textline " "
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bitfld.long 0x10 20.--21. " EXT_SRC1_DEST_SEL ,Destination select for External Source 1" "Disabled,DP_SYNC0 (ch23),DP_SYNC1 (ch27),DC1 (ch28)"
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textline " "
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bitfld.long 0x10 11.--13. " SMFC3_DEST_SEL ,Destination select for SMFC3" "MCU,IRT Encoding,IRT viewfinder,IRT playback,IC Playback,IC Pre Processing,?..."
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textline " "
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bitfld.long 0x10 7.--10. " SMFC2_DEST_SEL ,Destination select for SMFC2" "MCU,IRT Encoding,IRT viewfinder,IRT playback,IC Playback,IC Pre Processing,Reserved,DC1 (ch28),DC2 (ch41),DP_SYNC0 (ch23),DP_SYNC1 (ch27),DP_ASYNC1 (ch24),DP_ASYNC0 (ch29),Alt DC2 (ch41),Alt DP_ASYNC1 (ch24),Alt DP_ASYNC0 (ch29)"
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textline " "
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bitfld.long 0x10 4.--6. " SMFC1_DEST_SEL ,Destination select for SMFC1" "MCU,IRT Encoding,IRT viewfinder,IRT playback,IC Playback,IC Pre Processing,?..."
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textline " "
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bitfld.long 0x10 0.--3. " SMFC0_DEST_SEL ,Destination select for SMFC0" "MCU,IRT Encoding,IRT viewfinder,IRT playback,IC Playback,IC Pre Processing,Reserved,DC1 (ch28),DC2 (ch41),DP_SYNC0 (ch23),DP_SYNC1 (ch27),DP_ASYNC1 (ch24),DP_ASYNC0 (ch29),Alt DC2 (ch41),Alt DP_ASYNC1 (ch24),Alt DP_ASYNC0 (ch29)"
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group.long 0xb4++0xb
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;23.--20./19.--16. probably 1001 (ISP) should be Reserved
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line.long 0x00 "IPU_FS_DISP_FLOW1,IPU3E FSU Displaying Flow 1 Register"
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bitfld.long 0x00 20.--23. " DC1_SRC_SEL ,Source select for DS1/DS2 - MG (graphics) plane (ch28)" "MCU,Capture0 (smfc0),Capture2 (smfc2),IC encoding,IC viewfinder,IC playback,IRT Encoding,IRT viewfinder,IRT playback,ISP,Reserved,Autoref,Autoref+snoop1,External source 1,Snoop1,External source 2"
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textline " "
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bitfld.long 0x00 16.--19. " DC2_SRC_SEL ,Source select for DS3 (ch41)" "MCU,Capture0 (smfc0),Capture2 (smfc2),IC encoding,IC viewfinder,IC playback,IRT Encoding,IRT viewfinder,IRT playback,ISP,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x00 12.--15. " DP_ASYNC1_SRC_SEL ,Source select for DS1/DS2 - Vx (video) plane (ch24)" "MCU,Capture0 (smfc0),Capture2 (smfc2),IC encoding,IC viewfinder,IC playback,IRT Encoding,IRT viewfinder,IRT playback,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x00 8.--11. " DP_ASYNC0_SRC_SEL ,Source select for DS2 - MG (graphics) plane (ch29)" "MCU,Capture0 (smfc0),Capture2 (smfc2),IC encoding,IC viewfinder,IC playback,IRT Encoding,IRT viewfinder,IRT playback,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x00 4.--7. " DP_SYNC1_SRC_SEL ,Source select for DS1/DS2 - Vx (video) plane (ch27)" "MCU,Capture0 (smfc0),Capture2 (smfc2),IC encoding,IC viewfinder,IC playback,IRT Encoding,IRT viewfinder,IRT playback,Reserved,Reserved,External source 1,External source 2,Reserved,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x00 0.--3. " DP_SYNC0_SRC_SEL ,Source select for DS2 - MG (graphics) plane (ch23))" "MCU,Capture0 (smfc0),Capture2 (smfc2),IC encoding,IC viewfinder,IC playback,IRT Encoding,IRT viewfinder,IRT playback,Reserved,Reserved,External source 1,External source 2,Reserved,Snoop1,Snoop2"
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line.long 0x04 "IPU_FS_DISP_FLOW2,IPU3E FSU Displaying Flow 2 Register"
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bitfld.long 0x04 16.--19. " DC2_ALT_SRC_SEL ,Source select for Alternate DS3 (ch41)" "MCU,Capture0 (smfc0),Capture2 (smfc2),IC encoding,IC viewfinder,IC playback,IRT Encoding,IRT viewfinder,IRT playback,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x04 4.--7. " DP_ASYNC1_ALT_SRC_SEL ,Source select for alternate DS1/DS2 - Vx (video) plane (ch24)" "MCU,Capture0 (smfc0),Capture2 (smfc2),IC encoding,IC viewfinder,IC playback,IRT Encoding,IRT viewfinder,IRT playback,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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textline " "
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bitfld.long 0x04 0.--3. " DP_ASYNC0_ALT_SRC_SEL ,Source select for alternate DS2 - MG (graphics) plane (ch29)" "MCU,Capture0 (smfc0),Capture2 (smfc2),IC encoding,IC viewfinder,IC playback,IRT Encoding,IRT viewfinder,IRT playback,Reserved,Reserved,Autoref,Autoref+snoop1,Autoref+snoop2,Snoop1,Snoop2"
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width 17.
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line.long 0x08 "IPU_SKIP,IPU SKIP Register"
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hexmask.long.word 0x08 20.--31. 1. " VDI_SKIP ,VDI Skip"
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bitfld.long 0x08 16.--19. " VDI_MAX_RATIO_SKIP ,Maximum Ratio Skip for VDI" "Disabled,1,2,3,4,5,6,7,8,9,10,11,?..."
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textline " "
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bitfld.long 0x08 11.--15. " CSI_SKIP_IC_VF ,Skipping pattern of the frames send to the IC for view finder" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--10. " CSI_MAX_RATIO_SKIP_IC_VF ,CSI Maximum Ratio Skip for IC (view finder task)" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x08 3.--7. " CSI_SKIP_IC_ENC ,Skipping pattern of the frames send to the IC for encoding" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--2. " CSI_MAX_RATIO_SKIP_IC_ENC ,CSI Maximum Ratio Skip for IC (encoding task)" "0,1,2,3,4,5,6,7"
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group.long 0xc4++0x23
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line.long 0x00 "IPU_DISP_GEN,Display General control Register"
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bitfld.long 0x00 25. " DI1_COUNTER_RELEASE ,DI1 Counter release" "Cleared and stopped,Released and running"
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bitfld.long 0x00 24. " DI0_COUNTER_RELEASE ,DI0 Counter release" "Cleared and stopped,Released and running"
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textline " "
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bitfld.long 0x00 23. " CSI_VSYNC_DEST ,Destination of the VSYNC coming from the CSI's" "CSI0_VSYNC to DI0 & CSI1_VSYNC to DI1,CSI1_VSYNC to DI0 & CSI0_VSYNC to DI1"
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textline " "
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bitfld.long 0x00 22. " MCU_MAX_BURST_STOP ,MCU Maximal burst" "Unlimited,8-beat"
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textline " "
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bitfld.long 0x00 18.--21. " MCU_T ,MCU address space MSB-T" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..."
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textline " "
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bitfld.long 0x00 17. " MCU_DI_ID_9 ,Defines the DI that the MCU DC's access via channel #9" "Via DI0,Via DI1"
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textline " "
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bitfld.long 0x00 16. " MCU_DI_ID_8 ,Defines the DI that the MCU DC's access via channel #8" "Via DI0,Via DI1"
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textline " "
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bitfld.long 0x00 6. " DP_PIPE_CLR ,DP Pipe Clear" "Idle,Cleared"
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textline " "
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bitfld.long 0x00 5. " DP_FG_EN_ASYNC1 ,FG_EN - partial plane Enable for async flow 1" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 4. " DP_FG_EN_ASYNC0 ,FG_EN - partial plane Enable for async flow 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 3. " DP_ASYNC_DOUBLE_FLOW ,DP Async Double Flow" "Single,Double"
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textline " "
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bitfld.long 0x00 2. " DC2_DOUBLE_FLOW ,DC2 Double Flow" "Single,Double"
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textline " "
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bitfld.long 0x00 1. " DI1_DUAL_MODE ,DI1 dual mode control" "Not dual,Dual"
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textline " "
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bitfld.long 0x00 0. " DI0_DUAL_MODE ,DI0 dual mode control" "Not dual,Dual"
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line.long 0x04 "IPU_DISP_ALT1,Display Alternate flow control Register 1"
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bitfld.long 0x04 28.--31. " SEL_ALT_0 ,Select alternative parameters instead of DI Sync Wave Gen counter#" "Disabled,1,2,3,4,5,6,7,8,?..."
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hexmask.long.word 0x04 16.--27. 1. " STEP_REPEAT_ALT_0 ,Defines the amount of repetitions that will be performed by the counter"
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textline " "
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bitfld.long 0x04 15. " CNT_AUTO_RELOAD_ALT_0 ,Counter auto reload mode" "Not automatically,Automatically"
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bitfld.long 0x04 12.--14. " CNT_CLR_SEL_ALT_0 ,Counter Clear select" "Disabled,Triggered,Reserved,Reserved,Reserved,CSI VSYNC,External VSYNC,Always on"
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textline " "
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hexmask.long.word 0x04 0.--11. 1. " RUN_VALUE_M1_ALT_0 ,Counter pre defined value"
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line.long 0x08 "IPU_DISP_ALT2,Display Alternate flow control Register 2"
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bitfld.long 0x08 16.--18. " RUN_RESOLUTION_ALT_0 ,Counter Run Resolution" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x08 12.--14. " OFFSET_RESOLUTION_ALT0 ,Counter offset Resolution" "0,1,2,3,4,5,6,7"
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textline " "
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hexmask.long.word 0x08 0.--11. 1. " OFFSET_VALUE_ALT_0 ,Counter offset value"
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line.long 0x0c "IPU_DISP_ALT3,Display Alternate flow control Register 3"
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bitfld.long 0x0c 28.--31. " SEL_ALT_1 ,Select alternative parameters instead of DI Sync Wave Gen counter#" "Disabled,1,2,3,4,5,6,7,8,?..."
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textline " "
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hexmask.long.word 0x0c 16.--27. 1. " STEP_REPEAT_ALT_1 ,Defines the amount of repetitions that will be performed by the counter"
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textline " "
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bitfld.long 0x0c 15. " CNT_AUTO_RELOAD_ALT_1 ,Counter auto reload mode" "Not automatically,Automatically"
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textline " "
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bitfld.long 0x0c 12.--14. " CNT_CLR_SEL_ALT_1 ,Counter Clear select" "Disabled,Same as display clock,Reserved,Reserved,Reserved,CSI VSYNC,External VSYNC,Always on"
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textline " "
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hexmask.long.word 0x0c 0.--11. 1. " RUN_VALUE_M1_ALT_1 ,Counter pre defined value"
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line.long 0x10 "IPU_DISP_ALT4,Display Alternate flow control Register 4"
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bitfld.long 0x10 16.--18. " RUN_RESOLUTION_ALT_1 ,Counter Run Resolution" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x10 12.--14. " OFFSET_RESOLUTION_ALT1 ,Counter offset Resolution" "0,1,2,3,4,5,6,7"
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textline " "
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hexmask.long.word 0x10 0.--11. 1. " OFFSET_VALUE_ALT_1 ,Counter offset value"
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line.long 0x14 "IPU_SNOOP,IPU3E Autorefresh and Snooping Control Register"
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bitfld.long 0x14 16. " SNOOP2_SYNC_BYP ,Bypass of the synchronizer on emi_snooping2 signal" "Normal,Bypassed"
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hexmask.long.word 0x14 0.--9. 1. " AUTOREF_PER ,Autorefresh period minus 1"
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line.long 0x18 "IPU_MEM_RST,IPU3E Memory Reset Control Register"
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bitfld.long 0x18 31. " RST_MEM_START ,Memory Reset Start" "No reset,Reset"
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bitfld.long 0x18 22. " RST_MEM_EN[22] ,Reset Memory Enable (dmfc_wr)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 21. " RST_MEM_EN[21] ,Reset Memory Enable (dmfc_rd)" "Disabled,Enabled"
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bitfld.long 0x18 20. " RST_MEM_EN[20] ,Reset Memory Enable (dc_template)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 19. " RST_MEM_EN[19] ,Reset Memory Enable (isp_tbpr)" "Disabled,Enabled"
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bitfld.long 0x18 18. " RST_MEM_EN[18] ,Reset Memory Enable (fifo_ram)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 17. " RST_MEM_EN[17] ,Reset Memory Enable (ram_mix0)" "Disabled,Enabled"
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bitfld.long 0x18 16. " RST_MEM_EN[16] ,Reset Memory Enable (ram_pp0)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 15. " RST_MEM_EN[15] ,Reset Memory Enable (ram_mix1)" "Disabled,Enabled"
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bitfld.long 0x18 14. " RST_MEM_EN[14] ,Reset Memory Enable (ram_pp1)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 13. " RST_MEM_EN[13] ,Reset Memory Enable (isp_hist)" "Disabled,Enabled"
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bitfld.long 0x18 12. " RST_MEM_EN[12] ,Reset Memory Enable (isp_st)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 11. " RST_MEM_EN[11] ,Reset Memory Enable (ram_smfc)" "Disabled,Enabled"
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bitfld.long 0x18 10. " RST_MEM_EN[10] ,Reset Memory Enable (lut1)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 9. " RST_MEM_EN[9] ,Reset Memory Enable (lut0)" "Disabled,Enabled"
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bitfld.long 0x18 8. " RST_MEM_EN[8] ,Reset Memory Enable (dsom)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 7. " RST_MEM_EN[7] ,Reset Memory Enable (dstm)" "Disabled,Enabled"
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bitfld.long 0x18 6. " RST_MEM_EN[6] ,Reset Memory Enable (rm)" "Disabled,Enabled"
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textline " "
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bitfld.long 0x18 5. " RST_MEM_EN[5] ,Reset Memory Enable (bm)" "Disabled,Enabled"
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bitfld.long 0x18 4. " RST_MEM_EN[4] ,Reset Memory Enable (mpm)" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x18 3. " RST_MEM_EN[3] ,Reset Memory Enable (tpm)" "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " RST_MEM_EN[2] ,Reset Memory Enable (cpmem)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " RST_MEM_EN[1] ,Reset Memory Enable (alpha)" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " RST_MEM_EN[0] ,Reset Memory Enable (srm)" "Disabled,Enabled"
|
|
line.long 0x1c "IPU_PM,IPU3E Power modes Control Register"
|
|
bitfld.long 0x1c 31. " LPSR_MODE ,LPSR Mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 30. " DI1_SRM_CLOCK_CHANGE_MODE ,SRM clock change mode" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x1c 23.--29. 1. " DI1_CLK_PERIOD_1 ,DI1_CLK period option 1"
|
|
textline " "
|
|
hexmask.long.byte 0x1c 16.--22. 1. " DI1_CLK_PERIOD_0 ,DI1_CLK period option 0"
|
|
textline " "
|
|
bitfld.long 0x1c 15. " CLCOK_MODE_STAT ,Clock mode status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1c 14. " DI0_SRM_CLOCK_CHANGE_MODE ,SRM clock change mode" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x1c 7.--13. 1. " DI0_CLK_PERIOD_1 ,DI0_CLK period option 1"
|
|
textline " "
|
|
hexmask.long.byte 0x1c 0.--6. 1. " DI0_CLK_PERIOD_0 ,DI0_CLK period option 0"
|
|
line.long 0x20 "IPU_GPR,IPU3E General Purpose Register"
|
|
bitfld.long 0x20 31. " IPU_CH_BUF1_RDY1_CLR ,Defines the IPU_CH_BUF1_RDY1 properties" "W1s,W1c"
|
|
bitfld.long 0x20 30. " IPU_CH_BUF1_RDY0_CLR ,Defines the IPU_CH_BUF1_RDY0 properties" "W1s,W1c"
|
|
textline " "
|
|
bitfld.long 0x20 29. " IPU_CH_BUF0_RDY1_CLR ,Defines the IPU_CH_BUF0_RDY1 properties" "W1s,W1c"
|
|
bitfld.long 0x20 28. " IPU_CH_BUF0_RDY0_CLR ,Defines the IPU_CH_BUF0_RDY0 properties" "W1s,W1c"
|
|
textline " "
|
|
bitfld.long 0x20 27. " IPU_ALT_CH_BUF1_RDY1_CLR ,Defines the IPU_ALT_CH_BUF1_RDY1 properties" "W1s,W1c"
|
|
bitfld.long 0x20 26. " IPU_ALT_CH_BUF1_RDY0_CLR ,Defines the IPU_ALT_CH_BUF1_RDY0 properties" "W1s,W1c"
|
|
textline " "
|
|
bitfld.long 0x20 25. " IPU_ALT_CH_BUF0_RDY1_CLR ,Defines the IPU_ALT_CH_BUF0_RDY1 properties" "W1s,W1c"
|
|
bitfld.long 0x20 24. " IPU_ALT_CH_BUF0_RDY0_CLR ,Defines the IPU_ALT_CH_BUF0_RDY0 properties" "W1s,W1c"
|
|
textline " "
|
|
bitfld.long 0x20 23. " IPU_DI1_CLK_CHANGE_ACK_DIS ,Disable DI1's clock change mechanism" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x20 22. " IPU_DI0_CLK_CHANGE_ACK_DIS ,Disable DI0's clock change mechanism" "Not acknowledged,Acknowledged"
|
|
textline " "
|
|
bitfld.long 0x20 21. " IPU_CH_BUF2_RDY1_CLR ,Defines the IPU_CH_BUF2_RDY1 properties" "W1s,W1c"
|
|
bitfld.long 0x20 20. " IPU_CH_BUF2_RDY0_CLR ,Defines the IPU_CH_BUF2_RDY0 properties" "W1s,W1c"
|
|
textline " "
|
|
hexmask.long.tbyte 0x20 0.--19. 1. " IPU_GP ,IPU3E General Purpose bit"
|
|
width 21.
|
|
group.long 0x150++0x07
|
|
line.long 0x00 "IPU_CH_DB_MODE_SEL0,IPU Channel Double Buffer Mode Select 0 Register"
|
|
bitfld.long 0x00 31. " DMA_CH_DB_MODE_SEL_31 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 29. " DMA_CH_DB_MODE_SEL_29 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMA_CH_DB_MODE_SEL_28 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 27. " DMA_CH_DB_MODE_SEL_27 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DMA_CH_DB_MODE_SEL_24 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 23. " DMA_CH_DB_MODE_SEL_23 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DMA_CH_DB_MODE_SEL_22 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 21. " DMA_CH_DB_MODE_SEL_21 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DMA_CH_DB_MODE_SEL_20 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 18. " DMA_CH_DB_MODE_SEL_18 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DMA_CH_DB_MODE_SEL_17 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 15. " DMA_CH_DB_MODE_SEL_15 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMA_CH_DB_MODE_SEL_14 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 13. " DMA_CH_DB_MODE_SEL_13 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DMA_CH_DB_MODE_SEL_12 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 11. " DMA_CH_DB_MODE_SEL_11 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMA_CH_DB_MODE_SEL_7 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 6. " DMA_CH_DB_MODE_SEL_6 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DMA_CH_DB_MODE_SEL_5 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 4. " DMA_CH_DB_MODE_SEL_4 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMA_CH_DB_MODE_SEL_3 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 2. " DMA_CH_DB_MODE_SEL_2 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DMA_CH_DB_MODE_SEL_1 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 0. " DMA_CH_DB_MODE_SEL_0 ,Double buffer mode select" "Not used,Used"
|
|
line.long 0x04 "IPU_CH_DB_MODE_SEL1,IPU3E Channel Double Buffer Mode Select 1 Register"
|
|
bitfld.long 0x04 20. " DMA_CH_DB_MODE_SEL_52 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x04 19. " DMA_CH_DB_MODE_SEL_51 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 18. " DMA_CH_DB_MODE_SEL_50 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x04 17. " DMA_CH_DB_MODE_SEL_49 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DMA_CH_DB_MODE_SEL_48 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x04 15. " DMA_CH_DB_MODE_SEL_47 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 14. " DMA_CH_DB_MODE_SEL_46 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x04 13. " DMA_CH_DB_MODE_SEL_45 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DMA_CH_DB_MODE_SEL_44 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x04 11. " DMA_CH_DB_MODE_SEL_43 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DMA_CH_DB_MODE_SEL_42 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x04 9. " DMA_CH_DB_MODE_SEL_41 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DMA_CH_DB_MODE_SEL_40 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x04 1. " DMA_CH_DB_MODE_SEL_33 ,Double buffer mode select" "Not used,Used"
|
|
width 25.
|
|
group.long 0x168++0x07
|
|
line.long 0x00 "IPU_ALT_CH_DB_MODE_SEL0,IPU3E Alternate Channel Double Buffer Mode Select 0 Register"
|
|
bitfld.long 0x00 29. " DMA_CH_ALT_DB_MODE_SEL_29 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 24. " DMA_CH_ALT_DB_MODE_SEL_24 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMA_CH_ALT_DB_MODE_SEL_7 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 6. " DMA_CH_ALT_DB_MODE_SEL_6 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DMA_CH_ALT_DB_MODE_SEL_5 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 4. " DMA_CH_ALT_DB_MODE_SEL_4 ,Double buffer mode select" "Not used,Used"
|
|
line.long 0x04 "IPU_ALT_CH_DB_MODE_SEL1,IPU3E Alternate Channel Double Buffer Mode Select 1 Register"
|
|
bitfld.long 0x04 20. " DMA_CH_ALT_DB_MODE_SEL_52 ,Double buffer mode select" "Not used,Used"
|
|
bitfld.long 0x04 9. " DMA_CH_ALT_DB_MODE_SEL_41 ,Double buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DMA_CH_ALT_DB_MODE_SEL_33 ,Double buffer mode select" "Not used,Used"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "IPU_CH_TRB_MODE_SEL0,IPU Channel Triple Buffer Mode Select 0 Register"
|
|
bitfld.long 0x00 28. " DMA_CH_TRB_MODE_SEL_28 ,Triple buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 27. " DMA_CH_TRB_MODE_SEL_27 ,Triple buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DMA_CH_TRB_MODE_SEL_23 ,Triple buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 21. " DMA_CH_TRB_MODE_SEL_21 ,Triple buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMA_CH_TRB_MODE_SEL_13 ,Triple buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 10. " DMA_CH_TRB_MODE_SEL_10 ,Triple buffer mode select" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DMA_CH_TRB_MODE_SEL_9 ,Triple buffer mode select" "Not used,Used"
|
|
bitfld.long 0x00 8. " DMA_CH_TRB_MODE_SEL_8 ,Triple buffer mode select" "Not used,Used"
|
|
width 22.
|
|
tree "IPU Status registers"
|
|
group.long 0x200++0x3b
|
|
line.long 0x00 "IPU_INT_STAT_1,IPU Interrupt Status Register 1"
|
|
eventfld.long 0x00 31. " IDMAC_EOF_31 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 29. " IDMAC_EOF_29 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 28. " IDMAC_EOF_28 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 27. " IDMAC_EOF_27 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 24. " IDMAC_EOF_24 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 23. " IDMAC_EOF_23 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 22. " IDMAC_EOF_22 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 21. " IDMAC_EOF_21 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 20. " IDMAC_EOF_20 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 18. " IDMAC_EOF_18 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IDMAC_EOF_17 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 15. " IDMAC_EOF_15 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 14. " IDMAC_EOF_14 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 13. " IDMAC_EOF_13 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 12. " IDMAC_EOF_12 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 11. " IDMAC_EOF_11 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 10. " IDMAC_EOF_10 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 9. " IDMAC_EOF_9 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 8. " IDMAC_EOF_8 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 7. " IDMAC_EOF_7 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 6. " IDMAC_EOF_6 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 5. " IDMAC_EOF_5 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 4. " IDMAC_EOF_4 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 3. " IDMAC_EOF_3 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 2. " IDMAC_EOF_2 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x00 1. " IDMAC_EOF_1 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x00 0. " IDMAC_EOF_0 ,Enable End of Frame of Channel interrupt" "Cleared,Requested"
|
|
line.long 0x04 "IPU_INT_STAT_2,IPU Interrupt Status Register 2"
|
|
eventfld.long 0x04 20. " IDMAC_EOF_52 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x04 19. " IDMAC_EOF_51 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x04 18. " IDMAC_EOF_50 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x04 17. " IDMAC_EOF_49 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x04 16. " IDMAC_EOF_48 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x04 15. " IDMAC_EOF_47 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x04 14. " IDMAC_EOF_46 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x04 13. " IDMAC_EOF_45 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x04 12. " IDMAC_EOF_44 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x04 11. " IDMAC_EOF_43 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x04 10. " IDMAC_EOF_42 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x04 9. " IDMAC_EOF_41 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x04 8. " IDMAC_EOF_40 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x04 1. " IDMAC_EOF_33 ,End of Frame of Channel interrupt" "Cleared,Requested"
|
|
line.long 0x08 "IPU_INT_STAT_3,IPU Interrupt Status Register 3"
|
|
eventfld.long 0x08 31. " IDMAC_NFACK_31 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 29. " IDMAC_NFACK_29 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 28. " IDMAC_NFACK_28 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 27. " IDMAC_NFACK_27 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 24. " IDMAC_NFACK_24 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 23. " IDMAC_NFACK_23 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 22. " IDMAC_NFACK_22 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 21. " IDMAC_NFACK_21 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 20. " IDMAC_NFACK_20 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 18. " IDMAC_NFACK_18 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 17. " IDMAC_NFACK_17 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 15. " IDMAC_NFACK_15 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 14. " IDMAC_NFACK_14 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 13. " IDMAC_NFACK_13 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 12. " IDMAC_NFACK_12 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 11. " IDMAC_NFACK_11 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 10. " IDMAC_NFACK_10 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 9. " IDMAC_NFACK_9 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 8. " IDMAC_NFACK_8 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 7. " IDMAC_NFACK_7 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 6. " IDMAC_NFACK_6 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 5. " IDMAC_NFACK_5 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 4. " IDMAC_NFACK_4 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 3. " IDMAC_NFACK_3 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 2. " IDMAC_NFACK_2 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x08 1. " IDMAC_NFACK_1 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x08 0. " IDMAC_NFACK_0 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
line.long 0x0c "IPU_INT_STAT_4,IPU Interrupt Status Register 4"
|
|
eventfld.long 0x0C 20. " IDMAC_NFACK_52 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x0C 19. " IDMAC_NFACK_51 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x0C 18. " IDMAC_NFACK_50 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x0C 17. " IDMAC_NFACK_49 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x0C 16. " IDMAC_NFACK_48 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x0C 15. " IDMAC_NFACK_47 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x0C 14. " IDMAC_NFACK_46 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x0C 13. " IDMAC_NFACK_45 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x0C 12. " IDMAC_NFACK_44 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x0C 11. " IDMAC_NFACK_43 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x0C 10. " IDMAC_NFACK_42 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x0C 9. " IDMAC_NFACK_41 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x0C 8. " IDMAC_NFACK_40 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x0C 1. " IDMAC_NFACK_33 ,Enable New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
width 22.
|
|
line.long 0x10 "IPU_INT_STAT_5,IPU Interrupt Status Register 5"
|
|
eventfld.long 0x10 31. " IDMAC_NFB4EOF_ERR_31 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 29. " IDMAC_NFB4EOF_ERR_29 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 28. " IDMAC_NFB4EOF_ERR_28 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 27. " IDMAC_NFB4EOF_ERR_27 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 24. " IDMAC_NFB4EOF_ERR_24 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 23. " IDMAC_NFB4EOF_ERR_23 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 22. " IDMAC_NFB4EOF_ERR_22 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 21. " IDMAC_NFB4EOF_ERR_21 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 20. " IDMAC_NFB4EOF_ERR_20 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 18. " IDMAC_NFB4EOF_ERR_18 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 17. " IDMAC_NFB4EOF_ERR_17 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 15. " IDMAC_NFB4EOF_ERR_15 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 14. " IDMAC_NFB4EOF_ERR_14 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 13. " IDMAC_NFB4EOF_ERR_13 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 12. " IDMAC_NFB4EOF_ERR_12 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 11. " IDMAC_NFB4EOF_ERR_11 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 10. " IDMAC_NFB4EOF_ERR_10 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 9. " IDMAC_NFB4EOF_ERR_9 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 8. " IDMAC_NFB4EOF_ERR_8 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 7. " IDMAC_NFB4EOF_ERR_7 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 6. " IDMAC_NFB4EOF_ERR_6 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 5. " IDMAC_NFB4EOF_ERR_5 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 4. " IDMAC_NFB4EOF_ERR_4 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 3. " IDMAC_NFB4EOF_ERR_3 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 2. " IDMAC_NFB4EOF_ERR_2 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x10 1. " IDMAC_NFB4EOF_ERR_1 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x10 0. " IDMAC_NFB4EOF_ERR_0 ,New Frame before end-of-frame error indication of Channel interrupt" "Cleared,Requested"
|
|
line.long 0x14 "IPU_INT_STAT_6,IPU Interrupt Status Register 6"
|
|
eventfld.long 0x14 20. " IDMAC_NFB4EOF_ERR_52 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x14 19. " IDMAC_NFB4EOF_ERR_51 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x14 18. " IDMAC_NFB4EOF_ERR_50 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x14 17. " IDMAC_NFB4EOF_ERR_49 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x14 16. " IDMAC_NFB4EOF_ERR_48 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x14 15. " IDMAC_NFB4EOF_ERR_47 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x14 14. " IDMAC_NFB4EOF_ERR_46 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x14 13. " IDMAC_NFB4EOF_ERR_45 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x14 12. " IDMAC_NFB4EOF_ERR_44 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x14 11. " IDMAC_NFB4EOF_ERR_43 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x14 10. " IDMAC_NFB4EOF_ERR_42 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x14 9. " IDMAC_NFB4EOF_ERR_41 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x14 8. " IDMAC_NFB4EOF_ERR_40 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x14 1. " IDMAC_NFB4EOF_ERR_33 ,New Frame Ack of Channel interrupt" "Cleared,Requested"
|
|
width 22.
|
|
line.long 0x18 "IPU_INT_STAT_7,IPU Interrupt Status Register 7"
|
|
eventfld.long 0x18 31. " IDMAC_EOS_31 ,End of Scroll indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x18 29. " IDMAC_EOS_29 ,End of Scroll indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x18 28. " IDMAC_EOS_28 ,End of Scroll indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x18 27. " IDMAC_EOS_27 ,End of Scroll indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x18 24. " IDMAC_EOS_24 ,End of Scroll indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x18 23. " IDMAC_EOS_23 ,End of Scroll indication of Channel interrupt" "Cleared,Requested"
|
|
line.long 0x1c "IPU_INT_STAT_8,IPU Interrupt Status Register 8"
|
|
eventfld.long 0x1c 20. " IDMAC_EOS_52 ,End of Scroll of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x1c 19. " IDMAC_EOS_51 ,End of Scroll of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x1c 12. " IDMAC_EOS_44 ,End of Scroll of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x1c 11. " IDMAC_EOS_43 ,End of Scroll of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x1c 10. " IDMAC_EOS_42 ,End of Scroll of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x1c 9. " IDMAC_EOS_41 ,End of Scroll of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x1c 1. " IDMAC_EOS_33 ,End of Scroll of Channel interrupt" "Cleared,Requested"
|
|
line.long 0x20 "IPU_INT_STAT_9,IPU Interrupt Status Register 9"
|
|
eventfld.long 0x20 31. " CSI1_PUPE ,CSI1 parameters update error interrupt" "Cleared,Requested"
|
|
eventfld.long 0x20 30. " CSI0_PUPE ,CSI0 parameters update error interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x20 29. " ISP_PUPE ,ISP parameters update error interrupt" "Cleared,Requested"
|
|
eventfld.long 0x20 28. " IC_VF_BUF_OVF ,IC Buffer overflow for view finder interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x20 27. " IC_ENC_BUF_OVF ,IC Buffer overflow for encoding interrupt" "Cleared,Requested"
|
|
eventfld.long 0x20 26. " IC_BAYER_BUF_OVF ,IC Buffer overflow for Bayer coming interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x20 0. " VDI_FIFO1_OVF ,FIFO1 overflow Interrupt1" "Cleared,Requested"
|
|
width 22.
|
|
line.long 0x24 "IPU_INT_STAT_10,IPU Interrupt Status Register 10"
|
|
eventfld.long 0x24 30. " AXIR_ERR ,AXI read access interrupt status" "Cleared,Requested"
|
|
eventfld.long 0x24 29. " AXIW_ERR ,AXI write access interrupt status" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x24 28. " NON_PRIVILEGED_ACC_ERR ,Non Privileged Access Error interrupt status" "Cleared,Requested"
|
|
eventfld.long 0x24 26. " IC_BAYER_FRM_LOST_ERR ,IC's Bayer frame lost interrupt status" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x24 25. " IC_ENC_FRM_LOST_ERR ,IC's encoding frame lost interrupt status" "Disabled,Enabled"
|
|
eventfld.long 0x24 24. " IC_VF_FRM_LOST_ERR ,IC's view finder frame lost interrupt status" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x24 22. " DI1_TIME_OUT_ERR ,DI1 time out error interrupt status" "No interrupt,Interrupt"
|
|
eventfld.long 0x24 21. " DI0_TIME_OUT_ERR ,DI0 time outwore interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x24 20. " DI1_SYNC_DISP_ERR ,DI1 Synchronous display error status" "No interrupt,Interrupt"
|
|
eventfld.long 0x24 19. " DI0_SYNC_DISP_ERR ,DI0 Synchronous display error status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x24 18. " DC_TEARING_ERR_6 ,Tearing Error #6 status" "No interrupt,Interrupt"
|
|
eventfld.long 0x24 17. " DC_TEARING_ERR_2 ,Tearing Error #2 status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x24 16. " DC_TEARING_ERR_1 ,Tearing Error #1 status" "No interrupt,Interrupt"
|
|
eventfld.long 0x24 5. " ISP_RAM_HIST_OF ,Histogram RAM overflow/underun Interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x24 4. " ISP_RAM_ST_OF ,Statistics RAM overflow/underun Interrupt" "Cleared,Requested"
|
|
eventfld.long 0x24 3. " SMFC3_FRM_LOST ,Frame Lost of SMFC channel 3 interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x24 2. " SMFC2_FRM_LOST ,Frame Lost of SMFC channel 2 interrupt" "Cleared,Requested"
|
|
eventfld.long 0x24 1. " SMFC1_FRM_LOST ,Frame Lost of SMFC channel 1 interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x24 0. " SMFC0_FRM_LOST ,Frame Lost of SMFC channel 0 interrupt" "Cleared,Requested"
|
|
width 22.
|
|
line.long 0x28 "IPU_INT_STAT_11,IPU Interrupt Status Register 11"
|
|
eventfld.long 0x28 22. " IDMAC_EOBND_22 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x28 21. " IDMAC_EOBND_21 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x28 20. " IDMAC_EOBND_20 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x28 12. " IDMAC_EOBND_12 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x28 11. " IDMAC_EOBND_11 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x28 5. " IDMAC_EOBND_5 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x28 3. " IDMAC_EOBND_3 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x28 2. " IDMAC_EOBND_2 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x28 1. " IDMAC_EOBND_1 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x28 0. " IDMAC_EOBND_0 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
line.long 0x2c "IPU_INT_STAT_12,IPU Interrupt Status Register 12"
|
|
eventfld.long 0x2c 18. " IDMAC_EOBND_50 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x2c 17. " IDMAC_EOBND_49 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x2c 16. " IDMAC_EOBND_48 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x2c 15. " IDMAC_EOBND_47 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x2c 14. " IDMAC_EOBND_46 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x2c 13. " IDMAC_EOBND_45 ,End-of-band indication of Channel interrupt" "Cleared,Requested"
|
|
line.long 0x30 "IPU_INT_STAT_13,IPU Interrupt Status Register 13"
|
|
eventfld.long 0x30 31. " IDMAC_TH_31 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 29. " IDMAC_TH_29 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 28. " IDMAC_TH_28 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 27. " IDMAC_TH_27 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 24. " IDMAC_TH_24 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 23. " IDMAC_TH_23 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 22. " IDMAC_TH_22 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 21. " IDMAC_TH_21 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 20. " IDMAC_TH_20 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 18. " IDMAC_TH_18 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 17. " IDMAC_TH_17 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 15. " IDMAC_TH_15 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 14. " IDMAC_TH_14 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 13. " IDMAC_TH_13 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 12. " IDMAC_TH_12 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 11. " IDMAC_TH_11 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 10. " IDMAC_TH_10 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 9. " IDMAC_TH_9 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 8. " IDMAC_TH_8 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 7. " IDMAC_TH_7 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 6. " IDMAC_TH_6 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 5. " IDMAC_TH_5 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 4. " IDMAC_TH_4 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 3. " IDMAC_TH_3 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 2. " IDMAC_TH_2 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
eventfld.long 0x30 1. " IDMAC_TH_1 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x30 0. " IDMAC_TH_0 ,Threshold crossing indication of Channel interruptrupt" "Cleared,Requested"
|
|
line.long 0x34 "IPU_INT_STAT_14,IPU3E Interrupt Status Register 14"
|
|
eventfld.long 0x34 20. " IDMAC_TH_52 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x34 19. " IDMAC_TH_51 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x34 18. " IDMAC_TH_50 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x34 17. " IDMAC_TH_49 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x34 16. " IDMAC_TH_48 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x34 15. " IDMAC_TH_47 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x34 14. " IDMAC_TH_46 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x34 13. " IDMAC_TH_45 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x34 12. " IDMAC_TH_44 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x34 11. " IDMAC_TH_43 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x34 10. " IDMAC_TH_42 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x34 9. " IDMAC_TH_41 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x34 8. " IDMAC_TH_40 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
eventfld.long 0x34 1. " IDMAC_TH_33 ,Threshold crossing indication of Channel interrupt" "Cleared,Requested"
|
|
line.long 0x38 "IPU_INT_STAT_15,IPU Interrupt Status Register 15"
|
|
eventfld.long 0x38 31. " DI1_CNT_PRE_8 ,Trigger generated by counter #8 of DI1 interrupt status" "Cleared,Requested"
|
|
eventfld.long 0x38 30. " DI1_CNT_PRE_3 ,Trigger generated by counter #3 of DI1 interrupt status" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 29. " DI1_DISP_CLK_PRE , DI1_DISP_CLK interrupt status" "Cleared,Requested"
|
|
eventfld.long 0x38 28. " DI0_CNT_PRE_10 ,Trigger generated by counter #10 of DI0 interrupt status" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 27. " DI0_CNT_PRE_9 ,Trigger generated by counter #9 of DI0 interrupt status" "Cleared,Requested"
|
|
eventfld.long 0x38 26. " DI0_CNT_PRE_8 ,Trigger generated by counter #8 of DI0 interrupt status" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 25. " DI0_CNT_PRE_7 ,Trigger generated by counter #7 of DI0 interrupt status" "Cleared,Requested"
|
|
eventfld.long 0x38 24. " DI0_CNT_PRE_6 ,Trigger generated by counter #6 of DI0 interrupt status" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 23. " DI0_CNT_PRE_5 ,Trigger generated by counter #5 of DI0 interrupt status" "Cleared,Requested"
|
|
eventfld.long 0x38 22. " DI0_CNT_PRE_4 ,Trigger generated by counter #4 of DI0 interrupt status" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 21. " DI0_CNT_PRE_3 ,Trigger generated by counter #3 of DI0 interrupt status" "Cleared,Requested"
|
|
eventfld.long 0x38 20. " DI0_CNT_PRE_2 ,Trigger generated by counter #2 of DI0 interrupt status" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 19. " DI0_CNT_PRE_1 ,Trigger generated by counter #1 of DI0 interrupt status" "Cleared,Requested"
|
|
eventfld.long 0x38 18. " DI0_CNT_PRE_0 ,Trigger generated by counter #0 of DI0 interrupt status" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 17. " DC_ASYNC_STOP ,DP stops an async flow and moves to a sync flow interrupt status" "Cleared,Requested"
|
|
eventfld.long 0x38 16. " DC_DP_START ,DP start a new sync or async flow or when an async flow interrupt status" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 15. " DI_VSYNC_PRE_1 ,Status the DI1 interrupt indicating of a VSYNC signal" "Cleared,Requested"
|
|
eventfld.long 0x38 14. " DI_VSYNC_PRE_0 ,Status the DI0 interrupt indicating of a VSYNC signal" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 13. " DC_FC_6 ,Status the DC Frame Complete on channel #6 interrupt" "Cleared,Requested"
|
|
eventfld.long 0x38 12. " DC_FC_4 ,Status the DC Frame Complete on channel #4 interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 11. " DC_FC_3 ,Status the DC Frame Complete on channel #3 interrupt" "Cleared,Requested"
|
|
eventfld.long 0x38 10. " DC_FC_2 ,Status the DC Frame Complete on channel #2 interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 9. " DC_FC_1 ,Status the DC Frame Complete on channel #1 interrupt" "Cleared,Requested"
|
|
eventfld.long 0x38 8. " DC_FC_0 ,Status the DC Frame Complete on channel #0 interrupt" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 7. " DP_ASF_BRAKE ,DP Async Flow Brake status bit" "Cleared,Requested"
|
|
eventfld.long 0x38 6. " DP_SF_BRAKE ,DP Sync Flow Brake status bit" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 5. " DP_ASF_END ,DP Async Flow End status bit" "Cleared,Requested"
|
|
eventfld.long 0x38 4. " DP_ASF_START ,DP Async Flow Start status bit" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 3. " DP_SF_END ,DP Sync Flow End status bit" "Cleared,Requested"
|
|
eventfld.long 0x38 2. " DP_SF_START ,DP Sync Flow Start status bit" "Cleared,Requested"
|
|
textline " "
|
|
eventfld.long 0x38 1. " IPU_SNOOPING2_INT ,IPU3E snooping 2 interrupt status bit" "Cleared,Requested"
|
|
eventfld.long 0x38 0. " IPU_SNOOPING1_INT ,IPU3E snooping 1 interrupt status bit" "Cleared,Requested"
|
|
width 22.
|
|
rgroup.long 0x23c++0x17
|
|
line.long 0x00 "IPU_CUR_BUF_0,IPU Current Buffer Register 0"
|
|
bitfld.long 0x00 31. " DMA_CH_CUR_BUF_31 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 29. " DMA_CH_CUR_BUF_29 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMA_CH_CUR_BUF_28 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 27. " DMA_CH_CUR_BUF_27 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DMA_CH_CUR_BUF_24 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 23. " DMA_CH_CUR_BUF_23 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DMA_CH_CUR_BUF_22 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 21. " DMA_CH_CUR_BUF_21 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DMA_CH_CUR_BUF_20 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 18. " DMA_CH_CUR_BUF_18 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DMA_CH_CUR_BUF_17 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 15. " DMA_CH_CUR_BUF_15 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMA_CH_CUR_BUF_14 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 12. " DMA_CH_CUR_BUF_12 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DMA_CH_CUR_BUF_11 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 7. " DMA_CH_CUR_BUF_7 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DMA_CH_CUR_BUF_6 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 5. " DMA_CH_CUR_BUF_5 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMA_CH_CUR_BUF_4 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 3. " DMA_CH_CUR_BUF_3 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMA_CH_CUR_BUF_2 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x00 1. " DMA_CH_CUR_BUF_1 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA_CH_CUR_BUF_0 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
line.long 0x04 "IPU_CUR_BUF_1,IPU Current Buffer Register 1"
|
|
bitfld.long 0x04 20. " DMA_CH_CUR_BUF_52 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x04 19. " DMA_CH_CUR_BUF_51 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x04 18. " DMA_CH_CUR_BUF_50 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x04 17. " DMA_CH_CUR_BUF_49 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DMA_CH_CUR_BUF_48 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x04 15. " DMA_CH_CUR_BUF_47 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x04 14. " DMA_CH_CUR_BUF_46 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x04 13. " DMA_CH_CUR_BUF_45 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DMA_CH_CUR_BUF_44 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x04 11. " DMA_CH_CUR_BUF_43 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DMA_CH_CUR_BUF_42 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x04 9. " DMA_CH_CUR_BUF_41 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DMA_CH_CUR_BUF_40 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x04 1. " DMA_CH_CUR_BUF_33 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
width 22.
|
|
line.long 0x08 "IPU_ALT_CUR_BUF_0,IPU3E Alternate Current Buffer Register 0"
|
|
bitfld.long 0x08 29. " DMA_CH_ALT_CUR_BUF_29 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x08 24. " DMA_CH_ALT_CUR_BUF_24 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DMA_CH_ALT_CUR_BUF_7 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x08 6. " DMA_CH_ALT_CUR_BUF_6 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DMA_CH_ALT_CUR_BUF_5 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x08 4. " DMA_CH_ALT_CUR_BUF_4 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
line.long 0x0c "IPU_ALT_CUR_BUF_1,IPU3E Alternate Current Buffer Register 1"
|
|
bitfld.long 0x0c 20. " DMA_CH_ALT_CUR_BUF_52 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x0c 9. " DMA_CH_ALT_CUR_BUF_41 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " DMA_CH_ALT_CUR_BUF_33 ,Indicates which buffer is in use by DMA" "Buffer 0,Buffer 1"
|
|
width 22.
|
|
line.long 0x10 "IPU_SRM_STAT,IPU Shadow Registers Memory Status Register"
|
|
bitfld.long 0x10 9. " DI1_SRM_STAT ,Indicates that the SRM is currently updating the DI1" "Not updated,Updated"
|
|
bitfld.long 0x10 8. " DI0_SRM_STAT ,Indicates that the SRM is currently updating the DI0" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 7. " CSI1_SRM_STAT ,Indicates that the SRM is currently updating the CSI1" "Not updated,Updated"
|
|
bitfld.long 0x10 6. " CSI0_SRM_STAT ,Indicates that the SRM is currently updating the CSI0" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DC_6_SRM_STAT ,Indicates that the SRM is currently updating the DC group #6" "Not updated,Updated"
|
|
bitfld.long 0x10 4. " DC_2_SRM_STAT ,Indicates that the SRM is currently updating the DC group #2" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 3. " ISP_SRM_STAT ,Indicates that the SRM is currently updating the ISP" "Not updated,Updated"
|
|
bitfld.long 0x10 2. " DP_A1_SRM_STAT ,Indicates that the SRM is currently updating the DP async flow 1" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DP_A0_SRM_STAT ,Indicates that the SRM is currently updating the DP async flow 0" "Not updated,Updated"
|
|
bitfld.long 0x10 0. " DP_S_SRM_STAT ,Indicates that the SRM is currently updating the DP sync flow" "Not updated,Updated"
|
|
width 22.
|
|
line.long 0x14 "IPU_PROC_TASKS_STAT,IPU Processing Tasks Status Register"
|
|
bitfld.long 0x14 22.--23. " CSI2MEM_SMFC3_TSTAT ,Status of the SMFC flow #3" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
bitfld.long 0x14 20.--21. " CSI2MEM_SMFC2_TSTAT ,Status of the SMFC flow #2" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
textline " "
|
|
bitfld.long 0x14 18.--19. " CSI2MEM_SMFC1_TSTAT ,Status of the SMFC flow #1" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
bitfld.long 0x14 16.--17. " CSI2MEM_SMFC0_TSTAT ,Status of the SMFC flow #0" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
textline " "
|
|
bitfld.long 0x14 12.--14. " MEM2PRP_TSTAT ,Status of the pre processing tasks(viewfinder and encoding)" "IDLE,BOTH_ACTIVE,ENC_ACTIVE,VF_ACTIVE,BOTH_PAUSE,?..."
|
|
bitfld.long 0x14 10.--11. " PP_ROT_TSTAT ,Status of the rotation for post processing task" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
textline " "
|
|
bitfld.long 0x14 8.--9. " VF_ROT_TSTAT ,Status of the rotation for viewfinder task" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
bitfld.long 0x14 6.--7. " ENC_ROT_TSTAT ,Status of the rotation for encoding task" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
textline " "
|
|
bitfld.long 0x14 4.--5. " PP_TSTAT ,Status of the post processing task" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
bitfld.long 0x14 2.--3. " VF_TSTAT ,Status of the viewfinder task" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " ENC_TSTAT ,Status of the encoding task" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "IPU_DISP_TASKS_STAT,IPU Display Tasks Status Register"
|
|
bitfld.long 0x00 11. " DC_ASYNC2_CUR_FLOW ,Current asynchronous #2 flow via the DC" "Main,Alternate"
|
|
bitfld.long 0x00 8.--10. " DC_ASYNCH2_STAT ,Status of the Asynchronous flow #2 through the DC" "IDLE,PRIM_ACTIVE,ALT_ACTIVE,UPDATE_PARAM,PAUSE,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DC_ASYNC1_STAT ,Status of the Asynchronous flow #1 through the DC" "IDLE,ACTIVE,WAIT_FOR_READY,?..."
|
|
bitfld.long 0x00 3. " DP_ASYNC_CUR_FLOW ,Current asynchronous flow via the DP" "Main,Alternate"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DP_ASYNCH_TSTAT ,Status of the Asynchronous flow through the DP" "IDLE,PRIM_ACTIVE,ALT_ACTIVE,UPDATE_PARAM,PAUSE,?..."
|
|
rgroup.long 0x258++0x07
|
|
line.long 0x00 "IPU_TRIPLE_CUR_BUF_0,IPU Triple Current Buffer Register 0"
|
|
bitfld.long 0x00 26.--27. " DMA_CH_TRIPLE_CUR_BUF_13 ,Current buffer for triple buffer mode" "Buffer 0,Buffer 1,Buffer 2,?..."
|
|
bitfld.long 0x00 20.--21. " DMA_CH_TRIPLE_CUR_BUF_10 ,Current buffer for triple buffer mode" "Buffer 0,Buffer 1,Buffer 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " DMA_CH_TRIPLE_CUR_BUF_9 ,Current buffer for triple buffer mode" "Buffer 0,Buffer 1,Buffer 2,?..."
|
|
bitfld.long 0x00 16.--17. " DMA_CH_TRIPLE_CUR_BUF_8 ,Current buffer for triple buffer mode" "Buffer 0,Buffer 1,Buffer 2,?..."
|
|
line.long 0x04 "IPU_TRIPLE_CUR_BUF_1,IPU Triple Current Buffer Register 1"
|
|
bitfld.long 0x04 24.--25. " DMA_CH_TRIPLE_CUR_BUF_28 ,Current buffer for triple buffer mode" "Buffer 0,Buffer 1,Buffer 2,?..."
|
|
bitfld.long 0x04 22.--23. " DMA_CH_TRIPLE_CUR_BUF_27 ,Current buffer for triple buffer mode" "Buffer 0,Buffer 1,Buffer 2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " DMA_CH_TRIPLE_CUR_BUF_23 ,Current buffer for triple buffer mode" "Buffer 0,Buffer 1,Buffer 2,?..."
|
|
bitfld.long 0x04 10.--11. " DMA_CH_TRIPLE_CUR_BUF_21 ,Current buffer for triple buffer mode" "Buffer 0,Buffer 1,Buffer 2,?..."
|
|
width 22.
|
|
group.long 0x268++0x23
|
|
line.long 0x00 "IPU_CH_BUF0_RDY0,IPU Channels Buffer 0 Ready 0 Register"
|
|
bitfld.long 0x00 31. " DMA_CH_BUF0_RDY_31 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 29. " DMA_CH_BUF0_RDY_29 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMA_CH_BUF0_RDY_28 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 27. " DMA_CH_BUF0_RDY_27 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DMA_CH_BUF0_RDY_24 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 23. " DMA_CH_BUF0_RDY_23 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DMA_CH_BUF0_RDY_22 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 21. " DMA_CH_BUF0_RDY_21 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DMA_CH_BUF0_RDY_20 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " DMA_CH_BUF0_RDY_18 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DMA_CH_BUF0_RDY_17 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 15. " DMA_CH_BUF0_RDY_15 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMA_CH_BUF0_RDY_14 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 13. " DMA_CH_BUF0_RDY_13 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DMA_CH_BUF0_RDY_12 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " DMA_CH_BUF0_RDY_11 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DMA_CH_BUF0_RDY_10 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 9. " DMA_CH_BUF0_RDY_9 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA_CH_BUF0_RDY_8 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 7. " DMA_CH_BUF0_RDY_7 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DMA_CH_BUF0_RDY_6 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " DMA_CH_BUF0_RDY_5 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMA_CH_BUF0_RDY_4 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 3. " DMA_CH_BUF0_RDY_3 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMA_CH_BUF0_RDY_2 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " DMA_CH_BUF0_RDY_1 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMA_CH_BUF0_RDY_0 ,Buffer 0 is ready" "Not ready,Ready"
|
|
line.long 0x04 "IPU_CH_BUF0_RDY1,IPU Channels Buffer 0 Ready 1 Register"
|
|
bitfld.long 0x04 20. " DMA_CH_BUF0_RDY_52 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x04 19. " DMA_CH_BUF0_RDY_51 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x04 18. " DMA_CH_BUF0_RDY_50 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x04 17. " DMA_CH_BUF0_RDY_49 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x04 16. " DMA_CH_BUF0_RDY_48 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x04 15. " DMA_CH_BUF0_RDY_47 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x04 14. " DMA_CH_BUF0_RDY_46 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x04 13. " DMA_CH_BUF0_RDY_45 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DMA_CH_BUF0_RDY_44 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x04 11. " DMA_CH_BUF0_RDY_43 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DMA_CH_BUF0_RDY_42 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x04 9. " DMA_CH_BUF0_RDY_41 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DMA_CH_BUF0_RDY_40 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x04 1. " DMA_CH_BUF0_RDY_33 ,Buffer 0 is ready" "Not ready,Ready"
|
|
width 22.
|
|
line.long 0x08 "IPU_CH_BUF1_RDY0,IPU Channels Buffer 1 Ready 0 Register"
|
|
bitfld.long 0x08 31. " DMA_CH_BUF1_RDY_31 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 29. " DMA_CH_BUF1_RDY_29 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 28. " DMA_CH_BUF1_RDY_28 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 27. " DMA_CH_BUF1_RDY_27 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 24. " DMA_CH_BUF1_RDY_24 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 23. " DMA_CH_BUF1_RDY_23 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 22. " DMA_CH_BUF1_RDY_22 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 21. " DMA_CH_BUF1_RDY_21 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 20. " DMA_CH_BUF1_RDY_20 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 18. " DMA_CH_BUF1_RDY_18 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 17. " DMA_CH_BUF1_RDY_17 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 15. " DMA_CH_BUF1_RDY_15 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 14. " DMA_CH_BUF1_RDY_14 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 13. " DMA_CH_BUF1_RDY_13 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DMA_CH_BUF1_RDY_12 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 11. " DMA_CH_BUF1_RDY_11 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DMA_CH_BUF1_RDY_10 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 9. " DMA_CH_BUF1_RDY_9 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 8. " DMA_CH_BUF1_RDY_8 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 7. " DMA_CH_BUF1_RDY_7 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DMA_CH_BUF1_RDY_6 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 5. " DMA_CH_BUF1_RDY_5 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 4. " DMA_CH_BUF1_RDY_4 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 3. " DMA_CH_BUF1_RDY_3 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DMA_CH_BUF1_RDY_2 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x08 1. " DMA_CH_BUF1_RDY_1 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DMA_CH_BUF1_RDY_0 ,Buffer 1 is ready" "Not ready,Ready"
|
|
line.long 0x0c "IPU_CH_BUF1_RDY1,IPU3E Channels Buffer 1 Ready 1 Register"
|
|
bitfld.long 0x0c 20. " DMA_CH_BUF1_RDY_52 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x0c 19. " DMA_CH_BUF1_RDY_51 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0c 18. " DMA_CH_BUF1_RDY_50 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x0c 17. " DMA_CH_BUF1_RDY_49 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " DMA_CH_BUF1_RDY_48 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x0c 15. " DMA_CH_BUF1_RDY_47 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0c 14. " DMA_CH_BUF1_RDY_46 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x0c 13. " DMA_CH_BUF1_RDY_45 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " DMA_CH_BUF1_RDY_44 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x0c 11. " DMA_CH_BUF1_RDY_43 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " DMA_CH_BUF1_RDY_42 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x0c 9. " DMA_CH_BUF1_RDY_41 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " DMA_CH_BUF1_RDY_40 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x0c 1. " DMA_CH_BUF1_RDY_33 ,Buffer 1 is ready" "Not ready,Ready"
|
|
line.long 0x10 "IPU_ALT_CH_BUF0_RDY0,IPU Alternate Channels Buffer 0 Ready 0 Register"
|
|
bitfld.long 0x10 29. " DMA_CH_ALT_BUF0_RDY_29 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x10 24. " DMA_CH_ALT_BUF0_RDY_24 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x10 7. " DMA_CH_ALT_BUF0_RDY_7 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x10 6. " DMA_CH_ALT_BUF0_RDY_6 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x10 5. " DMA_CH_ALT_BUF0_RDY_5 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x10 4. " DMA_CH_ALT_BUF0_RDY_4 ,Buffer 0 is ready" "Not ready,Ready"
|
|
line.long 0x14 "IPU_ALT_CH_BUF0_RDY1,IPU Alternate Channels Buffer 0 Ready 1 Register"
|
|
bitfld.long 0x14 20. " DMA_CH_ALT_BUF0_RDY_52 ,Buffer 0 is ready" "Not ready,Ready"
|
|
bitfld.long 0x14 9. " DMA_CH_ALT_BUF0_RDY_41 ,Buffer 0 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DMA_CH_ALT_BUF0_RDY_33 ,Buffer 0 is ready" "Not ready,Ready"
|
|
line.long 0x18 "IPU_ALT_CH_BUF1_RDY0,IPU Alternate Channels Buffer 1 Ready 0 Register"
|
|
bitfld.long 0x18 29. " DMA_CH_ALT_BUF1_RDY_29 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x18 24. " DMA_CH_ALT_BUF1_RDY_24 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x18 7. " DMA_CH_ALT_BUF1_RDY_7 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x18 6. " DMA_CH_ALT_BUF1_RDY_6 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x18 5. " DMA_CH_ALT_BUF1_RDY_5 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x18 4. " DMA_CH_ALT_BUF1_RDY_4 ,Buffer 1 is ready" "Not ready,Ready"
|
|
line.long 0x1c "IPU_ALT_CH_BUF1_RDY1,IPU3E Alternate Channels Buffer 1 Ready 1 Register"
|
|
bitfld.long 0x1c 20. " DMA_CH_ALT_BUF1_RDY_52 ,Buffer 1 is ready" "Not ready,Ready"
|
|
bitfld.long 0x1c 9. " DMA_CH_ALT_BUF1_RDY_41 ,Buffer 1 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x1c 1. " DMA_CH_ALT_BUF1_RDY_33 ,Buffer 1 is ready" "Not ready,Ready"
|
|
line.long 0x20 "IPU_CH_BUF2_RDY0,IPU Channels Buffer 2 Ready 0 Register"
|
|
bitfld.long 0x20 28. " DMA_CH_BUF2_RDY_28 ,Buffer 2 is ready" "Not ready,Ready"
|
|
bitfld.long 0x20 27. " DMA_CH_BUF2_RDY_27 ,Buffer 2 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x20 23. " DMA_CH_BUF2_RDY_23 ,Buffer 2 is ready" "Not ready,Ready"
|
|
bitfld.long 0x20 21. " DMA_CH_BUF2_RDY_21 ,Buffer 2 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x20 13. " DMA_CH_BUF2_RDY_13 ,Buffer 2 is ready" "Not ready,Ready"
|
|
bitfld.long 0x20 10. " DMA_CH_BUF2_RDY_10 ,Buffer 2 is ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x20 9. " DMA_CH_BUF2_RDY_9 ,Buffer 2 is ready" "Not ready,Ready"
|
|
bitfld.long 0x20 8. " DMA_CH_BUF2_RDY_8 ,Buffer 2 is ready" "Not ready,Ready"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "IDMAC registers"
|
|
base ad:0x5e008000
|
|
width 22.
|
|
group.long 0x00++0x4f
|
|
line.long 0x00 "IDMAC_CONF,IDMAC Configuration Register"
|
|
bitfld.long 0x00 16. " P_ENDIAN ,Pixel Endianness" "Little,Big"
|
|
bitfld.long 0x00 5. " RDI ,Read Data Interleaving" "Not supported,Supported"
|
|
bitfld.long 0x00 3.--4. " WIDPT ,Write Interleaving Depth" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MAX_REQ_READ ,Maximum Read Requests" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "IDMAC_CH_EN_1,IDMAC Channel Enable 1 Register"
|
|
bitfld.long 0x04 31. " IDMAC_CH_EN_31 ,IDMAC Channel enable bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " IDMAC_CH_EN_29 ,IDMAC Channel enable bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " IDMAC_CH_EN_28 ,IDMAC Channel enable bit 28" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " IDMAC_CH_EN_27 ,IDMAC Channel enable bit 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " IDMAC_CH_EN_24 ,IDMAC Channel enable bit 24" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " IDMAC_CH_EN_23 ,IDMAC Channel enable bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 22. " IDMAC_CH_EN_22 ,IDMAC Channel enable bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " IDMAC_CH_EN_21 ,IDMAC Channel enable bit 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " IDMAC_CH_EN_20 ,IDMAC Channel enable bit 20" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " IDMAC_CH_EN_18 ,IDMAC Channel enable bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " IDMAC_CH_EN_17 ,IDMAC Channel enable bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " IDMAC_CH_EN_15 ,IDMAC Channel enable bit 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " IDMAC_CH_EN_14 ,IDMAC Channel enable bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " IDMAC_CH_EN_13 ,IDMAC Channel enable bit 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " IDMAC_CH_EN_12 ,IDMAC Channel enable bit 12" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " IDMAC_CH_EN_11 ,IDMAC Channel enable bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " IDMAC_CH_EN_10 ,IDMAC Channel enable bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " IDMAC_CH_EN_9 ,IDMAC Channel enable bit 9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " IDMAC_CH_EN_8 ,IDMAC Channel enable bit 8" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " IDMAC_CH_EN_7 ,IDMAC Channel enable bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " IDMAC_CH_EN_6 ,IDMAC Channel enable bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " IDMAC_CH_EN_5 ,IDMAC Channel enable bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " IDMAC_CH_EN_4 ,IDMAC Channel enable bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " IDMAC_CH_EN_3 ,IDMAC Channel enable bit 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " IDMAC_CH_EN_2 ,IDMAC Channel enable bit 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " IDMAC_CH_EN_1 ,IDMAC Channel enable bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " IDMAC_CH_EN_0 ,IDMAC Channel enable bit 0" "Disabled,Enabled"
|
|
line.long 0x08 "IDMAC_CH_EN_2,IDMAC Channel Enable 2 Register"
|
|
bitfld.long 0x08 20. " IDMAC_CH_EN_52 ,IDMAC Channel enable bit 52" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " IDMAC_CH_EN_51 ,IDMAC Channel enable bit 51" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " IDMAC_CH_EN_50 ,IDMAC Channel enable bit 50" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " IDMAC_CH_EN_49 ,IDMAC Channel enable bit 49" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " IDMAC_CH_EN_48 ,IDMAC Channel enable bit 48" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " IDMAC_CH_EN_47 ,IDMAC Channel enable bit 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " IDMAC_CH_EN_46 ,IDMAC Channel enable bit 46" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " IDMAC_CH_EN_45 ,IDMAC Channel enable bit 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " IDMAC_CH_EN_44 ,IDMAC Channel enable bit 44" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " IDMAC_CH_EN_43 ,IDMAC Channel enable bit 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " IDMAC_CH_EN_42 ,IDMAC Channel enable bit 42" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " IDMAC_CH_EN_41 ,IDMAC Channel enable bit 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " IDMAC_CH_EN_40 ,IDMAC Channel enable bit 40" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " IDMAC_CH_EN_33 ,IDMAC Channel enable bit 33" "Disabled,Enabled"
|
|
line.long 0x0c "IDMAC_SEP_ALPHA,IDMAC Separate Alpha Indication Register"
|
|
bitfld.long 0x0c 29. " IDMAC_SEP_AL_29 ,IDMAC Separate alpha indication bit 29" "Not read,Read"
|
|
bitfld.long 0x0c 27. " IDMAC_SEP_AL_27 ,IDMAC Separate alpha indication bit 27" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " IDMAC_SEP_AL_24 ,IDMAC Separate alpha indication bit 24" "Not read,Read"
|
|
bitfld.long 0x0c 23. " IDMAC_SEP_AL_23 ,IDMAC Separate alpha indication bit 23" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " IDMAC_SEP_AL_15 ,IDMAC Separate alpha indication bit 15" "Not read,Read"
|
|
bitfld.long 0x0c 14. " IDMAC_SEP_AL_14 ,IDMAC Separate alpha indication bit 14" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " IDMAC_SEP_AL_10 ,IDMAC Separate alpha indication bit 10" "Not read,Read"
|
|
line.long 0x10 "IDMAC_ALT_SEP_ALPHA,IDMAC Alternate Separate Alpha Indication Register"
|
|
bitfld.long 0x10 29. " IDMAC_ALT_SEP_AL_29 ,IDMAC Separate alpha indication bit 29" "Not read,Read"
|
|
bitfld.long 0x10 24. " IDMAC_ALT_SEP_AL_24 ,IDMAC Separate alpha indication bit 24" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x10 23. " IDMAC_ALT_SEP_AL_23 ,IDMAC Separate alpha indication bit 23" "Not read,Read"
|
|
line.long 0x14 "IDMAC_CH_PRI_1,IDMAC Channel Priority 1 Register"
|
|
bitfld.long 0x14 29. " IDMAC_CH_PRI_29 ,IDMAC Channel priority bit 29" "Low,High"
|
|
bitfld.long 0x14 28. " IDMAC_CH_PRI_28 ,IDMAC Channel priority bit 28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 27. " IDMAC_CH_PRI_27 ,IDMAC Channel priority bit 27" "Low,High"
|
|
bitfld.long 0x14 24. " IDMAC_CH_PRI_24 ,IDMAC Channel priority bit 24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 23. " IDMAC_CH_PRI_23 ,IDMAC Channel priority bit 23" "Low,High"
|
|
bitfld.long 0x14 22. " IDMAC_CH_PRI_22 ,IDMAC Channel priority bit 22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 21. " IDMAC_CH_PRI_21 ,IDMAC Channel priority bit 21" "Low,High"
|
|
bitfld.long 0x14 20. " IDMAC_CH_PRI_20 ,IDMAC Channel priority bit 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 15. " IDMAC_CH_PRI_15 ,IDMAC Channel priority bit 15" "Low,High"
|
|
bitfld.long 0x14 14. " IDMAC_CH_PRI_14 ,IDMAC Channel priority bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 13. " IDMAC_CH_PRI_13 ,IDMAC Channel priority bit 13" "Low,High"
|
|
bitfld.long 0x14 12. " IDMAC_CH_PRI_12 ,IDMAC Channel priority bit 12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 11. " IDMAC_CH_PRI_11 ,IDMAC Channel priority bit 11" "Low,High"
|
|
bitfld.long 0x14 10. " IDMAC_CH_PRI_10 ,IDMAC Channel priority bit 10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 9. " IDMAC_CH_PRI_9 ,IDMAC Channel priority bit 9" "Low,High"
|
|
bitfld.long 0x14 8. " IDMAC_CH_PRI_8 ,IDMAC Channel priority bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 7. " IDMAC_CH_PRI_7 ,IDMAC Channel priority bit 7" "Low,High"
|
|
bitfld.long 0x14 6. " IDMAC_CH_PRI_6 ,IDMAC Channel priority bit 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 5. " IDMAC_CH_PRI_5 ,IDMAC Channel priority bit 5" "Low,High"
|
|
bitfld.long 0x14 4. " IDMAC_CH_PRI_4 ,IDMAC Channel priority bit 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 3. " IDMAC_CH_PRI_3 ,IDMAC Channel priority bit 3" "Low,High"
|
|
bitfld.long 0x14 2. " IDMAC_CH_PRI_2 ,IDMAC Channel priority bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 1. " IDMAC_CH_PRI_1 ,IDMAC Channel priority bit 1" "Low,High"
|
|
bitfld.long 0x14 0. " IDMAC_CH_PRI_0 ,IDMAC Channel priority bit 0" "Low,High"
|
|
line.long 0x18 "IDMAC_CH_PRI_2,IDMAC Channel Priority 2 Register"
|
|
bitfld.long 0x18 18. " IDMAC_CH_PRI_50 ,IDMAC Channel priority bit 50" "Low,High"
|
|
bitfld.long 0x18 17. " IDMAC_CH_PRI_49 ,IDMAC Channel priority bit 49" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 16. " IDMAC_CH_PRI_48 ,IDMAC Channel priority bit 48" "Low,High"
|
|
bitfld.long 0x18 15. " IDMAC_CH_PRI_47 ,IDMAC Channel priority bit 47" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 14. " IDMAC_CH_PRI_46 ,IDMAC Channel priority bit 46" "Low,High"
|
|
bitfld.long 0x18 13. " IDMAC_CH_PRI_45 ,IDMAC Channel priority bit 45" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 12. " IDMAC_CH_PRI_44 ,IDMAC Channel priority bit 44" "Low,High"
|
|
bitfld.long 0x18 11. " IDMAC_CH_PRI_43 ,IDMAC Channel priority bit 43" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 10. " IDMAC_CH_PRI_42 ,IDMAC Channel priority bit 42" "Low,High"
|
|
bitfld.long 0x18 9. " IDMAC_CH_PRI_41 ,IDMAC Channel priority bit 41" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 8. " IDMAC_CH_PRI_40 ,IDMAC Channel priority bit 40" "Low,High"
|
|
line.long 0x1c "IDMAC_WM_EN_1,IDMAC Channel Watermark Enable 1 Register"
|
|
bitfld.long 0x1c 29. " IDMAC_WM_EN_29 ,IDMAC Watermark enable bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x1c 28. " IDMAC_WM_EN_28 ,IDMAC Watermark enable bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 27. " IDMAC_WM_EN_27 ,IDMAC Watermark enable bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x1c 24. " IDMAC_WM_EN_24 ,IDMAC Watermark enable bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 23. " IDMAC_WM_EN_23 ,IDMAC Watermark enable bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x1c 14. " IDMAC_WM_EN_14 ,IDMAC Watermark enable bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 13. " IDMAC_WM_EN_13 ,IDMAC Watermark enable bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x1c 12. " IDMAC_WM_EN_12 ,IDMAC Watermark enable bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 10. " IDMAC_WM_EN_10 ,IDMAC Watermark enable bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x1c 8. " IDMAC_WM_EN_8 ,IDMAC Watermark enable bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " IDMAC_WM_EN_3 ,IDMAC Watermark enable bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x1c 2. " IDMAC_WM_EN_2 ,IDMAC Watermark enable bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1c 1. " IDMAC_WM_EN_1 ,IDMAC Watermark enable bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x1c 0. " IDMAC_WM_EN_0 ,IDMAC Watermark enable bit 0" "Disabled,Enabled"
|
|
line.long 0x20 "IDMAC_WM_EN_2,IDMAC Channel Watermark Enable 2 Register"
|
|
bitfld.long 0x20 12. " IDMAC_WM_EN_44 ,IDMAC Watermark enable bit 44" "Disabled,Enabled"
|
|
bitfld.long 0x20 11. " IDMAC_WM_EN_43 ,IDMAC Watermark enable bit 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 10. " IDMAC_WM_EN_42 ,IDMAC Watermark enable bit 42" "Disabled,Enabled"
|
|
bitfld.long 0x20 9. " IDMAC_WM_EN_41 ,IDMAC Watermark enable bit 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " IDMAC_WM_EN_40 ,IDMAC Watermark enable bit 40" "Disabled,Enabled"
|
|
line.long 0x24 "IDMAC_LOCK_EN_1,IDMAC Channel Lock Enable 1 Register"
|
|
bitfld.long 0x24 22. " IDMAC_LOCK_EN_22 ,IDMAC lock enable bit 22" "Disabled,Enabled"
|
|
bitfld.long 0x24 21. " IDMAC_LOCK_EN_21 ,IDMAC lock enable bit 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " IDMAC_LOCK_EN_20 ,IDMAC lock enable bit 20" "Disabled,Enabled"
|
|
bitfld.long 0x24 15. " IDMAC_LOCK_EN_15 ,IDMAC lock enable bit 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 14. " IDMAC_LOCK_EN_14 ,IDMAC lock enable bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x24 12. " IDMAC_LOCK_EN_12 ,IDMAC lock enable bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 11. " IDMAC_LOCK_EN_11 ,IDMAC lock enable bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " IDMAC_LOCK_EN_5 ,IDMAC lock enable bit 5" "Disabled,Enabled"
|
|
line.long 0x28 "IDMAC_LOCK_EN_2,IDMAC Channel Lock Enable 2 Register"
|
|
bitfld.long 0x28 18. " IDMAC_LOCK_EN_50 ,IDMAC lock enable bit 50" "Disabled,Enabled"
|
|
bitfld.long 0x28 17. " IDMAC_LOCK_EN_49 ,IDMAC lock enable bit 49" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 16. " IDMAC_LOCK_EN_48 ,IDMAC lock enable bit 48" "Disabled,Enabled"
|
|
bitfld.long 0x28 15. " IDMAC_LOCK_EN_47 ,IDMAC lock enable bit 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 14. " IDMAC_LOCK_EN_46 ,IDMAC lock enable bit 46" "Disabled,Enabled"
|
|
bitfld.long 0x28 13. " IDMAC_LOCK_EN_45 ,IDMAC lock enable bit 45" "Disabled,Enabled"
|
|
line.long 0x2c "IDMAC_SUB_ADDR_0,IDMAC Channel Alternate address 0 Register"
|
|
hexmask.long.byte 0x2c 24.--30. 1. " IDMAC_SUB_ADDR_7 ,The CPMEM alternative entry 7"
|
|
hexmask.long.byte 0x2c 16.--22. 1. " IDMAC_SUB_ADDR_6 ,The CPMEM alternative entry 6"
|
|
textline " "
|
|
hexmask.long.byte 0x2c 8.--14. 1. " IDMAC_SUB_ADDR_5 ,The CPMEM alternative entry 5"
|
|
hexmask.long.byte 0x2c 0.--6. 1. " IDMAC_SUB_ADDR_4 ,The CPMEM alternative entry 4"
|
|
line.long 0x30 "IDMAC_SUB_ADDR_1,IDMAC Channel Alternate address 1 Register"
|
|
hexmask.long.byte 0x30 24.--30. 1. " IDMAC_SUB_ADDR_33 ,The CPMEM alternative entry 33"
|
|
hexmask.long.byte 0x30 16.--22. 1. " IDMAC_SUB_ADDR_29 ,The CPMEM alternative entry 29"
|
|
textline " "
|
|
hexmask.long.byte 0x30 8.--14. 1. " IDMAC_SUB_ADDR_24 ,The CPMEM alternative entry 24"
|
|
hexmask.long.byte 0x30 0.--6. 1. " IDMAC_SUB_ADDR_23 ,The CPMEM alternative entry 23"
|
|
line.long 0x34 "IDMAC_SUB_ADDR_2,IDMAC Channel Alternate address 2 Register"
|
|
hexmask.long.byte 0x34 16.--22. 1. " IDMAC_SUB_ADDR_52 ,The CPMEM alternative entry 52"
|
|
textline " "
|
|
hexmask.long.byte 0x34 8.--14. 1. " IDMAC_SUB_ADDR_51 ,The CPMEM alternative entry 51"
|
|
hexmask.long.byte 0x34 0.--6. 1. " IDMAC_SUB_ADDR_41 ,The CPMEM alternative entry 41"
|
|
line.long 0x38 "IDMAC_SUB_ADDR_3,IDMAC Channel Alternate address 3 Register"
|
|
hexmask.long.byte 0x38 24.--30. 1. " IDMAC_SUB_ADDR_27 ,The CPMEM alternative entry 27"
|
|
hexmask.long.byte 0x38 16.--22. 1. " IDMAC_SUB_ADDR_13 ,The CPMEM alternative entry 13"
|
|
textline " "
|
|
hexmask.long.byte 0x38 8.--14. 1. " IDMAC_SUB_ADDR_10 ,The CPMEM alternative entry 10"
|
|
hexmask.long.byte 0x38 0.--6. 1. " IDMAC_SUB_ADDR_9 ,The CPMEM alternative entry 9"
|
|
line.long 0x3c "IDMAC_SUB_ADDR_4,IDMAC Channel Alternate address 4 Register"
|
|
hexmask.long.byte 0x3c 16.--22. 1. " IDMAC_SUB_ADDR_21 ,The CPMEM alternative entry 21"
|
|
textline " "
|
|
hexmask.long.byte 0x3c 8.--14. 1. " IDMAC_SUB_ADDR_8 ,The CPMEM alternative entry 8"
|
|
hexmask.long.byte 0x3c 0.--6. 1. " IDMAC_SUB_ADDR_28 ,The CPMEM alternative entry 28"
|
|
line.long 0x40 "IDMAC_BNDM_EN_1,IDMAC Band Mode Enable 1 Register"
|
|
bitfld.long 0x40 22. " IDMAC_BNDM_EN_22 ,IDMAC Band Mode Enable bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x40 21. " IDMAC_BNDM_EN_21 ,IDMAC Band Mode Enable bit 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 20. " IDMAC_BNDM_EN_20 ,IDMAC Band Mode Enable bit 20" "Disabled,Enabled"
|
|
bitfld.long 0x40 12. " IDMAC_BNDM_EN_12 ,IDMAC Band Mode Enable bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 11. " IDMAC_BNDM_EN_11 ,IDMAC Band Mode Enable bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x40 5. " IDMAC_BNDM_EN_5 ,IDMAC Band Mode Enable bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 3. " IDMAC_BNDM_EN_3 ,IDMAC Band Mode Enable bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x40 2. " IDMAC_BNDM_EN_2 ,IDMAC Band Mode Enable bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 1. " IDMAC_BNDM_EN_1 ,IDMAC Band Mode Enable bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x40 0. " IDMAC_BNDM_EN_0 ,IDMAC Band Mode Enable bit 0" "Disabled,Enabled"
|
|
line.long 0x44 "IDMAC_BNDM_EN_2,IDMAC Band Mode Enable 2 Register"
|
|
bitfld.long 0x44 18. " IDMAC_BNDM_EN_50 ,IDMAC Band Mode Enable bit 50" "Disabled,Enabled"
|
|
bitfld.long 0x44 17. " IDMAC_BNDM_EN_49 ,IDMAC Band Mode Enable bit 49" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 16. " IDMAC_BNDM_EN_48 ,IDMAC Band Mode Enable bit 48" "Disabled,Enabled"
|
|
bitfld.long 0x44 15. " IDMAC_BNDM_EN_47 ,IDMAC Band Mode Enable bit 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 14. " IDMAC_BNDM_EN_46 ,IDMAC Band Mode Enable bit 46" "Disabled,Enabled"
|
|
bitfld.long 0x44 13. " IDMAC_BNDM_EN_45 ,IDMAC Band Mode Enable bit 45" "Disabled,Enabled"
|
|
line.long 0x48 "IDMAC_SC_CORD0,IDMAC Scroll Coordinations Register"
|
|
hexmask.long.word 0x48 16.--27. 1. " SX0 ,Scroll X coordination"
|
|
hexmask.long.word 0x48 0.--10. 1. " SY0 ,Scroll Y coordination"
|
|
line.long 0x4c "IDMAC_SC_CORD1,IDMAC Scroll Coordinations Register"
|
|
hexmask.long.word 0x4c 16.--27. 1. " SX1 ,Scroll X coordination"
|
|
hexmask.long.word 0x4c 0.--10. 1. " SY1 ,Scroll Y coordination"
|
|
rgroup.long 0x100++0x07
|
|
line.long 0x00 "IDMAC_CH_BUSY_1,IDMAC Channel Busy 1 Register"
|
|
bitfld.long 0x00 31. " IDMAC_CH_BUSY_31 ,IDMAC Channel busy bit 31" "Not busy,Busy"
|
|
bitfld.long 0x00 29. " IDMAC_CH_BUSY_29 ,IDMAC Channel busy bit 29" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IDMAC_CH_BUSY_28 ,IDMAC Channel busy bit 28" "Not busy,Busy"
|
|
bitfld.long 0x00 27. " IDMAC_CH_BUSY_27 ,IDMAC Channel busy bit 27" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 24. " IDMAC_CH_BUSY_24 ,IDMAC Channel busy bit 24" "Not busy,Busy"
|
|
bitfld.long 0x00 23. " IDMAC_CH_BUSY_23 ,IDMAC Channel busy bit 23" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IDMAC_CH_BUSY_22 ,IDMAC Channel busy bit 22" "Not busy,Busy"
|
|
bitfld.long 0x00 21. " IDMAC_CH_BUSY_21 ,IDMAC Channel busy bit 21" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 20. " IDMAC_CH_BUSY_20 ,IDMAC Channel busy bit 20" "Not busy,Busy"
|
|
bitfld.long 0x00 18. " IDMAC_CH_BUSY_18 ,IDMAC Channel busy bit 18" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IDMAC_CH_BUSY_17 ,IDMAC Channel busy bit 17" "Not busy,Busy"
|
|
bitfld.long 0x00 15. " IDMAC_CH_BUSY_15 ,IDMAC Channel busy bit 15" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 14. " IDMAC_CH_BUSY_14 ,IDMAC Channel busy bit 14" "Not busy,Busy"
|
|
bitfld.long 0x00 13. " IDMAC_CH_BUSY_13 ,IDMAC Channel busy bit 13" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDMAC_CH_BUSY_12 ,IDMAC Channel busy bit 12" "Not busy,Busy"
|
|
bitfld.long 0x00 11. " IDMAC_CH_BUSY_11 ,IDMAC Channel busy bit 11" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IDMAC_CH_BUSY_10 ,IDMAC Channel busy bit 10" "Not busy,Busy"
|
|
bitfld.long 0x00 9. " IDMAC_CH_BUSY_9 ,IDMAC Channel busy bit 9" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IDMAC_CH_BUSY_8 ,IDMAC Channel busy bit 8" "Not busy,Busy"
|
|
bitfld.long 0x00 7. " IDMAC_CH_BUSY_7 ,IDMAC Channel busy bit 7" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDMAC_CH_BUSY_6 ,IDMAC Channel busy bit 6" "Not busy,Busy"
|
|
bitfld.long 0x00 5. " IDMAC_CH_BUSY_5 ,IDMAC Channel busy bit 5" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDMAC_CH_BUSY_4 ,IDMAC Channel busy bit 4" "Not busy,Busy"
|
|
bitfld.long 0x00 3. " IDMAC_CH_BUSY_3 ,IDMAC Channel busy bit 3" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDMAC_CH_BUSY_2 ,IDMAC Channel busy bit 2" "Not busy,Busy"
|
|
bitfld.long 0x00 1. " IDMAC_CH_BUSY_1 ,IDMAC Channel busy bit 1" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDMAC_CH_BUSY_0 ,IDMAC Channel busy bit 0" "Not busy,Busy"
|
|
line.long 0x04 "IDMAC_CH_BUSY_2,IDMAC Channel Busy 2 Register"
|
|
bitfld.long 0x04 20. " IDMAC_CH_BUSY_52 ,IDMAC Channel busy bit 52" "Not busy,Busy"
|
|
bitfld.long 0x04 19. " IDMAC_CH_BUSY_51 ,IDMAC Channel busy bit 51" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 18. " IDMAC_CH_BUSY_50 ,IDMAC Channel busy bit 50" "Not busy,Busy"
|
|
bitfld.long 0x04 17. " IDMAC_CH_BUSY_49 ,IDMAC Channel busy bit 49" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 16. " IDMAC_CH_BUSY_48 ,IDMAC Channel busy bit 48" "Not busy,Busy"
|
|
bitfld.long 0x04 15. " IDMAC_CH_BUSY_47 ,IDMAC Channel busy bit 47" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 14. " IDMAC_CH_BUSY_46 ,IDMAC Channel busy bit 46" "Not busy,Busy"
|
|
bitfld.long 0x04 13. " IDMAC_CH_BUSY_45 ,IDMAC Channel busy bit 45" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 12. " IDMAC_CH_BUSY_44 ,IDMAC Channel busy bit 44" "Not busy,Busy"
|
|
bitfld.long 0x04 11. " IDMAC_CH_BUSY_43 ,IDMAC Channel busy bit 43" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 10. " IDMAC_CH_BUSY_42 ,IDMAC Channel busy bit 42" "Not busy,Busy"
|
|
bitfld.long 0x04 9. " IDMAC_CH_BUSY_41 ,IDMAC Channel busy bit 41" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x04 8. " IDMAC_CH_BUSY_40 ,IDMAC Channel busy bit 40" "Not busy,Busy"
|
|
bitfld.long 0x04 1. " IDMAC_CH_BUSY_33 ,IDMAC Channel busy bit 33" "Not busy,Busy"
|
|
width 0xB
|
|
tree.end
|
|
tree "DP registers"
|
|
base ad:0x5f040000
|
|
width 27.
|
|
group.long 0x00++0x117
|
|
line.long 0x00 "DP_COM_CONF_SYNC,DP Common Configuration Sync Flow Register"
|
|
bitfld.long 0x00 13. " DP_GAMMA_YUV_EN_SYNC ,GAMMA's YUV mode enable for sync flow" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DP_GAMMA_EN_SYNC ,GAMMA_EN - Gamma correction module enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DP_CSC_YUV_SAT_MODE_SYNC ,YUV saturation mode for color space conversion" "Y/U/V range 0-255/0-255/0-255,Y/U/V range 16-235/16-240/16-240"
|
|
bitfld.long 0x00 10. " DP_CSC_GAMUT_SAT_EN_SYNC ,Indicate if GAMUT saturation is enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DP_CSC_DEF_SYNC ,Enable or disable Color Space Conversion" "Disabled,Enable after combining,Enable before comb. on BG,Enable before comb. on FG"
|
|
bitfld.long 0x00 4.--6. " DP_COC_SYNC ,Cursor Operation Control" "Disabled,Full,Reversed,AND,Reserved,OR,XOR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " DP_GWCKE_SYNC ,Graphic Window Color Keying Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DP_GWAM_SYNC ,Graphic Window Alpha Mode" "Local,Global"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DP_GWSEL_SYNC ,Graphic Window Select" "Full,Partial"
|
|
bitfld.long 0x00 0. " DP_FG_EN_SYNC ,Partial plane Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DP_GRAPH_WIND_CTRL_SYNC,Graphic Window Alpha Value"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DP_GWAV_SYNC ,Graphic Window Alpha Value"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DP_GWCKR_SYNC ,Graphic Window Color Keying Red Component"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--15. 1. " DP_GWCKG_SYNC ,Graphic Window Color Keying Green Component"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DP_GWCKB_SYNC ,Graphic Window Color Keying Blue Component"
|
|
line.long 0x08 "DP_FG_POS_SYNC,DP partial plane Window Position Sync Flow Register"
|
|
hexmask.long.word 0x08 16.--26. 1. " DP_FGXP_SYNC ,FGXP partial plane Window X Position"
|
|
hexmask.long.word 0x08 0.--10. 1. " DP_FGYP_SYNC ,FGYP partial plane Window Y Position"
|
|
line.long 0x0c "DP_CUR_POS_SYNC,DP Cursor Position and Size Sync Flow Register"
|
|
hexmask.long.byte 0x0c 27.--31. 1. " DP_CYP_SYNC ,Cursor Y Position"
|
|
hexmask.long.word 0x0c 16.--26. 1. " DP_CYH_SYNC ,Cursor Height"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 11.--15. 1. " DP_CXP_SYNC ,Cursor X Position"
|
|
hexmask.long.word 0x0c 0.--10. 1. " DP_CXW_SYNC ,Cursor Width"
|
|
line.long 0x10 "DP_CUR_MAP_SYNC,DP Color Cursor Mapping Sync Flow Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " DP_CUR_COL_B_SYNC ,Blue component of the cursor color in color mode"
|
|
hexmask.long.byte 0x10 8.--15. 1. " DP_CUR_COL_G_SYNC ,Green component of the cursor color in color mode"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " DP_CUR_COL_R_SYNC ,Red component of the cursor color in color mode"
|
|
line.long 0x14 "DP_GAMMA_C_SYNC_0,DP Gamma Constants Sync Flow Register 0"
|
|
hexmask.long.word 0x14 16.--24. 1. " DP_GAMMA_C_SYNC_1 ,CONSTANT 1 parameter of Gamma Correction"
|
|
hexmask.long.word 0x14 0.--8. 1. " DP_GAMMA_C_SYNC_0 ,CONSTANT 0 parameter of Gamma Correction"
|
|
line.long 0x18 "DP_GAMMA_C_SYNC_1,DP Gamma Constants Sync Flow Register 1"
|
|
hexmask.long.word 0x18 16.--24. 1. " DP_GAMMA_C_SYNC_3 ,CONSTANT 3 parameter of Gamma Correction"
|
|
hexmask.long.word 0x18 0.--8. 1. " DP_GAMMA_C_SYNC_2 ,CONSTANT 2 parameter of Gamma Correction"
|
|
line.long 0x1C "DP_GAMMA_C_SYNC_2,DP Gamma Constants Sync Flow Register 2"
|
|
hexmask.long.word 0x1C 16.--24. 1. " DP_GAMMA_C_SYNC_5 ,CONSTANT 5 parameter of Gamma Correction"
|
|
hexmask.long.word 0x1C 0.--8. 1. " DP_GAMMA_C_SYNC_4 ,CONSTANT 4 parameter of Gamma Correction"
|
|
line.long 0x20 "DP_GAMMA_C_SYNC_3,DP Gamma Constants Sync Flow Register 3"
|
|
hexmask.long.word 0x20 16.--24. 1. " DP_GAMMA_C_SYNC_7 ,CONSTANT 7 parameter of Gamma Correction"
|
|
hexmask.long.word 0x20 0.--8. 1. " DP_GAMMA_C_SYNC_6 ,CONSTANT 6 parameter of Gamma Correction"
|
|
line.long 0x24 "DP_GAMMA_C_SYNC_4,DP Gamma Constants Sync Flow Register 4"
|
|
hexmask.long.word 0x24 16.--24. 1. " DP_GAMMA_C_SYNC_9 ,CONSTANT 9 parameter of Gamma Correction"
|
|
hexmask.long.word 0x24 0.--8. 1. " DP_GAMMA_C_SYNC_8 ,CONSTANT 8 parameter of Gamma Correction"
|
|
line.long 0x28 "DP_GAMMA_C_SYNC_5,DP Gamma Constants Sync Flow Register 5"
|
|
hexmask.long.word 0x28 16.--24. 1. " DP_GAMMA_C_SYNC_11 ,CONSTANT 11 parameter of Gamma Correction"
|
|
hexmask.long.word 0x28 0.--8. 1. " DP_GAMMA_C_SYNC_10 ,CONSTANT 10 parameter of Gamma Correction"
|
|
line.long 0x2C "DP_GAMMA_C_SYNC_6,DP Gamma Constants Sync Flow Register 6"
|
|
hexmask.long.word 0x2C 16.--24. 1. " DP_GAMMA_C_SYNC_13 ,CONSTANT 13 parameter of Gamma Correction"
|
|
hexmask.long.word 0x2C 0.--8. 1. " DP_GAMMA_C_SYNC_12 ,CONSTANT 12 parameter of Gamma Correction"
|
|
line.long 0x30 "DP_GAMMA_C_SYNC_7,DP Gamma Constants Sync Flow Register 7"
|
|
hexmask.long.word 0x30 16.--24. 1. " DP_GAMMA_C_SYNC_15 ,CONSTANT 15 parameter of Gamma Correction"
|
|
hexmask.long.word 0x30 0.--8. 1. " DP_GAMMA_C_SYNC_14 ,CONSTANT 14 parameter of Gamma Correction"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
line.long 0x34 "DP_GAMMA_C_SYNC_0,DP Gamma Constants Sync Flow Register 0"
|
|
else
|
|
line.long 0x34 "DP_GAMMA_S_SYNC_0,DP Gamma Correction Slope Sync Flow Register 0"
|
|
endif
|
|
hexmask.long.byte 0x34 24.--31. 1. " DP_GAMMA_S_SYNC_3 ,SLOPE 3 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x34 16.--23. 1. " DP_GAMMA_S_SYNC_2 ,SLOPE 2 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0x34 8.--15. 1. " DP_GAMMA_S_SYNC_1 ,SLOPE 1 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x34 0.--7. 1. " DP_GAMMA_S_SYNC_0 ,SLOPE 0 parameter of Gamma Correction"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
line.long 0x38 "DP_GAMMA_C_SYNC_1,DP Gamma Constants Sync Flow Register 1"
|
|
else
|
|
line.long 0x38 "DP_GAMMA_S_SYNC_1,DP Gamma Correction Slope Sync Flow Register 1"
|
|
endif
|
|
hexmask.long.byte 0x38 24.--31. 1. " DP_GAMMA_S_SYNC_7 ,SLOPE 7 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x38 16.--23. 1. " DP_GAMMA_S_SYNC_6 ,SLOPE 6 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0x38 8.--15. 1. " DP_GAMMA_S_SYNC_5 ,SLOPE 5 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x38 0.--7. 1. " DP_GAMMA_S_SYNC_4 ,SLOPE 4 parameter of Gamma Correction"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
line.long 0x3C "DP_GAMMA_C_SYNC_2,DP Gamma Constants Sync Flow Register 2"
|
|
else
|
|
line.long 0x3C "DP_GAMMA_S_SYNC_2,DP Gamma Correction Slope Sync Flow Register 2"
|
|
endif
|
|
hexmask.long.byte 0x3C 24.--31. 1. " DP_GAMMA_S_SYNC_11 ,SLOPE 11 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " DP_GAMMA_S_SYNC_10 ,SLOPE 10 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0x3C 8.--15. 1. " DP_GAMMA_S_SYNC_9 ,SLOPE 9 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " DP_GAMMA_S_SYNC_8 ,SLOPE 8 parameter of Gamma Correction"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
line.long 0x40 "DP_GAMMA_C_SYNC_3,DP Gamma Constants Sync Flow Register 3"
|
|
else
|
|
line.long 0x40 "DP_GAMMA_S_SYNC_3,DP Gamma Correction Slope Sync Flow Register 3"
|
|
endif
|
|
hexmask.long.byte 0x40 24.--31. 1. " DP_GAMMA_S_SYNC_15 ,SLOPE 15 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x40 16.--23. 1. " DP_GAMMA_S_SYNC_14 ,SLOPE 14 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0x40 8.--15. 1. " DP_GAMMA_S_SYNC_13 ,SLOPE 13 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x40 0.--7. 1. " DP_GAMMA_S_SYNC_12 ,SLOPE 12 parameter of Gamma Correction"
|
|
line.long 0x44 "DP_CSCA_SYNC_0,DP Color Space Conversion Control Sync Flow register 0"
|
|
hexmask.long.word 0x44 16.--25. 1. " DP_CSC_A_SYNC_1 ,A 1 parameter of color conversion"
|
|
hexmask.long.word 0x44 0.--9. 1. " DP_CSC_A_SYNC_0 ,A 0 parameter of color conversion"
|
|
line.long 0x48 "DP_CSCA_SYNC_1,DP Color Space Conversion Control Sync Flow register 1"
|
|
hexmask.long.word 0x48 16.--25. 1. " DP_CSC_A_SYNC_3 ,A 3 parameter of color conversion"
|
|
hexmask.long.word 0x48 0.--9. 1. " DP_CSC_A_SYNC_2 ,A 2 parameter of color conversion"
|
|
line.long 0x4C "DP_CSCA_SYNC_2,DP Color Space Conversion Control Sync Flow register 2"
|
|
hexmask.long.word 0x4C 16.--25. 1. " DP_CSC_A_SYNC_5 ,A 5 parameter of color conversion"
|
|
hexmask.long.word 0x4C 0.--9. 1. " DP_CSC_A_SYNC_4 ,A 4 parameter of color conversion"
|
|
line.long 0x50 "DP_CSCA_SYNC_3,DP Color Space Conversion Control Sync Flow register 3"
|
|
hexmask.long.word 0x50 16.--25. 1. " DP_CSC_A_SYNC_7 ,A 7 parameter of color conversion"
|
|
hexmask.long.word 0x50 0.--9. 1. " DP_CSC_A_SYNC_6 ,A 6 parameter of color conversion"
|
|
line.long 0x54 "DP_CSC_SYNC_0,DP Color Conversion Control Sync Flow register 0"
|
|
bitfld.long 0x54 30.--31. " DP_CSC_S0_SYNC ,S0 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0x54 16.--29. 1. " DP_CSC_B0_SYNC ,B0 parameter of color conversion"
|
|
textline " "
|
|
hexmask.long.word 0x54 0.--9. 1. " DP_CSC_A8_SYNC ,A parameter of color conversion"
|
|
line.long 0x58 "DP_CSC_SYNC_1,DP Color Conversion Control Sync Flow register 1"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
bitfld.long 0x58 30.--31. " DP_CSC_S2_SYNC ,S2 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0x58 16.--29. 1. " DP_CSC_B2_SYNC ,B2 parameter of color conversion"
|
|
textline " "
|
|
bitfld.long 0x58 14.--15. " DP_CSC_S1_SYNC ,S1 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0x58 0.--13. 1. " DP_CSC_B1_SYNC ,B1 parameter of color conversion"
|
|
else
|
|
bitfld.long 0x58 30.--31. " DP_CSC_S2_SYNC ,S0 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0x58 16.--29. 1. " DP_CSC_B2_SYNC ,B0 parameter of color conversion"
|
|
textline " "
|
|
bitfld.long 0x58 14.--15. " DP_CSC_S1_SYNC ,S0 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0x58 0.--13. 1. " DP_CSC_B1_SYNC ,B0 parameter of color conversion"
|
|
endif
|
|
line.long 0x5c "DP_CUR_POS_ALT,DP Cursor Position and Size Alternate Register"
|
|
hexmask.long.byte 0x5c 27.--31. 1. " DP_CYP_SYNC_ALT ,Cursor Y Position"
|
|
hexmask.long.word 0x5c 16.--26. 1. " DP_CYH_SYNC_ALT ,Cursor Height"
|
|
textline " "
|
|
hexmask.long.byte 0x5c 11.--15. 1. " DP_CXP_SYNC_ALT ,Cursor X Position"
|
|
hexmask.long.word 0x5c 0.--10. 1. " DP_CXW_SYNC_ALT ,Cursor Width"
|
|
line.long 0x60 "DP_COM_CONF_ASYNC0,DP Common Configuration async0 Flow Register"
|
|
bitfld.long 0x60 13. " DP_GAMMA_YUV_EN_ASYNC0 ,GAMMA's YUV mode enable for async flow 0" "Disabled,Enabled"
|
|
bitfld.long 0x60 12. " DP_GAMMA_EN_ASYNC0 ,GAMMA_EN - Gamma correction module enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 11. " DP_CSC_YUV_SAT_MODE_ASYNC0 ,YUV saturation mode for color space conversion" "Y/U/V range 0-255/0-255/0-255,Y/U/V range 16-235/16-240/16-240"
|
|
bitfld.long 0x60 10. " DP_CSC_GAMUT_SAT_EN_ASYNC0 ,Indicate if GAMUT saturation is enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 8.--9. " DP_CSC_DEF_ASYNC0 ,Enable or disable Color Space Conversion" "Disabled,Enable after combining,Enable before comb. on BG,Enable before comb. on FG"
|
|
bitfld.long 0x60 4.--6. " DP_COC_ASYNC0 ,Cursor Operation Control" "Disabled,Full,Reversed,AND,Reserved,OR,XOR,?..."
|
|
textline " "
|
|
bitfld.long 0x60 3. " DP_GWCKE_ASYNC0 ,Graphic Window Color Keying Enable" "Disabled,Enabled"
|
|
bitfld.long 0x60 2. " DP_GWAM_ASYNC0 ,Graphic Window Alpha Mode" "Local,Global"
|
|
textline " "
|
|
bitfld.long 0x60 1. " DP_GWSEL_ASYNC0 ,Graphic Window Select" "Full,Partial"
|
|
line.long 0x64 "DP_GRAPH_WIND_CTRL_ASYNC0,DP Graphic Window Control async0 Flow Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " DP_GWAV_ASYNC0 ,Graphic Window Alpha Value"
|
|
hexmask.long.byte 0x64 16.--23. 1. " DP_GWCKR_ASYNC0 ,Graphic Window Color Keying Red Component"
|
|
textline " "
|
|
hexmask.long.byte 0x64 8.--15. 1. " DP_GWCKG_ASYNC0 ,Graphic Window Color Keying Green Component"
|
|
hexmask.long.byte 0x64 0.--7. 1. " DP_GWCKB_ASYNC0 ,Graphic Window Color Keying Blue Component"
|
|
line.long 0x68 "DP_FG_POS_ASYNC0,DP partial plane Window Position async0 Flow Register"
|
|
hexmask.long.word 0x68 16.--26. 1. " DP_FGXP_ASYNC0 ,FGXP partial plane Window X Position"
|
|
hexmask.long.word 0x68 0.--10. 1. " DP_FGYP_ASYNC0 ,FGYP partial plane Window Y Position"
|
|
line.long 0x6c "DP_CUR_POS_ASYNC0,DP Cursor Position and Size async0 Flow Register"
|
|
hexmask.long.byte 0x6c 27.--31. 1. " DP_CYP_ASYNC0 ,Cursor Y Position"
|
|
hexmask.long.word 0x6c 16.--26. 1. " DP_CYH_ASYNC0 ,Cursor Height"
|
|
textline " "
|
|
hexmask.long.byte 0x6c 11.--15. 1. " DP_CXP_ASYNC0 ,Cursor X Position"
|
|
hexmask.long.word 0x6c 0.--10. 1. " DP_CXW_ASYNC0 ,Cursor Width"
|
|
line.long 0x70 "DP_CUR_MAP_ASYNC0,DP Color Cursor Mapping async0 Flow Register"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.byte 0x70 16.--23. 1. " CUR_COL_R_ASYNC0 ,Red component of the cursor color in color mode"
|
|
else
|
|
hexmask.long.byte 0x70 16.--23. 1. " CUR_COL_B_ASYNC0 ,Blue component of the cursor color in color mode"
|
|
endif
|
|
hexmask.long.byte 0x70 8.--15. 1. " CUR_COL_G_ASYNC0 ,Green component of the cursor color in color mode"
|
|
textline " "
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.byte 0x70 0.--7. 1. " CUR_COL_B_ASYNC0 ,Blue component of the cursor color in color mode"
|
|
else
|
|
hexmask.long.byte 0x70 0.--7. 1. " CUR_COL_R_ASYNC0 ,Red component of the cursor color in color mode"
|
|
endif
|
|
line.long 0x74 "DP_GAMMA_C_ASYNC0_0,DP Gamma Constants ASYNC0 Flow Register 0"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.word 0x74 16.--24. 1. " DP_GAMMA_C_ASYNC0_1 ,CONSTANT 1 parameter of Gamma Correction"
|
|
else
|
|
hexmask.long.word 0x74 16.--27. 1. " DP_GAMMA_C_ASYNC0_1 ,CONSTANT 1 parameter of Gamma Correction"
|
|
endif
|
|
hexmask.long.word 0x74 0.--8. 1. " DP_GAMMA_C_ASYNC0_0 ,CONSTANT 0 parameter of Gamma Correction"
|
|
line.long 0x78 "DP_GAMMA_C_ASYNC0_1,DP Gamma Constants ASYNC0 Flow Register 1"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.word 0x78 16.--24. 1. " DP_GAMMA_C_ASYNC0_3 ,CONSTANT 3 parameter of Gamma Correction"
|
|
else
|
|
hexmask.long.word 0x78 16.--27. 1. " DP_GAMMA_C_ASYNC0_3 ,CONSTANT 3 parameter of Gamma Correction"
|
|
endif
|
|
hexmask.long.word 0x78 0.--8. 1. " DP_GAMMA_C_ASYNC0_2 ,CONSTANT 2 parameter of Gamma Correction"
|
|
line.long 0x7C "DP_GAMMA_C_ASYNC0_2,DP Gamma Constants ASYNC0 Flow Register 2"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.word 0x7C 16.--24. 1. " DP_GAMMA_C_ASYNC0_5 ,CONSTANT 5 parameter of Gamma Correction"
|
|
else
|
|
hexmask.long.word 0x7C 16.--27. 1. " DP_GAMMA_C_ASYNC0_5 ,CONSTANT 5 parameter of Gamma Correction"
|
|
endif
|
|
hexmask.long.word 0x7C 0.--8. 1. " DP_GAMMA_C_ASYNC0_4 ,CONSTANT 4 parameter of Gamma Correction"
|
|
line.long 0x80 "DP_GAMMA_C_ASYNC0_3,DP Gamma Constants ASYNC0 Flow Register 3"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.word 0x80 16.--24. 1. " DP_GAMMA_C_ASYNC0_7 ,CONSTANT 7 parameter of Gamma Correction"
|
|
else
|
|
hexmask.long.word 0x80 16.--27. 1. " DP_GAMMA_C_ASYNC0_7 ,CONSTANT 7 parameter of Gamma Correction"
|
|
endif
|
|
hexmask.long.word 0x80 0.--8. 1. " DP_GAMMA_C_ASYNC0_6 ,CONSTANT 6 parameter of Gamma Correction"
|
|
line.long 0x84 "DP_GAMMA_C_ASYNC0_4,DP Gamma Constants ASYNC0 Flow Register 4"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.word 0x84 16.--24. 1. " DP_GAMMA_C_ASYNC0_9 ,CONSTANT 9 parameter of Gamma Correction"
|
|
else
|
|
hexmask.long.word 0x84 16.--27. 1. " DP_GAMMA_C_ASYNC0_9 ,CONSTANT 9 parameter of Gamma Correction"
|
|
endif
|
|
hexmask.long.word 0x84 0.--8. 1. " DP_GAMMA_C_ASYNC0_8 ,CONSTANT 8 parameter of Gamma Correction"
|
|
line.long 0x88 "DP_GAMMA_C_ASYNC0_5,DP Gamma Constants ASYNC0 Flow Register 5"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.word 0x88 16.--24. 1. " DP_GAMMA_C_ASYNC0_11 ,CONSTANT 11 parameter of Gamma Correction"
|
|
else
|
|
hexmask.long.word 0x88 16.--27. 1. " DP_GAMMA_C_ASYNC0_11 ,CONSTANT 11 parameter of Gamma Correction"
|
|
endif
|
|
hexmask.long.word 0x88 0.--8. 1. " DP_GAMMA_C_ASYNC0_10 ,CONSTANT 10 parameter of Gamma Correction"
|
|
line.long 0x8C "DP_GAMMA_C_ASYNC0_6,DP Gamma Constants ASYNC0 Flow Register 6"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.word 0x8C 16.--24. 1. " DP_GAMMA_C_ASYNC0_13 ,CONSTANT 13 parameter of Gamma Correction"
|
|
else
|
|
hexmask.long.word 0x8C 16.--27. 1. " DP_GAMMA_C_ASYNC0_13 ,CONSTANT 13 parameter of Gamma Correction"
|
|
endif
|
|
hexmask.long.word 0x8C 0.--8. 1. " DP_GAMMA_C_ASYNC0_12 ,CONSTANT 12 parameter of Gamma Correction"
|
|
line.long 0x90 "DP_GAMMA_C_ASYNC0_7,DP Gamma Constants ASYNC0 Flow Register 7"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.word 0x90 16.--24. 1. " DP_GAMMA_C_ASYNC0_15 ,CONSTANT 15 parameter of Gamma Correction"
|
|
else
|
|
hexmask.long.word 0x90 16.--27. 1. " DP_GAMMA_C_ASYNC0_15 ,CONSTANT 15 parameter of Gamma Correction"
|
|
endif
|
|
hexmask.long.word 0x90 0.--8. 1. " DP_GAMMA_C_ASYNC0_14 ,CONSTANT 14 parameter of Gamma Correction"
|
|
line.long 0x94 "DP_GAMMA_S_ASYNC0_0,DP Gamma Correction Slope async0 Flow Register 0"
|
|
hexmask.long.byte 0x94 24.--31. 1. " DP_GAMMA_S_ASYNC0_3 ,SLOPE 3 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x94 16.--23. 1. " DP_GAMMA_S_ASYNC0_2 ,SLOPE 2 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0x94 8.--15. 1. " DP_GAMMA_S_ASYNC0_1 ,SLOPE 1 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x94 0.--7. 1. " DP_GAMMA_S_ASYNC0_0 ,SLOPE 0 parameter of Gamma Correction"
|
|
line.long 0x98 "DP_GAMMA_S_ASYNC0_1,DP Gamma Correction Slope async0 Flow Register 1"
|
|
hexmask.long.byte 0x98 24.--31. 1. " DP_GAMMA_S_ASYNC0_7 ,SLOPE 7 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x98 16.--23. 1. " DP_GAMMA_S_ASYNC0_6 ,SLOPE 6 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0x98 8.--15. 1. " DP_GAMMA_S_ASYNC0_5 ,SLOPE 5 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x98 0.--7. 1. " DP_GAMMA_S_ASYNC0_4 ,SLOPE 4 parameter of Gamma Correction"
|
|
line.long 0x9C "DP_GAMMA_S_ASYNC0_2,DP Gamma Correction Slope async0 Flow Register 2"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " DP_GAMMA_S_ASYNC0_11 ,SLOPE 11 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " DP_GAMMA_S_ASYNC0_10 ,SLOPE 10 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0x9C 8.--15. 1. " DP_GAMMA_S_ASYNC0_9 ,SLOPE 9 parameter of Gamma Correction"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " DP_GAMMA_S_ASYNC0_8 ,SLOPE 8 parameter of Gamma Correction"
|
|
line.long 0xA0 "DP_GAMMA_S_ASYNC0_3,DP Gamma Correction Slope async0 Flow Register 3"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " DP_GAMMA_S_ASYNC0_15 ,SLOPE 15 parameter of Gamma Correction"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " DP_GAMMA_S_ASYNC0_14 ,SLOPE 14 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0xA0 8.--15. 1. " DP_GAMMA_S_ASYNC0_13 ,SLOPE 13 parameter of Gamma Correction"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " DP_GAMMA_S_ASYNC0_12 ,SLOPE 12 parameter of Gamma Correction"
|
|
line.long 0xA4 "DP_CSCA_ASYNC0_0,DP Color Space Conversion Control ASYNC0 Flow register 0"
|
|
hexmask.long.word 0xA4 16.--25. 1. " DP_CSC_A_ASYNC0_1 ,A 1 parameter of color conversion"
|
|
hexmask.long.word 0xA4 0.--9. 1. " DP_CSC_A_ASYNC0_0 ,A 0 parameter of color conversion"
|
|
line.long 0xA8 "DP_CSCA_ASYNC0_1,DP Color Space Conversion Control ASYNC0 Flow register 1"
|
|
hexmask.long.word 0xA8 16.--25. 1. " DP_CSC_A_ASYNC0_3 ,A 3 parameter of color conversion"
|
|
hexmask.long.word 0xA8 0.--9. 1. " DP_CSC_A_ASYNC0_2 ,A 2 parameter of color conversion"
|
|
line.long 0xAC "DP_CSCA_ASYNC0_2,DP Color Space Conversion Control ASYNC0 Flow register 2"
|
|
hexmask.long.word 0xAC 16.--25. 1. " DP_CSC_A_ASYNC0_5 ,A 5 parameter of color conversion"
|
|
hexmask.long.word 0xAC 0.--9. 1. " DP_CSC_A_ASYNC0_4 ,A 4 parameter of color conversion"
|
|
line.long 0xB0 "DP_CSCA_ASYNC0_3,DP Color Space Conversion Control ASYNC0 Flow register 3"
|
|
hexmask.long.word 0xB0 16.--25. 1. " DP_CSC_A_ASYNC0_7 ,A 7 parameter of color conversion"
|
|
hexmask.long.word 0xB0 0.--9. 1. " DP_CSC_A_ASYNC0_6 ,A 6 parameter of color conversion"
|
|
line.long 0xb4 "DP_CSC_ASYNC0_0,DP Color Conversion Control ASYNC0 Flow register 0"
|
|
bitfld.long 0xb4 30.--31. " DP_CSC_S0_ASYNC0 ,S0 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0xb4 16.--29. 1. " DP_CSC_B0_ASYNC0 ,B0 parameter of color conversion"
|
|
textline " "
|
|
hexmask.long.word 0xb4 0.--9. 1. " DP_CSC_A8_ASYNC0 ,A parameter of color conversion"
|
|
line.long 0xb8 "DP_CSC_ASYNC0_1,DP Color Conversion Control ASYNC0 Flow register 1"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
bitfld.long 0xb8 30.--31. " DP_CSC_S2_ASYNC0 ,S2 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0xb8 16.--29. 1. " DP_CSC_B2_ASYNC0 ,B2 parameter of color conversion"
|
|
textline " "
|
|
bitfld.long 0xb8 14.--15. " DP_CSC_S1_ASYNC0 ,S1 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0xb8 0.--13. 1. " DP_CSC_B1_ASYNC0 ,B1 parameter of color conversion"
|
|
else
|
|
bitfld.long 0xb8 30.--31. " DP_CSC_S2_ASYNC0 ,S0 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0xb8 16.--29. 1. " DP_CSC_B2_ASYNC0 ,B0 parameter of color conversion"
|
|
textline " "
|
|
bitfld.long 0xb8 14.--15. " DP_CSC_S1_ASYNC0 ,S0 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0xb8 0.--13. 1. " DP_CSC_B1_ASYNC0 ,B0 parameter of color conversion"
|
|
endif
|
|
line.long 0xbc "DP_COM_CONF_ASYNC1,DP Common Configuration ASYNC1 Flow Register"
|
|
bitfld.long 0xbc 13. " DP_GAMMA_YUV_EN_ASYNC1 ,GAMMA's YUV mode enable for async flow 1" "Disabled,Enabled"
|
|
bitfld.long 0xbc 12. " DP_GAMMA_EN_ASYNC1 ,GAMMA_EN - Gamma correction module enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xbc 11. " DP_CSC_YUV_SAT_MODE_ASYNC1 ,YUV saturation mode for color space conversion" "Y/U/V range 0-255/0-255/0-255,Y/U/V range 16-235/16-240/16-240"
|
|
bitfld.long 0xbc 10. " DP_CSC_GAMUT_SAT_EN_ASYNC1 ,Indicate if GAMUT saturation is enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xbc 8.--9. " DP_CSC_DEF_ASYNC1 ,Enable or disable Color Space Conversion" "Disabled,Enable after combining,Enable before comb. on BG,Enable before comb. on FG"
|
|
bitfld.long 0xbc 4.--6. " DP_COC_ASYNC1 ,Cursor Operation Control" "Disabled,Full,Reversed,AND,Reserved,OR,XOR,?..."
|
|
textline " "
|
|
bitfld.long 0xbc 3. " DP_GWCKE_ASYNC1 ,Graphic Window Color Keying Enable" "Disabled,Enabled"
|
|
bitfld.long 0xbc 2. " DP_GWAM_ASYNC1 ,Graphic Window Alpha Mode" "Local,Global"
|
|
textline " "
|
|
bitfld.long 0xbc 1. " DP_GWSEL_ASYNC1 ,Graphic Window Select" "Full,Partial"
|
|
line.long 0xc0 "DP_GRAPH_WIND_CTRL_ASYNC1,DP Graphic Window Control ASYNC1 Flow Register"
|
|
hexmask.long.byte 0xc0 24.--31. 1. " DP_GWAV_ASYNC1 ,Graphic Window Alpha Value"
|
|
hexmask.long.byte 0xc0 16.--23. 1. " DP_GWCKR_ASYNC1 ,Graphic Window Color Keying Red Component"
|
|
textline " "
|
|
hexmask.long.byte 0xc0 8.--15. 1. " DP_GWCKG_ASYNC1 ,Graphic Window Color Keying Green Component"
|
|
hexmask.long.byte 0xc0 0.--7. 1. " DP_GWCKB_ASYNC1 ,Graphic Window Color Keying Blue Component"
|
|
line.long 0xc4 "DP_FG_POS_ASYNC1,DP partial plane Window Position ASYNC1 Flow Register"
|
|
hexmask.long.word 0xc4 16.--26. 1. " DP_FGXP_ASYNC1 ,FGXP partial plane Window X Position"
|
|
hexmask.long.word 0xc4 0.--10. 1. " DP_FGYP_ASYNC1 ,FGYP partial plane Window Y Position"
|
|
line.long 0xc8 "DP_CUR_POS_ASYNC1,DP Cursor Position and Size ASYNC1 Flow Register"
|
|
hexmask.long.byte 0xc8 27.--31. 1. " DP_CYP_ASYNC1 ,Cursor Y Position"
|
|
hexmask.long.word 0xc8 16.--26. 1. " DP_CYH_ASYNC1 ,Cursor Height"
|
|
textline " "
|
|
hexmask.long.byte 0xc8 11.--15. 1. " DP_CXP_ASYNC1 ,Cursor X Position"
|
|
hexmask.long.word 0xc8 0.--10. 1. " DP_CXW_ASYNC1 ,Cursor Width"
|
|
line.long 0xcc "DP_CUR_MAP_ASYNC1,DP Color Cursor Mapping ASYNC1 Flow Register"
|
|
hexmask.long.byte 0xcc 16.--23. 1. " DP_CUR_COL_B_ASYNC1 ,Blue component of the cursor color in color mode"
|
|
hexmask.long.byte 0xcc 8.--15. 1. " CUR_COL_G_ASYNC1 ,Green component of the cursor color in color mode"
|
|
textline " "
|
|
hexmask.long.byte 0xcc 0.--7. 1. " CUR_COL_R_ASYNC1 ,Red component of the cursor color in color mode"
|
|
line.long 0xD0 "DP_GAMMA_C_ASYNC1_0,DP Gamma Constants ASYNC1 Flow Register 0"
|
|
hexmask.long.word 0xD0 16.--24. 1. " DP_GAMMA_C_ASYNC1_1 ,CONSTANT 1 parameter of Gamma Correction"
|
|
hexmask.long.word 0xD0 0.--8. 1. " DP_GAMMA_C_ASYNC1_0 ,CONSTANT 0 parameter of Gamma Correction"
|
|
line.long 0xD4 "DP_GAMMA_C_ASYNC1_1,DP Gamma Constants ASYNC1 Flow Register 1"
|
|
hexmask.long.word 0xD4 16.--24. 1. " DP_GAMMA_C_ASYNC1_3 ,CONSTANT 3 parameter of Gamma Correction"
|
|
hexmask.long.word 0xD4 0.--8. 1. " DP_GAMMA_C_ASYNC1_2 ,CONSTANT 2 parameter of Gamma Correction"
|
|
line.long 0xD8 "DP_GAMMA_C_ASYNC1_2,DP Gamma Constants ASYNC1 Flow Register 2"
|
|
hexmask.long.word 0xD8 16.--24. 1. " DP_GAMMA_C_ASYNC1_5 ,CONSTANT 5 parameter of Gamma Correction"
|
|
hexmask.long.word 0xD8 0.--8. 1. " DP_GAMMA_C_ASYNC1_4 ,CONSTANT 4 parameter of Gamma Correction"
|
|
line.long 0xDC "DP_GAMMA_C_ASYNC1_3,DP Gamma Constants ASYNC1 Flow Register 3"
|
|
hexmask.long.word 0xDC 16.--24. 1. " DP_GAMMA_C_ASYNC1_7 ,CONSTANT 7 parameter of Gamma Correction"
|
|
hexmask.long.word 0xDC 0.--8. 1. " DP_GAMMA_C_ASYNC1_6 ,CONSTANT 6 parameter of Gamma Correction"
|
|
line.long 0xE0 "DP_GAMMA_C_ASYNC1_4,DP Gamma Constants ASYNC1 Flow Register 4"
|
|
hexmask.long.word 0xE0 16.--24. 1. " DP_GAMMA_C_ASYNC1_9 ,CONSTANT 9 parameter of Gamma Correction"
|
|
hexmask.long.word 0xE0 0.--8. 1. " DP_GAMMA_C_ASYNC1_8 ,CONSTANT 8 parameter of Gamma Correction"
|
|
line.long 0xE4 "DP_GAMMA_C_ASYNC1_5,DP Gamma Constants ASYNC1 Flow Register 5"
|
|
hexmask.long.word 0xE4 16.--24. 1. " DP_GAMMA_C_ASYNC1_11 ,CONSTANT 11 parameter of Gamma Correction"
|
|
hexmask.long.word 0xE4 0.--8. 1. " DP_GAMMA_C_ASYNC1_10 ,CONSTANT 10 parameter of Gamma Correction"
|
|
line.long 0xE8 "DP_GAMMA_C_ASYNC1_6,DP Gamma Constants ASYNC1 Flow Register 6"
|
|
hexmask.long.word 0xE8 16.--24. 1. " DP_GAMMA_C_ASYNC1_13 ,CONSTANT 13 parameter of Gamma Correction"
|
|
hexmask.long.word 0xE8 0.--8. 1. " DP_GAMMA_C_ASYNC1_12 ,CONSTANT 12 parameter of Gamma Correction"
|
|
line.long 0xEC "DP_GAMMA_C_ASYNC1_7,DP Gamma Constants ASYNC1 Flow Register 7"
|
|
hexmask.long.word 0xEC 16.--24. 1. " DP_GAMMA_C_ASYNC1_15 ,CONSTANT 15 parameter of Gamma Correction"
|
|
hexmask.long.word 0xEC 0.--8. 1. " DP_GAMMA_C_ASYNC1_14 ,CONSTANT 14 parameter of Gamma Correction"
|
|
line.long 0xF0 "DP_GAMMA_S_ASYNC1_0,DP Gamma Correction Slope async1 Flow Register0"
|
|
hexmask.long.byte 0xF0 24.--31. 1. " DP_GAMMA_S_ASYNC1_3 ,SLOPE 3 parameter of Gamma Correction"
|
|
hexmask.long.byte 0xF0 16.--23. 1. " DP_GAMMA_S_ASYNC1_2 ,SLOPE 2 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0xF0 8.--15. 1. " DP_GAMMA_S_ASYNC1_1 ,SLOPE 1 parameter of Gamma Correction"
|
|
hexmask.long.byte 0xF0 0.--7. 1. " DP_GAMMA_S_ASYNC1_0 ,SLOPE 0 parameter of Gamma Correction"
|
|
line.long 0xF4 "DP_GAMMA_S_ASYNC1_1,DP Gamma Correction Slope async1 Flow Register1"
|
|
hexmask.long.byte 0xF4 24.--31. 1. " DP_GAMMA_S_ASYNC1_7 ,SLOPE 7 parameter of Gamma Correction"
|
|
hexmask.long.byte 0xF4 16.--23. 1. " DP_GAMMA_S_ASYNC1_6 ,SLOPE 6 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0xF4 8.--15. 1. " DP_GAMMA_S_ASYNC1_5 ,SLOPE 5 parameter of Gamma Correction"
|
|
hexmask.long.byte 0xF4 0.--7. 1. " DP_GAMMA_S_ASYNC1_4 ,SLOPE 4 parameter of Gamma Correction"
|
|
line.long 0xF8 "DP_GAMMA_S_ASYNC1_2,DP Gamma Correction Slope async1 Flow Register2"
|
|
hexmask.long.byte 0xF8 24.--31. 1. " DP_GAMMA_S_ASYNC1_11 ,SLOPE 11 parameter of Gamma Correction"
|
|
hexmask.long.byte 0xF8 16.--23. 1. " DP_GAMMA_S_ASYNC1_10 ,SLOPE 10 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0xF8 8.--15. 1. " DP_GAMMA_S_ASYNC1_9 ,SLOPE 9 parameter of Gamma Correction"
|
|
hexmask.long.byte 0xF8 0.--7. 1. " DP_GAMMA_S_ASYNC1_8 ,SLOPE 8 parameter of Gamma Correction"
|
|
line.long 0xFC "DP_GAMMA_S_ASYNC1_3,DP Gamma Correction Slope async1 Flow Register3"
|
|
hexmask.long.byte 0xFC 24.--31. 1. " DP_GAMMA_S_ASYNC1_15 ,SLOPE 15 parameter of Gamma Correction"
|
|
hexmask.long.byte 0xFC 16.--23. 1. " DP_GAMMA_S_ASYNC1_14 ,SLOPE 14 parameter of Gamma Correction"
|
|
textline " "
|
|
hexmask.long.byte 0xFC 8.--15. 1. " DP_GAMMA_S_ASYNC1_13 ,SLOPE 13 parameter of Gamma Correction"
|
|
hexmask.long.byte 0xFC 0.--7. 1. " DP_GAMMA_S_ASYNC1_12 ,SLOPE 12 parameter of Gamma Correction"
|
|
line.long 0x100 "DP_CSCA_ASYNC1_0,DP Color Space Conversion Control ASYNC1 Flow register 0"
|
|
hexmask.long.word 0x100 16.--25. 1. " DP_CSC_A_ASYNC1_1 ,A 1 parameter of color conversion"
|
|
hexmask.long.word 0x100 0.--9. 1. " DP_CSC_A_ASYNC1_0 ,A 0 parameter of color conversion"
|
|
line.long 0x104 "DP_CSCA_ASYNC1_1,DP Color Space Conversion Control ASYNC1 Flow register 1"
|
|
hexmask.long.word 0x104 16.--25. 1. " DP_CSC_A_ASYNC1_3 ,A 3 parameter of color conversion"
|
|
hexmask.long.word 0x104 0.--9. 1. " DP_CSC_A_ASYNC1_2 ,A 2 parameter of color conversion"
|
|
line.long 0x108 "DP_CSCA_ASYNC1_2,DP Color Space Conversion Control ASYNC1 Flow register 2"
|
|
hexmask.long.word 0x108 16.--25. 1. " DP_CSC_A_ASYNC1_5 ,A 5 parameter of color conversion"
|
|
hexmask.long.word 0x108 0.--9. 1. " DP_CSC_A_ASYNC1_4 ,A 4 parameter of color conversion"
|
|
line.long 0x10C "DP_CSCA_ASYNC1_3,DP Color Space Conversion Control ASYNC1 Flow register 3"
|
|
hexmask.long.word 0x10C 16.--25. 1. " DP_CSC_A_ASYNC1_7 ,A 7 parameter of color conversion"
|
|
hexmask.long.word 0x10C 0.--9. 1. " DP_CSC_A_ASYNC1_6 ,A 6 parameter of color conversion"
|
|
line.long 0x110 "DP_CSC_ASYNC1_0,DP Color Conversion Control ASYNC1 Flow register 0"
|
|
bitfld.long 0x110 30.--31. " DP_CSC_S0_ASYNC1 ,S0 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0x110 16.--29. 1. " DP_CSC_B0_ASYNC1 ,B0 parameter of color conversion"
|
|
textline " "
|
|
hexmask.long.word 0x110 0.--9. 1. " DP_CSC_A8_ASYNC1 ,A parameter of color conversion"
|
|
line.long 0x114 "DP_CSC_ASYNC1_1,DP Color Conversion Control ASYNC1 Flow register 1"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
bitfld.long 0x114 30.--31. " DP_CSC_S2_ASYNC1 ,S2 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0x114 16.--29. 1. " DP_CSC_B2_ASYNC1 ,B2 parameter of color conversion"
|
|
textline " "
|
|
bitfld.long 0x114 14.--15. " DP_CSC_S1_ASYNC1 ,S1 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0x114 0.--13. 1. " DP_CSC_B1_ASYNC1 ,B1 parameter of color conversion"
|
|
else
|
|
bitfld.long 0x114 30.--31. " DP_CSC_S2_ASYNC1 ,S0 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0x114 16.--29. 1. " DP_CSC_B2_ASYNC1 ,B0 parameter of color conversion"
|
|
textline " "
|
|
bitfld.long 0x114 14.--15. " DP_CSC_S1_ASYNC1 ,S0 parameter of color conversion" "2,1,0,-1"
|
|
hexmask.long.word 0x114 0.--13. 1. " DP_CSC_B1_ASYNC1 ,B0 parameter of color conversion"
|
|
endif
|
|
base ad:0x5e018000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DP_DEBUG_CNT,DP Debug Control register"
|
|
bitfld.long 0x00 5.--7. " BRAKE_CNT_1 ,Counts the breaking events for unit #1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. " BRAKE_STATUS_EN_1 ,Enables the break/status unit #1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " BRAKE_CNT_0 ,Counts the breaking events for unit #0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " BRAKE_STATUS_EN_0 ,Enables the break/status unit #0" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "DP_DEBUG_STAT,DP Debug Status register"
|
|
bitfld.long 0x00 29. " CYP_EN_OLD_1 ,Async flow has been broken in the middle of a cursor" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " COMBYP_EN_OLD_1 ,Async flow has been broken in the middle of combining" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FG_ACTIVE_1 ,Displaying the partial frame has been started" "Not occurred,Occurred"
|
|
hexmask.long.word 0x00 16.--26. 1. " V_CNT_OLD_1 ,The exact row where the async flow has been broken"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CYP_EN_OLD_0 ,Async flow has been broken in the middle of a cursor" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " COMBYP_EN_OLD_0 ,Async flow has been broken in the middle of combining" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FG_ACTIVE_0 ,Displaying the partial frame has been started for async flow" "Not occurred,Occurred"
|
|
hexmask.long.word 0x00 0.--10. 1. " V_CNT_OLD_0 ,The exact row where the async flow has been broken"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IC registers"
|
|
base ad:0x5e020000
|
|
width 16.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "IC_CONF,IC Configuration Register"
|
|
bitfld.long 0x00 31. " CSI_MEM_WR_EN ,CSI direct memory write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RWS_EN ,Raw sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " IC_KEY_COLOR_EN ,Key color enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " IC_GLB_LOC_A ,Global alpha" "Local,Global"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PP_ROT_EN ,Postprocessing rotation task enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PP_CMB ,Postprocessing task combining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PP_CSC2 ,Postprocessing task color conversion RGB-->YUV enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PP_CSC1 ,Postprocessing task color conversion YUV-->RGB enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PP_EN ,Postprocessing task enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PRPVF_ROT_EN ,Preprocessing rotation task for viewfinder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PRPVF_CMB ,Preprocessing task for view-finder combining enable" "Disabled,Enabled"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
textline " "
|
|
bitfld.long 0x00 10. " PRPVF_CSC2 ,Preprocessing task for view-finder second color conversion enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 9. " PRPVF_CSC1 ,Preprocessing task for view-finder first color conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PRPVF_EN ,Preprocessing task for view-finder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PRPENC_ROT_EN ,Preprocessing rotation task for encoding enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PRPENC_CSC1 ,Preprocessing task for encoding color conversion enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PRPENC_EN ,Preprocessing task for encoding enable" "Disabled,Enabled"
|
|
line.long 0x04 "IC_PRP_ENC_RSC,IC Preprocessing Encoder Resizing Coefficients Register"
|
|
bitfld.long 0x04 30.--31. " PRPENC_DS_R_V ,Preprocessing task for encoding downsizing vertical ratio" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--29. 1. " PRPENC_RS_R_V ,Preprocessing task for encoding resizing vertical ratio"
|
|
bitfld.long 0x04 14.--15. " PRPENC_DS_R_H ,Preprocessing task for encoding downsizing horizontal ratio" "1,2,4,?..."
|
|
hexmask.long.word 0x04 0.--13. 1. " PRPENC_RS_R_H ,Preprocessing task for encoding resizing horizontal ratio"
|
|
line.long 0x08 "IC_PRP_VF_RSC,IC Preprocessing View-Finder Resizing Coefficients Register"
|
|
bitfld.long 0x08 30.--31. " PRPVF_DS_R_V ,Preprocessing task for encoding downsizing vertical ratio" "0,1,2,3"
|
|
hexmask.long.word 0x08 16.--29. 1. " PRPVF_RS_R_V ,Preprocessing task for encoding resizing vertical ratio"
|
|
bitfld.long 0x08 14.--15. " PRPVF_DS_R_H ,Preprocessing task for encoding downsizing horizontal ratio" "1,2,4,?..."
|
|
hexmask.long.word 0x08 0.--13. 1. " PRPVF_RS_R_H ,Preprocessing task for view-finding resizing horizontal ratio"
|
|
line.long 0x0c "IC_PP_RSC,IC Postprocessing Resizing Coefficients Register"
|
|
bitfld.long 0x0c 30.--31. " PP_DS_R_V ,Postprocessing task downsizing vertical ratio" "0,1,2,3"
|
|
hexmask.long.word 0x0c 16.--29. 1. " PP_RS_R_V ,Postprocessing task resizing vertical ratio"
|
|
bitfld.long 0x0c 14.--15. " PP_DS_R_H ,Postprocessing task downsizing horizontal ratio" "1,2,4,?..."
|
|
hexmask.long.word 0x0c 0.--13. 1. " PP_RS_R_H ,Postprocessing task resizing horizontal ratio"
|
|
line.long 0x10 "IC_CMBP_1,IC Combining Parameters Register 1"
|
|
hexmask.long.byte 0x10 8.--15. 1. " IC_PP_ALPHA_V ,Postprocessing task global alpha"
|
|
hexmask.long.byte 0x10 0.--7. 1. " IC_PRPVF_ALPHA_V ,Preprocessing task for encoding global alpha"
|
|
line.long 0x14 "IC_CMBP_2,IC Combining Parameters Register 2"
|
|
hexmask.long.byte 0x14 16.--23. 1. " IC_KEY_COLOR_R ,Key color red"
|
|
hexmask.long.byte 0x14 8.--15. 1. " IC_KEY_COLOR_G ,Key color green"
|
|
hexmask.long.byte 0x14 0.--7. 1. " IC_KEY_COLOR_B ,Key color blue"
|
|
line.long 0x18 "IC_IDMAC_1,IC IDMAC Parameters 1 Register"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
bitfld.long 0x18 25. " ALT_CB7_BURST_16 ,Number of pixels within a burst coming from the IDMAC for IC's CB7" "8,16"
|
|
bitfld.long 0x18 24. " ALT_CB6_BURST_16 ,Number of active cycles within a burst coming coming from the IDMAC for IC's CB6" "8,16"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 22. " T3_FLIP_RS ,LEFT/RIGHT flip for Post Processing (PP) task" "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " T2_FLIP_RS ,LEFT/RIGHT flip for View Finder (VF) task" "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " T1_FLIP_RS ,LEFT/RIGHT flip for Encoding (ENC) task" "Disabled,Enabled"
|
|
bitfld.long 0x18 19. " T3_FLIP_UD ,UP/DOWN flip for Post Processing (PP) task" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 18. " T3_FLIP_LR ,LEFT/RIGHT flip for Post Processing (PP) task" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " T3_ROT ,Rotation for Post Processing (PP) task" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " T2_FLIP_UD ,UP/DOWN flip for View Finder (VF) task" "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " T2_FLIP_LR ,LEFT/RIGHT flip for View Finder (VF) task" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 14. " T2_ROT ,Rotation for View Finder (VF) task" "Disabled,Enabled"
|
|
bitfld.long 0x18 13. " T1_FLIP_UD ,UP/DOWN flip for Encoding (ENC) task" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " T1_FLIP_LR ,LEFT/RIGHT flip for Encoding (ENC) task" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " T1_ROT ,Rotation for Encoding (ENC) task" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " CB7_BURST_16 ,Number of active cycles within a burst coming from the IDMAC for IC's CB7" "8,16"
|
|
bitfld.long 0x18 6. " CB6_BURST_16 ,Number of active cycles within a burst coming from the IDMAC for IC's CB6" "8,16"
|
|
bitfld.long 0x18 5. " CB5_BURST_16 ,Number of active cycles within a burst coming from the IDMAC for IC's CB5" "8,16"
|
|
bitfld.long 0x18 4. " CB4_BURST_16 ,Number of active cycles within a burst coming from the IDMAC for IC's CB4" "8,16"
|
|
textline " "
|
|
bitfld.long 0x18 3. " CB3_BURST_16 ,Number of active cycles within a burst coming from the IDMAC for IC's CB3" "8,16"
|
|
bitfld.long 0x18 2. " CB2_BURST_16 ,Number of active cycles within a burst coming from the IDMAC for IC's CB2" "8,16"
|
|
bitfld.long 0x18 1. " CB1_BURST_16 ,Number of active cycles within a burst coming from the IDMAC for IC's CB1" "8,16"
|
|
bitfld.long 0x18 0. " CB0_BURST_16 ,Number of active cycles within a burst coming from the IDMAC for IC's CB0" "8,16"
|
|
line.long 0x1c "IC_IDMAC_2,IC IDMAC Parameters 2 Register"
|
|
hexmask.long.word 0x1C 20.--29. 1. " T3_FR_HEIGHT ,Frame Height for Post Processing (PP) task"
|
|
hexmask.long.word 0x1C 10.--19. 1. " T2_FR_HEIGHT ,Frame Height for View Finder (VF) task"
|
|
hexmask.long.word 0x1C 0.--9. 1. " T1_FR_HEIGHT ,Frame Height for Encoding (ENC) task"
|
|
line.long 0x20 "IC_IDMAC_3,IC IDMAC Parameters 3 Register"
|
|
hexmask.long.word 0x20 20.--29. 1. " T3_FR_WIDTH ,Frame Width for Post Processing (PP) task"
|
|
hexmask.long.word 0x20 10.--19. 1. " T2_FR_WIDTH ,Frame Width for View Finder (VF) task"
|
|
hexmask.long.word 0x20 0.--9. 1. " T1_FR_WIDTH ,Frame Width for Encoding (ENC) task"
|
|
line.long 0x24 "IC_IDMAC_4,IC IDMAC Parameters 4 Register"
|
|
bitfld.long 0x24 12.--15. " RM_BRDG_MAX_RQ ,RM memory Bridge Max Requests" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 8.--11. " IBM_BRDG_MAX_RQ ,IBM memory Bridge Max Requests" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 4.--7. " MPM_DMFC_BRDG_MAX_RQ ,MPM memory Bridge Max Requests for the IC DMFC interface" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 0.--3. " MPM_RW_BRDG_MAX_RQ ,MPM memory Bridge Max Requests between MPM's read and writes" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSI0 registers"
|
|
base ad:0x5e030000
|
|
width 20.
|
|
group.long 0x00++0x1b
|
|
line.long 0x00 "CSI0_SENS_CONF,CSI0 Sensor Configuration Register"
|
|
bitfld.long 0x00 31. " CSI0_DATA_EN_POL ,Invert IPP_IND_SENSB_DATA_EN input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 29. " CSI0_FORCE_EOF ,Force End of frame" "No effect,Forced"
|
|
bitfld.long 0x00 28. " CSI0_JPEG_MODE ,JPEG Mode" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CSI0_JPEG8_EN ,JPEG8 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " CSI0_DATA_DEST ,Destination of the data coming from the CSI" ",IC,IDMAC via SMFC,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSI0_DIV_RATIO ,Clock division ratio minus 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CSI0_EXT_VSYNC ,External VSYNC enable" "Internal,External"
|
|
bitfld.long 0x00 11.--14. " CSI0_DATA_WIDTH ,Number of bits per color" "4,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--10. " CSI0_SENS_DATA_FORMAT ,Data format from the sensor" "Full RGB or YUV444,YUV422 (YUYV...),YUV422 (UYVY...),Bayer or Generic,RGB565,RGB555,RGB444,JPEG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSI0_PACK_TIGHT ,CSI0 Pack Tight" "Not tight,Tight"
|
|
bitfld.long 0x00 4.--6. " CSI0_SENS_PRTCL ,Sensor protocol" "Gated clock mode,Non-gated clock mode,CCIR progressive mode (BT.656),CCIR interlaced mode (BT.656),CCIR progressive (BT.1120 DDR),CCIR progressive (BT.1120 SDR),CCIR interlaced mode (BT.1120 DDR),CCIR interlaced mode (BT.1120 SDR)"
|
|
bitfld.long 0x00 3. " CSI0_SENS_PIX_CLK_POL ,Invert pixel clock input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSI0_DATA_POL ,Invert data input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 1. " CSI0_HSYNC_POL ,Invert IPP_IND_SENSB_HSYNC input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " CSI0_VSYNC_POL ,Invert IPP_IND_SENSB_VSYNC input" "Not inverted,Inverted"
|
|
line.long 0x04 "CSI0_SENS_FRM_SIZE,CSI0 Sense Frame Size Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " CSI0_SENS_FRM_HEIGHT ,Sensor frame height minus 1"
|
|
hexmask.long.word 0x04 0.--12. 1. " CSI0_SENS_FRM_WIDTH ,Sensor frame width minus 1"
|
|
line.long 0x08 "CSI0_ACT_FRM_SIZE,CSI0 Actual Frame Size Register"
|
|
hexmask.long.word 0x08 16.--27. 1. " CSI0_ACT_FRM_HEIGHT ,Sensor frame height minus 1"
|
|
hexmask.long.word 0x08 0.--12. 1. " CSI0_ACT_FRM_WIDTH ,Sensor frame width minus 1"
|
|
line.long 0x0c "CSI0_OUT_FRM_CTRL,CSI0 Output Control Register"
|
|
bitfld.long 0x0c 31. " CSI0_HORZ_DWNS ,Enable horizontal downsizing" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " CSI0_VERT_DWNS ,Enable vertical downsizing" "Disabled,Enabled"
|
|
hexmask.long.word 0x0c 16.--28. 1. " CSI0_HSC ,Number of columns to skip"
|
|
textline " "
|
|
hexmask.long.word 0x0c 0.--11. 1. " CSI0_VSC ,Number of rows to skip"
|
|
line.long 0x10 "CSI0_TST_CTRL,CSI0 Test Control Register"
|
|
bitfld.long 0x10 24. " CSI0_TEST_GEN_MODE ,Test generator mode" "Inactive,Active"
|
|
hexmask.long.byte 0x10 16.--23. 1. " CSI0_PG_B_VALUE ,Pattern generator B value"
|
|
hexmask.long.byte 0x10 8.--15. 1. " CSI0_PG_G_VALUE ,Pattern generator G value"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " CSI0_PG_R_VALUE ,Pattern generator R value"
|
|
line.long 0x14 "CSI0_CCIR_CODE_1,CSI0 Output Control Register 1"
|
|
bitfld.long 0x14 24. " CSI0_CCIR_ERR_DET_EN ,Enable error detection and correction for CCIR interlaced mode with protection bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 19.--21. " CSI0_STRT_FLD0_ACTV ,Start of field 0 active line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16.--18. " CSI0_END_FLD0_ACTV ,End of field 0 active line command (I)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 9.--11. " CSI0_STRT_FLD0_BLNK_2ND ,Start of field 0 second blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. " CSI0_END_FLD0_BLNK_2ND ,End of field 0 second blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. " CSI0_STRT_FLD0_BLNK_1ST ,Start of field 0 first blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " CSI0_END_FLD0_BLNK_1ST ,End of field 0 first blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CSI0_CCIR_CODE_2,CSI0 CCIR Code Register 2"
|
|
bitfld.long 0x18 19.--21. " CSI0_STRT_FLD1_ACTV ,Start of field 1 active line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 16.--18. " CSI0_END_FLD1_ACTV ,End of field 1 active line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. " CSI0_STRT_FLD1_BLNK_2ND ,Start of field 1 second blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 6.--8. " CSI0_END_FLD1_BLNK_2ND ,End of field 1 second blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3.--5. " CSI0_STRT_FLD1_BLNK_1ST ,Start of field 1 first blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. " CSI0_END_FLD1_BLNK_1ST ,End of field 1 first blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
if (((per.l(ad:0x5e030000))&0x70)==0x20)||(((per.l(ad:0x5e030000))&0x70)==0x30)
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "CSI0_CCIR_CODE_3,CSI0 CCIR Code Register 3"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CSI0_CCIR_PRECOM ,CCIR pre command (3X8bit)"
|
|
elif (((per.l(ad:0x5e030000))&0x70)==0x40)||(((per.l(ad:0x5e030000))&0x70)==0x50)||(((per.l(ad:0x5e030000))&0x70)==0x60)||(((per.l(ad:0x5e030000))&0x70)==0x70)
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "CSI0_CCIR_CODE_3,CSI0 CCIR Code Register 3"
|
|
hexmask.long 0x00 0.--29. 1. " CSI0_CCIR_PRECOM ,CCIR pre command (3X10bit)"
|
|
else
|
|
hgroup.long 0x1c++0x3
|
|
hide.long 0x00 "CSI0_CCIR_CODE_3,CSI0 CCIR Code Register 3"
|
|
endif
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
group.long 0x20++0xd3
|
|
line.long 0x00 "CSI0_DI,CSI0 Data Identifier Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CSI0_MIPI_DI3 ,Holds the Data Identifier #3 handled by the CSI"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSI0_MIPI_DI2 ,Holds the Data Identifier #2 handled by the CSI"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSI0_MIPI_DI1 ,Holds the Data Identifier #1 handled by the CSI"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSI0_MIPI_DI0 ,Holds the Data Identifier #0 handled by the CSI"
|
|
line.long 0x04 "CSI0_SKIP,CSI0 SKIP Register"
|
|
bitfld.long 0x04 19.--23. " CSI0_SKIP_ISP ,Skipping pattern of the frames send to the ISP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--18. " CSI0_MAX_RATIO_SKIP_ISP ,CSI0 Maximum Ratio Skip for ISP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 3.--7. " CSI0_SKIP_SMFC ,Skipping pattern of the frames send to the SMFC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--2. " CSI0_MAX_RATIO_SKIP_SMFC ,CSI0 Maximum Ratio Skip for SMFC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "CSI0_CPD_CTRL,CSI0 Compander Control Register"
|
|
bitfld.long 0x08 2.--4. " CSI0_CPD ,Enable the compander in the path to different destination" "ISP,IC,IDMAC via SMFC,?..."
|
|
bitfld.long 0x08 1. " CSI0_RED_ROW_BEGIN ,Color of first row in the frame" "GBGB,GRGR"
|
|
bitfld.long 0x08 0. " CSI0_GREEN_P_BEGIN ,Color of first component in the frame" "Blue or red,Green"
|
|
line.long 0xC "CSI0_CPD_RC_0,CSI0 Red component Compander Constants Register 0"
|
|
hexmask.long.word 0xC 16.--25. 1. " CSI0_CPD_RC_1 ,CONSTANT 1 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0xC 0.--9. 1. " CSI0_CPD_RC_0 ,CONSTANT 0 Parameter of Compander (Red component)"
|
|
line.long 0x10 "CSI0_CPD_RC_1,CSI0 Red component Compander Constants Register 1"
|
|
hexmask.long.word 0x10 16.--25. 1. " CSI0_CPD_RC_3 ,CONSTANT 3 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x10 0.--9. 1. " CSI0_CPD_RC_2 ,CONSTANT 2 Parameter of Compander (Red component)"
|
|
line.long 0x14 "CSI0_CPD_RC_2,CSI0 Red component Compander Constants Register 2"
|
|
hexmask.long.word 0x14 16.--25. 1. " CSI0_CPD_RC_5 ,CONSTANT 5 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x14 0.--9. 1. " CSI0_CPD_RC_4 ,CONSTANT 4 Parameter of Compander (Red component)"
|
|
line.long 0x18 "CSI0_CPD_RC_3,CSI0 Red component Compander Constants Register 3"
|
|
hexmask.long.word 0x18 16.--25. 1. " CSI0_CPD_RC_7 ,CONSTANT 7 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x18 0.--9. 1. " CSI0_CPD_RC_6 ,CONSTANT 6 Parameter of Compander (Red component)"
|
|
line.long 0x1C "CSI0_CPD_RC_4,CSI0 Red component Compander Constants Register 4"
|
|
hexmask.long.word 0x1C 16.--25. 1. " CSI0_CPD_RC_9 ,CONSTANT 9 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x1C 0.--9. 1. " CSI0_CPD_RC_8 ,CONSTANT 8 Parameter of Compander (Red component)"
|
|
line.long 0x20 "CSI0_CPD_RC_5,CSI0 Red component Compander Constants Register 5"
|
|
hexmask.long.word 0x20 16.--25. 1. " CSI0_CPD_RC_11 ,CONSTANT 11 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x20 0.--9. 1. " CSI0_CPD_RC_10 ,CONSTANT 10 Parameter of Compander (Red component)"
|
|
line.long 0x24 "CSI0_CPD_RC_6,CSI0 Red component Compander Constants Register 6"
|
|
hexmask.long.word 0x24 16.--25. 1. " CSI0_CPD_RC_13 ,CONSTANT 13 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x24 0.--9. 1. " CSI0_CPD_RC_12 ,CONSTANT 12 Parameter of Compander (Red component)"
|
|
line.long 0x28 "CSI0_CPD_RC_7,CSI0 Red component Compander Constants Register 7"
|
|
hexmask.long.word 0x28 16.--25. 1. " CSI0_CPD_RC_15 ,CONSTANT 15 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x28 0.--9. 1. " CSI0_CPD_RC_14 ,CONSTANT 14 Parameter of Compander (Red component)"
|
|
line.long 0x2C "CSI0_CPD_RS_0,CSI0 Red component Compander SLOPE Register 0"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " CSI0_CPD_RS_3 ,SLOPE 3 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " CSI0_CPD_RS_2 ,SLOPE 2 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " CSI0_CPD_RS_1 ,SLOPE 1 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " CSI0_CPD_RS_0 ,SLOPE 0 Parameter of Compander (Red component)"
|
|
line.long 0x30 "CSI0_CPD_RS_1,CSI0 Red component Compander SLOPE Register 1"
|
|
hexmask.long.byte 0x30 24.--31. 1. " CSI0_CPD_RS_7 ,SLOPE 7 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x30 16.--23. 1. " CSI0_CPD_RS_6 ,SLOPE 6 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x30 8.--15. 1. " CSI0_CPD_RS_5 ,SLOPE 5 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x30 0.--7. 1. " CSI0_CPD_RS_4 ,SLOPE 4 Parameter of Compander (Red component)"
|
|
line.long 0x34 "CSI0_CPD_RS_2,CSI0 Red component Compander SLOPE Register 2"
|
|
hexmask.long.byte 0x34 24.--31. 1. " CSI0_CPD_RS_11 ,SLOPE 11 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x34 16.--23. 1. " CSI0_CPD_RS_10 ,SLOPE 10 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x34 8.--15. 1. " CSI0_CPD_RS_9 ,SLOPE 9 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x34 0.--7. 1. " CSI0_CPD_RS_8 ,SLOPE 8 Parameter of Compander (Red component)"
|
|
line.long 0x38 "CSI0_CPD_RS_3,CSI0 Red component Compander SLOPE Register 3"
|
|
hexmask.long.byte 0x38 24.--31. 1. " CSI0_CPD_RS_15 ,SLOPE 15 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x38 16.--23. 1. " CSI0_CPD_RS_14 ,SLOPE 14 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x38 8.--15. 1. " CSI0_CPD_RS_13 ,SLOPE 13 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x38 0.--7. 1. " CSI0_CPD_RS_12 ,SLOPE 12 Parameter of Compander (Red component)"
|
|
line.long 0x3C "CSI0_CPD_GRC_0,CSI0 GR component Compander Constants Register 0"
|
|
hexmask.long.word 0x3C 16.--24. 1. " CSI0_CPD_GRC_1 ,CONSTANT 1 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x3C 0.--8. 1. " CSI0_CPD_GRC_0 ,CONSTANT 0 Parameter of Compander (GR component)"
|
|
line.long 0x40 "CSI0_CPD_GRC_1,CSI0 GR component Compander Constants Register 1"
|
|
hexmask.long.word 0x40 16.--24. 1. " CSI0_CPD_GRC_3 ,CONSTANT 3 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x40 0.--8. 1. " CSI0_CPD_GRC_2 ,CONSTANT 2 Parameter of Compander (GR component)"
|
|
line.long 0x44 "CSI0_CPD_GRC_2,CSI0 GR component Compander Constants Register 2"
|
|
hexmask.long.word 0x44 16.--24. 1. " CSI0_CPD_GRC_5 ,CONSTANT 5 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x44 0.--8. 1. " CSI0_CPD_GRC_4 ,CONSTANT 4 Parameter of Compander (GR component)"
|
|
line.long 0x48 "CSI0_CPD_GRC_3,CSI0 GR component Compander Constants Register 3"
|
|
hexmask.long.word 0x48 16.--24. 1. " CSI0_CPD_GRC_7 ,CONSTANT 7 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x48 0.--8. 1. " CSI0_CPD_GRC_6 ,CONSTANT 6 Parameter of Compander (GR component)"
|
|
line.long 0x4C "CSI0_CPD_GRC_4,CSI0 GR component Compander Constants Register 4"
|
|
hexmask.long.word 0x4C 16.--24. 1. " CSI0_CPD_GRC_9 ,CONSTANT 9 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x4C 0.--8. 1. " CSI0_CPD_GRC_8 ,CONSTANT 8 Parameter of Compander (GR component)"
|
|
line.long 0x50 "CSI0_CPD_GRC_5,CSI0 GR component Compander Constants Register 5"
|
|
hexmask.long.word 0x50 16.--24. 1. " CSI0_CPD_GRC_11 ,CONSTANT 11 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x50 0.--8. 1. " CSI0_CPD_GRC_10 ,CONSTANT 10 Parameter of Compander (GR component)"
|
|
line.long 0x54 "CSI0_CPD_GRC_6,CSI0 GR component Compander Constants Register 6"
|
|
hexmask.long.word 0x54 16.--24. 1. " CSI0_CPD_GRC_13 ,CONSTANT 13 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x54 0.--8. 1. " CSI0_CPD_GRC_12 ,CONSTANT 12 Parameter of Compander (GR component)"
|
|
line.long 0x58 "CSI0_CPD_GRC_7,CSI0 GR component Compander Constants Register 7"
|
|
hexmask.long.word 0x58 16.--24. 1. " CSI0_CPD_GRC_15 ,CONSTANT 15 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x58 0.--8. 1. " CSI0_CPD_GRC_14 ,CONSTANT 14 Parameter of Compander (GR component)"
|
|
line.long 0x5C "CSI0_CPD_GRS_0,CSI0 GR component Compander SLOPE Register 0"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " CSI0_CPD_GRS_3 ,SLOPE 3 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " CSI0_CPD_GRS_2 ,SLOPE 2 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " CSI0_CPD_GRS_1 ,SLOPE 1 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " CSI0_CPD_GRS_0 ,SLOPE 0 Parameter of Compander (GR component)"
|
|
line.long 0x60 "CSI0_CPD_GRS_1,CSI0 GR component Compander SLOPE Register 1"
|
|
hexmask.long.byte 0x60 24.--31. 1. " CSI0_CPD_GRS_7 ,SLOPE 7 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x60 16.--23. 1. " CSI0_CPD_GRS_6 ,SLOPE 6 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x60 8.--15. 1. " CSI0_CPD_GRS_5 ,SLOPE 5 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x60 0.--7. 1. " CSI0_CPD_GRS_4 ,SLOPE 4 Parameter of Compander (GR component)"
|
|
line.long 0x64 "CSI0_CPD_GRS_2,CSI0 GR component Compander SLOPE Register 2"
|
|
hexmask.long.byte 0x64 24.--31. 1. " CSI0_CPD_GRS_11 ,SLOPE 11 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x64 16.--23. 1. " CSI0_CPD_GRS_10 ,SLOPE 10 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x64 8.--15. 1. " CSI0_CPD_GRS_9 ,SLOPE 9 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x64 0.--7. 1. " CSI0_CPD_GRS_8 ,SLOPE 8 Parameter of Compander (GR component)"
|
|
line.long 0x68 "CSI0_CPD_GRS_3,CSI0 GR component Compander SLOPE Register 3"
|
|
hexmask.long.byte 0x68 24.--31. 1. " CSI0_CPD_GRS_15 ,SLOPE 15 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x68 16.--23. 1. " CSI0_CPD_GRS_14 ,SLOPE 14 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x68 8.--15. 1. " CSI0_CPD_GRS_13 ,SLOPE 13 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x68 0.--7. 1. " CSI0_CPD_GRS_12 ,SLOPE 12 Parameter of Compander (GR component)"
|
|
line.long 0x6C "CSI0_CPD_GBC_0,CSI0 GB component Compander Constants Register 0"
|
|
hexmask.long.word 0x6C 16.--24. 1. " CSI0_CPD_GBC_1 ,CONSTANT 1 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x6C 0.--8. 1. " CSI0_CPD_GBC_0 ,CONSTANT 0 Parameter of Compander (GB component)"
|
|
line.long 0x70 "CSI0_CPD_GBC_1,CSI0 GB component Compander Constants Register 1"
|
|
hexmask.long.word 0x70 16.--24. 1. " CSI0_CPD_GBC_3 ,CONSTANT 3 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x70 0.--8. 1. " CSI0_CPD_GBC_2 ,CONSTANT 2 Parameter of Compander (GB component)"
|
|
line.long 0x74 "CSI0_CPD_GBC_2,CSI0 GB component Compander Constants Register 2"
|
|
hexmask.long.word 0x74 16.--24. 1. " CSI0_CPD_GBC_5 ,CONSTANT 5 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x74 0.--8. 1. " CSI0_CPD_GBC_4 ,CONSTANT 4 Parameter of Compander (GB component)"
|
|
line.long 0x78 "CSI0_CPD_GBC_3,CSI0 GB component Compander Constants Register 3"
|
|
hexmask.long.word 0x78 16.--24. 1. " CSI0_CPD_GBC_7 ,CONSTANT 7 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x78 0.--8. 1. " CSI0_CPD_GBC_6 ,CONSTANT 6 Parameter of Compander (GB component)"
|
|
line.long 0x7C "CSI0_CPD_GBC_4,CSI0 GB component Compander Constants Register 4"
|
|
hexmask.long.word 0x7C 16.--24. 1. " CSI0_CPD_GBC_9 ,CONSTANT 9 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x7C 0.--8. 1. " CSI0_CPD_GBC_8 ,CONSTANT 8 Parameter of Compander (GB component)"
|
|
line.long 0x80 "CSI0_CPD_GBC_5,CSI0 GB component Compander Constants Register 5"
|
|
hexmask.long.word 0x80 16.--24. 1. " CSI0_CPD_GBC_11 ,CONSTANT 11 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x80 0.--8. 1. " CSI0_CPD_GBC_10 ,CONSTANT 10 Parameter of Compander (GB component)"
|
|
line.long 0x84 "CSI0_CPD_GBC_6,CSI0 GB component Compander Constants Register 6"
|
|
hexmask.long.word 0x84 16.--24. 1. " CSI0_CPD_GBC_13 ,CONSTANT 13 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x84 0.--8. 1. " CSI0_CPD_GBC_12 ,CONSTANT 12 Parameter of Compander (GB component)"
|
|
line.long 0x88 "CSI0_CPD_GBC_7,CSI0 GB component Compander Constants Register 7"
|
|
hexmask.long.word 0x88 16.--24. 1. " CSI0_CPD_GBC_15 ,CONSTANT 15 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x88 0.--8. 1. " CSI0_CPD_GBC_14 ,CONSTANT 14 Parameter of Compander (GB component)"
|
|
line.long 0x8C "CSI0_CPD_GBS_0,CSI0 GB component Compander SLOPE Register 0"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " CSI0_CPD_GBS_3 ,SLOPE 3 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " CSI0_CPD_GBS_2 ,SLOPE 2 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " CSI0_CPD_GBS_1 ,SLOPE 1 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " CSI0_CPD_GBS_0 ,SLOPE 0 Parameter of Compander (GB component)"
|
|
line.long 0x90 "CSI0_CPD_GBS_1,CSI0 GB component Compander SLOPE Register 1"
|
|
hexmask.long.byte 0x90 24.--31. 1. " CSI0_CPD_GBS_7 ,SLOPE 7 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x90 16.--23. 1. " CSI0_CPD_GBS_6 ,SLOPE 6 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x90 8.--15. 1. " CSI0_CPD_GBS_5 ,SLOPE 5 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x90 0.--7. 1. " CSI0_CPD_GBS_4 ,SLOPE 4 Parameter of Compander (GB component)"
|
|
line.long 0x94 "CSI0_CPD_GBS_2,CSI0 GB component Compander SLOPE Register 2"
|
|
hexmask.long.byte 0x94 24.--31. 1. " CSI0_CPD_GBS_11 ,SLOPE 11 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x94 16.--23. 1. " CSI0_CPD_GBS_10 ,SLOPE 10 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x94 8.--15. 1. " CSI0_CPD_GBS_9 ,SLOPE 9 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x94 0.--7. 1. " CSI0_CPD_GBS_8 ,SLOPE 8 Parameter of Compander (GB component)"
|
|
line.long 0x98 "CSI0_CPD_GBS_3,CSI0 GB component Compander SLOPE Register 3"
|
|
hexmask.long.byte 0x98 24.--31. 1. " CSI0_CPD_GBS_15 ,SLOPE 15 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x98 16.--23. 1. " CSI0_CPD_GBS_14 ,SLOPE 14 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x98 8.--15. 1. " CSI0_CPD_GBS_13 ,SLOPE 13 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x98 0.--7. 1. " CSI0_CPD_GBS_12 ,SLOPE 12 Parameter of Compander (GB component)"
|
|
line.long 0x9C "CSI0_CPD_BC_0,CSI0 Blue component Compander Constants Register 0"
|
|
hexmask.long.word 0x9C 16.--24. 1. " CSI0_CPD_BC_1 ,CONSTANT 1 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0x9C 0.--8. 1. " CSI0_CPD_BC_0 ,CONSTANT 0 Parameter of Compander (Blue component)"
|
|
line.long 0xA0 "CSI0_CPD_BC_1,CSI0 Blue component Compander Constants Register 1"
|
|
hexmask.long.word 0xA0 16.--24. 1. " CSI0_CPD_BC_3 ,CONSTANT 3 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xA0 0.--8. 1. " CSI0_CPD_BC_2 ,CONSTANT 2 Parameter of Compander (Blue component)"
|
|
line.long 0xA4 "CSI0_CPD_BC_2,CSI0 Blue component Compander Constants Register 2"
|
|
hexmask.long.word 0xA4 16.--24. 1. " CSI0_CPD_BC_5 ,CONSTANT 5 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xA4 0.--8. 1. " CSI0_CPD_BC_4 ,CONSTANT 4 Parameter of Compander (Blue component)"
|
|
line.long 0xA8 "CSI0_CPD_BC_3,CSI0 Blue component Compander Constants Register 3"
|
|
hexmask.long.word 0xA8 16.--24. 1. " CSI0_CPD_BC_7 ,CONSTANT 7 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xA8 0.--8. 1. " CSI0_CPD_BC_6 ,CONSTANT 6 Parameter of Compander (Blue component)"
|
|
line.long 0xAC "CSI0_CPD_BC_4,CSI0 Blue component Compander Constants Register 4"
|
|
hexmask.long.word 0xAC 16.--24. 1. " CSI0_CPD_BC_9 ,CONSTANT 9 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xAC 0.--8. 1. " CSI0_CPD_BC_8 ,CONSTANT 8 Parameter of Compander (Blue component)"
|
|
line.long 0xB0 "CSI0_CPD_BC_5,CSI0 Blue component Compander Constants Register 5"
|
|
hexmask.long.word 0xB0 16.--24. 1. " CSI0_CPD_BC_11 ,CONSTANT 11 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xB0 0.--8. 1. " CSI0_CPD_BC_10 ,CONSTANT 10 Parameter of Compander (Blue component)"
|
|
line.long 0xB4 "CSI0_CPD_BC_6,CSI0 Blue component Compander Constants Register 6"
|
|
hexmask.long.word 0xB4 16.--24. 1. " CSI0_CPD_BC_13 ,CONSTANT 13 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xB4 0.--8. 1. " CSI0_CPD_BC_12 ,CONSTANT 12 Parameter of Compander (Blue component)"
|
|
line.long 0xB8 "CSI0_CPD_BC_7,CSI0 Blue component Compander Constants Register 7"
|
|
hexmask.long.word 0xB8 16.--24. 1. " CSI0_CPD_BC_15 ,CONSTANT 15 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xB8 0.--8. 1. " CSI0_CPD_BC_14 ,CONSTANT 14 Parameter of Compander (Blue component)"
|
|
line.long 0xBC "CSI0_CPD_BS_0,CSI0 Blue component Compander SLOPE Register 0"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " CSI0_CPD_BS_3 ,SLOPE 3 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " CSI0_CPD_BS_2 ,SLOPE 2 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " CSI0_CPD_BS_1 ,SLOPE 1 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " CSI0_CPD_BS_0 ,SLOPE 0 Parameter of Compander (Blue component)"
|
|
line.long 0xC0 "CSI0_CPD_BS_1,CSI0 Blue component Compander SLOPE Register 1"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " CSI0_CPD_BS_7 ,SLOPE 7 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " CSI0_CPD_BS_6 ,SLOPE 6 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " CSI0_CPD_BS_5 ,SLOPE 5 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " CSI0_CPD_BS_4 ,SLOPE 4 Parameter of Compander (Blue component)"
|
|
line.long 0xC4 "CSI0_CPD_BS_2,CSI0 Blue component Compander SLOPE Register 2"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " CSI0_CPD_BS_11 ,SLOPE 11 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " CSI0_CPD_BS_10 ,SLOPE 10 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " CSI0_CPD_BS_9 ,SLOPE 9 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " CSI0_CPD_BS_8 ,SLOPE 8 Parameter of Compander (Blue component)"
|
|
line.long 0xC8 "CSI0_CPD_BS_3,CSI0 Blue component Compander SLOPE Register 3"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " CSI0_CPD_BS_15 ,SLOPE 15 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " CSI0_CPD_BS_14 ,SLOPE 14 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " CSI0_CPD_BS_13 ,SLOPE 13 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " CSI0_CPD_BS_12 ,SLOPE 12 Parameter of Compander (Blue component)"
|
|
line.long 0xcc "CSI0_CPD_OFFSET1,CSI0 Compander Offset Register 1"
|
|
hexmask.long.word 0xcc 20.--29. 1. " CSI0_CPD_B_OFFSET ,CSI0 Blue component offset"
|
|
hexmask.long.word 0xcc 10.--19. 1. " CSI0_GB_OFFSET ,CSI0 Green Blue component offset"
|
|
hexmask.long.word 0xcc 0.--9. 1. " CSI0_GR_OFFSET ,CSI0 Green Red component offset"
|
|
line.long 0xd0 "CSI0_CPD_OFFSET2,CSI0 Compander Offset Register 2"
|
|
hexmask.long.word 0xd0 0.--9. 1. " CSI0_CPD_R_OFFSET ,CSI0 Red component offset"
|
|
else
|
|
sif (cpuis("IMX6*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CSI0_DI,CSI0 Data Identifier Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CSI0_MIPI_DI3 ,Holds the Data Identifier #3 handled by the CSI"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSI0_MIPI_DI2 ,Holds the Data Identifier #2 handled by the CSI"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSI0_MIPI_DI1 ,Holds the Data Identifier #1 handled by the CSI"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSI0_MIPI_DI0 ,Holds the Data Identifier #0 handled by the CSI"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CSI0_SKIP,CSI0 SKIP Register"
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 8.--9. " CSI0_ID_2_SKIP ,Data from the CSI0 to the SMFC has an ID associated with it" "00,01,10,11"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3.--7. " CSI0_SKIP_SMFC ,Skipping pattern of the frames send to the SMFC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " CSI0_MAX_RATIO_SKIP_SMFC ,CSI0 Maximum Ratio Skip for SMFC" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSI1 registers"
|
|
base ad:0x5e038000
|
|
width 20.
|
|
group.long 0x00++0x1b
|
|
line.long 0x00 "CSI1_SENS_CONF,CSI1 Sensor Configuration Register"
|
|
bitfld.long 0x00 31. " CSI1_DATA_EN_POL ,Invert IPP_IND_SENSB_DATA_EN input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 29. " CSI1_FORCE_EOF ,Force End of frame" "No effect,Forced"
|
|
bitfld.long 0x00 28. " CSI1_JPEG_MODE ,JPEG Mode" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CSI1_JPEG8_EN ,JPEG8 enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " CSI1_DATA_DEST ,Destination of the data coming from the CSI" ",IC,IDMAC via SMFC,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSI1_DIV_RATIO ,Clock division ratio minus 1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CSI1_EXT_VSYNC ,External VSYNC enable" "Internal,External"
|
|
bitfld.long 0x00 11.--14. " CSI1_DATA_WIDTH ,Number of bits per color" ",8,,10,,,,,,16,?..."
|
|
bitfld.long 0x00 8.--10. " CSI1_SENS_DATA_FORMAT ,Data format from the sensor" "Full RGB or YUV444,YUV422 (YUYV...),YUV422 (UYVY...),Bayer or Generic,RGB565,RGB555,RGB444,JPEG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSI1_PACK_TIGHT ,CSI1 Pack Tight" "Not tight,Tight"
|
|
bitfld.long 0x00 4.--6. " CSI1_SENS_PRTCL ,Sensor protocol" "Gated clock mode,Non-gated clock mode,CCIR progressive mode (BT.656),CCIR interlaced mode (BT.656),CCIR progressive (BT.1120 DDR),CCIR progressive (BT.1120 SDR),CCIR interlaced mode (BT.1120 DDR),CCIR interlaced mode (BT.1120 SDR)"
|
|
bitfld.long 0x00 3. " CSI1_SENS_PIX_CLK_POL ,Invert pixel clock input" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSI1_DATA_POL ,Invert data input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 1. " CSI1_HSYNC_POL ,Invert IPP_IND_SENSB_HSYNC input" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " CSI1_VSYNC_POL ,Invert IPP_IND_SENSB_VSYNC input" "Not inverted,Inverted"
|
|
line.long 0x04 "CSI1_SENS_FRM_SIZE,CSI1 Sense Frame Size Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " CSI1_SENS_FRM_HEIGHT ,Sensor frame height minus 1"
|
|
hexmask.long.word 0x04 0.--12. 1. " CSI1_SENS_FRM_WIDTH ,Sensor frame width minus 1"
|
|
line.long 0x08 "CSI1_ACT_FRM_SIZE,CSI1 Actual Frame Size Register"
|
|
hexmask.long.word 0x08 16.--27. 1. " CSI1_ACT_FRM_HEIGHT ,Sensor frame height minus 1"
|
|
hexmask.long.word 0x08 0.--12. 1. " CSI1_ACT_FRM_WIDTH ,Sensor frame width minus 1"
|
|
line.long 0x0c "CSI1_OUT_FRM_CTRL,CSI1 Output Control Register"
|
|
bitfld.long 0x0c 31. " CSI1_HORZ_DWNS ,Enable horizontal downsizing" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " CSI1_VERT_DWNS ,Enable vertical downsizing" "Disabled,Enabled"
|
|
hexmask.long.word 0x0c 16.--28. 1. " CSI1_HSC ,Number of columns to skip"
|
|
textline " "
|
|
hexmask.long.word 0x0c 0.--11. 1. " CSI1_VSC ,Number of rows to skip"
|
|
line.long 0x10 "CSI1_TST_CTRL,CSI1 Test Control Register"
|
|
bitfld.long 0x10 24. " CSI1_TEST_GEN_MODE ,Test generator mode" "Inactive,Active"
|
|
hexmask.long.byte 0x10 16.--23. 1. " CSI1_PG_B_VALUE ,Pattern generator B value"
|
|
hexmask.long.byte 0x10 8.--15. 1. " CSI1_PG_G_VALUE ,Pattern generator G value"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " CSI1_PG_R_VALUE ,Pattern generator R value"
|
|
line.long 0x14 "CSI1_CCIR_CODE_1,CSI1 Output Control Register 1"
|
|
bitfld.long 0x14 24. " CSI1_CCIR_ERR_DET_EN ,Enable error detection and correction for CCIR interlaced mode with protection bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 19.--21. " CSI1_STRT_FLD0_ACTV ,Start of field 0 active line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16.--18. " CSI1_END_FLD0_ACTV ,End of field 0 active line command (I)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 9.--11. " CSI1_STRT_FLD0_BLNK_2ND ,Start of field 0 second blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 6.--8. " CSI1_END_FLD0_BLNK_2ND ,End of field 0 second blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. " CSI1_STRT_FLD0_BLNK_1ST ,Start of field 0 first blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " CSI1_END_FLD0_BLNK_1ST ,End of field 0 first blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CSI1_CCIR_CODE_2,CSI1 CCIR Code Register 2"
|
|
bitfld.long 0x18 19.--21. " CSI1_STRT_FLD1_ACTV ,Start of field 1 active line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 16.--18. " CSI1_END_FLD1_ACTV ,End of field 1 active line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 9.--11. " CSI1_STRT_FLD1_BLNK_2ND ,Start of field 1 second blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 6.--8. " CSI1_END_FLD1_BLNK_2ND ,End of field 1 second blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 3.--5. " CSI1_STRT_FLD1_BLNK_1ST ,Start of field 1 first blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 0.--2. " CSI1_END_FLD1_BLNK_1ST ,End of field 1 first blanking line command (I)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
if (((per.l(ad:0x5e038000))&0x70)==0x20)||(((per.l(ad:0x5e038000))&0x70)==0x30)
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "CSI1_CCIR_CODE_3,CSI1 CCIR Code Register 3"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CSI1_CCIR_PRECOM ,CCIR pre command (3X8bit)"
|
|
elif (((per.l(ad:0x5e038000))&0x70)==0x40)||(((per.l(ad:0x5e038000))&0x70)==0x50)||(((per.l(ad:0x5e038000))&0x70)==0x60)||(((per.l(ad:0x5e038000))&0x70)==0x70)
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "CSI1_CCIR_CODE_3,CSI1 CCIR Code Register 3"
|
|
hexmask.long 0x00 0.--29. 1. " CSI1_CCIR_PRECOM ,CCIR pre command (3X10bit)"
|
|
else
|
|
hgroup.long 0x1c++0x3
|
|
hide.long 0x00 "CSI1_CCIR_CODE_3,CSI1 CCIR Code Register 3"
|
|
endif
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
group.long 0x20++0xd3
|
|
line.long 0x00 "CSI1_DI,CSI1 Data Identifier Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CSI1_MIPI_DI3 ,Holds the Data Identifier #3 handled by the CSI"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSI1_MIPI_DI2 ,Holds the Data Identifier #2 handled by the CSI"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSI1_MIPI_DI1 ,Holds the Data Identifier #1 handled by the CSI"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSI1_MIPI_DI0 ,Holds the Data Identifier #0 handled by the CSI"
|
|
line.long 0x04 "CSI1_SKIP,CSI1 SKIP Register"
|
|
bitfld.long 0x04 19.--23. " CSI1_SKIP_ISP ,Skipping pattern of the frames send to the ISP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--18. " CSI1_MAX_RATIO_SKIP_ISP ,CSI1 Maximum Ratio Skip for ISP" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 3.--7. " CSI1_SKIP_SMFC ,Skipping pattern of the frames send to the SMFC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--2. " CSI1_MAX_RATIO_SKIP_SMFC ,CSI1 Maximum Ratio Skip for SMFC" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "CSI1_CPD_CTRL,CSI1 Compander Control Register"
|
|
bitfld.long 0x08 2.--4. " CSI1_CPD ,Enable the compander in the path to different destination" "ISP,IC,IDMAC via SMFC,?..."
|
|
bitfld.long 0x08 1. " CSI1_RED_ROW_BEGIN ,Color of first row in the frame" "GBGB,GRGR"
|
|
bitfld.long 0x08 0. " CSI1_GREEN_P_BEGIN ,Color of first component in the frame" "Blue or red,Green"
|
|
line.long 0xC "CSI1_CPD_RC_0,CSI1 Red component Compander Constants Register 0"
|
|
hexmask.long.word 0xC 16.--25. 1. " CSI1_CPD_RC_1 ,CONSTANT 1 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0xC 0.--9. 1. " CSI1_CPD_RC_0 ,CONSTANT 0 Parameter of Compander (Red component)"
|
|
line.long 0x10 "CSI1_CPD_RC_1,CSI1 Red component Compander Constants Register 1"
|
|
hexmask.long.word 0x10 16.--25. 1. " CSI1_CPD_RC_3 ,CONSTANT 3 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x10 0.--9. 1. " CSI1_CPD_RC_2 ,CONSTANT 2 Parameter of Compander (Red component)"
|
|
line.long 0x14 "CSI1_CPD_RC_2,CSI1 Red component Compander Constants Register 2"
|
|
hexmask.long.word 0x14 16.--25. 1. " CSI1_CPD_RC_5 ,CONSTANT 5 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x14 0.--9. 1. " CSI1_CPD_RC_4 ,CONSTANT 4 Parameter of Compander (Red component)"
|
|
line.long 0x18 "CSI1_CPD_RC_3,CSI1 Red component Compander Constants Register 3"
|
|
hexmask.long.word 0x18 16.--25. 1. " CSI1_CPD_RC_7 ,CONSTANT 7 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x18 0.--9. 1. " CSI1_CPD_RC_6 ,CONSTANT 6 Parameter of Compander (Red component)"
|
|
line.long 0x1C "CSI1_CPD_RC_4,CSI1 Red component Compander Constants Register 4"
|
|
hexmask.long.word 0x1C 16.--25. 1. " CSI1_CPD_RC_9 ,CONSTANT 9 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x1C 0.--9. 1. " CSI1_CPD_RC_8 ,CONSTANT 8 Parameter of Compander (Red component)"
|
|
line.long 0x20 "CSI1_CPD_RC_5,CSI1 Red component Compander Constants Register 5"
|
|
hexmask.long.word 0x20 16.--25. 1. " CSI1_CPD_RC_11 ,CONSTANT 11 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x20 0.--9. 1. " CSI1_CPD_RC_10 ,CONSTANT 10 Parameter of Compander (Red component)"
|
|
line.long 0x24 "CSI1_CPD_RC_6,CSI1 Red component Compander Constants Register 6"
|
|
hexmask.long.word 0x24 16.--25. 1. " CSI1_CPD_RC_13 ,CONSTANT 13 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x24 0.--9. 1. " CSI1_CPD_RC_12 ,CONSTANT 12 Parameter of Compander (Red component)"
|
|
line.long 0x28 "CSI1_CPD_RC_7,CSI1 Red component Compander Constants Register 7"
|
|
hexmask.long.word 0x28 16.--25. 1. " CSI1_CPD_RC_15 ,CONSTANT 15 Parameter of Compander (Red component)"
|
|
hexmask.long.word 0x28 0.--9. 1. " CSI1_CPD_RC_14 ,CONSTANT 14 Parameter of Compander (Red component)"
|
|
line.long 0x2C "CSI1_CPD_RS_0,CSI1 Red component Compander SLOPE Register 0"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " CSI1_CPD_RS_3 ,SLOPE 3 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " CSI1_CPD_RS_2 ,SLOPE 2 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " CSI1_CPD_RS_1 ,SLOPE 1 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " CSI1_CPD_RS_0 ,SLOPE 0 Parameter of Compander (Red component)"
|
|
line.long 0x30 "CSI1_CPD_RS_1,CSI1 Red component Compander SLOPE Register 1"
|
|
hexmask.long.byte 0x30 24.--31. 1. " CSI1_CPD_RS_7 ,SLOPE 7 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x30 16.--23. 1. " CSI1_CPD_RS_6 ,SLOPE 6 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x30 8.--15. 1. " CSI1_CPD_RS_5 ,SLOPE 5 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x30 0.--7. 1. " CSI1_CPD_RS_4 ,SLOPE 4 Parameter of Compander (Red component)"
|
|
line.long 0x34 "CSI1_CPD_RS_2,CSI1 Red component Compander SLOPE Register 2"
|
|
hexmask.long.byte 0x34 24.--31. 1. " CSI1_CPD_RS_11 ,SLOPE 11 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x34 16.--23. 1. " CSI1_CPD_RS_10 ,SLOPE 10 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x34 8.--15. 1. " CSI1_CPD_RS_9 ,SLOPE 9 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x34 0.--7. 1. " CSI1_CPD_RS_8 ,SLOPE 8 Parameter of Compander (Red component)"
|
|
line.long 0x38 "CSI1_CPD_RS_3,CSI1 Red component Compander SLOPE Register 3"
|
|
hexmask.long.byte 0x38 24.--31. 1. " CSI1_CPD_RS_15 ,SLOPE 15 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x38 16.--23. 1. " CSI1_CPD_RS_14 ,SLOPE 14 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x38 8.--15. 1. " CSI1_CPD_RS_13 ,SLOPE 13 Parameter of Compander (Red component)"
|
|
hexmask.long.byte 0x38 0.--7. 1. " CSI1_CPD_RS_12 ,SLOPE 12 Parameter of Compander (Red component)"
|
|
line.long 0x3C "CSI1_CPD_GRC_0,CSI1 GR component Compander Constants Register 0"
|
|
hexmask.long.word 0x3C 16.--24. 1. " CSI1_CPD_GRC_1 ,CONSTANT 1 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x3C 0.--8. 1. " CSI1_CPD_GRC_0 ,CONSTANT 0 Parameter of Compander (GR component)"
|
|
line.long 0x40 "CSI1_CPD_GRC_1,CSI1 GR component Compander Constants Register 1"
|
|
hexmask.long.word 0x40 16.--24. 1. " CSI1_CPD_GRC_3 ,CONSTANT 3 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x40 0.--8. 1. " CSI1_CPD_GRC_2 ,CONSTANT 2 Parameter of Compander (GR component)"
|
|
line.long 0x44 "CSI1_CPD_GRC_2,CSI1 GR component Compander Constants Register 2"
|
|
hexmask.long.word 0x44 16.--24. 1. " CSI1_CPD_GRC_5 ,CONSTANT 5 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x44 0.--8. 1. " CSI1_CPD_GRC_4 ,CONSTANT 4 Parameter of Compander (GR component)"
|
|
line.long 0x48 "CSI1_CPD_GRC_3,CSI1 GR component Compander Constants Register 3"
|
|
hexmask.long.word 0x48 16.--24. 1. " CSI1_CPD_GRC_7 ,CONSTANT 7 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x48 0.--8. 1. " CSI1_CPD_GRC_6 ,CONSTANT 6 Parameter of Compander (GR component)"
|
|
line.long 0x4C "CSI1_CPD_GRC_4,CSI1 GR component Compander Constants Register 4"
|
|
hexmask.long.word 0x4C 16.--24. 1. " CSI1_CPD_GRC_9 ,CONSTANT 9 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x4C 0.--8. 1. " CSI1_CPD_GRC_8 ,CONSTANT 8 Parameter of Compander (GR component)"
|
|
line.long 0x50 "CSI1_CPD_GRC_5,CSI1 GR component Compander Constants Register 5"
|
|
hexmask.long.word 0x50 16.--24. 1. " CSI1_CPD_GRC_11 ,CONSTANT 11 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x50 0.--8. 1. " CSI1_CPD_GRC_10 ,CONSTANT 10 Parameter of Compander (GR component)"
|
|
line.long 0x54 "CSI1_CPD_GRC_6,CSI1 GR component Compander Constants Register 6"
|
|
hexmask.long.word 0x54 16.--24. 1. " CSI1_CPD_GRC_13 ,CONSTANT 13 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x54 0.--8. 1. " CSI1_CPD_GRC_12 ,CONSTANT 12 Parameter of Compander (GR component)"
|
|
line.long 0x58 "CSI1_CPD_GRC_7,CSI1 GR component Compander Constants Register 7"
|
|
hexmask.long.word 0x58 16.--24. 1. " CSI1_CPD_GRC_15 ,CONSTANT 15 Parameter of Compander (GR component)"
|
|
hexmask.long.word 0x58 0.--8. 1. " CSI1_CPD_GRC_14 ,CONSTANT 14 Parameter of Compander (GR component)"
|
|
line.long 0x5C "CSI1_CPD_GRS_0,CSI1 GR component Compander SLOPE Register 0"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " CSI1_CPD_GRS_3 ,SLOPE 3 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " CSI1_CPD_GRS_2 ,SLOPE 2 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " CSI1_CPD_GRS_1 ,SLOPE 1 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " CSI1_CPD_GRS_0 ,SLOPE 0 Parameter of Compander (GR component)"
|
|
line.long 0x60 "CSI1_CPD_GRS_1,CSI1 GR component Compander SLOPE Register 1"
|
|
hexmask.long.byte 0x60 24.--31. 1. " CSI1_CPD_GRS_7 ,SLOPE 7 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x60 16.--23. 1. " CSI1_CPD_GRS_6 ,SLOPE 6 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x60 8.--15. 1. " CSI1_CPD_GRS_5 ,SLOPE 5 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x60 0.--7. 1. " CSI1_CPD_GRS_4 ,SLOPE 4 Parameter of Compander (GR component)"
|
|
line.long 0x64 "CSI1_CPD_GRS_2,CSI1 GR component Compander SLOPE Register 2"
|
|
hexmask.long.byte 0x64 24.--31. 1. " CSI1_CPD_GRS_11 ,SLOPE 11 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x64 16.--23. 1. " CSI1_CPD_GRS_10 ,SLOPE 10 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x64 8.--15. 1. " CSI1_CPD_GRS_9 ,SLOPE 9 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x64 0.--7. 1. " CSI1_CPD_GRS_8 ,SLOPE 8 Parameter of Compander (GR component)"
|
|
line.long 0x68 "CSI1_CPD_GRS_3,CSI1 GR component Compander SLOPE Register 3"
|
|
hexmask.long.byte 0x68 24.--31. 1. " CSI1_CPD_GRS_15 ,SLOPE 15 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x68 16.--23. 1. " CSI1_CPD_GRS_14 ,SLOPE 14 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x68 8.--15. 1. " CSI1_CPD_GRS_13 ,SLOPE 13 Parameter of Compander (GR component)"
|
|
hexmask.long.byte 0x68 0.--7. 1. " CSI1_CPD_GRS_12 ,SLOPE 12 Parameter of Compander (GR component)"
|
|
line.long 0x6C "CSI1_CPD_GBC_0,CSI1 GB component Compander Constants Register 0"
|
|
hexmask.long.word 0x6C 16.--24. 1. " CSI1_CPD_GBC_1 ,CONSTANT 1 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x6C 0.--8. 1. " CSI1_CPD_GBC_0 ,CONSTANT 0 Parameter of Compander (GB component)"
|
|
line.long 0x70 "CSI1_CPD_GBC_1,CSI1 GB component Compander Constants Register 1"
|
|
hexmask.long.word 0x70 16.--24. 1. " CSI1_CPD_GBC_3 ,CONSTANT 3 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x70 0.--8. 1. " CSI1_CPD_GBC_2 ,CONSTANT 2 Parameter of Compander (GB component)"
|
|
line.long 0x74 "CSI1_CPD_GBC_2,CSI1 GB component Compander Constants Register 2"
|
|
hexmask.long.word 0x74 16.--24. 1. " CSI1_CPD_GBC_5 ,CONSTANT 5 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x74 0.--8. 1. " CSI1_CPD_GBC_4 ,CONSTANT 4 Parameter of Compander (GB component)"
|
|
line.long 0x78 "CSI1_CPD_GBC_3,CSI1 GB component Compander Constants Register 3"
|
|
hexmask.long.word 0x78 16.--24. 1. " CSI1_CPD_GBC_7 ,CONSTANT 7 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x78 0.--8. 1. " CSI1_CPD_GBC_6 ,CONSTANT 6 Parameter of Compander (GB component)"
|
|
line.long 0x7C "CSI1_CPD_GBC_4,CSI1 GB component Compander Constants Register 4"
|
|
hexmask.long.word 0x7C 16.--24. 1. " CSI1_CPD_GBC_9 ,CONSTANT 9 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x7C 0.--8. 1. " CSI1_CPD_GBC_8 ,CONSTANT 8 Parameter of Compander (GB component)"
|
|
line.long 0x80 "CSI1_CPD_GBC_5,CSI1 GB component Compander Constants Register 5"
|
|
hexmask.long.word 0x80 16.--24. 1. " CSI1_CPD_GBC_11 ,CONSTANT 11 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x80 0.--8. 1. " CSI1_CPD_GBC_10 ,CONSTANT 10 Parameter of Compander (GB component)"
|
|
line.long 0x84 "CSI1_CPD_GBC_6,CSI1 GB component Compander Constants Register 6"
|
|
hexmask.long.word 0x84 16.--24. 1. " CSI1_CPD_GBC_13 ,CONSTANT 13 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x84 0.--8. 1. " CSI1_CPD_GBC_12 ,CONSTANT 12 Parameter of Compander (GB component)"
|
|
line.long 0x88 "CSI1_CPD_GBC_7,CSI1 GB component Compander Constants Register 7"
|
|
hexmask.long.word 0x88 16.--24. 1. " CSI1_CPD_GBC_15 ,CONSTANT 15 Parameter of Compander (GB component)"
|
|
hexmask.long.word 0x88 0.--8. 1. " CSI1_CPD_GBC_14 ,CONSTANT 14 Parameter of Compander (GB component)"
|
|
line.long 0x8C "CSI1_CPD_GBS_0,CSI1 GB component Compander SLOPE Register 0"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " CSI1_CPD_GBS_3 ,SLOPE 3 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " CSI1_CPD_GBS_2 ,SLOPE 2 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " CSI1_CPD_GBS_1 ,SLOPE 1 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " CSI1_CPD_GBS_0 ,SLOPE 0 Parameter of Compander (GB component)"
|
|
line.long 0x90 "CSI1_CPD_GBS_1,CSI1 GB component Compander SLOPE Register 1"
|
|
hexmask.long.byte 0x90 24.--31. 1. " CSI1_CPD_GBS_7 ,SLOPE 7 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x90 16.--23. 1. " CSI1_CPD_GBS_6 ,SLOPE 6 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x90 8.--15. 1. " CSI1_CPD_GBS_5 ,SLOPE 5 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x90 0.--7. 1. " CSI1_CPD_GBS_4 ,SLOPE 4 Parameter of Compander (GB component)"
|
|
line.long 0x94 "CSI1_CPD_GBS_2,CSI1 GB component Compander SLOPE Register 2"
|
|
hexmask.long.byte 0x94 24.--31. 1. " CSI1_CPD_GBS_11 ,SLOPE 11 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x94 16.--23. 1. " CSI1_CPD_GBS_10 ,SLOPE 10 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x94 8.--15. 1. " CSI1_CPD_GBS_9 ,SLOPE 9 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x94 0.--7. 1. " CSI1_CPD_GBS_8 ,SLOPE 8 Parameter of Compander (GB component)"
|
|
line.long 0x98 "CSI1_CPD_GBS_3,CSI1 GB component Compander SLOPE Register 3"
|
|
hexmask.long.byte 0x98 24.--31. 1. " CSI1_CPD_GBS_15 ,SLOPE 15 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x98 16.--23. 1. " CSI1_CPD_GBS_14 ,SLOPE 14 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x98 8.--15. 1. " CSI1_CPD_GBS_13 ,SLOPE 13 Parameter of Compander (GB component)"
|
|
hexmask.long.byte 0x98 0.--7. 1. " CSI1_CPD_GBS_12 ,SLOPE 12 Parameter of Compander (GB component)"
|
|
line.long 0x9C "CSI1_CPD_BC_0,CSI1 Blue component Compander Constants Register 0"
|
|
hexmask.long.word 0x9C 16.--24. 1. " CSI1_CPD_BC_1 ,CONSTANT 1 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0x9C 0.--8. 1. " CSI1_CPD_BC_0 ,CONSTANT 0 Parameter of Compander (Blue component)"
|
|
line.long 0xA0 "CSI1_CPD_BC_1,CSI1 Blue component Compander Constants Register 1"
|
|
hexmask.long.word 0xA0 16.--24. 1. " CSI1_CPD_BC_3 ,CONSTANT 3 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xA0 0.--8. 1. " CSI1_CPD_BC_2 ,CONSTANT 2 Parameter of Compander (Blue component)"
|
|
line.long 0xA4 "CSI1_CPD_BC_2,CSI1 Blue component Compander Constants Register 2"
|
|
hexmask.long.word 0xA4 16.--24. 1. " CSI1_CPD_BC_5 ,CONSTANT 5 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xA4 0.--8. 1. " CSI1_CPD_BC_4 ,CONSTANT 4 Parameter of Compander (Blue component)"
|
|
line.long 0xA8 "CSI1_CPD_BC_3,CSI1 Blue component Compander Constants Register 3"
|
|
hexmask.long.word 0xA8 16.--24. 1. " CSI1_CPD_BC_7 ,CONSTANT 7 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xA8 0.--8. 1. " CSI1_CPD_BC_6 ,CONSTANT 6 Parameter of Compander (Blue component)"
|
|
line.long 0xAC "CSI1_CPD_BC_4,CSI1 Blue component Compander Constants Register 4"
|
|
hexmask.long.word 0xAC 16.--24. 1. " CSI1_CPD_BC_9 ,CONSTANT 9 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xAC 0.--8. 1. " CSI1_CPD_BC_8 ,CONSTANT 8 Parameter of Compander (Blue component)"
|
|
line.long 0xB0 "CSI1_CPD_BC_5,CSI1 Blue component Compander Constants Register 5"
|
|
hexmask.long.word 0xB0 16.--24. 1. " CSI1_CPD_BC_11 ,CONSTANT 11 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xB0 0.--8. 1. " CSI1_CPD_BC_10 ,CONSTANT 10 Parameter of Compander (Blue component)"
|
|
line.long 0xB4 "CSI1_CPD_BC_6,CSI1 Blue component Compander Constants Register 6"
|
|
hexmask.long.word 0xB4 16.--24. 1. " CSI1_CPD_BC_13 ,CONSTANT 13 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xB4 0.--8. 1. " CSI1_CPD_BC_12 ,CONSTANT 12 Parameter of Compander (Blue component)"
|
|
line.long 0xB8 "CSI1_CPD_BC_7,CSI1 Blue component Compander Constants Register 7"
|
|
hexmask.long.word 0xB8 16.--24. 1. " CSI1_CPD_BC_15 ,CONSTANT 15 Parameter of Compander (Blue component)"
|
|
hexmask.long.word 0xB8 0.--8. 1. " CSI1_CPD_BC_14 ,CONSTANT 14 Parameter of Compander (Blue component)"
|
|
line.long 0xBC "CSI1_CPD_BS_0,CSI1 Blue component Compander SLOPE Register 0"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " CSI1_CPD_BS_3 ,SLOPE 3 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " CSI1_CPD_BS_2 ,SLOPE 2 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " CSI1_CPD_BS_1 ,SLOPE 1 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " CSI1_CPD_BS_0 ,SLOPE 0 Parameter of Compander (Blue component)"
|
|
line.long 0xC0 "CSI1_CPD_BS_1,CSI1 Blue component Compander SLOPE Register 1"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " CSI1_CPD_BS_7 ,SLOPE 7 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " CSI1_CPD_BS_6 ,SLOPE 6 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " CSI1_CPD_BS_5 ,SLOPE 5 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " CSI1_CPD_BS_4 ,SLOPE 4 Parameter of Compander (Blue component)"
|
|
line.long 0xC4 "CSI1_CPD_BS_2,CSI1 Blue component Compander SLOPE Register 2"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " CSI1_CPD_BS_11 ,SLOPE 11 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " CSI1_CPD_BS_10 ,SLOPE 10 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " CSI1_CPD_BS_9 ,SLOPE 9 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " CSI1_CPD_BS_8 ,SLOPE 8 Parameter of Compander (Blue component)"
|
|
line.long 0xC8 "CSI1_CPD_BS_3,CSI1 Blue component Compander SLOPE Register 3"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " CSI1_CPD_BS_15 ,SLOPE 15 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " CSI1_CPD_BS_14 ,SLOPE 14 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " CSI1_CPD_BS_13 ,SLOPE 13 Parameter of Compander (Blue component)"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " CSI1_CPD_BS_12 ,SLOPE 12 Parameter of Compander (Blue component)"
|
|
line.long 0xcc "CSI1_CPD_OFFSET1,CSI1 Compander Offset Register 1"
|
|
hexmask.long.word 0xcc 20.--29. 1. " CSI1_CPD_B_OFFSET ,CSI1 Blue component offset"
|
|
hexmask.long.word 0xcc 10.--19. 1. " CSI1_GB_OFFSET ,CSI1 Green Blue component offset"
|
|
hexmask.long.word 0xcc 0.--9. 1. " CSI1_GR_OFFSET ,CSI1 Green Red component offset"
|
|
line.long 0xd0 "CSI1_CPD_OFFSET2,CSI1 Compander Offset Register 2"
|
|
hexmask.long.word 0xd0 0.--9. 1. " CSI1_CPD_R_OFFSET ,CSI1 Red component offset"
|
|
else
|
|
sif (cpuis("IMX6*"))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CSI1_DI,CSI1 Data Identifier Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CSI1_MIPI_DI3 ,Holds the Data Identifier #3 handled by the CSI"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSI1_MIPI_DI2 ,Holds the Data Identifier #2 handled by the CSI"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CSI1_MIPI_DI1 ,Holds the Data Identifier #1 handled by the CSI"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSI1_MIPI_DI0 ,Holds the Data Identifier #0 handled by the CSI"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CSI1_SKIP,CSI1 SKIP Register"
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 8.--9. " CSI1_ID_2_SKIP ,Data from the CSI1 to the SMFC has an ID associated with it" "00,01,10,11"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3.--7. " CSI1_SKIP_SMFC ,Skipping pattern of the frames send to the SMFC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--2. " CSI1_MAX_RATIO_SKIP_SMFC ,CSI1 Maximum Ratio Skip for SMFC" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DI0 registers"
|
|
base ad:0x5e040000
|
|
width 17.
|
|
group.long 0x00++0x57
|
|
line.long 0x00 "DI0_GENERAL,DI0 General Register"
|
|
bitfld.long 0x00 31. " DI0_PIN8_PIN15_SEL ,Route PIN8 over PIN15" "Not routed,Routed"
|
|
bitfld.long 0x00 28.--30. " DI0_DISP_Y_SEL ,DI0 Display Vertical coordinate (Y) select" "Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Counter 6,Counter 7,Counter 8"
|
|
bitfld.long 0x00 24.--27. " DI0_CLOCK_STOP_MODE ,DI clock stop mode" "Next edge,Next event of Cnt. 1,Next event of Cnt. 2,Next event of Cnt. 3,Next event of Cnt. 4,Next event of Cnt. 5,Next event of Cnt. 6,Next event of Cnt. 7,Next event of Cnt. 8,Next event of Cnt. 9,,,EOL/now,EOF/now,EOL/next line,EOF/next frame"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DI0_DISP_CLOCK_INIT ,Display clock's initial mode" "Stopped,Running"
|
|
bitfld.long 0x00 22. " DI0_MASK_SEL ,DI0 Mask select" "Counter 2,Extracted MASK data"
|
|
bitfld.long 0x00 21. " DI0_VSYNC_EXT ,DI0 External VSYNC" "Internally,External"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DI0_CLK_EXT ,DI0 External Clock" "Internally,External"
|
|
bitfld.long 0x00 18.--19. " DI0_WATCHDOG_MODE ,DI0 watchdog mode" "4,16,64,128"
|
|
bitfld.long 0x00 17. " DI0_POLARITY_DISP_CLK ,DI0 Output Clock's polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DI0_SYNC_COUNT_SEL ,Selects synchronous flow synchronization counter in DI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " DI0_ERR_TREATMENT ,In case of synchronous flow error there are 2 ways to handle the display" "Drive the last component,To wait"
|
|
bitfld.long 0x00 10. " DI0_ERM_VSYNC_SEL ,DI0 error recovery module's VSYNC source select" "Vsync_pre,Vsync_post"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DI0_POLARITY_CS1 ,DI0 Chip Select's 1 polarity" "Active Low,Active High"
|
|
bitfld.long 0x00 8. " DI0_POLARITY_CS0 ,DI0 Chip Select's 0 polarity" "Active Low,Active High"
|
|
bitfld.long 0x00 7. " DI0_POLARITY_8 ,DI0 output pin 8 polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DI0_POLARITY_7 ,DI0 output pin 7 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 5. " DI0_POLARITY_6 ,DI0 output pin 6 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 4. " DI0_POLARITY_5 ,DI0 output pin 5 polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DI0_POLARITY_4 ,DI0 output pin 4 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 2. " DI0_POLARITY_3 ,DI0 output pin 3 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 1. " DI0_POLARITY_2 ,DI0 output pin 2 polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DI0_POLARITY_1 ,DI0 output pin 1 polarity" "Active low,Active high"
|
|
line.long 0x04 "DI0_BS_CLKGEN0,DI0 Base Sync Clock Gen 0 Register"
|
|
hexmask.long.word 0x04 16.--24. 1. " DI0_DISP_CLK_OFFSET ,DI0 Display Clock Offset"
|
|
hexmask.long.byte 0x04 4.--11. 1. " DI0_DISP_CLK_PERIOD1 ,DI0 Display Clock Period (integer part)"
|
|
hexmask.long.byte 0x04 0.--3. 1. " DI0_DISP_CLK_PERIOD0 ,DI0 Display Clock Period (fractional part)"
|
|
line.long 0x08 "DI0_BS_CLKGEN1,DI0 Base Sync Clock Gen 1 Register"
|
|
hexmask.long.byte 0x08 17.--24. 1. " DI0_DISP_CLK_DOWN1 ,DI0 display clock falling edge position (integer part)"
|
|
bitfld.long 0x08 16. " DI0_DISP_CLK_DOWN0 ,DI0 display clock falling edge position(fractional part)" "0,1"
|
|
hexmask.long.byte 0x08 1.--8. 1. " DI0_DISP_CLK_UP1 ,DI0 display clock rising edge position (integer part)"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DI0_DISP_CLK_UP0 ,DI0 display clock rising edge position (fractional part)" "0,1"
|
|
line.long 0x0c "DI0_SW_GEN0_1,DI0 Sync Wave Gen 1 Register 0"
|
|
hexmask.long.word 0x0C 19.--30. 1. " DI0_RUN_VALUE_M1_1 ,DI0 counter #1 pre defined value"
|
|
bitfld.long 0x0C 16.--18. " DI0_RUN_RESOLUTION_1 ,DI0 counter #1 Run Resolution" "Disabled,The same trig.,,,,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x0C 3.--14. 1. " DI0_OFFSET_VALUE_1 ,DI0 counter #1 offset value"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " DI0_OFFSET_RESOLUTION_1 ,DI0 counter #1 offset Resolution" "Disabled,The same trig.,,,,CSI VSYNC,External VSYNC,Always on"
|
|
line.long 0x10 "DI0_SW_GEN0_2,DI0 Sync Wave Gen 2 Register 0"
|
|
hexmask.long.word 0x10 19.--30. 1. " DI0_RUN_VALUE_M1_2 ,DI0 counter #2 pre defined value"
|
|
bitfld.long 0x10 16.--18. " DI0_RUN_RESOLUTION_2 ,DI0 counter #2 Run Resolution" "Disabled,The same trig.,Counter 1,,,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x10 3.--14. 1. " DI0_OFFSET_VALUE_2 ,DI0 counter #2 offset value"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " DI0_OFFSET_RESOLUTION_2 ,DI0 counter #2 offset Resolution" "Disabled,The same trig.,Counter 1,,,CSI VSYNC,External VSYNC,Always on"
|
|
line.long 0x14 "DI0_SW_GEN0_3,DI0 Sync Wave Gen 3 Register 0"
|
|
hexmask.long.word 0x14 19.--30. 1. " DI0_RUN_VALUE_M1_3 ,DI0 counter #3 pre defined value"
|
|
bitfld.long 0x14 16.--18. " DI0_RUN_RESOLUTION_3 ,DI0 counter #3 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x14 3.--14. 1. " DI0_OFFSET_VALUE_3 ,counter #3 offset value"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " DI0_OFFSET_RESOLUTION_3 ,DI0 counter #3 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,,CSI VSYNC,External VSYNC,Always on"
|
|
line.long 0x18 "DI0_SW_GEN0_4,DI0 Sync Wave Gen 4 Register 0"
|
|
hexmask.long.word 0x18 19.--30. 1. " DI0_RUN_VALUE_M1_4 ,DI0 counter #4 pre defined value"
|
|
bitfld.long 0x18 16.--18. " DI0_RUN_RESOLUTION_4 ,DI0 counter #4 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x18 3.--14. 1. " DI0_OFFSET_VALUE_4 ,DI0 counter #4 offset value"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " DI0_OFFSET_RESOLUTION_4 ,DI0 counter #4 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,CSI VSYNC,External VSYNC,Always on"
|
|
line.long 0x1c "DI0_SW_GEN0_5,DI0 Sync Wave Gen 5 Register 0"
|
|
hexmask.long.word 0x1C 19.--30. 1. " DI0_RUN_VALUE_M1_5 ,DI0 counter #5 pre defined value"
|
|
bitfld.long 0x1C 16.--18. " DI0_RUN_RESOLUTION_5 ,DI0 counter #5 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,External VSYNC,Always on"
|
|
hexmask.long.word 0x1C 3.--14. 1. " DI0_OFFSET_VALUE_5 ,DI0 counter #5 offset value"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " DI0_OFFSET_RESOLUTION_5 ,DI0 counter #5 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,External VSYNC,Always on"
|
|
line.long 0x20 "DI0_SW_GEN0_6,DI0 Sync Wave Gen 6 Register 0"
|
|
hexmask.long.word 0x20 19.--30. 1. " DI0_RUN_VALUE_M1_6 ,DI0 counter #6 pre defined value"
|
|
bitfld.long 0x20 16.--18. " DI0_RUN_RESOLUTION_6 ,DI0 counter #6 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
hexmask.long.word 0x20 3.--14. 1. " DI0_OFFSET_VALUE_6 ,DI0 counter #6 offset value"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " DI0_OFFSET_RESOLUTION_6 ,DI0 counter #6 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
line.long 0x24 "DI0_SW_GEN0_7,DI0 Sync Wave Gen 7 Register 0"
|
|
hexmask.long.word 0x24 19.--30. 1. " DI0_RUN_VALUE_M1_7 ,DI0 counter #7 pre defined value"
|
|
bitfld.long 0x24 16.--18. " DI0_RUN_RESOLUTION_7 ,DI0 counter #7 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
hexmask.long.word 0x24 3.--14. 1. " DI0_OFFSET_VALUE_7 ,DI0 counter #7 offset value"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " DI0_OFFSET_RESOLUTION_7 ,DI0 counter #7 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
line.long 0x28 "DI0_SW_GEN0_8,DI0 Sync Wave Gen 8 Register 0"
|
|
hexmask.long.word 0x28 19.--30. 1. " DI0_RUN_VALUE_M1_8 ,DI0 counter #8 pre defined value"
|
|
bitfld.long 0x28 16.--18. " DI0_RUN_RESOLUTION_8 ,DI0 counter #8 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
hexmask.long.word 0x28 3.--14. 1. " DI0_OFFSET_VALUE_8 ,DI0 counter #8 offset value"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " DI0_OFFSET_RESOLUTION_8 ,DI0 counter #8 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
line.long 0x2c "DI0_SW_GEN0_9,DI0 Sync Wave Gen 9 Register 0"
|
|
hexmask.long.word 0x2C 19.--30. 1. " DI0_RUN_VALUE_M1_9 ,DI0 counter #9 pre defined value"
|
|
bitfld.long 0x2C 16.--18. " DI0_RUN_RESOLUTION_9 ,DI0 counter #9 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
hexmask.long.word 0x2C 3.--14. 1. " DI0_OFFSET_VALUE_9 ,DI0 counter #9 offset value"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " DI0_OFFSET_RESOLUTION_9 ,DI0 counter #9 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
textline " "
|
|
line.long 0x30 "DI0_SW_GEN1_1,DI0 Sync Wave 1 Gen Register 1"
|
|
bitfld.long 0x30 29.--30. " DI0_CNT_POLARITY_GEN_EN_1 ,DI0 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
|
|
bitfld.long 0x30 28. " DI0_CNT_AUTO_RELOAD_1 ,Counter auto reload mode" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x30 25.--27. " DI0_CNT_CLR_SEL_1 ,Counter Clear select" "Disabled,The same trig.,,,,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x30 16.--24. 1. " DI0_CNT_DOWN_1 ,Counter falling edge position"
|
|
textline " "
|
|
bitfld.long 0x30 12.--14. " DI0_CNT_POLARITY_TRIGGER_SEL_1 ,DI0 Counter's toggling trigger select" "Disabled,The same trig.,,,,CSI VSYNC,External VSYNC,Always on"
|
|
bitfld.long 0x30 9.--11. " DI0_CNT_POLARITY_CLR_SEL_1 ,DI0 counter's polarity Clear select" "Always inverted,Kept the same,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x30 1.--8. 1. " DI0_CNT_UP_1_1 ,Counter rising edge position(integer part)"
|
|
bitfld.long 0x30 0. " DI0_CNT_UP_1_0 ,Counter rising edge position(fractional part)" "0,1"
|
|
line.long 0x34 "DI0_SW_GEN1_2,DI0 Sync Wave 2 Gen Register 1"
|
|
bitfld.long 0x34 29.--30. " DI0_CNT_POLARITY_GEN_EN_2 ,DI0 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
|
|
bitfld.long 0x34 28. " DI0_CNT_AUTO_RELOAD_2 ,Counter auto reload mode" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x34 25.--27. " DI0_CNT_CLR_SEL_2 ,Counter Clear select" "Disabled,The same trig.,Counter 1,,,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x34 16.--24. 1. " DI0_CNT_DOWN_2 ,Counter falling edge position"
|
|
textline " "
|
|
bitfld.long 0x34 12.--14. " DI0_CNT_POLARITY_TRIGGER_SEL_2 ,DI0 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,,,CSI VSYNC,External VSYNC,Always on"
|
|
bitfld.long 0x34 9.--11. " DI0_CNT_POLARITY_CLR_SEL_2 ,DI0 counter's polarity Clear select" "Always inverted,Kept the same,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x34 1.--8. 1. " DI0_CNT_UP_2_1 ,Counter rising edge position(integer part)"
|
|
bitfld.long 0x34 0. " DI0_CNT_UP_2_0 ,Counter rising edge position(fractional part)" "0,1"
|
|
line.long 0x38 "DI0_SW_GEN1_3,DI0 Sync Wave 3 Gen Register 1"
|
|
bitfld.long 0x38 29.--30. " DI0_CNT_POLARITY_GEN_EN_3 ,DI0 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
|
|
bitfld.long 0x38 28. " DI0_CNT_AUTO_RELOAD_3 ,Counter auto reload mode" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x38 25.--27. " DI0_CNT_CLR_SEL_3 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x38 16.--24. 1. " DI0_CNT_DOWN_3 ,Counter falling edge position"
|
|
textline " "
|
|
bitfld.long 0x38 12.--14. " DI0_CNT_POLARITY_TRIGGER_SEL_3 ,DI0 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,,CSI VSYNC,External VSYNC,Always on"
|
|
bitfld.long 0x38 9.--11. " DI0_CNT_POLARITY_CLR_SEL_3 ,DI0 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x38 1.--8. 1. " DI0_CNT_UP_3_1 ,Counter rising edge position(integer part)"
|
|
bitfld.long 0x38 0. " DI0_CNT_UP_3_0 ,Counter rising edge position(fractional part)" "0,1"
|
|
line.long 0x3c "DI0_SW_GEN1_4,DI0 Sync Wave 4 Gen Register 1"
|
|
bitfld.long 0x3C 29.--30. " DI0_CNT_POLARITY_GEN_EN_4 ,DI0 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
|
|
bitfld.long 0x3C 28. " DI0_CNT_AUTO_RELOAD_4 ,Counter auto reload mode" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x3C 25.--27. " DI0_CNT_CLR_SEL_4 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x3C 16.--24. 1. " DI0_CNT_DOWN_4 ,Counter falling edge position"
|
|
textline " "
|
|
bitfld.long 0x3C 12.--14. " DI0_CNT_POLARITY_TRIGGER_SEL_4 ,DI0 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,CSI VSYNC,External VSYNC,Always on"
|
|
bitfld.long 0x3C 9.--11. " DI0_CNT_POLARITY_CLR_SEL_4 ,DI0 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,Inverted if set Counter 3,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x3C 1.--8. 1. " DI0_CNT_UP_4_1 ,Counter rising edge position(integer part)"
|
|
bitfld.long 0x3C 0. " DI0_CNT_UP_4_0 ,Counter rising edge position(fractional part)" "0,1"
|
|
line.long 0x40 "DI0_SW_GEN1_5,DI0 Sync Wave 5 Gen Register 1"
|
|
bitfld.long 0x40 29.--30. " DI0_CNT_POLARITY_GEN_EN_5 ,DI0 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
|
|
bitfld.long 0x40 28. " DI0_CNT_AUTO_RELOAD_5 ,Counter auto reload mode" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x40 25.--27. " DI0_CNT_CLR_SEL_5 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,External VSYNC,Always on"
|
|
hexmask.long.word 0x40 16.--24. 1. " DI0_CNT_DOWN_5 ,Counter falling edge position"
|
|
textline " "
|
|
bitfld.long 0x40 12.--14. " DI0_CNT_POLARITY_TRIGGER_SEL_5 ,DI0 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,External VSYNC,Always on"
|
|
bitfld.long 0x40 9.--11. " DI0_CNT_POLARITY_CLR_SEL_5 ,DI0 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,Inverted if set Counter 3,Inverted if set Counter 4,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x40 1.--8. 1. " DI0_CNT_UP_5_1 ,Counter rising edge position(integer part)"
|
|
bitfld.long 0x40 0. " DI0_CNT_UP_5_0 ,Counter rising edge position(fractional part)" "0,1"
|
|
line.long 0x44 "DI0_SW_GEN1_6,DI0 Sync Wave 6 Gen Register 1"
|
|
bitfld.long 0x44 29.--30. " DI0_CNT_POLARITY_GEN_EN_6 ,DI0 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
|
|
bitfld.long 0x44 28. " DI0_CNT_AUTO_RELOAD_6 ,Counter auto reload mode" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x44 25.--27. " DI0_CNT_CLR_SEL_6 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
hexmask.long.word 0x44 16.--24. 1. " DI0_CNT_DOWN_6 ,Counter falling edge position"
|
|
textline " "
|
|
bitfld.long 0x44 12.--14. " DI0_CNT_POLARITY_TRIGGER_SEL_6 ,DI0 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
bitfld.long 0x44 9.--11. " DI0_CNT_POLARITY_CLR_SEL_6 ,DI0 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,Inverted if set Counter 3,Inverted if set Counter 4,Inverted if set Counter 5,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x44 1.--8. 1. " DI0_CNT_UP_6_1 ,Counter rising edge position(integer part)"
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|
bitfld.long 0x44 0. " DI0_CNT_UP_6_0 ,Counter rising edge position(fractional part)" "0,1"
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line.long 0x48 "DI0_SW_GEN1_7,DI0 Sync Wave 7 Gen Register 1"
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bitfld.long 0x48 29.--30. " DI0_CNT_POLARITY_GEN_EN_7 ,DI0 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
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bitfld.long 0x48 28. " DI0_CNT_AUTO_RELOAD_7 ,Counter auto reload mode" "Not reloaded,Reloaded"
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textline " "
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bitfld.long 0x48 25.--27. " DI0_CNT_CLR_SEL_7 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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hexmask.long.word 0x48 16.--24. 1. " DI0_CNT_DOWN_7 ,Counter falling edge position"
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textline " "
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bitfld.long 0x48 12.--14. " DI0_CNT_POLARITY_TRIGGER_SEL_7 ,DI0 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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bitfld.long 0x48 9.--11. " DI0_CNT_POLARITY_CLR_SEL_7 ,DI0 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,Inverted if set Counter 3,Inverted if set Counter 4,Inverted if set Counter 5,Inverted if set Counter 6"
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textline " "
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hexmask.long.byte 0x48 1.--8. 1. " DI0_CNT_UP_7_1 ,Counter rising edge position(integer part)"
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bitfld.long 0x48 0. " DI0_CNT_UP_7_0 ,Counter rising edge position(fractional part)" "0,1"
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line.long 0x4c "DI0_SW_GEN1_8,DI0 Sync Wave 8 Gen Register 1"
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bitfld.long 0x4c 29.--30. " DI0_CNT_POLARITY_GEN_EN_8 ,DI0 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
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|
bitfld.long 0x4c 28. " DI0_CNT_AUTO_RELOAD_8 ,Counter auto reload mode" "Not reloaded,Reloaded"
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|
textline " "
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bitfld.long 0x4c 25.--27. " DI0_CNT_CLR_SEL_8 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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hexmask.long.word 0x4c 16.--24. 1. " DI0_CNT_DOWN_8 ,Counter falling edge position"
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textline " "
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bitfld.long 0x4c 12.--14. " DI0_CNT_POLARITY_TRIGGER_SEL_8 ,DI0 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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bitfld.long 0x4c 9.--11. " DI0_CNT_POLARITY_CLR_SEL_8 ,DI0 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,Inverted if set Counter 3,Inverted if set Counter 4,Inverted if set Counter 5,Inverted if set Counter 6"
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textline " "
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hexmask.long.byte 0x4c 1.--8. 1. " DI0_CNT_UP_8_1 ,Counter rising edge position(integer part)"
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bitfld.long 0x4c 0. " DI0_CNT_UP_8_0 ,Counter rising edge position(fractional part)" "0,1"
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line.long 0x50 "DI0_SW_GEN1_9,DI0 Sync Wave 9 Gen Register 1"
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bitfld.long 0x50 29.--31. " DI0_GENTIME_SEL_9 ,Counter #9 main waveform select" "Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Counter 6,Counter 7,Counter 8"
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bitfld.long 0x50 28. " DI0_CNT_AUTO_RELOAD_9 ,Counter auto reload mode" "Not reloaded,Reloaded"
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|
textline " "
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bitfld.long 0x50 25.--27. " DI0_CNT_CLR_SEL_9 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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hexmask.long.word 0x50 16.--24. 1. " DI0_CNT_DOWN_9 ,Counter falling edge position"
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textline " "
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bitfld.long 0x50 15. " DI0_TAG_SEL_9 ,Tag's source select" "Triggering counter,Counter 9"
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hexmask.long.byte 0x50 1.--8. 1. " DI0_CNT_UP_9_1 ,Counter rising edge position(integer part)"
|
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textline " "
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bitfld.long 0x50 0. " DI0_CNT_UP_9_0 ,Counter rising edge position(fractional part)" "0,1"
|
|
line.long 0x54 "DI0_SYNC_AS_GEN,DI0 Sync Assistance Gen Register"
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|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||(cpuis("IMX6*")))
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bitfld.long 0x54 28. " DI0_SYNC_START_EN ,DI0_SYNC_START_EN" "Disabled,Enabled"
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|
textline " "
|
|
endif
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bitfld.long 0x54 13.--15. " DI0_VSYNC_SEL ,VSYNC select" "1,2,3,4,5,6,7,8"
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hexmask.long.word 0x54 0.--11. 1. " DI0_SYNC_START ,DI0 Sync start"
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tree "DI0_DW_GEN 0-11 (Serial display)"
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group.long 0x58++0x2f
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line.long 0x0 "DI0_DW_GEN_0 ,DI0 Data Wave Gen 0 Registers"
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hexmask.long.byte 0x0 24.--31. 1. " DI0_SERIAL_PERIOD_0 ,DI0 Serial Period 0 "
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hexmask.long.byte 0x0 16.--23. 1. " DI0_START_PERIOD_0 ,DI0 start period"
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bitfld.long 0x0 14.--15. " DI0_CST_0 ,DI0 Chip Select pointer for waveform 0 " "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
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bitfld.long 0x0 4.--8. " DI0_SERIAL_VALID_BITS_0 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
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bitfld.long 0x0 2.--3. " DI0_SERIAL_RS_0 ,DI0 Serial RS" "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
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bitfld.long 0x0 0.--1. " DI0_SERIAL_CLK_0 ,DI0 serial clock" "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
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line.long 0x4 "DI0_DW_GEN_1 ,DI0 Data Wave Gen 1 Registers"
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hexmask.long.byte 0x4 24.--31. 1. " DI0_SERIAL_PERIOD_1 ,DI0 Serial Period 1 "
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hexmask.long.byte 0x4 16.--23. 1. " DI0_START_PERIOD_1 ,DI0 start period"
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bitfld.long 0x4 14.--15. " DI0_CST_1 ,DI0 Chip Select pointer for waveform 1 " "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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bitfld.long 0x4 4.--8. " DI0_SERIAL_VALID_BITS_1 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
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bitfld.long 0x4 2.--3. " DI0_SERIAL_RS_1 ,DI0 Serial RS" "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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bitfld.long 0x4 0.--1. " DI0_SERIAL_CLK_1 ,DI0 serial clock" "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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line.long 0x8 "DI0_DW_GEN_2 ,DI0 Data Wave Gen 2 Registers"
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hexmask.long.byte 0x8 24.--31. 1. " DI0_SERIAL_PERIOD_2 ,DI0 Serial Period 2 "
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hexmask.long.byte 0x8 16.--23. 1. " DI0_START_PERIOD_2 ,DI0 start period"
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bitfld.long 0x8 14.--15. " DI0_CST_2 ,DI0 Chip Select pointer for waveform 2 " "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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bitfld.long 0x8 4.--8. " DI0_SERIAL_VALID_BITS_2 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
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bitfld.long 0x8 2.--3. " DI0_SERIAL_RS_2 ,DI0 Serial RS" "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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bitfld.long 0x8 0.--1. " DI0_SERIAL_CLK_2 ,DI0 serial clock" "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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line.long 0xC "DI0_DW_GEN_3 ,DI0 Data Wave Gen 3 Registers"
|
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hexmask.long.byte 0xC 24.--31. 1. " DI0_SERIAL_PERIOD_3 ,DI0 Serial Period 3 "
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hexmask.long.byte 0xC 16.--23. 1. " DI0_START_PERIOD_3 ,DI0 start period"
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bitfld.long 0xC 14.--15. " DI0_CST_3 ,DI0 Chip Select pointer for waveform 3 " "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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bitfld.long 0xC 4.--8. " DI0_SERIAL_VALID_BITS_3 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
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bitfld.long 0xC 2.--3. " DI0_SERIAL_RS_3 ,DI0 Serial RS" "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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bitfld.long 0xC 0.--1. " DI0_SERIAL_CLK_3 ,DI0 serial clock" "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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line.long 0x10 "DI0_DW_GEN_4 ,DI0 Data Wave Gen 4 Registers"
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hexmask.long.byte 0x10 24.--31. 1. " DI0_SERIAL_PERIOD_4 ,DI0 Serial Period 4 "
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hexmask.long.byte 0x10 16.--23. 1. " DI0_START_PERIOD_4 ,DI0 start period"
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bitfld.long 0x10 14.--15. " DI0_CST_4 ,DI0 Chip Select pointer for waveform 4 " "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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bitfld.long 0x10 4.--8. " DI0_SERIAL_VALID_BITS_4 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x10 2.--3. " DI0_SERIAL_RS_4 ,DI0 Serial RS" "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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bitfld.long 0x10 0.--1. " DI0_SERIAL_CLK_4 ,DI0 serial clock" "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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line.long 0x14 "DI0_DW_GEN_5 ,DI0 Data Wave Gen 5 Registers"
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hexmask.long.byte 0x14 24.--31. 1. " DI0_SERIAL_PERIOD_5 ,DI0 Serial Period 5 "
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hexmask.long.byte 0x14 16.--23. 1. " DI0_START_PERIOD_5 ,DI0 start period"
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bitfld.long 0x14 14.--15. " DI0_CST_5 ,DI0 Chip Select pointer for waveform 5 " "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
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bitfld.long 0x14 4.--8. " DI0_SERIAL_VALID_BITS_5 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
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bitfld.long 0x14 2.--3. " DI0_SERIAL_RS_5 ,DI0 Serial RS" "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
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bitfld.long 0x14 0.--1. " DI0_SERIAL_CLK_5 ,DI0 serial clock" "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
|
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line.long 0x18 "DI0_DW_GEN_6 ,DI0 Data Wave Gen 6 Registers"
|
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hexmask.long.byte 0x18 24.--31. 1. " DI0_SERIAL_PERIOD_6 ,DI0 Serial Period 6 "
|
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hexmask.long.byte 0x18 16.--23. 1. " DI0_START_PERIOD_6 ,DI0 start period"
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bitfld.long 0x18 14.--15. " DI0_CST_6 ,DI0 Chip Select pointer for waveform 6 " "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
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bitfld.long 0x18 4.--8. " DI0_SERIAL_VALID_BITS_6 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
|
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bitfld.long 0x18 2.--3. " DI0_SERIAL_RS_6 ,DI0 Serial RS" "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
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bitfld.long 0x18 0.--1. " DI0_SERIAL_CLK_6 ,DI0 serial clock" "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
|
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line.long 0x1C "DI0_DW_GEN_7 ,DI0 Data Wave Gen 7 Registers"
|
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hexmask.long.byte 0x1C 24.--31. 1. " DI0_SERIAL_PERIOD_7 ,DI0 Serial Period 7 "
|
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hexmask.long.byte 0x1C 16.--23. 1. " DI0_START_PERIOD_7 ,DI0 start period"
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bitfld.long 0x1C 14.--15. " DI0_CST_7 ,DI0 Chip Select pointer for waveform 7 " "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
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bitfld.long 0x1C 4.--8. " DI0_SERIAL_VALID_BITS_7 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x1C 2.--3. " DI0_SERIAL_RS_7 ,DI0 Serial RS" "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
|
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bitfld.long 0x1C 0.--1. " DI0_SERIAL_CLK_7 ,DI0 serial clock" "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
|
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line.long 0x20 "DI0_DW_GEN_8 ,DI0 Data Wave Gen 8 Registers"
|
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hexmask.long.byte 0x20 24.--31. 1. " DI0_SERIAL_PERIOD_8 ,DI0 Serial Period 8 "
|
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hexmask.long.byte 0x20 16.--23. 1. " DI0_START_PERIOD_8 ,DI0 start period"
|
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bitfld.long 0x20 14.--15. " DI0_CST_8 ,DI0 Chip Select pointer for waveform 8 " "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
|
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bitfld.long 0x20 4.--8. " DI0_SERIAL_VALID_BITS_8 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
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bitfld.long 0x20 2.--3. " DI0_SERIAL_RS_8 ,DI0 Serial RS" "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
|
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bitfld.long 0x20 0.--1. " DI0_SERIAL_CLK_8 ,DI0 serial clock" "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
|
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line.long 0x24 "DI0_DW_GEN_9 ,DI0 Data Wave Gen 9 Registers"
|
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hexmask.long.byte 0x24 24.--31. 1. " DI0_SERIAL_PERIOD_9 ,DI0 Serial Period 9 "
|
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hexmask.long.byte 0x24 16.--23. 1. " DI0_START_PERIOD_9 ,DI0 start period"
|
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bitfld.long 0x24 14.--15. " DI0_CST_9 ,DI0 Chip Select pointer for waveform 9 " "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
|
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bitfld.long 0x24 4.--8. " DI0_SERIAL_VALID_BITS_9 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
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bitfld.long 0x24 2.--3. " DI0_SERIAL_RS_9 ,DI0 Serial RS" "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
|
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bitfld.long 0x24 0.--1. " DI0_SERIAL_CLK_9 ,DI0 serial clock" "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
|
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line.long 0x28 "DI0_DW_GEN_10,DI0 Data Wave Gen 10 Registers"
|
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hexmask.long.byte 0x28 24.--31. 1. " DI0_SERIAL_PERIOD_10 ,DI0 Serial Period 10"
|
|
hexmask.long.byte 0x28 16.--23. 1. " DI0_START_PERIOD_10 ,DI0 start period"
|
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bitfld.long 0x28 14.--15. " DI0_CST_10 ,DI0 Chip Select pointer for waveform 10" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
|
|
bitfld.long 0x28 4.--8. " DI0_SERIAL_VALID_BITS_10 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x28 2.--3. " DI0_SERIAL_RS_10 ,DI0 Serial RS" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
|
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bitfld.long 0x28 0.--1. " DI0_SERIAL_CLK_10 ,DI0 serial clock" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
|
|
line.long 0x2C "DI0_DW_GEN_11,DI0 Data Wave Gen 11 Registers"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " DI0_SERIAL_PERIOD_11 ,DI0 Serial Period 11"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " DI0_START_PERIOD_11 ,DI0 start period"
|
|
bitfld.long 0x2C 14.--15. " DI0_CST_11 ,DI0 Chip Select pointer for waveform 11" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
|
|
bitfld.long 0x2C 4.--8. " DI0_SERIAL_VALID_BITS_11 ,DI0 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x2C 2.--3. " DI0_SERIAL_RS_11 ,DI0 Serial RS" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
|
|
bitfld.long 0x2C 0.--1. " DI0_SERIAL_CLK_11 ,DI0 serial clock" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
|
|
tree.end
|
|
tree "DI0_DW_GEN 0-11 (Parallel display)"
|
|
group.long 0x58++0x2f
|
|
line.long 0x0 "DI0_DW_GEN_0 ,DI0 Data Wave Gen 0 Registers"
|
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hexmask.long.byte 0x0 24.--31. 1. " DI0_ACCESS_SIZE_0 ,DI0 Access Size 0 "
|
|
hexmask.long.byte 0x0 16.--23. 1. " DI0_COMPONENT_SIZE_0 ,DI0 component Size"
|
|
bitfld.long 0x0 14.--15. " DI0_CST_0 ,DI0 Chip Select pointer for waveform 0 " "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
|
|
bitfld.long 0x0 12.--13. " DI0_PT_6_0 ,DI0 PIN_17 pointer for waveform 0 " "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " DI0_PT_5_0 ,DI0 PIN_16 pointer for waveform 0 " "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
|
|
bitfld.long 0x0 8.--9. " DI0_PT_4_0 ,DI0 PIN_15 pointer for waveform 0 " "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
|
|
bitfld.long 0x0 6.--7. " DI0_PT_3_0 ,DI0 PIN_14 pointer for waveform 0 " "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
|
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bitfld.long 0x0 4.--5. " DI0_PT_2_0 ,DI0 PIN_13 pointer for waveform 0 " "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
|
|
textline " "
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bitfld.long 0x0 2.--3. " DI0_PT_1_0 ,DI0 PIN_12 pointer for waveform 0 " "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
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bitfld.long 0x0 0.--1. " DI0_PT_0_0 ,DI0 PIN_11 pointer for waveform 0 " "DI0_DW_SET0_0 ,DI0_DW_SET1_0 ,DI0_DW_SET2_0 ,DI0_DW_SET3_0 "
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line.long 0x4 "DI0_DW_GEN_1 ,DI0 Data Wave Gen 1 Registers"
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hexmask.long.byte 0x4 24.--31. 1. " DI0_ACCESS_SIZE_1 ,DI0 Access Size 1 "
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hexmask.long.byte 0x4 16.--23. 1. " DI0_COMPONENT_SIZE_1 ,DI0 component Size"
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bitfld.long 0x4 14.--15. " DI0_CST_1 ,DI0 Chip Select pointer for waveform 1 " "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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bitfld.long 0x4 12.--13. " DI0_PT_6_1 ,DI0 PIN_17 pointer for waveform 1 " "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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textline " "
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bitfld.long 0x4 10.--11. " DI0_PT_5_1 ,DI0 PIN_16 pointer for waveform 1 " "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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bitfld.long 0x4 8.--9. " DI0_PT_4_1 ,DI0 PIN_15 pointer for waveform 1 " "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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bitfld.long 0x4 6.--7. " DI0_PT_3_1 ,DI0 PIN_14 pointer for waveform 1 " "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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bitfld.long 0x4 4.--5. " DI0_PT_2_1 ,DI0 PIN_13 pointer for waveform 1 " "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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textline " "
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bitfld.long 0x4 2.--3. " DI0_PT_1_1 ,DI0 PIN_12 pointer for waveform 1 " "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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bitfld.long 0x4 0.--1. " DI0_PT_0_1 ,DI0 PIN_11 pointer for waveform 1 " "DI0_DW_SET0_1 ,DI0_DW_SET1_1 ,DI0_DW_SET2_1 ,DI0_DW_SET3_1 "
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line.long 0x8 "DI0_DW_GEN_2 ,DI0 Data Wave Gen 2 Registers"
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hexmask.long.byte 0x8 24.--31. 1. " DI0_ACCESS_SIZE_2 ,DI0 Access Size 2 "
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hexmask.long.byte 0x8 16.--23. 1. " DI0_COMPONENT_SIZE_2 ,DI0 component Size"
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bitfld.long 0x8 14.--15. " DI0_CST_2 ,DI0 Chip Select pointer for waveform 2 " "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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bitfld.long 0x8 12.--13. " DI0_PT_6_2 ,DI0 PIN_17 pointer for waveform 2 " "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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textline " "
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bitfld.long 0x8 10.--11. " DI0_PT_5_2 ,DI0 PIN_16 pointer for waveform 2 " "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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bitfld.long 0x8 8.--9. " DI0_PT_4_2 ,DI0 PIN_15 pointer for waveform 2 " "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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bitfld.long 0x8 6.--7. " DI0_PT_3_2 ,DI0 PIN_14 pointer for waveform 2 " "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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bitfld.long 0x8 4.--5. " DI0_PT_2_2 ,DI0 PIN_13 pointer for waveform 2 " "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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textline " "
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bitfld.long 0x8 2.--3. " DI0_PT_1_2 ,DI0 PIN_12 pointer for waveform 2 " "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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bitfld.long 0x8 0.--1. " DI0_PT_0_2 ,DI0 PIN_11 pointer for waveform 2 " "DI0_DW_SET0_2 ,DI0_DW_SET1_2 ,DI0_DW_SET2_2 ,DI0_DW_SET3_2 "
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line.long 0xC "DI0_DW_GEN_3 ,DI0 Data Wave Gen 3 Registers"
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hexmask.long.byte 0xC 24.--31. 1. " DI0_ACCESS_SIZE_3 ,DI0 Access Size 3 "
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hexmask.long.byte 0xC 16.--23. 1. " DI0_COMPONENT_SIZE_3 ,DI0 component Size"
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bitfld.long 0xC 14.--15. " DI0_CST_3 ,DI0 Chip Select pointer for waveform 3 " "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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bitfld.long 0xC 12.--13. " DI0_PT_6_3 ,DI0 PIN_17 pointer for waveform 3 " "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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textline " "
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bitfld.long 0xC 10.--11. " DI0_PT_5_3 ,DI0 PIN_16 pointer for waveform 3 " "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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bitfld.long 0xC 8.--9. " DI0_PT_4_3 ,DI0 PIN_15 pointer for waveform 3 " "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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bitfld.long 0xC 6.--7. " DI0_PT_3_3 ,DI0 PIN_14 pointer for waveform 3 " "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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bitfld.long 0xC 4.--5. " DI0_PT_2_3 ,DI0 PIN_13 pointer for waveform 3 " "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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textline " "
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bitfld.long 0xC 2.--3. " DI0_PT_1_3 ,DI0 PIN_12 pointer for waveform 3 " "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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bitfld.long 0xC 0.--1. " DI0_PT_0_3 ,DI0 PIN_11 pointer for waveform 3 " "DI0_DW_SET0_3 ,DI0_DW_SET1_3 ,DI0_DW_SET2_3 ,DI0_DW_SET3_3 "
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line.long 0x10 "DI0_DW_GEN_4 ,DI0 Data Wave Gen 4 Registers"
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hexmask.long.byte 0x10 24.--31. 1. " DI0_ACCESS_SIZE_4 ,DI0 Access Size 4 "
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hexmask.long.byte 0x10 16.--23. 1. " DI0_COMPONENT_SIZE_4 ,DI0 component Size"
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bitfld.long 0x10 14.--15. " DI0_CST_4 ,DI0 Chip Select pointer for waveform 4 " "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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bitfld.long 0x10 12.--13. " DI0_PT_6_4 ,DI0 PIN_17 pointer for waveform 4 " "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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textline " "
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bitfld.long 0x10 10.--11. " DI0_PT_5_4 ,DI0 PIN_16 pointer for waveform 4 " "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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bitfld.long 0x10 8.--9. " DI0_PT_4_4 ,DI0 PIN_15 pointer for waveform 4 " "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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bitfld.long 0x10 6.--7. " DI0_PT_3_4 ,DI0 PIN_14 pointer for waveform 4 " "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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bitfld.long 0x10 4.--5. " DI0_PT_2_4 ,DI0 PIN_13 pointer for waveform 4 " "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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textline " "
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bitfld.long 0x10 2.--3. " DI0_PT_1_4 ,DI0 PIN_12 pointer for waveform 4 " "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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bitfld.long 0x10 0.--1. " DI0_PT_0_4 ,DI0 PIN_11 pointer for waveform 4 " "DI0_DW_SET0_4 ,DI0_DW_SET1_4 ,DI0_DW_SET2_4 ,DI0_DW_SET3_4 "
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line.long 0x14 "DI0_DW_GEN_5 ,DI0 Data Wave Gen 5 Registers"
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hexmask.long.byte 0x14 24.--31. 1. " DI0_ACCESS_SIZE_5 ,DI0 Access Size 5 "
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hexmask.long.byte 0x14 16.--23. 1. " DI0_COMPONENT_SIZE_5 ,DI0 component Size"
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bitfld.long 0x14 14.--15. " DI0_CST_5 ,DI0 Chip Select pointer for waveform 5 " "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
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bitfld.long 0x14 12.--13. " DI0_PT_6_5 ,DI0 PIN_17 pointer for waveform 5 " "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
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textline " "
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bitfld.long 0x14 10.--11. " DI0_PT_5_5 ,DI0 PIN_16 pointer for waveform 5 " "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
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bitfld.long 0x14 8.--9. " DI0_PT_4_5 ,DI0 PIN_15 pointer for waveform 5 " "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
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bitfld.long 0x14 6.--7. " DI0_PT_3_5 ,DI0 PIN_14 pointer for waveform 5 " "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
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bitfld.long 0x14 4.--5. " DI0_PT_2_5 ,DI0 PIN_13 pointer for waveform 5 " "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
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textline " "
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bitfld.long 0x14 2.--3. " DI0_PT_1_5 ,DI0 PIN_12 pointer for waveform 5 " "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
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bitfld.long 0x14 0.--1. " DI0_PT_0_5 ,DI0 PIN_11 pointer for waveform 5 " "DI0_DW_SET0_5 ,DI0_DW_SET1_5 ,DI0_DW_SET2_5 ,DI0_DW_SET3_5 "
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line.long 0x18 "DI0_DW_GEN_6 ,DI0 Data Wave Gen 6 Registers"
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hexmask.long.byte 0x18 24.--31. 1. " DI0_ACCESS_SIZE_6 ,DI0 Access Size 6 "
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hexmask.long.byte 0x18 16.--23. 1. " DI0_COMPONENT_SIZE_6 ,DI0 component Size"
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bitfld.long 0x18 14.--15. " DI0_CST_6 ,DI0 Chip Select pointer for waveform 6 " "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
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bitfld.long 0x18 12.--13. " DI0_PT_6_6 ,DI0 PIN_17 pointer for waveform 6 " "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
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textline " "
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bitfld.long 0x18 10.--11. " DI0_PT_5_6 ,DI0 PIN_16 pointer for waveform 6 " "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
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bitfld.long 0x18 8.--9. " DI0_PT_4_6 ,DI0 PIN_15 pointer for waveform 6 " "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
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bitfld.long 0x18 6.--7. " DI0_PT_3_6 ,DI0 PIN_14 pointer for waveform 6 " "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
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bitfld.long 0x18 4.--5. " DI0_PT_2_6 ,DI0 PIN_13 pointer for waveform 6 " "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
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textline " "
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bitfld.long 0x18 2.--3. " DI0_PT_1_6 ,DI0 PIN_12 pointer for waveform 6 " "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
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bitfld.long 0x18 0.--1. " DI0_PT_0_6 ,DI0 PIN_11 pointer for waveform 6 " "DI0_DW_SET0_6 ,DI0_DW_SET1_6 ,DI0_DW_SET2_6 ,DI0_DW_SET3_6 "
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line.long 0x1C "DI0_DW_GEN_7 ,DI0 Data Wave Gen 7 Registers"
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hexmask.long.byte 0x1C 24.--31. 1. " DI0_ACCESS_SIZE_7 ,DI0 Access Size 7 "
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hexmask.long.byte 0x1C 16.--23. 1. " DI0_COMPONENT_SIZE_7 ,DI0 component Size"
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bitfld.long 0x1C 14.--15. " DI0_CST_7 ,DI0 Chip Select pointer for waveform 7 " "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
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bitfld.long 0x1C 12.--13. " DI0_PT_6_7 ,DI0 PIN_17 pointer for waveform 7 " "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
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textline " "
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bitfld.long 0x1C 10.--11. " DI0_PT_5_7 ,DI0 PIN_16 pointer for waveform 7 " "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
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bitfld.long 0x1C 8.--9. " DI0_PT_4_7 ,DI0 PIN_15 pointer for waveform 7 " "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
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bitfld.long 0x1C 6.--7. " DI0_PT_3_7 ,DI0 PIN_14 pointer for waveform 7 " "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
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bitfld.long 0x1C 4.--5. " DI0_PT_2_7 ,DI0 PIN_13 pointer for waveform 7 " "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
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textline " "
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bitfld.long 0x1C 2.--3. " DI0_PT_1_7 ,DI0 PIN_12 pointer for waveform 7 " "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
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bitfld.long 0x1C 0.--1. " DI0_PT_0_7 ,DI0 PIN_11 pointer for waveform 7 " "DI0_DW_SET0_7 ,DI0_DW_SET1_7 ,DI0_DW_SET2_7 ,DI0_DW_SET3_7 "
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line.long 0x20 "DI0_DW_GEN_8 ,DI0 Data Wave Gen 8 Registers"
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hexmask.long.byte 0x20 24.--31. 1. " DI0_ACCESS_SIZE_8 ,DI0 Access Size 8 "
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hexmask.long.byte 0x20 16.--23. 1. " DI0_COMPONENT_SIZE_8 ,DI0 component Size"
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bitfld.long 0x20 14.--15. " DI0_CST_8 ,DI0 Chip Select pointer for waveform 8 " "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
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bitfld.long 0x20 12.--13. " DI0_PT_6_8 ,DI0 PIN_17 pointer for waveform 8 " "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
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textline " "
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bitfld.long 0x20 10.--11. " DI0_PT_5_8 ,DI0 PIN_16 pointer for waveform 8 " "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
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bitfld.long 0x20 8.--9. " DI0_PT_4_8 ,DI0 PIN_15 pointer for waveform 8 " "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
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bitfld.long 0x20 6.--7. " DI0_PT_3_8 ,DI0 PIN_14 pointer for waveform 8 " "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
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bitfld.long 0x20 4.--5. " DI0_PT_2_8 ,DI0 PIN_13 pointer for waveform 8 " "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
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textline " "
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bitfld.long 0x20 2.--3. " DI0_PT_1_8 ,DI0 PIN_12 pointer for waveform 8 " "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
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bitfld.long 0x20 0.--1. " DI0_PT_0_8 ,DI0 PIN_11 pointer for waveform 8 " "DI0_DW_SET0_8 ,DI0_DW_SET1_8 ,DI0_DW_SET2_8 ,DI0_DW_SET3_8 "
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line.long 0x24 "DI0_DW_GEN_9 ,DI0 Data Wave Gen 9 Registers"
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hexmask.long.byte 0x24 24.--31. 1. " DI0_ACCESS_SIZE_9 ,DI0 Access Size 9 "
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hexmask.long.byte 0x24 16.--23. 1. " DI0_COMPONENT_SIZE_9 ,DI0 component Size"
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bitfld.long 0x24 14.--15. " DI0_CST_9 ,DI0 Chip Select pointer for waveform 9 " "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
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bitfld.long 0x24 12.--13. " DI0_PT_6_9 ,DI0 PIN_17 pointer for waveform 9 " "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
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textline " "
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bitfld.long 0x24 10.--11. " DI0_PT_5_9 ,DI0 PIN_16 pointer for waveform 9 " "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
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bitfld.long 0x24 8.--9. " DI0_PT_4_9 ,DI0 PIN_15 pointer for waveform 9 " "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
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bitfld.long 0x24 6.--7. " DI0_PT_3_9 ,DI0 PIN_14 pointer for waveform 9 " "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
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bitfld.long 0x24 4.--5. " DI0_PT_2_9 ,DI0 PIN_13 pointer for waveform 9 " "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
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textline " "
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bitfld.long 0x24 2.--3. " DI0_PT_1_9 ,DI0 PIN_12 pointer for waveform 9 " "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
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bitfld.long 0x24 0.--1. " DI0_PT_0_9 ,DI0 PIN_11 pointer for waveform 9 " "DI0_DW_SET0_9 ,DI0_DW_SET1_9 ,DI0_DW_SET2_9 ,DI0_DW_SET3_9 "
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line.long 0x28 "DI0_DW_GEN_10,DI0 Data Wave Gen 10 Registers"
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hexmask.long.byte 0x28 24.--31. 1. " DI0_ACCESS_SIZE_10 ,DI0 Access Size 10"
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hexmask.long.byte 0x28 16.--23. 1. " DI0_COMPONENT_SIZE_10 ,DI0 component Size"
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bitfld.long 0x28 14.--15. " DI0_CST_10 ,DI0 Chip Select pointer for waveform 10" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
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bitfld.long 0x28 12.--13. " DI0_PT_6_10 ,DI0 PIN_17 pointer for waveform 10" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
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textline " "
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bitfld.long 0x28 10.--11. " DI0_PT_5_10 ,DI0 PIN_16 pointer for waveform 10" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
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bitfld.long 0x28 8.--9. " DI0_PT_4_10 ,DI0 PIN_15 pointer for waveform 10" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
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bitfld.long 0x28 6.--7. " DI0_PT_3_10 ,DI0 PIN_14 pointer for waveform 10" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
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bitfld.long 0x28 4.--5. " DI0_PT_2_10 ,DI0 PIN_13 pointer for waveform 10" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
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textline " "
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bitfld.long 0x28 2.--3. " DI0_PT_1_10 ,DI0 PIN_12 pointer for waveform 10" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
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bitfld.long 0x28 0.--1. " DI0_PT_0_10 ,DI0 PIN_11 pointer for waveform 10" "DI0_DW_SET0_10,DI0_DW_SET1_10,DI0_DW_SET2_10,DI0_DW_SET3_10"
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line.long 0x2C "DI0_DW_GEN_11,DI0 Data Wave Gen 11 Registers"
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hexmask.long.byte 0x2C 24.--31. 1. " DI0_ACCESS_SIZE_11 ,DI0 Access Size 11"
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hexmask.long.byte 0x2C 16.--23. 1. " DI0_COMPONENT_SIZE_11 ,DI0 component Size"
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bitfld.long 0x2C 14.--15. " DI0_CST_11 ,DI0 Chip Select pointer for waveform 11" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
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bitfld.long 0x2C 12.--13. " DI0_PT_6_11 ,DI0 PIN_17 pointer for waveform 11" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
|
|
textline " "
|
|
bitfld.long 0x2C 10.--11. " DI0_PT_5_11 ,DI0 PIN_16 pointer for waveform 11" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
|
|
bitfld.long 0x2C 8.--9. " DI0_PT_4_11 ,DI0 PIN_15 pointer for waveform 11" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
|
|
bitfld.long 0x2C 6.--7. " DI0_PT_3_11 ,DI0 PIN_14 pointer for waveform 11" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
|
|
bitfld.long 0x2C 4.--5. " DI0_PT_2_11 ,DI0 PIN_13 pointer for waveform 11" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
|
|
textline " "
|
|
bitfld.long 0x2C 2.--3. " DI0_PT_1_11 ,DI0 PIN_12 pointer for waveform 11" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
|
|
bitfld.long 0x2C 0.--1. " DI0_PT_0_11 ,DI0 PIN_11 pointer for waveform 11" "DI0_DW_SET0_11,DI0_DW_SET1_11,DI0_DW_SET2_11,DI0_DW_SET3_11"
|
|
tree.end
|
|
textline " "
|
|
group.long 0x88++0xeb
|
|
line.long 0x0 "DI0_DW_SET0_0 ,DI0 Data Wave Set 0 0 Registers"
|
|
hexmask.long.word 0x0 16.--24. 1. " DI0_DATA_CNT_DOWN0_0 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x0 0.--8. 1. " DI0_DATA_CNT_UP0_0 ,Waveform's rising edge position"
|
|
line.long 0x4 "DI0_DW_SET0_1 ,DI0 Data Wave Set 0 1 Registers"
|
|
hexmask.long.word 0x4 16.--24. 1. " DI0_DATA_CNT_DOWN0_1 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x4 0.--8. 1. " DI0_DATA_CNT_UP0_1 ,Waveform's rising edge position"
|
|
line.long 0x8 "DI0_DW_SET0_2 ,DI0 Data Wave Set 0 2 Registers"
|
|
hexmask.long.word 0x8 16.--24. 1. " DI0_DATA_CNT_DOWN0_2 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x8 0.--8. 1. " DI0_DATA_CNT_UP0_2 ,Waveform's rising edge position"
|
|
line.long 0xC "DI0_DW_SET0_3 ,DI0 Data Wave Set 0 3 Registers"
|
|
hexmask.long.word 0xC 16.--24. 1. " DI0_DATA_CNT_DOWN0_3 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xC 0.--8. 1. " DI0_DATA_CNT_UP0_3 ,Waveform's rising edge position"
|
|
line.long 0x10 "DI0_DW_SET0_4 ,DI0 Data Wave Set 0 4 Registers"
|
|
hexmask.long.word 0x10 16.--24. 1. " DI0_DATA_CNT_DOWN0_4 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x10 0.--8. 1. " DI0_DATA_CNT_UP0_4 ,Waveform's rising edge position"
|
|
line.long 0x14 "DI0_DW_SET0_5 ,DI0 Data Wave Set 0 5 Registers"
|
|
hexmask.long.word 0x14 16.--24. 1. " DI0_DATA_CNT_DOWN0_5 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x14 0.--8. 1. " DI0_DATA_CNT_UP0_5 ,Waveform's rising edge position"
|
|
line.long 0x18 "DI0_DW_SET0_6 ,DI0 Data Wave Set 0 6 Registers"
|
|
hexmask.long.word 0x18 16.--24. 1. " DI0_DATA_CNT_DOWN0_6 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x18 0.--8. 1. " DI0_DATA_CNT_UP0_6 ,Waveform's rising edge position"
|
|
line.long 0x1C "DI0_DW_SET0_7 ,DI0 Data Wave Set 0 7 Registers"
|
|
hexmask.long.word 0x1C 16.--24. 1. " DI0_DATA_CNT_DOWN0_7 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x1C 0.--8. 1. " DI0_DATA_CNT_UP0_7 ,Waveform's rising edge position"
|
|
line.long 0x20 "DI0_DW_SET0_8 ,DI0 Data Wave Set 0 8 Registers"
|
|
hexmask.long.word 0x20 16.--24. 1. " DI0_DATA_CNT_DOWN0_8 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x20 0.--8. 1. " DI0_DATA_CNT_UP0_8 ,Waveform's rising edge position"
|
|
line.long 0x24 "DI0_DW_SET0_9 ,DI0 Data Wave Set 0 9 Registers"
|
|
hexmask.long.word 0x24 16.--24. 1. " DI0_DATA_CNT_DOWN0_9 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x24 0.--8. 1. " DI0_DATA_CNT_UP0_9 ,Waveform's rising edge position"
|
|
line.long 0x28 "DI0_DW_SET0_10,DI0 Data Wave Set 0 10 Registers"
|
|
hexmask.long.word 0x28 16.--24. 1. " DI0_DATA_CNT_DOWN0_10 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x28 0.--8. 1. " DI0_DATA_CNT_UP0_10 ,Waveform's rising edge position"
|
|
line.long 0x2C "DI0_DW_SET0_11,DI0 Data Wave Set 0 11 Registers"
|
|
hexmask.long.word 0x2C 16.--24. 1. " DI0_DATA_CNT_DOWN0_11 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x2C 0.--8. 1. " DI0_DATA_CNT_UP0_11 ,Waveform's rising edge position"
|
|
line.long 0x30 "DI0_DW_SET1_0 ,DI0 Data Wave Set 1 0 Registers"
|
|
hexmask.long.word 0x30 16.--24. 1. " DI0_DATA_CNT_DOWN1_0 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x30 0.--8. 1. " DI0_DATA_CNT_UP1_0 ,Waveform's rising edge position"
|
|
line.long 0x34 "DI0_DW_SET1_1 ,DI0 Data Wave Set 1 1 Registers"
|
|
hexmask.long.word 0x34 16.--24. 1. " DI0_DATA_CNT_DOWN1_1 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x34 0.--8. 1. " DI0_DATA_CNT_UP1_1 ,Waveform's rising edge position"
|
|
line.long 0x38 "DI0_DW_SET1_2 ,DI0 Data Wave Set 1 2 Registers"
|
|
hexmask.long.word 0x38 16.--24. 1. " DI0_DATA_CNT_DOWN1_2 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x38 0.--8. 1. " DI0_DATA_CNT_UP1_2 ,Waveform's rising edge position"
|
|
line.long 0x3C "DI0_DW_SET1_3 ,DI0 Data Wave Set 1 3 Registers"
|
|
hexmask.long.word 0x3C 16.--24. 1. " DI0_DATA_CNT_DOWN1_3 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x3C 0.--8. 1. " DI0_DATA_CNT_UP1_3 ,Waveform's rising edge position"
|
|
line.long 0x40 "DI0_DW_SET1_4 ,DI0 Data Wave Set 1 4 Registers"
|
|
hexmask.long.word 0x40 16.--24. 1. " DI0_DATA_CNT_DOWN1_4 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x40 0.--8. 1. " DI0_DATA_CNT_UP1_4 ,Waveform's rising edge position"
|
|
line.long 0x44 "DI0_DW_SET1_5 ,DI0 Data Wave Set 1 5 Registers"
|
|
hexmask.long.word 0x44 16.--24. 1. " DI0_DATA_CNT_DOWN1_5 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x44 0.--8. 1. " DI0_DATA_CNT_UP1_5 ,Waveform's rising edge position"
|
|
line.long 0x48 "DI0_DW_SET1_6 ,DI0 Data Wave Set 1 6 Registers"
|
|
hexmask.long.word 0x48 16.--24. 1. " DI0_DATA_CNT_DOWN1_6 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x48 0.--8. 1. " DI0_DATA_CNT_UP1_6 ,Waveform's rising edge position"
|
|
line.long 0x4C "DI0_DW_SET1_7 ,DI0 Data Wave Set 1 7 Registers"
|
|
hexmask.long.word 0x4C 16.--24. 1. " DI0_DATA_CNT_DOWN1_7 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x4C 0.--8. 1. " DI0_DATA_CNT_UP1_7 ,Waveform's rising edge position"
|
|
line.long 0x50 "DI0_DW_SET1_8 ,DI0 Data Wave Set 1 8 Registers"
|
|
hexmask.long.word 0x50 16.--24. 1. " DI0_DATA_CNT_DOWN1_8 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x50 0.--8. 1. " DI0_DATA_CNT_UP1_8 ,Waveform's rising edge position"
|
|
line.long 0x54 "DI0_DW_SET1_9 ,DI0 Data Wave Set 1 9 Registers"
|
|
hexmask.long.word 0x54 16.--24. 1. " DI0_DATA_CNT_DOWN1_9 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x54 0.--8. 1. " DI0_DATA_CNT_UP1_9 ,Waveform's rising edge position"
|
|
line.long 0x58 "DI0_DW_SET1_10,DI0 Data Wave Set 1 10 Registers"
|
|
hexmask.long.word 0x58 16.--24. 1. " DI0_DATA_CNT_DOWN1_10 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x58 0.--8. 1. " DI0_DATA_CNT_UP1_10 ,Waveform's rising edge position"
|
|
line.long 0x5C "DI0_DW_SET1_11,DI0 Data Wave Set 1 11 Registers"
|
|
hexmask.long.word 0x5C 16.--24. 1. " DI0_DATA_CNT_DOWN1_11 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x5C 0.--8. 1. " DI0_DATA_CNT_UP1_11 ,Waveform's rising edge position"
|
|
line.long 0x60 "DI0_DW_SET2_0 ,DI0 Data Wave Set 2 0 Registers"
|
|
hexmask.long.word 0x60 16.--24. 1. " DI0_DATA_CNT_DOWN2_0 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x60 0.--8. 1. " DI0_DATA_CNT_UP2_0 ,Waveform's rising edge position"
|
|
line.long 0x64 "DI0_DW_SET2_1 ,DI0 Data Wave Set 2 1 Registers"
|
|
hexmask.long.word 0x64 16.--24. 1. " DI0_DATA_CNT_DOWN2_1 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x64 0.--8. 1. " DI0_DATA_CNT_UP2_1 ,Waveform's rising edge position"
|
|
line.long 0x68 "DI0_DW_SET2_2 ,DI0 Data Wave Set 2 2 Registers"
|
|
hexmask.long.word 0x68 16.--24. 1. " DI0_DATA_CNT_DOWN2_2 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x68 0.--8. 1. " DI0_DATA_CNT_UP2_2 ,Waveform's rising edge position"
|
|
line.long 0x6C "DI0_DW_SET2_3 ,DI0 Data Wave Set 2 3 Registers"
|
|
hexmask.long.word 0x6C 16.--24. 1. " DI0_DATA_CNT_DOWN2_3 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x6C 0.--8. 1. " DI0_DATA_CNT_UP2_3 ,Waveform's rising edge position"
|
|
line.long 0x70 "DI0_DW_SET2_4 ,DI0 Data Wave Set 2 4 Registers"
|
|
hexmask.long.word 0x70 16.--24. 1. " DI0_DATA_CNT_DOWN2_4 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x70 0.--8. 1. " DI0_DATA_CNT_UP2_4 ,Waveform's rising edge position"
|
|
line.long 0x74 "DI0_DW_SET2_5 ,DI0 Data Wave Set 2 5 Registers"
|
|
hexmask.long.word 0x74 16.--24. 1. " DI0_DATA_CNT_DOWN2_5 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x74 0.--8. 1. " DI0_DATA_CNT_UP2_5 ,Waveform's rising edge position"
|
|
line.long 0x78 "DI0_DW_SET2_6 ,DI0 Data Wave Set 2 6 Registers"
|
|
hexmask.long.word 0x78 16.--24. 1. " DI0_DATA_CNT_DOWN2_6 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x78 0.--8. 1. " DI0_DATA_CNT_UP2_6 ,Waveform's rising edge position"
|
|
line.long 0x7C "DI0_DW_SET2_7 ,DI0 Data Wave Set 2 7 Registers"
|
|
hexmask.long.word 0x7C 16.--24. 1. " DI0_DATA_CNT_DOWN2_7 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x7C 0.--8. 1. " DI0_DATA_CNT_UP2_7 ,Waveform's rising edge position"
|
|
line.long 0x80 "DI0_DW_SET2_8 ,DI0 Data Wave Set 2 8 Registers"
|
|
hexmask.long.word 0x80 16.--24. 1. " DI0_DATA_CNT_DOWN2_8 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x80 0.--8. 1. " DI0_DATA_CNT_UP2_8 ,Waveform's rising edge position"
|
|
line.long 0x84 "DI0_DW_SET2_9 ,DI0 Data Wave Set 2 9 Registers"
|
|
hexmask.long.word 0x84 16.--24. 1. " DI0_DATA_CNT_DOWN2_9 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x84 0.--8. 1. " DI0_DATA_CNT_UP2_9 ,Waveform's rising edge position"
|
|
line.long 0x88 "DI0_DW_SET2_10,DI0 Data Wave Set 2 10 Registers"
|
|
hexmask.long.word 0x88 16.--24. 1. " DI0_DATA_CNT_DOWN2_10 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x88 0.--8. 1. " DI0_DATA_CNT_UP2_10 ,Waveform's rising edge position"
|
|
line.long 0x8C "DI0_DW_SET2_11,DI0 Data Wave Set 2 11 Registers"
|
|
hexmask.long.word 0x8C 16.--24. 1. " DI0_DATA_CNT_DOWN2_11 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x8C 0.--8. 1. " DI0_DATA_CNT_UP2_11 ,Waveform's rising edge position"
|
|
line.long 0x90 "DI0_DW_SET3_0 ,DI0 Data Wave Set 3 0 Registers"
|
|
hexmask.long.word 0x90 16.--24. 1. " DI0_DATA_CNT_DOWN3_0 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x90 0.--8. 1. " DI0_DATA_CNT_UP3_0 ,Waveform's rising edge position"
|
|
line.long 0x94 "DI0_DW_SET3_1 ,DI0 Data Wave Set 3 1 Registers"
|
|
hexmask.long.word 0x94 16.--24. 1. " DI0_DATA_CNT_DOWN3_1 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x94 0.--8. 1. " DI0_DATA_CNT_UP3_1 ,Waveform's rising edge position"
|
|
line.long 0x98 "DI0_DW_SET3_2 ,DI0 Data Wave Set 3 2 Registers"
|
|
hexmask.long.word 0x98 16.--24. 1. " DI0_DATA_CNT_DOWN3_2 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x98 0.--8. 1. " DI0_DATA_CNT_UP3_2 ,Waveform's rising edge position"
|
|
line.long 0x9C "DI0_DW_SET3_3 ,DI0 Data Wave Set 3 3 Registers"
|
|
hexmask.long.word 0x9C 16.--24. 1. " DI0_DATA_CNT_DOWN3_3 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x9C 0.--8. 1. " DI0_DATA_CNT_UP3_3 ,Waveform's rising edge position"
|
|
line.long 0xA0 "DI0_DW_SET3_4 ,DI0 Data Wave Set 3 4 Registers"
|
|
hexmask.long.word 0xA0 16.--24. 1. " DI0_DATA_CNT_DOWN3_4 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xA0 0.--8. 1. " DI0_DATA_CNT_UP3_4 ,Waveform's rising edge position"
|
|
line.long 0xA4 "DI0_DW_SET3_5 ,DI0 Data Wave Set 3 5 Registers"
|
|
hexmask.long.word 0xA4 16.--24. 1. " DI0_DATA_CNT_DOWN3_5 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xA4 0.--8. 1. " DI0_DATA_CNT_UP3_5 ,Waveform's rising edge position"
|
|
line.long 0xA8 "DI0_DW_SET3_6 ,DI0 Data Wave Set 3 6 Registers"
|
|
hexmask.long.word 0xA8 16.--24. 1. " DI0_DATA_CNT_DOWN3_6 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xA8 0.--8. 1. " DI0_DATA_CNT_UP3_6 ,Waveform's rising edge position"
|
|
line.long 0xAC "DI0_DW_SET3_7 ,DI0 Data Wave Set 3 7 Registers"
|
|
hexmask.long.word 0xAC 16.--24. 1. " DI0_DATA_CNT_DOWN3_7 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xAC 0.--8. 1. " DI0_DATA_CNT_UP3_7 ,Waveform's rising edge position"
|
|
line.long 0xB0 "DI0_DW_SET3_8 ,DI0 Data Wave Set 3 8 Registers"
|
|
hexmask.long.word 0xB0 16.--24. 1. " DI0_DATA_CNT_DOWN3_8 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xB0 0.--8. 1. " DI0_DATA_CNT_UP3_8 ,Waveform's rising edge position"
|
|
line.long 0xB4 "DI0_DW_SET3_9 ,DI0 Data Wave Set 3 9 Registers"
|
|
hexmask.long.word 0xB4 16.--24. 1. " DI0_DATA_CNT_DOWN3_9 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xB4 0.--8. 1. " DI0_DATA_CNT_UP3_9 ,Waveform's rising edge position"
|
|
line.long 0xB8 "DI0_DW_SET3_10,DI0 Data Wave Set 3 10 Registers"
|
|
hexmask.long.word 0xB8 16.--24. 1. " DI0_DATA_CNT_DOWN3_10 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xB8 0.--8. 1. " DI0_DATA_CNT_UP3_10 ,Waveform's rising edge position"
|
|
line.long 0xBC "DI0_DW_SET3_11,DI0 Data Wave Set 3 11 Registers"
|
|
hexmask.long.word 0xBC 16.--24. 1. " DI0_DATA_CNT_DOWN3_11 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xBC 0.--8. 1. " DI0_DATA_CNT_UP3_11 ,Waveform's rising edge position"
|
|
line.long 0xC0 "DI0_STP_REP_1,DI0 Step Repeat 1 Registers"
|
|
hexmask.long.word 0xC0 16.--27. 1. " DI0_STEP_REPEAT_1 ,Step Repeat 1"
|
|
hexmask.long.word 0xC0 0.--11. 1. " DI0_STEP_REPEAT_0 ,Step Repeat 0"
|
|
line.long 0xC4 "DI0_STP_REP_2,DI0 Step Repeat 2 Registers"
|
|
hexmask.long.word 0xC4 16.--27. 1. " DI0_STEP_REPEAT_3 ,Step Repeat 3"
|
|
hexmask.long.word 0xC4 0.--11. 1. " DI0_STEP_REPEAT_2 ,Step Repeat 2"
|
|
line.long 0xC8 "DI0_STP_REP_3,DI0 Step Repeat 3 Registers"
|
|
hexmask.long.word 0xC8 16.--27. 1. " DI0_STEP_REPEAT_5 ,Step Repeat 5"
|
|
hexmask.long.word 0xC8 0.--11. 1. " DI0_STEP_REPEAT_4 ,Step Repeat 4"
|
|
line.long 0xCC "DI0_STP_REP_4,DI0 Step Repeat 4 Registers"
|
|
hexmask.long.word 0xCC 16.--27. 1. " DI0_STEP_REPEAT_7 ,Step Repeat 7"
|
|
hexmask.long.word 0xCC 0.--11. 1. " DI0_STEP_REPEAT_6 ,Step Repeat 6"
|
|
line.long 0xd0 "DI0_STP_REP_9,DI0 Step Repeat 9 Registers"
|
|
hexmask.long.word 0xd0 0.--11. 1. " DI0_STEP_REPEAT_9 ,Step Repeat 9"
|
|
line.long 0xd4 "DI0_SER_CONF,DI0 Serial Display Control Register"
|
|
bitfld.long 0xd4 28.--31. " DI0_SERIAL_LLA_PNTR_RS_R_1 ,RS 3 waveform pointer for read low level access" "1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0xd4 24.--27. " DI0_SERIAL_LLA_PNTR_RS_R_0 ,RS 2 waveform pointer for read low level access" "1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
bitfld.long 0xd4 20.--23. " DI0_SERIAL_LLA_PNTR_RS_W_1 ,RS 1 waveform pointer for write low level access" "1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
textline " "
|
|
bitfld.long 0xd4 16.--19. " DI0_SERIAL_LLA_PNTR_RS_W_0 ,RS 0 waveform pointer for write low level access" "1,2,3,4,5,6,7,8,9,10,11,12,?..."
|
|
hexmask.long.byte 0xd4 8.--15. 1. " DI0_SERIAL_LATCH ,DI0 Serial Latch"
|
|
bitfld.long 0xd4 5. " DI0_LLA_SER_ACCESS ,Direct Low Level Access to Serial display" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xd4 4. " DI0_SER_CLK_POLARITY ,Serial Clock Polarity" "Not inverted,Inverted"
|
|
bitfld.long 0xd4 3. " DI0_SERIAL_DATA_POLARITY ,Serial Data Polarity" "Not inverted,Inverted"
|
|
bitfld.long 0xd4 2. " DI0_SERIAL_RS_POLARITY ,Serial RS Polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0xd4 1. " DI0_SERIAL_CS_POLARITY ,Serial Chip Select Polarity" "Not inverted,Inverted"
|
|
bitfld.long 0xd4 0. " DI0_WAIT4SERIAL ,Wait for Serial" "Not wait,Wait"
|
|
line.long 0xd8 "DI0_SSC,DI0 Special Signals Control Register"
|
|
bitfld.long 0xd8 23. " DI0_PIN17_ERM ,DI0 PIN17 error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 22. " DI0_PIN16_ERM ,DI0 PIN16 error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 21. " DI0_PIN15_ERM ,DI0 PIN15 error recovery mode" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0xd8 20. " DI0_PIN14_ERM ,DI0 PIN14 error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 19. " DI0_PIN13_ERM ,DI0 PIN13 error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 18. " DI0_PIN12_ERM ,DI0 PIN12 error recovery mode" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0xd8 17. " DI0_PIN11_ERM ,DI0 PIN11 error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 16. " DI0_CS_ERM ,DI0 CS error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 5. " DI0_WAIT_ON ,Wait On" "Continued,Held"
|
|
textline " "
|
|
bitfld.long 0xd8 3. " DI0_BYTE_EN_RD_IN ,Byte Enable Read In" "R/W [17:16],W [17:16]/R [19:18]"
|
|
bitfld.long 0xd8 0.--2. " DI0_BYTE_EN_PNTR ,Byte Enable Pointer" "Pin_11,Pin_12,Pin_13,Pin_14,Pin_15,Pin_16,Pin_17,CS pin"
|
|
line.long 0xdc "DI0_POL,DI0 Polarity Register"
|
|
bitfld.long 0xdc 26. " DI0_WAIT_POLARITY ,WAIT polarity" "Active low,Active high"
|
|
bitfld.long 0xdc 25. " DI0_CS1_BYTE_EN_POLARITY ,Byte Enable associated with CS1 polarity" "Active low,Active high"
|
|
bitfld.long 0xdc 24. " DI0_CS0_BYTE_EN_POLARITY ,Byte Enable associated with CS0 polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 23. " DI0_CS1_DATA_POLARITY ,Data Polarity associated with CS1" "Active low,Active high"
|
|
bitfld.long 0xdc 22. " DI0_CS1_POLARITY_17 ,DI0 output pin's polarity for CS1" "Active low,Active high"
|
|
bitfld.long 0xdc 21. " DI0_CS1_POLARITY_16 ,DI0 output pin's polarity for CS1" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 20. " DI0_CS1_POLARITY_15 ,DI0 output pin's polarity for CS1" "Active low,Active high"
|
|
bitfld.long 0xdc 19. " DI0_CS1_POLARITY_14 ,DI0 output pin's polarity for CS1" "Active low,Active high"
|
|
bitfld.long 0xdc 18. " DI0_CS1_POLARITY_13 ,DI0 output pin's polarity for CS1" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 17. " DI0_CS1_POLARITY_12 ,DI0 output pin's polarity for CS1" "Active low,Active high"
|
|
bitfld.long 0xdc 16. " DI0_CS1_POLARITY_11 ,DI0 output pin's polarity for CS1" "Active low,Active high"
|
|
bitfld.long 0xdc 15. " DI0_CS0_DATA_POLARITY ,Data Polarity associated with CS0" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 14. " DI0_CS0_POLARITY_17 ,DI0 output pin's polarity for CS0" "Active low,Active high"
|
|
bitfld.long 0xdc 13. " DI0_CS0_POLARITY_16 ,DI0 output pin's polarity for CS0" "Active low,Active high"
|
|
bitfld.long 0xdc 12. " DI0_CS0_POLARITY_15 ,DI0 output pin's polarity for CS0" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 11. " DI0_CS0_POLARITY_14 ,DI0 output pin's polarity for CS0" "Active low,Active high"
|
|
bitfld.long 0xdc 10. " DI0_CS0_POLARITY_13 ,DI0 output pin's polarity for CS0" "Active low,Active high"
|
|
bitfld.long 0xdc 9. " DI0_CS0_POLARITY_12 ,DI0 output pin's polarity for CS0" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 8. " DI0_CS0_POLARITY_11 ,DI0 output pin's polarity for CS0" "Active low,Active high"
|
|
bitfld.long 0xdc 7. " DI0_DRDY_DATA_POLARITY ,Data Polarity associated with DRDY" "Active low,Active high"
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|
bitfld.long 0xdc 6. " DI0_DRDY_POLARITY_17 ,DI0 output pin's polarity for DRDY" "Active low,Active high"
|
|
textline " "
|
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bitfld.long 0xdc 5. " DI0_DRDY_POLARITY_16 ,DI0 output pin's polarity for DRDY" "Active low,Active high"
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|
bitfld.long 0xdc 4. " DI0_DRDY_POLARITY_15 ,DI0 output pin's polarity for DRDY" "Active low,Active high"
|
|
bitfld.long 0xdc 3. " DI0_DRDY_POLARITY_14 ,DI0 output pin's polarity for DRDY" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 2. " DI0_DRDY_POLARITY_13 ,DI0 output pin's polarity for DRDY" "Active low,Active high"
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|
bitfld.long 0xdc 1. " DI0_DRDY_POLARITY_12 ,DI0 output pin's polarity for DRDY" "Active low,Active high"
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bitfld.long 0xdc 0. " DI0_DRDY_POLARITY_11 ,DI0 output pin's polarity for DRDY" "Active low,Active high"
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line.long 0xe0 "DI0_AW0,DI0 Active Window 0 Register"
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bitfld.long 0xe0 28.--31. " DI0_AW_TRIG_SEL ,Selects the trigger for sending data during the display's active window" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on,?..."
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hexmask.long.word 0xe0 16.--27. 1. " DI0_AW_HEND ,Horizontal end of the active window"
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bitfld.long 0xe0 12.--15. " DI0_AW_HCOUNT_SEL ,Selects the counter that counts the horizontal position of the display's active window" "Disabled,,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Counter 6,Counter 7,Counter 8,?..."
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|
textline " "
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hexmask.long.word 0xe0 0.--11. 1. " DI0_AW_HSTART ,Horizontal start of the active window"
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line.long 0xe4 "DI0_AW1,DI0 Active Window 1 Register"
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hexmask.long.word 0xe4 16.--27. 1. " DI0_AW_VEND ,Vertical end of the active window"
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bitfld.long 0xe4 12.--15. " DI0_AW_VCOUNT_SEL ,Selects the counter that counts the vertical position of the display's active window" "Disabled,,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Counter 6,Counter 7,Counter 8,?..."
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hexmask.long.word 0xe4 0.--11. 1. " DI0_AW_VSTART ,Vertical start of the active window"
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line.long 0xe8 "DI0_SCR_CONF,DI0 Screen Configuration Register"
|
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hexmask.long.word 0xe8 0.--11. 1. " DI0_SCREEN_HEIGHT ,Number of display rows"
|
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rgroup.long 0x174++0x03
|
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line.long 0x00 "DI0_STAT,DI0 Status Register"
|
|
bitfld.long 0x00 3. " DI0_CNTR_FIFO_FULL ,DI0_CNTR_FIFO_FULL" "Not full,Full"
|
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bitfld.long 0x00 2. " DI0_CNTR_FIFO_EMPTY ,DI0_CNTR_FIFO_EMPTY" "Not empty,Empty"
|
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bitfld.long 0x00 1. " DI0_READ_FIFO_FULL ,DI0_READ_FIFO_FULL" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DI0_READ_FIFO_EMPTY ,DI0_READ_FIFO_EMPTY" "Not empty,Empty"
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|
width 0x0B
|
|
tree.end
|
|
tree "DI1 registers"
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|
base ad:0x5e048000
|
|
width 17.
|
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group.long 0x00++0x57
|
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line.long 0x00 "DI1_GENERAL,DI1 General Register"
|
|
bitfld.long 0x00 31. " DI1_PIN8_PIN15_SEL ,Route PIN8 over PIN15" "Not routed,Routed"
|
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bitfld.long 0x00 28.--30. " DI1_DISP_Y_SEL ,DI1 Display Vertical coordinate (Y) select" "Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Counter 6,Counter 7,Counter 8"
|
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bitfld.long 0x00 24.--27. " DI1_CLOCK_STOP_MODE ,DI clock stop mode" "Next edge,Next event of Cnt. 1,Next event of Cnt. 2,Next event of Cnt. 3,Next event of Cnt. 4,Next event of Cnt. 5,Next event of Cnt. 6,Next event of Cnt. 7,Next event of Cnt. 8,Next event of Cnt. 9,,,EOL/now,EOF/now,EOL/next line,EOF/next frame"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DI1_DISP_CLOCK_INIT ,Display clock's initial mode" "Stopped,Running"
|
|
bitfld.long 0x00 22. " DI1_MASK_SEL ,DI1 Mask select" "Counter 2,Extracted MASK data"
|
|
bitfld.long 0x00 21. " DI1_VSYNC_EXT ,DI1 External VSYNC" "Internally,External"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DI1_CLK_EXT ,DI1 External Clock" "Internally,External"
|
|
bitfld.long 0x00 18.--19. " DI1_WATCHDOG_MODE ,DI1 watchdog mode" "4,16,64,128"
|
|
bitfld.long 0x00 17. " DI1_POLARITY_DISP_CLK ,DI1 Output Clock's polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " DI1_SYNC_COUNT_SEL ,Selects synchronous flow synchronization counter in DI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 11. " DI1_ERR_TREATMENT ,In case of synchronous flow error there are 2 ways to handle the display" "Drive the last component,To wait"
|
|
bitfld.long 0x00 10. " DI1_ERM_VSYNC_SEL ,DI1 error recovery module's VSYNC source select" "Vsync_pre,Vsync_post"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DI1_POLARITY_CS1 ,DI1 Chip Select's 1 polarity" "Active Low,Active High"
|
|
bitfld.long 0x00 8. " DI1_POLARITY_CS0 ,DI1 Chip Select's 0 polarity" "Active Low,Active High"
|
|
bitfld.long 0x00 7. " DI1_POLARITY_8 ,DI1 output pin 8 polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DI1_POLARITY_7 ,DI1 output pin 7 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 5. " DI1_POLARITY_6 ,DI1 output pin 6 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 4. " DI1_POLARITY_5 ,DI1 output pin 5 polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DI1_POLARITY_4 ,DI1 output pin 4 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 2. " DI1_POLARITY_3 ,DI1 output pin 3 polarity" "Active low,Active high"
|
|
bitfld.long 0x00 1. " DI1_POLARITY_2 ,DI1 output pin 2 polarity" "Active low,Active high"
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textline " "
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bitfld.long 0x00 0. " DI1_POLARITY_1 ,DI1 output pin 1 polarity" "Active low,Active high"
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line.long 0x04 "DI1_BS_CLKGEN0,DI1 Base Sync Clock Gen 0 Register"
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hexmask.long.word 0x04 16.--24. 1. " DI1_DISP_CLK_OFFSET ,DI1 Display Clock Offset"
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hexmask.long.byte 0x04 4.--11. 1. " DI1_DISP_CLK_PERIOD1 ,DI1 Display Clock Period (integer part)"
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hexmask.long.byte 0x04 0.--3. 1. " DI1_DISP_CLK_PERIOD0 ,DI1 Display Clock Period (fractional part)"
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line.long 0x08 "DI1_BS_CLKGEN1,DI1 Base Sync Clock Gen 1 Register"
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hexmask.long.byte 0x08 17.--24. 1. " DI1_DISP_CLK_DOWN1 ,DI1 display clock falling edge position (integer part)"
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bitfld.long 0x08 16. " DI1_DISP_CLK_DOWN0 ,DI1 display clock falling edge position(fractional part)" "0,1"
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hexmask.long.byte 0x08 1.--8. 1. " DI1_DISP_CLK_UP1 ,DI1 display clock rising edge position (integer part)"
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textline " "
|
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bitfld.long 0x08 0. " DI1_DISP_CLK_UP0 ,DI1 display clock rising edge position (fractional part)" "0,1"
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line.long 0x0c "DI1_SW_GEN0_1,DI1 Sync Wave Gen 1 Register 0"
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hexmask.long.word 0x0C 19.--30. 1. " DI1_RUN_VALUE_M1_1 ,DI1 counter #1 pre defined value"
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bitfld.long 0x0C 16.--18. " DI1_RUN_RESOLUTION_1 ,DI1 counter #1 Run Resolution" "Disabled,The same trig.,,,,CSI VSYNC,External VSYNC,Always on"
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hexmask.long.word 0x0C 3.--14. 1. " DI1_OFFSET_VALUE_1 ,DI1 counter #1 offset value"
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textline " "
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bitfld.long 0x0C 0.--2. " DI1_OFFSET_RESOLUTION_1 ,DI1 counter #1 offset Resolution" "Disabled,The same trig.,,,,CSI VSYNC,External VSYNC,Always on"
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line.long 0x10 "DI1_SW_GEN0_2,DI1 Sync Wave Gen 2 Register 0"
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hexmask.long.word 0x10 19.--30. 1. " DI1_RUN_VALUE_M1_2 ,DI1 counter #2 pre defined value"
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bitfld.long 0x10 16.--18. " DI1_RUN_RESOLUTION_2 ,DI1 counter #2 Run Resolution" "Disabled,The same trig.,Counter 1,,,CSI VSYNC,External VSYNC,Always on"
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hexmask.long.word 0x10 3.--14. 1. " DI1_OFFSET_VALUE_2 ,DI1 counter #2 offset value"
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textline " "
|
|
bitfld.long 0x10 0.--2. " DI1_OFFSET_RESOLUTION_2 ,DI1 counter #2 offset Resolution" "Disabled,The same trig.,Counter 1,,,CSI VSYNC,External VSYNC,Always on"
|
|
line.long 0x14 "DI1_SW_GEN0_3,DI1 Sync Wave Gen 3 Register 0"
|
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hexmask.long.word 0x14 19.--30. 1. " DI1_RUN_VALUE_M1_3 ,DI1 counter #3 pre defined value"
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bitfld.long 0x14 16.--18. " DI1_RUN_RESOLUTION_3 ,DI1 counter #3 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,,CSI VSYNC,External VSYNC,Always on"
|
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hexmask.long.word 0x14 3.--14. 1. " DI1_OFFSET_VALUE_3 ,counter #3 offset value"
|
|
textline " "
|
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bitfld.long 0x14 0.--2. " DI1_OFFSET_RESOLUTION_3 ,DI1 counter #3 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,,CSI VSYNC,External VSYNC,Always on"
|
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line.long 0x18 "DI1_SW_GEN0_4,DI1 Sync Wave Gen 4 Register 0"
|
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hexmask.long.word 0x18 19.--30. 1. " DI1_RUN_VALUE_M1_4 ,DI1 counter #4 pre defined value"
|
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bitfld.long 0x18 16.--18. " DI1_RUN_RESOLUTION_4 ,DI1 counter #4 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,CSI VSYNC,External VSYNC,Always on"
|
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hexmask.long.word 0x18 3.--14. 1. " DI1_OFFSET_VALUE_4 ,DI1 counter #4 offset value"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " DI1_OFFSET_RESOLUTION_4 ,DI1 counter #4 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,CSI VSYNC,External VSYNC,Always on"
|
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line.long 0x1c "DI1_SW_GEN0_5,DI1 Sync Wave Gen 5 Register 0"
|
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hexmask.long.word 0x1C 19.--30. 1. " DI1_RUN_VALUE_M1_5 ,DI1 counter #5 pre defined value"
|
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bitfld.long 0x1C 16.--18. " DI1_RUN_RESOLUTION_5 ,DI1 counter #5 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,External VSYNC,Always on"
|
|
hexmask.long.word 0x1C 3.--14. 1. " DI1_OFFSET_VALUE_5 ,DI1 counter #5 offset value"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " DI1_OFFSET_RESOLUTION_5 ,DI1 counter #5 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,External VSYNC,Always on"
|
|
line.long 0x20 "DI1_SW_GEN0_6,DI1 Sync Wave Gen 6 Register 0"
|
|
hexmask.long.word 0x20 19.--30. 1. " DI1_RUN_VALUE_M1_6 ,DI1 counter #6 pre defined value"
|
|
bitfld.long 0x20 16.--18. " DI1_RUN_RESOLUTION_6 ,DI1 counter #6 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
hexmask.long.word 0x20 3.--14. 1. " DI1_OFFSET_VALUE_6 ,DI1 counter #6 offset value"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " DI1_OFFSET_RESOLUTION_6 ,DI1 counter #6 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
line.long 0x24 "DI1_SW_GEN0_7,DI1 Sync Wave Gen 7 Register 0"
|
|
hexmask.long.word 0x24 19.--30. 1. " DI1_RUN_VALUE_M1_7 ,DI1 counter #7 pre defined value"
|
|
bitfld.long 0x24 16.--18. " DI1_RUN_RESOLUTION_7 ,DI1 counter #7 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
hexmask.long.word 0x24 3.--14. 1. " DI1_OFFSET_VALUE_7 ,DI1 counter #7 offset value"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " DI1_OFFSET_RESOLUTION_7 ,DI1 counter #7 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
line.long 0x28 "DI1_SW_GEN0_8,DI1 Sync Wave Gen 8 Register 0"
|
|
hexmask.long.word 0x28 19.--30. 1. " DI1_RUN_VALUE_M1_8 ,DI1 counter #8 pre defined value"
|
|
bitfld.long 0x28 16.--18. " DI1_RUN_RESOLUTION_8 ,DI1 counter #8 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
hexmask.long.word 0x28 3.--14. 1. " DI1_OFFSET_VALUE_8 ,DI1 counter #8 offset value"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " DI1_OFFSET_RESOLUTION_8 ,DI1 counter #8 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
line.long 0x2c "DI1_SW_GEN0_9,DI1 Sync Wave Gen 9 Register 0"
|
|
hexmask.long.word 0x2C 19.--30. 1. " DI1_RUN_VALUE_M1_9 ,DI1 counter #9 pre defined value"
|
|
bitfld.long 0x2C 16.--18. " DI1_RUN_RESOLUTION_9 ,DI1 counter #9 Run Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
hexmask.long.word 0x2C 3.--14. 1. " DI1_OFFSET_VALUE_9 ,DI1 counter #9 offset value"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " DI1_OFFSET_RESOLUTION_9 ,DI1 counter #9 offset Resolution" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
|
|
textline " "
|
|
line.long 0x30 "DI1_SW_GEN1_1,DI1 Sync Wave 1 Gen Register 1"
|
|
bitfld.long 0x30 29.--30. " DI1_CNT_POLARITY_GEN_EN_1 ,DI1 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
|
|
bitfld.long 0x30 28. " DI1_CNT_AUTO_RELOAD_1 ,Counter auto reload mode" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x30 25.--27. " DI1_CNT_CLR_SEL_1 ,Counter Clear select" "Disabled,The same trig.,,,,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x30 16.--24. 1. " DI1_CNT_DOWN_1 ,Counter falling edge position"
|
|
textline " "
|
|
bitfld.long 0x30 12.--14. " DI1_CNT_POLARITY_TRIGGER_SEL_1 ,DI1 Counter's toggling trigger select" "Disabled,The same trig.,,,,CSI VSYNC,External VSYNC,Always on"
|
|
bitfld.long 0x30 9.--11. " DI1_CNT_POLARITY_CLR_SEL_1 ,DI1 counter's polarity Clear select" "Always inverted,Kept the same,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x30 1.--8. 1. " DI1_CNT_UP_1_1 ,Counter rising edge position(integer part)"
|
|
bitfld.long 0x30 0. " DI1_CNT_UP_1_0 ,Counter rising edge position(fractional part)" "0,1"
|
|
line.long 0x34 "DI1_SW_GEN1_2,DI1 Sync Wave 2 Gen Register 1"
|
|
bitfld.long 0x34 29.--30. " DI1_CNT_POLARITY_GEN_EN_2 ,DI1 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
|
|
bitfld.long 0x34 28. " DI1_CNT_AUTO_RELOAD_2 ,Counter auto reload mode" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x34 25.--27. " DI1_CNT_CLR_SEL_2 ,Counter Clear select" "Disabled,The same trig.,Counter 1,,,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x34 16.--24. 1. " DI1_CNT_DOWN_2 ,Counter falling edge position"
|
|
textline " "
|
|
bitfld.long 0x34 12.--14. " DI1_CNT_POLARITY_TRIGGER_SEL_2 ,DI1 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,,,CSI VSYNC,External VSYNC,Always on"
|
|
bitfld.long 0x34 9.--11. " DI1_CNT_POLARITY_CLR_SEL_2 ,DI1 counter's polarity Clear select" "Always inverted,Kept the same,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x34 1.--8. 1. " DI1_CNT_UP_2_1 ,Counter rising edge position(integer part)"
|
|
bitfld.long 0x34 0. " DI1_CNT_UP_2_0 ,Counter rising edge position(fractional part)" "0,1"
|
|
line.long 0x38 "DI1_SW_GEN1_3,DI1 Sync Wave 3 Gen Register 1"
|
|
bitfld.long 0x38 29.--30. " DI1_CNT_POLARITY_GEN_EN_3 ,DI1 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
|
|
bitfld.long 0x38 28. " DI1_CNT_AUTO_RELOAD_3 ,Counter auto reload mode" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x38 25.--27. " DI1_CNT_CLR_SEL_3 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x38 16.--24. 1. " DI1_CNT_DOWN_3 ,Counter falling edge position"
|
|
textline " "
|
|
bitfld.long 0x38 12.--14. " DI1_CNT_POLARITY_TRIGGER_SEL_3 ,DI1 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,,CSI VSYNC,External VSYNC,Always on"
|
|
bitfld.long 0x38 9.--11. " DI1_CNT_POLARITY_CLR_SEL_3 ,DI1 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x38 1.--8. 1. " DI1_CNT_UP_3_1 ,Counter rising edge position(integer part)"
|
|
bitfld.long 0x38 0. " DI1_CNT_UP_3_0 ,Counter rising edge position(fractional part)" "0,1"
|
|
line.long 0x3c "DI1_SW_GEN1_4,DI1 Sync Wave 4 Gen Register 1"
|
|
bitfld.long 0x3C 29.--30. " DI1_CNT_POLARITY_GEN_EN_4 ,DI1 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
|
|
bitfld.long 0x3C 28. " DI1_CNT_AUTO_RELOAD_4 ,Counter auto reload mode" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x3C 25.--27. " DI1_CNT_CLR_SEL_4 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,CSI VSYNC,External VSYNC,Always on"
|
|
hexmask.long.word 0x3C 16.--24. 1. " DI1_CNT_DOWN_4 ,Counter falling edge position"
|
|
textline " "
|
|
bitfld.long 0x3C 12.--14. " DI1_CNT_POLARITY_TRIGGER_SEL_4 ,DI1 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,CSI VSYNC,External VSYNC,Always on"
|
|
bitfld.long 0x3C 9.--11. " DI1_CNT_POLARITY_CLR_SEL_4 ,DI1 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,Inverted if set Counter 3,?..."
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textline " "
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hexmask.long.byte 0x3C 1.--8. 1. " DI1_CNT_UP_4_1 ,Counter rising edge position(integer part)"
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bitfld.long 0x3C 0. " DI1_CNT_UP_4_0 ,Counter rising edge position(fractional part)" "0,1"
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line.long 0x40 "DI1_SW_GEN1_5,DI1 Sync Wave 5 Gen Register 1"
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bitfld.long 0x40 29.--30. " DI1_CNT_POLARITY_GEN_EN_5 ,DI1 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
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bitfld.long 0x40 28. " DI1_CNT_AUTO_RELOAD_5 ,Counter auto reload mode" "Not reloaded,Reloaded"
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textline " "
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bitfld.long 0x40 25.--27. " DI1_CNT_CLR_SEL_5 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,External VSYNC,Always on"
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hexmask.long.word 0x40 16.--24. 1. " DI1_CNT_DOWN_5 ,Counter falling edge position"
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textline " "
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bitfld.long 0x40 12.--14. " DI1_CNT_POLARITY_TRIGGER_SEL_5 ,DI1 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,External VSYNC,Always on"
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bitfld.long 0x40 9.--11. " DI1_CNT_POLARITY_CLR_SEL_5 ,DI1 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,Inverted if set Counter 3,Inverted if set Counter 4,?..."
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textline " "
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hexmask.long.byte 0x40 1.--8. 1. " DI1_CNT_UP_5_1 ,Counter rising edge position(integer part)"
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bitfld.long 0x40 0. " DI1_CNT_UP_5_0 ,Counter rising edge position(fractional part)" "0,1"
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line.long 0x44 "DI1_SW_GEN1_6,DI1 Sync Wave 6 Gen Register 1"
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bitfld.long 0x44 29.--30. " DI1_CNT_POLARITY_GEN_EN_6 ,DI1 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
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bitfld.long 0x44 28. " DI1_CNT_AUTO_RELOAD_6 ,Counter auto reload mode" "Not reloaded,Reloaded"
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textline " "
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bitfld.long 0x44 25.--27. " DI1_CNT_CLR_SEL_6 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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hexmask.long.word 0x44 16.--24. 1. " DI1_CNT_DOWN_6 ,Counter falling edge position"
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textline " "
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bitfld.long 0x44 12.--14. " DI1_CNT_POLARITY_TRIGGER_SEL_6 ,DI1 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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bitfld.long 0x44 9.--11. " DI1_CNT_POLARITY_CLR_SEL_6 ,DI1 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,Inverted if set Counter 3,Inverted if set Counter 4,Inverted if set Counter 5,?..."
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textline " "
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hexmask.long.byte 0x44 1.--8. 1. " DI1_CNT_UP_6_1 ,Counter rising edge position(integer part)"
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bitfld.long 0x44 0. " DI1_CNT_UP_6_0 ,Counter rising edge position(fractional part)" "0,1"
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line.long 0x48 "DI1_SW_GEN1_7,DI1 Sync Wave 7 Gen Register 1"
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bitfld.long 0x48 29.--30. " DI1_CNT_POLARITY_GEN_EN_7 ,DI1 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
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bitfld.long 0x48 28. " DI1_CNT_AUTO_RELOAD_7 ,Counter auto reload mode" "Not reloaded,Reloaded"
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textline " "
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bitfld.long 0x48 25.--27. " DI1_CNT_CLR_SEL_7 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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hexmask.long.word 0x48 16.--24. 1. " DI1_CNT_DOWN_7 ,Counter falling edge position"
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textline " "
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bitfld.long 0x48 12.--14. " DI1_CNT_POLARITY_TRIGGER_SEL_7 ,DI1 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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bitfld.long 0x48 9.--11. " DI1_CNT_POLARITY_CLR_SEL_7 ,DI1 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,Inverted if set Counter 3,Inverted if set Counter 4,Inverted if set Counter 5,Inverted if set Counter 6"
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textline " "
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hexmask.long.byte 0x48 1.--8. 1. " DI1_CNT_UP_7_1 ,Counter rising edge position(integer part)"
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bitfld.long 0x48 0. " DI1_CNT_UP_7_0 ,Counter rising edge position(fractional part)" "0,1"
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line.long 0x4c "DI1_SW_GEN1_8,DI1 Sync Wave 8 Gen Register 1"
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bitfld.long 0x4c 29.--30. " DI1_CNT_POLARITY_GEN_EN_8 ,DI1 Counter polarity generator enable" "Disabled,Value multiple of 2,Enabled,Reached its pre defined value"
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bitfld.long 0x4c 28. " DI1_CNT_AUTO_RELOAD_8 ,Counter auto reload mode" "Not reloaded,Reloaded"
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textline " "
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bitfld.long 0x4c 25.--27. " DI1_CNT_CLR_SEL_8 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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hexmask.long.word 0x4c 16.--24. 1. " DI1_CNT_DOWN_8 ,Counter falling edge position"
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textline " "
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bitfld.long 0x4c 12.--14. " DI1_CNT_POLARITY_TRIGGER_SEL_8 ,DI1 Counter's toggling trigger select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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bitfld.long 0x4c 9.--11. " DI1_CNT_POLARITY_CLR_SEL_8 ,DI1 counter's polarity Clear select" "Always inverted,Kept the same,Inverted if set Counter 1,Inverted if set Counter 2,Inverted if set Counter 3,Inverted if set Counter 4,Inverted if set Counter 5,Inverted if set Counter 6"
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textline " "
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hexmask.long.byte 0x4c 1.--8. 1. " DI1_CNT_UP_8_1 ,Counter rising edge position(integer part)"
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bitfld.long 0x4c 0. " DI1_CNT_UP_8_0 ,Counter rising edge position(fractional part)" "0,1"
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line.long 0x50 "DI1_SW_GEN1_9,DI1 Sync Wave 9 Gen Register 1"
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bitfld.long 0x50 29.--31. " DI1_GENTIME_SEL_9 ,Counter #9 main waveform select" "Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Counter 6,Counter 7,Counter 8"
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bitfld.long 0x50 28. " DI1_CNT_AUTO_RELOAD_9 ,Counter auto reload mode" "Not reloaded,Reloaded"
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textline " "
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bitfld.long 0x50 25.--27. " DI1_CNT_CLR_SEL_9 ,Counter Clear select" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on"
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hexmask.long.word 0x50 16.--24. 1. " DI1_CNT_DOWN_9 ,Counter falling edge position"
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textline " "
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bitfld.long 0x50 15. " DI1_TAG_SEL_9 ,Tag's source select" "Triggering counter,Counter 9"
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hexmask.long.byte 0x50 1.--8. 1. " DI1_CNT_UP_9_1 ,Counter rising edge position(integer part)"
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textline " "
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bitfld.long 0x50 0. " DI1_CNT_UP_9_0 ,Counter rising edge position(fractional part)" "0,1"
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line.long 0x54 "DI1_SYNC_AS_GEN,DI1 Sync Assistance Gen Register"
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sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||(cpuis("IMX6*")))
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bitfld.long 0x54 28. " DI1_SYNC_START_EN ,DI0_SYNC_START_EN" "Disabled,Enabled"
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|
textline " "
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endif
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bitfld.long 0x54 13.--15. " DI1_VSYNC_SEL ,VSYNC select" "1,2,3,4,5,6,7,8"
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hexmask.long.word 0x54 0.--11. 1. " DI1_SYNC_START ,DI1 Sync start"
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tree "DI1_DW_GEN 0-11 (Serial display)"
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group.long 0x58++0x2f
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line.long 0x0 "DI1_DW_GEN_0 ,DI1 Data Wave Gen 0 Registers"
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hexmask.long.byte 0x0 24.--31. 1. " DI1_SERIAL_PERIOD_0 ,DI1 Serial Period 0 "
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hexmask.long.byte 0x0 16.--23. 1. " DI1_START_PERIOD_0 ,DI1 start period"
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bitfld.long 0x0 14.--15. " DI1_CST_0 ,DI1 Chip Select pointer for waveform 0 " "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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bitfld.long 0x0 4.--8. " DI1_SERIAL_VALID_BITS_0 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x0 2.--3. " DI1_SERIAL_RS_0 ,DI1 Serial RS" "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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bitfld.long 0x0 0.--1. " DI1_SERIAL_CLK_0 ,DI1 serial clock" "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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line.long 0x4 "DI1_DW_GEN_1 ,DI1 Data Wave Gen 1 Registers"
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hexmask.long.byte 0x4 24.--31. 1. " DI1_SERIAL_PERIOD_1 ,DI1 Serial Period 1 "
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hexmask.long.byte 0x4 16.--23. 1. " DI1_START_PERIOD_1 ,DI1 start period"
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bitfld.long 0x4 14.--15. " DI1_CST_1 ,DI1 Chip Select pointer for waveform 1 " "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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bitfld.long 0x4 4.--8. " DI1_SERIAL_VALID_BITS_1 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x4 2.--3. " DI1_SERIAL_RS_1 ,DI1 Serial RS" "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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bitfld.long 0x4 0.--1. " DI1_SERIAL_CLK_1 ,DI1 serial clock" "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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line.long 0x8 "DI1_DW_GEN_2 ,DI1 Data Wave Gen 2 Registers"
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hexmask.long.byte 0x8 24.--31. 1. " DI1_SERIAL_PERIOD_2 ,DI1 Serial Period 2 "
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hexmask.long.byte 0x8 16.--23. 1. " DI1_START_PERIOD_2 ,DI1 start period"
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bitfld.long 0x8 14.--15. " DI1_CST_2 ,DI1 Chip Select pointer for waveform 2 " "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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bitfld.long 0x8 4.--8. " DI1_SERIAL_VALID_BITS_2 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x8 2.--3. " DI1_SERIAL_RS_2 ,DI1 Serial RS" "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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bitfld.long 0x8 0.--1. " DI1_SERIAL_CLK_2 ,DI1 serial clock" "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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line.long 0xC "DI1_DW_GEN_3 ,DI1 Data Wave Gen 3 Registers"
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hexmask.long.byte 0xC 24.--31. 1. " DI1_SERIAL_PERIOD_3 ,DI1 Serial Period 3 "
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hexmask.long.byte 0xC 16.--23. 1. " DI1_START_PERIOD_3 ,DI1 start period"
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bitfld.long 0xC 14.--15. " DI1_CST_3 ,DI1 Chip Select pointer for waveform 3 " "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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bitfld.long 0xC 4.--8. " DI1_SERIAL_VALID_BITS_3 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0xC 2.--3. " DI1_SERIAL_RS_3 ,DI1 Serial RS" "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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bitfld.long 0xC 0.--1. " DI1_SERIAL_CLK_3 ,DI1 serial clock" "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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line.long 0x10 "DI1_DW_GEN_4 ,DI1 Data Wave Gen 4 Registers"
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hexmask.long.byte 0x10 24.--31. 1. " DI1_SERIAL_PERIOD_4 ,DI1 Serial Period 4 "
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hexmask.long.byte 0x10 16.--23. 1. " DI1_START_PERIOD_4 ,DI1 start period"
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bitfld.long 0x10 14.--15. " DI1_CST_4 ,DI1 Chip Select pointer for waveform 4 " "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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bitfld.long 0x10 4.--8. " DI1_SERIAL_VALID_BITS_4 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x10 2.--3. " DI1_SERIAL_RS_4 ,DI1 Serial RS" "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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bitfld.long 0x10 0.--1. " DI1_SERIAL_CLK_4 ,DI1 serial clock" "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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line.long 0x14 "DI1_DW_GEN_5 ,DI1 Data Wave Gen 5 Registers"
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hexmask.long.byte 0x14 24.--31. 1. " DI1_SERIAL_PERIOD_5 ,DI1 Serial Period 5 "
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hexmask.long.byte 0x14 16.--23. 1. " DI1_START_PERIOD_5 ,DI1 start period"
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bitfld.long 0x14 14.--15. " DI1_CST_5 ,DI1 Chip Select pointer for waveform 5 " "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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bitfld.long 0x14 4.--8. " DI1_SERIAL_VALID_BITS_5 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
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bitfld.long 0x14 2.--3. " DI1_SERIAL_RS_5 ,DI1 Serial RS" "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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bitfld.long 0x14 0.--1. " DI1_SERIAL_CLK_5 ,DI1 serial clock" "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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line.long 0x18 "DI1_DW_GEN_6 ,DI1 Data Wave Gen 6 Registers"
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hexmask.long.byte 0x18 24.--31. 1. " DI1_SERIAL_PERIOD_6 ,DI1 Serial Period 6 "
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hexmask.long.byte 0x18 16.--23. 1. " DI1_START_PERIOD_6 ,DI1 start period"
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bitfld.long 0x18 14.--15. " DI1_CST_6 ,DI1 Chip Select pointer for waveform 6 " "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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bitfld.long 0x18 4.--8. " DI1_SERIAL_VALID_BITS_6 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x18 2.--3. " DI1_SERIAL_RS_6 ,DI1 Serial RS" "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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bitfld.long 0x18 0.--1. " DI1_SERIAL_CLK_6 ,DI1 serial clock" "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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line.long 0x1C "DI1_DW_GEN_7 ,DI1 Data Wave Gen 7 Registers"
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hexmask.long.byte 0x1C 24.--31. 1. " DI1_SERIAL_PERIOD_7 ,DI1 Serial Period 7 "
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hexmask.long.byte 0x1C 16.--23. 1. " DI1_START_PERIOD_7 ,DI1 start period"
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bitfld.long 0x1C 14.--15. " DI1_CST_7 ,DI1 Chip Select pointer for waveform 7 " "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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bitfld.long 0x1C 4.--8. " DI1_SERIAL_VALID_BITS_7 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x1C 2.--3. " DI1_SERIAL_RS_7 ,DI1 Serial RS" "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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bitfld.long 0x1C 0.--1. " DI1_SERIAL_CLK_7 ,DI1 serial clock" "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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line.long 0x20 "DI1_DW_GEN_8 ,DI1 Data Wave Gen 8 Registers"
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hexmask.long.byte 0x20 24.--31. 1. " DI1_SERIAL_PERIOD_8 ,DI1 Serial Period 8 "
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hexmask.long.byte 0x20 16.--23. 1. " DI1_START_PERIOD_8 ,DI1 start period"
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bitfld.long 0x20 14.--15. " DI1_CST_8 ,DI1 Chip Select pointer for waveform 8 " "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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bitfld.long 0x20 4.--8. " DI1_SERIAL_VALID_BITS_8 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
|
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bitfld.long 0x20 2.--3. " DI1_SERIAL_RS_8 ,DI1 Serial RS" "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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bitfld.long 0x20 0.--1. " DI1_SERIAL_CLK_8 ,DI1 serial clock" "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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line.long 0x24 "DI1_DW_GEN_9 ,DI1 Data Wave Gen 9 Registers"
|
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hexmask.long.byte 0x24 24.--31. 1. " DI1_SERIAL_PERIOD_9 ,DI1 Serial Period 9 "
|
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hexmask.long.byte 0x24 16.--23. 1. " DI1_START_PERIOD_9 ,DI1 start period"
|
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bitfld.long 0x24 14.--15. " DI1_CST_9 ,DI1 Chip Select pointer for waveform 9 " "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
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bitfld.long 0x24 4.--8. " DI1_SERIAL_VALID_BITS_9 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
|
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bitfld.long 0x24 2.--3. " DI1_SERIAL_RS_9 ,DI1 Serial RS" "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
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bitfld.long 0x24 0.--1. " DI1_SERIAL_CLK_9 ,DI1 serial clock" "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
|
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line.long 0x28 "DI1_DW_GEN_10,DI1 Data Wave Gen 10 Registers"
|
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hexmask.long.byte 0x28 24.--31. 1. " DI1_SERIAL_PERIOD_10 ,DI1 Serial Period 10"
|
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hexmask.long.byte 0x28 16.--23. 1. " DI1_START_PERIOD_10 ,DI1 start period"
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bitfld.long 0x28 14.--15. " DI1_CST_10 ,DI1 Chip Select pointer for waveform 10" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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bitfld.long 0x28 4.--8. " DI1_SERIAL_VALID_BITS_10 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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textline " "
|
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bitfld.long 0x28 2.--3. " DI1_SERIAL_RS_10 ,DI1 Serial RS" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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bitfld.long 0x28 0.--1. " DI1_SERIAL_CLK_10 ,DI1 serial clock" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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line.long 0x2C "DI1_DW_GEN_11,DI1 Data Wave Gen 11 Registers"
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hexmask.long.byte 0x2C 24.--31. 1. " DI1_SERIAL_PERIOD_11 ,DI1 Serial Period 11"
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hexmask.long.byte 0x2C 16.--23. 1. " DI1_START_PERIOD_11 ,DI1 start period"
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bitfld.long 0x2C 14.--15. " DI1_CST_11 ,DI1 Chip Select pointer for waveform 11" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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bitfld.long 0x2C 4.--8. " DI1_SERIAL_VALID_BITS_11 ,DI1 Serial valid bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x2C 2.--3. " DI1_SERIAL_RS_11 ,DI1 Serial RS" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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bitfld.long 0x2C 0.--1. " DI1_SERIAL_CLK_11 ,DI1 serial clock" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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tree.end
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tree "DI1_DW_GEN 0-11 (Parallel display)"
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group.long 0x58++0x2f
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line.long 0x0 "DI1_DW_GEN_0 ,DI1 Data Wave Gen 0 Registers"
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hexmask.long.byte 0x0 24.--31. 1. " DI1_ACCESS_SIZE_0 ,DI1 Access Size 0 "
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hexmask.long.byte 0x0 16.--23. 1. " DI1_COMPONENT_SIZE_0 ,DI1 component Size"
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bitfld.long 0x0 14.--15. " DI1_CST_0 ,DI1 Chip Select pointer for waveform 0 " "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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bitfld.long 0x0 12.--13. " DI1_PT_6_0 ,DI1 PIN_17 pointer for waveform 0 " "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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textline " "
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bitfld.long 0x0 10.--11. " DI1_PT_5_0 ,DI1 PIN_16 pointer for waveform 0 " "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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bitfld.long 0x0 8.--9. " DI1_PT_4_0 ,DI1 PIN_15 pointer for waveform 0 " "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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bitfld.long 0x0 6.--7. " DI1_PT_3_0 ,DI1 PIN_14 pointer for waveform 0 " "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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bitfld.long 0x0 4.--5. " DI1_PT_2_0 ,DI1 PIN_13 pointer for waveform 0 " "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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textline " "
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bitfld.long 0x0 2.--3. " DI1_PT_1_0 ,DI1 PIN_12 pointer for waveform 0 " "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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bitfld.long 0x0 0.--1. " DI1_PT_0_0 ,DI1 PIN_11 pointer for waveform 0 " "DI1_DW_SET0_0 ,DI1_DW_SET1_0 ,DI1_DW_SET2_0 ,DI1_DW_SET3_0 "
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line.long 0x4 "DI1_DW_GEN_1 ,DI1 Data Wave Gen 1 Registers"
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hexmask.long.byte 0x4 24.--31. 1. " DI1_ACCESS_SIZE_1 ,DI1 Access Size 1 "
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hexmask.long.byte 0x4 16.--23. 1. " DI1_COMPONENT_SIZE_1 ,DI1 component Size"
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bitfld.long 0x4 14.--15. " DI1_CST_1 ,DI1 Chip Select pointer for waveform 1 " "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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bitfld.long 0x4 12.--13. " DI1_PT_6_1 ,DI1 PIN_17 pointer for waveform 1 " "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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textline " "
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bitfld.long 0x4 10.--11. " DI1_PT_5_1 ,DI1 PIN_16 pointer for waveform 1 " "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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bitfld.long 0x4 8.--9. " DI1_PT_4_1 ,DI1 PIN_15 pointer for waveform 1 " "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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bitfld.long 0x4 6.--7. " DI1_PT_3_1 ,DI1 PIN_14 pointer for waveform 1 " "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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bitfld.long 0x4 4.--5. " DI1_PT_2_1 ,DI1 PIN_13 pointer for waveform 1 " "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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textline " "
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bitfld.long 0x4 2.--3. " DI1_PT_1_1 ,DI1 PIN_12 pointer for waveform 1 " "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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bitfld.long 0x4 0.--1. " DI1_PT_0_1 ,DI1 PIN_11 pointer for waveform 1 " "DI1_DW_SET0_1 ,DI1_DW_SET1_1 ,DI1_DW_SET2_1 ,DI1_DW_SET3_1 "
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line.long 0x8 "DI1_DW_GEN_2 ,DI1 Data Wave Gen 2 Registers"
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hexmask.long.byte 0x8 24.--31. 1. " DI1_ACCESS_SIZE_2 ,DI1 Access Size 2 "
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hexmask.long.byte 0x8 16.--23. 1. " DI1_COMPONENT_SIZE_2 ,DI1 component Size"
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bitfld.long 0x8 14.--15. " DI1_CST_2 ,DI1 Chip Select pointer for waveform 2 " "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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bitfld.long 0x8 12.--13. " DI1_PT_6_2 ,DI1 PIN_17 pointer for waveform 2 " "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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textline " "
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bitfld.long 0x8 10.--11. " DI1_PT_5_2 ,DI1 PIN_16 pointer for waveform 2 " "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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bitfld.long 0x8 8.--9. " DI1_PT_4_2 ,DI1 PIN_15 pointer for waveform 2 " "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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bitfld.long 0x8 6.--7. " DI1_PT_3_2 ,DI1 PIN_14 pointer for waveform 2 " "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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bitfld.long 0x8 4.--5. " DI1_PT_2_2 ,DI1 PIN_13 pointer for waveform 2 " "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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textline " "
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bitfld.long 0x8 2.--3. " DI1_PT_1_2 ,DI1 PIN_12 pointer for waveform 2 " "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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bitfld.long 0x8 0.--1. " DI1_PT_0_2 ,DI1 PIN_11 pointer for waveform 2 " "DI1_DW_SET0_2 ,DI1_DW_SET1_2 ,DI1_DW_SET2_2 ,DI1_DW_SET3_2 "
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line.long 0xC "DI1_DW_GEN_3 ,DI1 Data Wave Gen 3 Registers"
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hexmask.long.byte 0xC 24.--31. 1. " DI1_ACCESS_SIZE_3 ,DI1 Access Size 3 "
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hexmask.long.byte 0xC 16.--23. 1. " DI1_COMPONENT_SIZE_3 ,DI1 component Size"
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bitfld.long 0xC 14.--15. " DI1_CST_3 ,DI1 Chip Select pointer for waveform 3 " "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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bitfld.long 0xC 12.--13. " DI1_PT_6_3 ,DI1 PIN_17 pointer for waveform 3 " "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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textline " "
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bitfld.long 0xC 10.--11. " DI1_PT_5_3 ,DI1 PIN_16 pointer for waveform 3 " "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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bitfld.long 0xC 8.--9. " DI1_PT_4_3 ,DI1 PIN_15 pointer for waveform 3 " "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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bitfld.long 0xC 6.--7. " DI1_PT_3_3 ,DI1 PIN_14 pointer for waveform 3 " "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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bitfld.long 0xC 4.--5. " DI1_PT_2_3 ,DI1 PIN_13 pointer for waveform 3 " "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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textline " "
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bitfld.long 0xC 2.--3. " DI1_PT_1_3 ,DI1 PIN_12 pointer for waveform 3 " "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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bitfld.long 0xC 0.--1. " DI1_PT_0_3 ,DI1 PIN_11 pointer for waveform 3 " "DI1_DW_SET0_3 ,DI1_DW_SET1_3 ,DI1_DW_SET2_3 ,DI1_DW_SET3_3 "
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line.long 0x10 "DI1_DW_GEN_4 ,DI1 Data Wave Gen 4 Registers"
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hexmask.long.byte 0x10 24.--31. 1. " DI1_ACCESS_SIZE_4 ,DI1 Access Size 4 "
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hexmask.long.byte 0x10 16.--23. 1. " DI1_COMPONENT_SIZE_4 ,DI1 component Size"
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bitfld.long 0x10 14.--15. " DI1_CST_4 ,DI1 Chip Select pointer for waveform 4 " "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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bitfld.long 0x10 12.--13. " DI1_PT_6_4 ,DI1 PIN_17 pointer for waveform 4 " "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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textline " "
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bitfld.long 0x10 10.--11. " DI1_PT_5_4 ,DI1 PIN_16 pointer for waveform 4 " "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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bitfld.long 0x10 8.--9. " DI1_PT_4_4 ,DI1 PIN_15 pointer for waveform 4 " "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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bitfld.long 0x10 6.--7. " DI1_PT_3_4 ,DI1 PIN_14 pointer for waveform 4 " "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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bitfld.long 0x10 4.--5. " DI1_PT_2_4 ,DI1 PIN_13 pointer for waveform 4 " "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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textline " "
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bitfld.long 0x10 2.--3. " DI1_PT_1_4 ,DI1 PIN_12 pointer for waveform 4 " "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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bitfld.long 0x10 0.--1. " DI1_PT_0_4 ,DI1 PIN_11 pointer for waveform 4 " "DI1_DW_SET0_4 ,DI1_DW_SET1_4 ,DI1_DW_SET2_4 ,DI1_DW_SET3_4 "
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line.long 0x14 "DI1_DW_GEN_5 ,DI1 Data Wave Gen 5 Registers"
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hexmask.long.byte 0x14 24.--31. 1. " DI1_ACCESS_SIZE_5 ,DI1 Access Size 5 "
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hexmask.long.byte 0x14 16.--23. 1. " DI1_COMPONENT_SIZE_5 ,DI1 component Size"
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bitfld.long 0x14 14.--15. " DI1_CST_5 ,DI1 Chip Select pointer for waveform 5 " "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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bitfld.long 0x14 12.--13. " DI1_PT_6_5 ,DI1 PIN_17 pointer for waveform 5 " "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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textline " "
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bitfld.long 0x14 10.--11. " DI1_PT_5_5 ,DI1 PIN_16 pointer for waveform 5 " "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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bitfld.long 0x14 8.--9. " DI1_PT_4_5 ,DI1 PIN_15 pointer for waveform 5 " "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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bitfld.long 0x14 6.--7. " DI1_PT_3_5 ,DI1 PIN_14 pointer for waveform 5 " "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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bitfld.long 0x14 4.--5. " DI1_PT_2_5 ,DI1 PIN_13 pointer for waveform 5 " "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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textline " "
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bitfld.long 0x14 2.--3. " DI1_PT_1_5 ,DI1 PIN_12 pointer for waveform 5 " "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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bitfld.long 0x14 0.--1. " DI1_PT_0_5 ,DI1 PIN_11 pointer for waveform 5 " "DI1_DW_SET0_5 ,DI1_DW_SET1_5 ,DI1_DW_SET2_5 ,DI1_DW_SET3_5 "
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line.long 0x18 "DI1_DW_GEN_6 ,DI1 Data Wave Gen 6 Registers"
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hexmask.long.byte 0x18 24.--31. 1. " DI1_ACCESS_SIZE_6 ,DI1 Access Size 6 "
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hexmask.long.byte 0x18 16.--23. 1. " DI1_COMPONENT_SIZE_6 ,DI1 component Size"
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bitfld.long 0x18 14.--15. " DI1_CST_6 ,DI1 Chip Select pointer for waveform 6 " "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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bitfld.long 0x18 12.--13. " DI1_PT_6_6 ,DI1 PIN_17 pointer for waveform 6 " "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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textline " "
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bitfld.long 0x18 10.--11. " DI1_PT_5_6 ,DI1 PIN_16 pointer for waveform 6 " "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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bitfld.long 0x18 8.--9. " DI1_PT_4_6 ,DI1 PIN_15 pointer for waveform 6 " "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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bitfld.long 0x18 6.--7. " DI1_PT_3_6 ,DI1 PIN_14 pointer for waveform 6 " "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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bitfld.long 0x18 4.--5. " DI1_PT_2_6 ,DI1 PIN_13 pointer for waveform 6 " "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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textline " "
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bitfld.long 0x18 2.--3. " DI1_PT_1_6 ,DI1 PIN_12 pointer for waveform 6 " "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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bitfld.long 0x18 0.--1. " DI1_PT_0_6 ,DI1 PIN_11 pointer for waveform 6 " "DI1_DW_SET0_6 ,DI1_DW_SET1_6 ,DI1_DW_SET2_6 ,DI1_DW_SET3_6 "
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line.long 0x1C "DI1_DW_GEN_7 ,DI1 Data Wave Gen 7 Registers"
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hexmask.long.byte 0x1C 24.--31. 1. " DI1_ACCESS_SIZE_7 ,DI1 Access Size 7 "
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hexmask.long.byte 0x1C 16.--23. 1. " DI1_COMPONENT_SIZE_7 ,DI1 component Size"
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bitfld.long 0x1C 14.--15. " DI1_CST_7 ,DI1 Chip Select pointer for waveform 7 " "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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bitfld.long 0x1C 12.--13. " DI1_PT_6_7 ,DI1 PIN_17 pointer for waveform 7 " "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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textline " "
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bitfld.long 0x1C 10.--11. " DI1_PT_5_7 ,DI1 PIN_16 pointer for waveform 7 " "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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bitfld.long 0x1C 8.--9. " DI1_PT_4_7 ,DI1 PIN_15 pointer for waveform 7 " "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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bitfld.long 0x1C 6.--7. " DI1_PT_3_7 ,DI1 PIN_14 pointer for waveform 7 " "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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bitfld.long 0x1C 4.--5. " DI1_PT_2_7 ,DI1 PIN_13 pointer for waveform 7 " "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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textline " "
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bitfld.long 0x1C 2.--3. " DI1_PT_1_7 ,DI1 PIN_12 pointer for waveform 7 " "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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bitfld.long 0x1C 0.--1. " DI1_PT_0_7 ,DI1 PIN_11 pointer for waveform 7 " "DI1_DW_SET0_7 ,DI1_DW_SET1_7 ,DI1_DW_SET2_7 ,DI1_DW_SET3_7 "
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line.long 0x20 "DI1_DW_GEN_8 ,DI1 Data Wave Gen 8 Registers"
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hexmask.long.byte 0x20 24.--31. 1. " DI1_ACCESS_SIZE_8 ,DI1 Access Size 8 "
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hexmask.long.byte 0x20 16.--23. 1. " DI1_COMPONENT_SIZE_8 ,DI1 component Size"
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bitfld.long 0x20 14.--15. " DI1_CST_8 ,DI1 Chip Select pointer for waveform 8 " "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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bitfld.long 0x20 12.--13. " DI1_PT_6_8 ,DI1 PIN_17 pointer for waveform 8 " "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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textline " "
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bitfld.long 0x20 10.--11. " DI1_PT_5_8 ,DI1 PIN_16 pointer for waveform 8 " "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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bitfld.long 0x20 8.--9. " DI1_PT_4_8 ,DI1 PIN_15 pointer for waveform 8 " "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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bitfld.long 0x20 6.--7. " DI1_PT_3_8 ,DI1 PIN_14 pointer for waveform 8 " "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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bitfld.long 0x20 4.--5. " DI1_PT_2_8 ,DI1 PIN_13 pointer for waveform 8 " "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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textline " "
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bitfld.long 0x20 2.--3. " DI1_PT_1_8 ,DI1 PIN_12 pointer for waveform 8 " "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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bitfld.long 0x20 0.--1. " DI1_PT_0_8 ,DI1 PIN_11 pointer for waveform 8 " "DI1_DW_SET0_8 ,DI1_DW_SET1_8 ,DI1_DW_SET2_8 ,DI1_DW_SET3_8 "
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line.long 0x24 "DI1_DW_GEN_9 ,DI1 Data Wave Gen 9 Registers"
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hexmask.long.byte 0x24 24.--31. 1. " DI1_ACCESS_SIZE_9 ,DI1 Access Size 9 "
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hexmask.long.byte 0x24 16.--23. 1. " DI1_COMPONENT_SIZE_9 ,DI1 component Size"
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bitfld.long 0x24 14.--15. " DI1_CST_9 ,DI1 Chip Select pointer for waveform 9 " "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
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bitfld.long 0x24 12.--13. " DI1_PT_6_9 ,DI1 PIN_17 pointer for waveform 9 " "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
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textline " "
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bitfld.long 0x24 10.--11. " DI1_PT_5_9 ,DI1 PIN_16 pointer for waveform 9 " "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
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bitfld.long 0x24 8.--9. " DI1_PT_4_9 ,DI1 PIN_15 pointer for waveform 9 " "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
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bitfld.long 0x24 6.--7. " DI1_PT_3_9 ,DI1 PIN_14 pointer for waveform 9 " "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
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bitfld.long 0x24 4.--5. " DI1_PT_2_9 ,DI1 PIN_13 pointer for waveform 9 " "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
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textline " "
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bitfld.long 0x24 2.--3. " DI1_PT_1_9 ,DI1 PIN_12 pointer for waveform 9 " "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
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|
bitfld.long 0x24 0.--1. " DI1_PT_0_9 ,DI1 PIN_11 pointer for waveform 9 " "DI1_DW_SET0_9 ,DI1_DW_SET1_9 ,DI1_DW_SET2_9 ,DI1_DW_SET3_9 "
|
|
line.long 0x28 "DI1_DW_GEN_10,DI1 Data Wave Gen 10 Registers"
|
|
hexmask.long.byte 0x28 24.--31. 1. " DI1_ACCESS_SIZE_10 ,DI1 Access Size 10"
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|
hexmask.long.byte 0x28 16.--23. 1. " DI1_COMPONENT_SIZE_10 ,DI1 component Size"
|
|
bitfld.long 0x28 14.--15. " DI1_CST_10 ,DI1 Chip Select pointer for waveform 10" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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|
bitfld.long 0x28 12.--13. " DI1_PT_6_10 ,DI1 PIN_17 pointer for waveform 10" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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|
textline " "
|
|
bitfld.long 0x28 10.--11. " DI1_PT_5_10 ,DI1 PIN_16 pointer for waveform 10" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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|
bitfld.long 0x28 8.--9. " DI1_PT_4_10 ,DI1 PIN_15 pointer for waveform 10" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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|
bitfld.long 0x28 6.--7. " DI1_PT_3_10 ,DI1 PIN_14 pointer for waveform 10" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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|
bitfld.long 0x28 4.--5. " DI1_PT_2_10 ,DI1 PIN_13 pointer for waveform 10" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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|
textline " "
|
|
bitfld.long 0x28 2.--3. " DI1_PT_1_10 ,DI1 PIN_12 pointer for waveform 10" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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|
bitfld.long 0x28 0.--1. " DI1_PT_0_10 ,DI1 PIN_11 pointer for waveform 10" "DI1_DW_SET0_10,DI1_DW_SET1_10,DI1_DW_SET2_10,DI1_DW_SET3_10"
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|
line.long 0x2C "DI1_DW_GEN_11,DI1 Data Wave Gen 11 Registers"
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|
hexmask.long.byte 0x2C 24.--31. 1. " DI1_ACCESS_SIZE_11 ,DI1 Access Size 11"
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|
hexmask.long.byte 0x2C 16.--23. 1. " DI1_COMPONENT_SIZE_11 ,DI1 component Size"
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|
bitfld.long 0x2C 14.--15. " DI1_CST_11 ,DI1 Chip Select pointer for waveform 11" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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|
bitfld.long 0x2C 12.--13. " DI1_PT_6_11 ,DI1 PIN_17 pointer for waveform 11" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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|
textline " "
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|
bitfld.long 0x2C 10.--11. " DI1_PT_5_11 ,DI1 PIN_16 pointer for waveform 11" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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|
bitfld.long 0x2C 8.--9. " DI1_PT_4_11 ,DI1 PIN_15 pointer for waveform 11" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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|
bitfld.long 0x2C 6.--7. " DI1_PT_3_11 ,DI1 PIN_14 pointer for waveform 11" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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|
bitfld.long 0x2C 4.--5. " DI1_PT_2_11 ,DI1 PIN_13 pointer for waveform 11" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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|
textline " "
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|
bitfld.long 0x2C 2.--3. " DI1_PT_1_11 ,DI1 PIN_12 pointer for waveform 11" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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bitfld.long 0x2C 0.--1. " DI1_PT_0_11 ,DI1 PIN_11 pointer for waveform 11" "DI1_DW_SET0_11,DI1_DW_SET1_11,DI1_DW_SET2_11,DI1_DW_SET3_11"
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|
tree.end
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|
textline " "
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|
group.long 0x88++0xeb
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|
line.long 0x0 "DI1_DW_SET0_0 ,DI1 Data Wave Set 0 0 Registers"
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|
hexmask.long.word 0x0 16.--24. 1. " DI1_DATA_CNT_DOWN0_0 ,Waveform's falling edge position"
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|
hexmask.long.word 0x0 0.--8. 1. " DI1_DATA_CNT_UP0_0 ,Waveform's rising edge position"
|
|
line.long 0x4 "DI1_DW_SET0_1 ,DI1 Data Wave Set 0 1 Registers"
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|
hexmask.long.word 0x4 16.--24. 1. " DI1_DATA_CNT_DOWN0_1 ,Waveform's falling edge position"
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|
hexmask.long.word 0x4 0.--8. 1. " DI1_DATA_CNT_UP0_1 ,Waveform's rising edge position"
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|
line.long 0x8 "DI1_DW_SET0_2 ,DI1 Data Wave Set 0 2 Registers"
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|
hexmask.long.word 0x8 16.--24. 1. " DI1_DATA_CNT_DOWN0_2 ,Waveform's falling edge position"
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|
hexmask.long.word 0x8 0.--8. 1. " DI1_DATA_CNT_UP0_2 ,Waveform's rising edge position"
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|
line.long 0xC "DI1_DW_SET0_3 ,DI1 Data Wave Set 0 3 Registers"
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|
hexmask.long.word 0xC 16.--24. 1. " DI1_DATA_CNT_DOWN0_3 ,Waveform's falling edge position"
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|
hexmask.long.word 0xC 0.--8. 1. " DI1_DATA_CNT_UP0_3 ,Waveform's rising edge position"
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|
line.long 0x10 "DI1_DW_SET0_4 ,DI1 Data Wave Set 0 4 Registers"
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|
hexmask.long.word 0x10 16.--24. 1. " DI1_DATA_CNT_DOWN0_4 ,Waveform's falling edge position"
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|
hexmask.long.word 0x10 0.--8. 1. " DI1_DATA_CNT_UP0_4 ,Waveform's rising edge position"
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|
line.long 0x14 "DI1_DW_SET0_5 ,DI1 Data Wave Set 0 5 Registers"
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|
hexmask.long.word 0x14 16.--24. 1. " DI1_DATA_CNT_DOWN0_5 ,Waveform's falling edge position"
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|
hexmask.long.word 0x14 0.--8. 1. " DI1_DATA_CNT_UP0_5 ,Waveform's rising edge position"
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|
line.long 0x18 "DI1_DW_SET0_6 ,DI1 Data Wave Set 0 6 Registers"
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|
hexmask.long.word 0x18 16.--24. 1. " DI1_DATA_CNT_DOWN0_6 ,Waveform's falling edge position"
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|
hexmask.long.word 0x18 0.--8. 1. " DI1_DATA_CNT_UP0_6 ,Waveform's rising edge position"
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|
line.long 0x1C "DI1_DW_SET0_7 ,DI1 Data Wave Set 0 7 Registers"
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|
hexmask.long.word 0x1C 16.--24. 1. " DI1_DATA_CNT_DOWN0_7 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x1C 0.--8. 1. " DI1_DATA_CNT_UP0_7 ,Waveform's rising edge position"
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|
line.long 0x20 "DI1_DW_SET0_8 ,DI1 Data Wave Set 0 8 Registers"
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|
hexmask.long.word 0x20 16.--24. 1. " DI1_DATA_CNT_DOWN0_8 ,Waveform's falling edge position"
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|
hexmask.long.word 0x20 0.--8. 1. " DI1_DATA_CNT_UP0_8 ,Waveform's rising edge position"
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|
line.long 0x24 "DI1_DW_SET0_9 ,DI1 Data Wave Set 0 9 Registers"
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|
hexmask.long.word 0x24 16.--24. 1. " DI1_DATA_CNT_DOWN0_9 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x24 0.--8. 1. " DI1_DATA_CNT_UP0_9 ,Waveform's rising edge position"
|
|
line.long 0x28 "DI1_DW_SET0_10,DI1 Data Wave Set 0 10 Registers"
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|
hexmask.long.word 0x28 16.--24. 1. " DI1_DATA_CNT_DOWN0_10 ,Waveform's falling edge position"
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|
hexmask.long.word 0x28 0.--8. 1. " DI1_DATA_CNT_UP0_10 ,Waveform's rising edge position"
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|
line.long 0x2C "DI1_DW_SET0_11,DI1 Data Wave Set 0 11 Registers"
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|
hexmask.long.word 0x2C 16.--24. 1. " DI1_DATA_CNT_DOWN0_11 ,Waveform's falling edge position"
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|
hexmask.long.word 0x2C 0.--8. 1. " DI1_DATA_CNT_UP0_11 ,Waveform's rising edge position"
|
|
line.long 0x30 "DI1_DW_SET1_0 ,DI1 Data Wave Set 1 0 Registers"
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|
hexmask.long.word 0x30 16.--24. 1. " DI1_DATA_CNT_DOWN1_0 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x30 0.--8. 1. " DI1_DATA_CNT_UP1_0 ,Waveform's rising edge position"
|
|
line.long 0x34 "DI1_DW_SET1_1 ,DI1 Data Wave Set 1 1 Registers"
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|
hexmask.long.word 0x34 16.--24. 1. " DI1_DATA_CNT_DOWN1_1 ,Waveform's falling edge position"
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|
hexmask.long.word 0x34 0.--8. 1. " DI1_DATA_CNT_UP1_1 ,Waveform's rising edge position"
|
|
line.long 0x38 "DI1_DW_SET1_2 ,DI1 Data Wave Set 1 2 Registers"
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|
hexmask.long.word 0x38 16.--24. 1. " DI1_DATA_CNT_DOWN1_2 ,Waveform's falling edge position"
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|
hexmask.long.word 0x38 0.--8. 1. " DI1_DATA_CNT_UP1_2 ,Waveform's rising edge position"
|
|
line.long 0x3C "DI1_DW_SET1_3 ,DI1 Data Wave Set 1 3 Registers"
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|
hexmask.long.word 0x3C 16.--24. 1. " DI1_DATA_CNT_DOWN1_3 ,Waveform's falling edge position"
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|
hexmask.long.word 0x3C 0.--8. 1. " DI1_DATA_CNT_UP1_3 ,Waveform's rising edge position"
|
|
line.long 0x40 "DI1_DW_SET1_4 ,DI1 Data Wave Set 1 4 Registers"
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|
hexmask.long.word 0x40 16.--24. 1. " DI1_DATA_CNT_DOWN1_4 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x40 0.--8. 1. " DI1_DATA_CNT_UP1_4 ,Waveform's rising edge position"
|
|
line.long 0x44 "DI1_DW_SET1_5 ,DI1 Data Wave Set 1 5 Registers"
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|
hexmask.long.word 0x44 16.--24. 1. " DI1_DATA_CNT_DOWN1_5 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x44 0.--8. 1. " DI1_DATA_CNT_UP1_5 ,Waveform's rising edge position"
|
|
line.long 0x48 "DI1_DW_SET1_6 ,DI1 Data Wave Set 1 6 Registers"
|
|
hexmask.long.word 0x48 16.--24. 1. " DI1_DATA_CNT_DOWN1_6 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x48 0.--8. 1. " DI1_DATA_CNT_UP1_6 ,Waveform's rising edge position"
|
|
line.long 0x4C "DI1_DW_SET1_7 ,DI1 Data Wave Set 1 7 Registers"
|
|
hexmask.long.word 0x4C 16.--24. 1. " DI1_DATA_CNT_DOWN1_7 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x4C 0.--8. 1. " DI1_DATA_CNT_UP1_7 ,Waveform's rising edge position"
|
|
line.long 0x50 "DI1_DW_SET1_8 ,DI1 Data Wave Set 1 8 Registers"
|
|
hexmask.long.word 0x50 16.--24. 1. " DI1_DATA_CNT_DOWN1_8 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x50 0.--8. 1. " DI1_DATA_CNT_UP1_8 ,Waveform's rising edge position"
|
|
line.long 0x54 "DI1_DW_SET1_9 ,DI1 Data Wave Set 1 9 Registers"
|
|
hexmask.long.word 0x54 16.--24. 1. " DI1_DATA_CNT_DOWN1_9 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x54 0.--8. 1. " DI1_DATA_CNT_UP1_9 ,Waveform's rising edge position"
|
|
line.long 0x58 "DI1_DW_SET1_10,DI1 Data Wave Set 1 10 Registers"
|
|
hexmask.long.word 0x58 16.--24. 1. " DI1_DATA_CNT_DOWN1_10 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x58 0.--8. 1. " DI1_DATA_CNT_UP1_10 ,Waveform's rising edge position"
|
|
line.long 0x5C "DI1_DW_SET1_11,DI1 Data Wave Set 1 11 Registers"
|
|
hexmask.long.word 0x5C 16.--24. 1. " DI1_DATA_CNT_DOWN1_11 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x5C 0.--8. 1. " DI1_DATA_CNT_UP1_11 ,Waveform's rising edge position"
|
|
line.long 0x60 "DI1_DW_SET2_0 ,DI1 Data Wave Set 2 0 Registers"
|
|
hexmask.long.word 0x60 16.--24. 1. " DI1_DATA_CNT_DOWN2_0 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x60 0.--8. 1. " DI1_DATA_CNT_UP2_0 ,Waveform's rising edge position"
|
|
line.long 0x64 "DI1_DW_SET2_1 ,DI1 Data Wave Set 2 1 Registers"
|
|
hexmask.long.word 0x64 16.--24. 1. " DI1_DATA_CNT_DOWN2_1 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x64 0.--8. 1. " DI1_DATA_CNT_UP2_1 ,Waveform's rising edge position"
|
|
line.long 0x68 "DI1_DW_SET2_2 ,DI1 Data Wave Set 2 2 Registers"
|
|
hexmask.long.word 0x68 16.--24. 1. " DI1_DATA_CNT_DOWN2_2 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x68 0.--8. 1. " DI1_DATA_CNT_UP2_2 ,Waveform's rising edge position"
|
|
line.long 0x6C "DI1_DW_SET2_3 ,DI1 Data Wave Set 2 3 Registers"
|
|
hexmask.long.word 0x6C 16.--24. 1. " DI1_DATA_CNT_DOWN2_3 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x6C 0.--8. 1. " DI1_DATA_CNT_UP2_3 ,Waveform's rising edge position"
|
|
line.long 0x70 "DI1_DW_SET2_4 ,DI1 Data Wave Set 2 4 Registers"
|
|
hexmask.long.word 0x70 16.--24. 1. " DI1_DATA_CNT_DOWN2_4 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x70 0.--8. 1. " DI1_DATA_CNT_UP2_4 ,Waveform's rising edge position"
|
|
line.long 0x74 "DI1_DW_SET2_5 ,DI1 Data Wave Set 2 5 Registers"
|
|
hexmask.long.word 0x74 16.--24. 1. " DI1_DATA_CNT_DOWN2_5 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x74 0.--8. 1. " DI1_DATA_CNT_UP2_5 ,Waveform's rising edge position"
|
|
line.long 0x78 "DI1_DW_SET2_6 ,DI1 Data Wave Set 2 6 Registers"
|
|
hexmask.long.word 0x78 16.--24. 1. " DI1_DATA_CNT_DOWN2_6 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x78 0.--8. 1. " DI1_DATA_CNT_UP2_6 ,Waveform's rising edge position"
|
|
line.long 0x7C "DI1_DW_SET2_7 ,DI1 Data Wave Set 2 7 Registers"
|
|
hexmask.long.word 0x7C 16.--24. 1. " DI1_DATA_CNT_DOWN2_7 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x7C 0.--8. 1. " DI1_DATA_CNT_UP2_7 ,Waveform's rising edge position"
|
|
line.long 0x80 "DI1_DW_SET2_8 ,DI1 Data Wave Set 2 8 Registers"
|
|
hexmask.long.word 0x80 16.--24. 1. " DI1_DATA_CNT_DOWN2_8 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x80 0.--8. 1. " DI1_DATA_CNT_UP2_8 ,Waveform's rising edge position"
|
|
line.long 0x84 "DI1_DW_SET2_9 ,DI1 Data Wave Set 2 9 Registers"
|
|
hexmask.long.word 0x84 16.--24. 1. " DI1_DATA_CNT_DOWN2_9 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x84 0.--8. 1. " DI1_DATA_CNT_UP2_9 ,Waveform's rising edge position"
|
|
line.long 0x88 "DI1_DW_SET2_10,DI1 Data Wave Set 2 10 Registers"
|
|
hexmask.long.word 0x88 16.--24. 1. " DI1_DATA_CNT_DOWN2_10 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x88 0.--8. 1. " DI1_DATA_CNT_UP2_10 ,Waveform's rising edge position"
|
|
line.long 0x8C "DI1_DW_SET2_11,DI1 Data Wave Set 2 11 Registers"
|
|
hexmask.long.word 0x8C 16.--24. 1. " DI1_DATA_CNT_DOWN2_11 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x8C 0.--8. 1. " DI1_DATA_CNT_UP2_11 ,Waveform's rising edge position"
|
|
line.long 0x90 "DI1_DW_SET3_0 ,DI1 Data Wave Set 3 0 Registers"
|
|
hexmask.long.word 0x90 16.--24. 1. " DI1_DATA_CNT_DOWN3_0 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x90 0.--8. 1. " DI1_DATA_CNT_UP3_0 ,Waveform's rising edge position"
|
|
line.long 0x94 "DI1_DW_SET3_1 ,DI1 Data Wave Set 3 1 Registers"
|
|
hexmask.long.word 0x94 16.--24. 1. " DI1_DATA_CNT_DOWN3_1 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x94 0.--8. 1. " DI1_DATA_CNT_UP3_1 ,Waveform's rising edge position"
|
|
line.long 0x98 "DI1_DW_SET3_2 ,DI1 Data Wave Set 3 2 Registers"
|
|
hexmask.long.word 0x98 16.--24. 1. " DI1_DATA_CNT_DOWN3_2 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x98 0.--8. 1. " DI1_DATA_CNT_UP3_2 ,Waveform's rising edge position"
|
|
line.long 0x9C "DI1_DW_SET3_3 ,DI1 Data Wave Set 3 3 Registers"
|
|
hexmask.long.word 0x9C 16.--24. 1. " DI1_DATA_CNT_DOWN3_3 ,Waveform's falling edge position"
|
|
hexmask.long.word 0x9C 0.--8. 1. " DI1_DATA_CNT_UP3_3 ,Waveform's rising edge position"
|
|
line.long 0xA0 "DI1_DW_SET3_4 ,DI1 Data Wave Set 3 4 Registers"
|
|
hexmask.long.word 0xA0 16.--24. 1. " DI1_DATA_CNT_DOWN3_4 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xA0 0.--8. 1. " DI1_DATA_CNT_UP3_4 ,Waveform's rising edge position"
|
|
line.long 0xA4 "DI1_DW_SET3_5 ,DI1 Data Wave Set 3 5 Registers"
|
|
hexmask.long.word 0xA4 16.--24. 1. " DI1_DATA_CNT_DOWN3_5 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xA4 0.--8. 1. " DI1_DATA_CNT_UP3_5 ,Waveform's rising edge position"
|
|
line.long 0xA8 "DI1_DW_SET3_6 ,DI1 Data Wave Set 3 6 Registers"
|
|
hexmask.long.word 0xA8 16.--24. 1. " DI1_DATA_CNT_DOWN3_6 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xA8 0.--8. 1. " DI1_DATA_CNT_UP3_6 ,Waveform's rising edge position"
|
|
line.long 0xAC "DI1_DW_SET3_7 ,DI1 Data Wave Set 3 7 Registers"
|
|
hexmask.long.word 0xAC 16.--24. 1. " DI1_DATA_CNT_DOWN3_7 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xAC 0.--8. 1. " DI1_DATA_CNT_UP3_7 ,Waveform's rising edge position"
|
|
line.long 0xB0 "DI1_DW_SET3_8 ,DI1 Data Wave Set 3 8 Registers"
|
|
hexmask.long.word 0xB0 16.--24. 1. " DI1_DATA_CNT_DOWN3_8 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xB0 0.--8. 1. " DI1_DATA_CNT_UP3_8 ,Waveform's rising edge position"
|
|
line.long 0xB4 "DI1_DW_SET3_9 ,DI1 Data Wave Set 3 9 Registers"
|
|
hexmask.long.word 0xB4 16.--24. 1. " DI1_DATA_CNT_DOWN3_9 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xB4 0.--8. 1. " DI1_DATA_CNT_UP3_9 ,Waveform's rising edge position"
|
|
line.long 0xB8 "DI1_DW_SET3_10,DI1 Data Wave Set 3 10 Registers"
|
|
hexmask.long.word 0xB8 16.--24. 1. " DI1_DATA_CNT_DOWN3_10 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xB8 0.--8. 1. " DI1_DATA_CNT_UP3_10 ,Waveform's rising edge position"
|
|
line.long 0xBC "DI1_DW_SET3_11,DI1 Data Wave Set 3 11 Registers"
|
|
hexmask.long.word 0xBC 16.--24. 1. " DI1_DATA_CNT_DOWN3_11 ,Waveform's falling edge position"
|
|
hexmask.long.word 0xBC 0.--8. 1. " DI1_DATA_CNT_UP3_11 ,Waveform's rising edge position"
|
|
line.long 0xC0 "DI1_STP_REP_1,DI1 Step Repeat 1 Registers"
|
|
hexmask.long.word 0xC0 16.--27. 1. " DI1_STEP_REPEAT_1 ,Step Repeat 1"
|
|
hexmask.long.word 0xC0 0.--11. 1. " DI1_STEP_REPEAT_0 ,Step Repeat 0"
|
|
line.long 0xC4 "DI1_STP_REP_2,DI1 Step Repeat 2 Registers"
|
|
hexmask.long.word 0xC4 16.--27. 1. " DI1_STEP_REPEAT_3 ,Step Repeat 3"
|
|
hexmask.long.word 0xC4 0.--11. 1. " DI1_STEP_REPEAT_2 ,Step Repeat 2"
|
|
line.long 0xC8 "DI1_STP_REP_3,DI1 Step Repeat 3 Registers"
|
|
hexmask.long.word 0xC8 16.--27. 1. " DI1_STEP_REPEAT_5 ,Step Repeat 5"
|
|
hexmask.long.word 0xC8 0.--11. 1. " DI1_STEP_REPEAT_4 ,Step Repeat 4"
|
|
line.long 0xCC "DI1_STP_REP_4,DI1 Step Repeat 4 Registers"
|
|
hexmask.long.word 0xCC 16.--27. 1. " DI1_STEP_REPEAT_7 ,Step Repeat 7"
|
|
hexmask.long.word 0xCC 0.--11. 1. " DI1_STEP_REPEAT_6 ,Step Repeat 6"
|
|
line.long 0xd0 "DI1_STP_REP_9,DI1 Step Repeat 9 Registers"
|
|
hexmask.long.word 0xd0 0.--11. 1. " DI1_STEP_REPEAT_9 ,Step Repeat 9"
|
|
line.long 0xd4 "DI1_SER_CONF,DI1 Serial Display Control Register"
|
|
bitfld.long 0xd4 28.--31. " DI1_SERIAL_LLA_PNTR_RS_R_1 ,RS 3 waveform pointer for read low level access" "1,2,3,4,5,6,7,8,9,10,11,12,?..."
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|
bitfld.long 0xd4 24.--27. " DI1_SERIAL_LLA_PNTR_RS_R_0 ,RS 2 waveform pointer for read low level access" "1,2,3,4,5,6,7,8,9,10,11,12,?..."
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|
bitfld.long 0xd4 20.--23. " DI1_SERIAL_LLA_PNTR_RS_W_1 ,RS 1 waveform pointer for write low level access" "1,2,3,4,5,6,7,8,9,10,11,12,?..."
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|
textline " "
|
|
bitfld.long 0xd4 16.--19. " DI1_SERIAL_LLA_PNTR_RS_W_0 ,RS 0 waveform pointer for write low level access" "1,2,3,4,5,6,7,8,9,10,11,12,?..."
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|
hexmask.long.byte 0xd4 8.--15. 1. " DI1_SERIAL_LATCH ,DI1 Serial Latch"
|
|
bitfld.long 0xd4 5. " DI1_LLA_SER_ACCESS ,Direct Low Level Access to Serial display" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xd4 4. " DI1_SER_CLK_POLARITY ,Serial Clock Polarity" "Not inverted,Inverted"
|
|
bitfld.long 0xd4 3. " DI1_SERIAL_DATA_POLARITY ,Serial Data Polarity" "Not inverted,Inverted"
|
|
bitfld.long 0xd4 2. " DI1_SERIAL_RS_POLARITY ,Serial RS Polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0xd4 1. " DI1_SERIAL_CS_POLARITY ,Serial Chip Select Polarity" "Not inverted,Inverted"
|
|
bitfld.long 0xd4 0. " DI1_WAIT4SERIAL ,Wait for Serial" "Not wait,Wait"
|
|
line.long 0xd8 "DI1_SSC,DI1 Special Signals Control Register"
|
|
bitfld.long 0xd8 23. " DI1_PIN17_ERM ,DI1 PIN17 error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 22. " DI1_PIN16_ERM ,DI1 PIN16 error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 21. " DI1_PIN15_ERM ,DI1 PIN15 error recovery mode" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0xd8 20. " DI1_PIN14_ERM ,DI1 PIN14 error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 19. " DI1_PIN13_ERM ,DI1 PIN13 error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 18. " DI1_PIN12_ERM ,DI1 PIN12 error recovery mode" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0xd8 17. " DI1_PIN11_ERM ,DI1 PIN11 error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 16. " DI1_CS_ERM ,DI1 CS error recovery mode" "No error,Error"
|
|
bitfld.long 0xd8 5. " DI1_WAIT_ON ,Wait On" "Continued,Held"
|
|
textline " "
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|
bitfld.long 0xd8 4. " DI1_BYTE_EN_POLARITY ,Byte Enable polarity" "Active low,Active high"
|
|
textline " "
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bitfld.long 0xd8 3. " DI1_BYTE_EN_RD_IN ,Byte Enable Read In" "R/W [17:16],W [17:16]/R [19:18]"
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bitfld.long 0xd8 0.--2. " DI1_BYTE_EN_PNTR ,Byte Enable Pointer" "Pin_11,Pin_12,Pin_13,Pin_14,Pin_15,Pin_16,Pin_17,CS pin"
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|
line.long 0xdc "DI1_POL,DI1 Polarity Register"
|
|
bitfld.long 0xdc 26. " DI1_WAIT_POLARITY ,WAIT polarity" "Active low,Active high"
|
|
bitfld.long 0xdc 25. " DI1_CS1_BYTE_EN_POLARITY ,Byte Enable associated with CS1 polarity" "Active low,Active high"
|
|
bitfld.long 0xdc 24. " DI1_CS0_BYTE_EN_POLARITY ,Byte Enable associated with CS0 polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 23. " DI1_CS1_DATA_POLARITY ,Data Polarity associated with CS1" "Active low,Active high"
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|
bitfld.long 0xdc 22. " DI1_CS1_POLARITY_17 ,DI1 output pin's polarity for CS1" "Active low,Active high"
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|
bitfld.long 0xdc 21. " DI1_CS1_POLARITY_16 ,DI1 output pin's polarity for CS1" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 20. " DI1_CS1_POLARITY_15 ,DI1 output pin's polarity for CS1" "Active low,Active high"
|
|
bitfld.long 0xdc 19. " DI1_CS1_POLARITY_14 ,DI1 output pin's polarity for CS1" "Active low,Active high"
|
|
bitfld.long 0xdc 18. " DI1_CS1_POLARITY_13 ,DI1 output pin's polarity for CS1" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 17. " DI1_CS1_POLARITY_12 ,DI1 output pin's polarity for CS1" "Active low,Active high"
|
|
bitfld.long 0xdc 16. " DI1_CS1_POLARITY_11 ,DI1 output pin's polarity for CS1" "Active low,Active high"
|
|
bitfld.long 0xdc 15. " DI1_CS0_DATA_POLARITY ,Data Polarity associated with CS0" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 14. " DI1_CS0_POLARITY_17 ,DI1 output pin's polarity for CS0" "Active low,Active high"
|
|
bitfld.long 0xdc 13. " DI1_CS0_POLARITY_16 ,DI1 output pin's polarity for CS0" "Active low,Active high"
|
|
bitfld.long 0xdc 12. " DI1_CS0_POLARITY_15 ,DI1 output pin's polarity for CS0" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 11. " DI1_CS0_POLARITY_14 ,DI1 output pin's polarity for CS0" "Active low,Active high"
|
|
bitfld.long 0xdc 10. " DI1_CS0_POLARITY_13 ,DI1 output pin's polarity for CS0" "Active low,Active high"
|
|
bitfld.long 0xdc 9. " DI1_CS0_POLARITY_12 ,DI1 output pin's polarity for CS0" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 8. " DI1_CS0_POLARITY_11 ,DI1 output pin's polarity for CS0" "Active low,Active high"
|
|
bitfld.long 0xdc 7. " DI1_DRDY_DATA_POLARITY ,Data Polarity associated with DRDY" "Active low,Active high"
|
|
bitfld.long 0xdc 6. " DI1_DRDY_POLARITY_17 ,DI1 output pin's polarity for DRDY" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 5. " DI1_DRDY_POLARITY_16 ,DI1 output pin's polarity for DRDY" "Active low,Active high"
|
|
bitfld.long 0xdc 4. " DI1_DRDY_POLARITY_15 ,DI1 output pin's polarity for DRDY" "Active low,Active high"
|
|
bitfld.long 0xdc 3. " DI1_DRDY_POLARITY_14 ,DI1 output pin's polarity for DRDY" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0xdc 2. " DI1_DRDY_POLARITY_13 ,DI1 output pin's polarity for DRDY" "Active low,Active high"
|
|
bitfld.long 0xdc 1. " DI1_DRDY_POLARITY_12 ,DI1 output pin's polarity for DRDY" "Active low,Active high"
|
|
bitfld.long 0xdc 0. " DI1_DRDY_POLARITY_11 ,DI1 output pin's polarity for DRDY" "Active low,Active high"
|
|
line.long 0xe0 "DI1_AW0,DI1 Active Window 0 Register"
|
|
bitfld.long 0xe0 28.--31. " DI1_AW_TRIG_SEL ,Selects the trigger for sending data during the display's active window" "Disabled,The same trig.,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Always on,?..."
|
|
hexmask.long.word 0xe0 16.--27. 1. " DI1_AW_HEND ,Horizontal end of the active window"
|
|
bitfld.long 0xe0 12.--15. " DI1_AW_HCOUNT_SEL ,Selects the counter that counts the horizontal position of the display's active window" "Disabled,,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Counter 6,Counter 7,Counter 8,?..."
|
|
textline " "
|
|
hexmask.long.word 0xe0 0.--11. 1. " DI1_AW_HSTART ,Horizontal start of the active window"
|
|
line.long 0xe4 "DI1_AW1,DI1 Active Window 1 Register"
|
|
hexmask.long.word 0xe4 16.--27. 1. " DI1_AW_VEND ,Vertical end of the active window"
|
|
bitfld.long 0xe4 12.--15. " DI1_AW_VCOUNT_SEL ,Selects the counter that counts the vertical position of the display's active window" "Disabled,,Counter 1,Counter 2,Counter 3,Counter 4,Counter 5,Counter 6,Counter 7,Counter 8,?..."
|
|
hexmask.long.word 0xe4 0.--11. 1. " DI1_AW_VSTART ,Vertical start of the active window"
|
|
line.long 0xe8 "DI1_SCR_CONF,DI1 Screen Configuration Register"
|
|
hexmask.long.word 0xe8 0.--11. 1. " DI1_SCREEN_HEIGHT ,Number of display rows"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "DI1_STAT,DI1 Status Register"
|
|
bitfld.long 0x00 3. " DI1_CNTR_FIFO_FULL ,DI1_CNTR_FIFO_FULL" "Not full,Full"
|
|
bitfld.long 0x00 2. " DI1_CNTR_FIFO_EMPTY ,DI1_CNTR_FIFO_EMPTY" "Not empty,Empty"
|
|
bitfld.long 0x00 1. " DI1_READ_FIFO_FULL ,DI1_READ_FIFO_FULL" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DI1_READ_FIFO_EMPTY ,DI1_READ_FIFO_EMPTY" "Not empty,Empty"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SMFC registers"
|
|
base ad:0x5e050000
|
|
width 17.
|
|
group.long 0x00++0x57
|
|
line.long 0x00 "SMFC_MAP,SMFC Mapping Register"
|
|
bitfld.long 0x00 9.--11. " MAP_CH3 ,DMASMFC channel 3 mapping bits" "CSI0 ID=0,CSI0 ID=1,CSI0 ID=2,CSI0 ID=3,CSI1 ID=0,CSI1 ID=1,CSI1 ID=2,CSI1 ID=3"
|
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bitfld.long 0x00 6.--8. " MAP_CH2 ,DMASMFC channel 2 mapping bits" "CSI0 ID=0,CSI0 ID=1,CSI0 ID=2,CSI0 ID=3,CSI1 ID=0,CSI1 ID=1,CSI1 ID=2,CSI1 ID=3"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " MAP_CH1 ,DMASMFC channel 1 mapping bits" "CSI0 ID=0,CSI0 ID=1,CSI0 ID=2,CSI0 ID=3,CSI1 ID=0,CSI1 ID=1,CSI1 ID=2,CSI1 ID=3"
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bitfld.long 0x00 0.--2. " MAP_CH0 ,DMASMFC channel 0 mapping bits" "CSI0 ID=0,CSI0 ID=1,CSI0 ID=2,CSI0 ID=3,CSI1 ID=0,CSI1 ID=1,CSI1 ID=2,CSI1 ID=3"
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line.long 0x04 "SMFC_WMC,SMFC Water Mark Control Register"
|
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bitfld.long 0x04 25.--27. " WM3_CLR ,Watermark 'clear' level of DMASMFC channel 3" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
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bitfld.long 0x04 22.--24. " WM3_SET ,Watermark 'set' level of DMASMFC channel 3" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
|
|
textline " "
|
|
bitfld.long 0x04 19.--21. " WM2_CLR ,Watermark 'clear' level of DMASMFC channel 2" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
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bitfld.long 0x04 16.--18. " WM2_SET ,Watermark 'set' level of DMASMFC channel 2" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " WM1_CLR ,Watermark 'clear' level of DMASMFC channel 1" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
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bitfld.long 0x04 6.--8. " WM1_SET ,Watermark 'set' level of DMASMFC channel 1" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
|
|
textline " "
|
|
bitfld.long 0x04 3.--5. " WM0_CLR ,Watermark 'clear' level of DMASMFC channel 0" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
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bitfld.long 0x04 0.--2. " WM0_SET ,Watermark 'set' level of DMASMFC channel 0" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
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line.long 0x08 "SMFC_BS,SMFC Burst Size Register"
|
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bitfld.long 0x08 12.--15. " BURST3_SIZE ,Burst Size of SMFCDMA channel 3" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
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bitfld.long 0x08 8.--11. " BURST2_SIZE ,Burst Size of SMFCDMA channel 2" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " BURST1_SIZE ,Burst Size of SMFCDMA channel 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
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bitfld.long 0x08 0.--3. " BURST0_SIZE ,Burst Size of SMFCDMA channel 0" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
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width 0xb
|
|
tree.end
|
|
tree "DC registers"
|
|
base ad:0x5e058000
|
|
width 18.
|
|
tree "Channel 0"
|
|
group.long 0x00++0x1b
|
|
line.long 0x00 "DC_READ_CH_CONF,DC Read Channel Configuration Register"
|
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hexmask.long.word 0x00 16.--31. 1. " TIME_OUT_VALUE ,Time out value"
|
|
bitfld.long 0x00 11. " CS_ID_3 ,Maps an asynchronous display to a chip select" "CS0,CS1"
|
|
bitfld.long 0x00 10. " CS_ID_2 ,Maps an asynchronous display to a chip select" "CS0,CS1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CS_ID_1 ,Maps an asynchronous display to a chip select" "CS0,CS1"
|
|
bitfld.long 0x00 8. " CS_ID_0 ,Maps an asynchronous display to a chip select" "CS0,CS1"
|
|
bitfld.long 0x00 6. " CHAN_MASK_DEFAULT_0 ,Event mask bit for the read channel" "High. prior. used/rest masked,All used/Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " W_SIZE_0 ,Word Size" "8 bits,16 LSB bits,24 MSB bits,32 bits"
|
|
bitfld.long 0x00 2.--3. " PROG_DISP_ID_0 ,The field defines which one of the 4 displays can be read" "0,1,2,3"
|
|
bitfld.long 0x00 1. " PROG_DI_ID_0 ,This bit select the DI which a read transaction can be performed to" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RD_CHANNEL_EN ,Enables the read channel" "Disabled,Enabled"
|
|
line.long 0x04 "DC_READ_CH_ADDR,DC Read Channel Start Address Register"
|
|
hexmask.long 0x04 0.--28. 1. " ST_ADDR_0 ,Start address within the display's memory space (Channel 0)"
|
|
line.long 0x08 "DC_RL0_CH_0,DC Routine Link Register 0 Channel 0"
|
|
hexmask.long.byte 0x08 24.--31. 1. " COD_NL_START_CHAN_0 ,Pointer to the address within the microcode memory (NL)"
|
|
bitfld.long 0x08 16.--19. " COD_NL_PRIORITY_CHAN_0 ,Priority of the new line (NL) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x08 8.--15. 1. " COD_NF_START_CHAN_0 ,Pointer to the address within the microcode memory (NF)"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " COD_NF_PRIORITY_CHAN_0 ,Priority of the new frame (NF) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x0c "DC_RL1_CH_0,DC Routine Link Register 1 Channel 0"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " COD_NFIELD_START_CHAN_0 ,Pointer to the address within the microcode memory (new field)"
|
|
bitfld.long 0x0C 16.--19. " COD_NFIELD_PRIORITY_CHAN_0 ,Priority of the new field event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x0C 8.--15. 1. " COD_EOF_START_CHAN_0 ,Pointer to the address within the microcode memory (EOF)"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " COD_EOF_PRIORITY_CHAN_0 ,Priority of the end-of-frame (EOF) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x10 "DC_RL2_CH_0,DC Routine Link Register 2 Channel 0"
|
|
hexmask.long.byte 0x10 24.--31. 1. " COD_EOFIELD_START_CHAN_0 ,Pointer to the address within the microcode memory (end-of-field)"
|
|
bitfld.long 0x10 16.--19. " COD_EOFIELD_PRIORITY_CHAN_0 ,Priority of the end-of-field event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x10 8.--15. 1. " COD_EOL_START_CHAN_0 ,Pointer to the address within the microcode memory (EOL)"
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " COD_EOL_PRIORITY_CHAN_0 ,Priority of the end-of-line event (EOL) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x14 "DC_RL3_CH_0,DC Routine Link Register 3 Channel 0"
|
|
hexmask.long.byte 0x14 24.--31. 1. " COD_NEW_CHAN_START_CHAN_0 ,Pointer to the address within the microcode memory (new channel)"
|
|
bitfld.long 0x14 16.--19. " COD_NEW_CHAN_PRIORITY_CHAN_0 ,Priority of the new channel event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x14 8.--15. 1. " COD_NEW_ADDR_START_CHAN_0 ,Pointer to the address within the microcode memory (new address)"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " COD_NEW_ADDR_PRIORITY_CHAN_0 ,Priority of the new address event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x18 "DC_RL4_CH_0,DC Routine Link Register 4 Channel 0"
|
|
hexmask.long.byte 0x18 8.--15. 1. " COD_NEW_DATA_START_CHAN_0 ,Pointer to the address within the microcode memory (new data)"
|
|
bitfld.long 0x18 0.--3. " COD_NEW_DATA_PRIORITY_CHAN_0 ,Priority of the new data event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x1c++0x1b
|
|
line.long 0x00 "DC_WR_CH_CONF_1,DC Write Channel 1 Configuration Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " PROG_START_TIME_1 ,Delay between display's vertical synchronization pulse and the start time point of DC's channel 1 window"
|
|
bitfld.long 0x00 9. " FIELD_MODE_1 ,Field mode bit for channel #1" "Frame,Field"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHAN_MASK_DEFAULT_1 ,Event mask bit for channel #1" "High. prior. used/rest masked,All used/Not masked"
|
|
bitfld.long 0x00 5.--7. " PROG_CHAN_TYP_1 ,This field define the mode of operation of channel #1" "Disabled,,,,Normal without anti-tearing,Normal with anti-tearing,,Add. cmd. ch. added"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " PROG_DISP_ID_1 ,The field defines which one of the 4 displays is associated with channel #1" "0,1,2,3"
|
|
bitfld.long 0x00 2. " PROG_DI_ID_1 ,Select the DI which a transaction associated with channel #1 can be performed to" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " W_SIZE_1 ,Word Size associated with channel #1" "8 bits,16 LSB,24 MSB,32 bits"
|
|
line.long 0x04 "DC_WR_CH_ADDR_1,DC Write Channel 1 Configuration Register"
|
|
hexmask.long 0x04 0.--28. 1. " ST_ADDR_1 ,Start address within the display's memory space (Channel 1)"
|
|
line.long 0x08 "DC_RL0_CH_1,DC Routine Link Register 0 Channel 1"
|
|
hexmask.long.byte 0x08 24.--31. 1. " COD_NL_START_CHAN_1 ,Pointer to the address within the microcode memory (NL)"
|
|
bitfld.long 0x08 16.--19. " COD_NL_PRIORITY_CHAN_1 ,Priority of the new line (NL) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x08 8.--15. 1. " COD_NF_START_CHAN_1 ,Pointer to the address within the microcode memory (NF)"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " COD_NF_PRIORITY_CHAN_1 ,Priority of the new frame (NF) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x0c "DC_RL1_CH_1,DC Routine Link Register 1 Channel 1"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " COD_NFIELD_START_CHAN_1 ,Pointer to the address within the microcode memory (new field)"
|
|
bitfld.long 0x0C 16.--19. " COD_NFIELD_PRIORITY_CHAN_1 ,Priority of the new field event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x0C 8.--15. 1. " COD_EOF_START_CHAN_1 ,Pointer to the address within the microcode memory (EOF)"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " COD_EOF_PRIORITY_CHAN_1 ,Priority of the end-of-frame (EOF) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x10 "DC_RL2_CH_1,DC Routine Link Register 2 Channel 1"
|
|
hexmask.long.byte 0x10 24.--31. 1. " COD_EOFIELD_START_CHAN_1 ,Pointer to the address within the microcode memory (end-of-field)"
|
|
bitfld.long 0x10 16.--19. " COD_EOFIELD_PRIORITY_CHAN_1 ,Priority of the end-of-field event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x10 8.--15. 1. " COD_EOL_START_CHAN_1 ,Pointer to the address within the microcode memory (EOL)"
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " COD_EOL_PRIORITY_CHAN_1 ,Priority of the end of line (EOL) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x14 "DC_RL3_CH_1,DC Routine Link Register 3 Channel 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. " COD_NEW_CHAN_START_CHAN_1 ,Pointer to the address within the microcode memory (new channel)"
|
|
bitfld.long 0x14 16.--19. " COD_NEW_CHAN_PRIORITY_CHAN_1 ,Priority of the new channel event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x14 8.--15. 1. " COD_NEW_ADDR_START_CHAN_1 ,Pointer to the address within the microcode memory (new address)"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " COD_NEW_ADDR_PRIORITY_CHAN_1 ,Priority of the new address event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x18 "DC_RL4_CH_1,DC Routine Link Register 4 Channel 1"
|
|
hexmask.long.byte 0x18 8.--15. 1. " COD_NEW_DATA_START_CHAN_1 ,Pointer to the address within the microcode memory (new data)"
|
|
bitfld.long 0x18 0.--3. " COD_NEW_DATA_PRIORITY_CHAN_1 ,Priority of the new data event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x38++0x1b
|
|
line.long 0x00 "DC_WR_CH_CONF_2,DC Write Channel 2 Configuration Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " PROG_START_TIME_2 ,Delay between display's vertical synchronization pulse and the start time point of DC's channel 2 window"
|
|
bitfld.long 0x00 8. " CHAN_MASK_DEFAULT_2 ,Event mask bit for channel #2" "High. prior. used/rest masked,All used/Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " PROG_CHAN_TYP_2 ,Mode of operation of channel #2" "Disabled,,,,Normal without anti-tearing,Normal with anti-tearing,,Add. cmd. ch. added"
|
|
bitfld.long 0x00 3.--4. " PROG_DISP_ID_2 ,The field defines which one of the 4 displays is associated with channel #2" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PROG_DI_ID_2 ,Select the DI which a transaction associated with channel #2 can be performed to" "0,1"
|
|
bitfld.long 0x00 0.--1. " W_SIZE_2 ,Word Size" "8 bits,16 LSB,24 MSB,32 bits"
|
|
textline " "
|
|
line.long 0x04 "DC_WR_CH_ADDR_2,DC Write Channel 2 Configuration Register"
|
|
hexmask.long 0x04 0.--28. 1. " ST_ADDR_2 ,Start address within the display's memory space (Channel 2)"
|
|
line.long 0x08 "DC_RL0_CH_2,DC Routine Link Register 0 Channel 2"
|
|
hexmask.long.byte 0x08 24.--31. 1. " COD_NL_START_CHAN_2 ,Pointer to the address within the microcode memory (NL)"
|
|
bitfld.long 0x08 16.--19. " COD_NL_PRIORITY_CHAN_2 ,Priority of the new line (NL) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x08 8.--15. 1. " COD_NF_START_CHAN_2 ,Pointer to the address within the microcode memory (NF)"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " COD_NF_PRIORITY_CHAN_2 ,Priority of the new frame (NF) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x0c "DC_RL1_CH_2,DC Routine Link Register 1 Channel 2"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " COD_NFIELD_START_CHAN_2 ,Pointer to the address within the microcode memory (new field)"
|
|
bitfld.long 0x0C 16.--19. " COD_NFIELD_PRIORITY_CHAN_2 ,Priority of the new field event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x0C 8.--15. 1. " COD_EOF_START_CHAN_2 ,Pointer to the address within the microcode memory (EOF)"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " COD_EOF_PRIORITY_CHAN_2 ,Priority of the end-of-frame (EOF) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x10 "DC_RL2_CH_2,DC Routine Link Register 2 Channel 2"
|
|
hexmask.long.byte 0x10 24.--31. 1. " COD_EOFIELD_START_CHAN_2 ,Pointer to the address within the microcode memory (end-of-field)"
|
|
bitfld.long 0x10 16.--19. " COD_EOFIELD_PRIORITY_CHAN_2 ,Priority of the end-of-field event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x10 8.--15. 1. " COD_EOL_START_CHAN_2 ,Pointer to the address within the microcode memory (EOL)"
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " COD_EOL_PRIORITY_CHAN_2 ,Priority of the end of line (EOL) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x14 "DC_RL3_CH_2,DC Routine Link Register 3 Channel 2"
|
|
hexmask.long.byte 0x14 24.--31. 1. " COD_NEW_CHAN_START_CHAN_2 ,Pointer to the address within the microcode memory (new channel)"
|
|
bitfld.long 0x14 16.--19. " COD_NEW_CHAN_PRIORITY_CHAN_2 ,Priority of the new channel event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x14 8.--15. 1. " COD_NEW_ADDR_START_CHAN_2 ,Pointer to the address within the microcode memory (new address)"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " COD_NEW_ADDR_PRIORITY_CHAN_2 ,Priority of the new address event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x18 "DC_RL4_CH_2,DC Routine Link Register 4 Channel 2"
|
|
hexmask.long.byte 0x18 8.--15. 1. " COD_NEW_DATA_START_CHAN_2 ,Pointer to the address within the microcode memory (new data)"
|
|
bitfld.long 0x18 0.--3. " COD_NEW_DATA_PRIORITY_CHAN_2 ,Priority of the new data event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DC_CMD_CH_CONF_3,DC Command Channel 3 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " COD_CMND_START_CHAN_RS1_3 ,Pointer to the address within the microcode memory (command start event)"
|
|
hexmask.long.byte 0x00 8.--15. 1. " COD_CMND_START_CHAN_RS0_3 ,Pointer to the address within the microcode memory (command start event)"
|
|
bitfld.long 0x00 0.--1. " W_SIZE_3 ,Word Size associated with channel #3" "8 bits,16 LSB,24 MSB,32 bits"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DC_CMD_CH_CONF_4,DC Command Channel 4 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " COD_CMND_START_CHAN_RS1_4 ,Pointer to the address within the microcode memory (command start event)"
|
|
hexmask.long.byte 0x00 8.--15. 1. " COD_CMND_START_CHAN_RS0_4 ,Pointer to the address within the microcode memory (command start event)"
|
|
bitfld.long 0x00 0.--1. " W_SIZE_4 ,Word Size associated with channel #4" "8 bits,16 LSB,24 MSB,32 bits"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x5c++0x1b
|
|
line.long 0x00 "DC_WR_CH_CONF_5,DC Write Channel 5 Configuration Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " PROG_START_TIME_5 ,Delay between display's vertical synchronization pulse and the start time point of DC's channel 5 window"
|
|
bitfld.long 0x00 9. " FIELD_MODE_5 ,Field mode bit for channel #5" "Frame,Field"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CHAN_MASK_DEFAULT_5 ,Event mask bit for channel #5" "High. prior. used/rest masked,All used/Not masked"
|
|
bitfld.long 0x00 5.--7. " PROG_CHAN_TYP_5 ,Mode of operation of channel #5" "Disabled,,,,Normal without anti-tearing,Normal with anti-tearing,,Add. cmd. ch. added"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " PROG_DISP_ID_5 ,Defines which one of the 4 displays is associated with channel #5" "0,1,2,3"
|
|
bitfld.long 0x00 2. " PROG_DI_ID_5 ,Select the DI which a transaction associated with channel #5 can be performed to" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " W_SIZE_5 ,Word Size associated with channel #5" "8 bits,16 LSB,24 MSB,32 bits"
|
|
textline " "
|
|
line.long 0x04 "DC_WR_CH_ADDR_5,DC Write Channel 5 Configuration Register"
|
|
hexmask.long 0x04 0.--28. 1. " ST_ADDR_5 ,Start address within the display's memory space (Channel 5)"
|
|
line.long 0x08 "DC_RL0_CH_5,DC Routine Link Register 0 Channel 5"
|
|
hexmask.long.byte 0x08 24.--31. 1. " COD_NL_START_CHAN_5 ,Pointer to the address within the microcode memory (NL)"
|
|
bitfld.long 0x08 16.--19. " COD_NL_PRIORITY_CHAN_5 ,Priority of the new line (NL) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x08 8.--15. 1. " COD_NF_START_CHAN_5 ,Pointer to the address within the microcode memory (NF)"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " COD_NF_PRIORITY_CHAN_5 ,Priority of the new frame (NF) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x0c "DC_RL1_CH_5,DC Routine Link Register 1 Channel 5"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " COD_NFIELD_START_CHAN_5 ,Pointer to the address within the microcode memory (new field)"
|
|
bitfld.long 0x0C 16.--19. " COD_NFIELD_PRIORITY_CHAN_5 ,Priority of the new field event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x0C 8.--15. 1. " COD_EOF_START_CHAN_5 ,Pointer to the address within the microcode memory (EOF)"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " COD_EOF_PRIORITY_CHAN_5 ,Priority of the end-of-frame (EOF) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x10 "DC_RL2_CH_5,DC Routine Link Register 2 Channel 5"
|
|
hexmask.long.byte 0x10 24.--31. 1. " COD_EOFIELD_START_CHAN_5 ,Pointer to the address within the microcode memory (end-of-field)"
|
|
bitfld.long 0x10 16.--19. " COD_EOFIELD_PRIORITY_CHAN_5 ,Priority of the end-of-field event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x10 8.--15. 1. " COD_EOL_START_CHAN_5 ,Pointer to the address within the microcode memory (EOL)"
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " COD_EOL_PRIORITY_CHAN_5 ,Priority of the end of line (EOL) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x14 "DC_RL3_CH_5,DC Routine Link Register 3 Channel 5"
|
|
hexmask.long.byte 0x14 24.--31. 1. " COD_NEW_CHAN_START_CHAN_5 ,Pointer to the address within the microcode memory (new channel)"
|
|
bitfld.long 0x14 16.--19. " COD_NEW_CHAN_PRIORITY_CHAN_5 ,Priority of the new channel event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x14 8.--15. 1. " COD_NEW_ADDR_START_CHAN_5 ,Pointer to the address within the microcode memory (new address)"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " COD_NEW_ADDR_PRIORITY_CHAN_5 ,Priority of the new address event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x18 "DC_RL4_CH_5,DC Routine Link Register 4 Channel 5"
|
|
hexmask.long.byte 0x18 8.--15. 1. " COD_NEW_DATA_START_CHAN_5 ,Pointer to the address within the microcode memory (new data)"
|
|
bitfld.long 0x18 0.--3. " COD_NEW_DATA_PRIORITY_CHAN_5 ,Priority of the new data event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0x78++0x1b
|
|
line.long 0x00 "DC_WR_CH_CONF_6,DC Write Channel 6 Configuration Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " PROG_START_TIME_6 ,Delay between display's vertical synchronization pulse and the start time point of DC's channel 6 window"
|
|
bitfld.long 0x00 8. " CHAN_MASK_DEFAULT_6 ,Event mask bit for channel #6" "High. prior. used/rest masked,All used/Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " PROG_CHAN_TYP_6 ,Mode of operation of channel #6" "Disabled,,,,Normal without anti-tearing,Normal with anti-tearing,,Add. cmd. ch. added"
|
|
bitfld.long 0x00 3.--4. " PROG_DISP_ID_6 ,Defines which one of the 4 displays is associated with channel #6" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PROG_DI_ID_6 ,Select the DI which a transaction associated with channel #6 can be performed to" "0,1"
|
|
bitfld.long 0x00 0.--1. " W_SIZE_6 ,Word Size associated with channel #6" "8 bits,16 LSB,24 MSB,32 bits"
|
|
textline " "
|
|
line.long 0x04 "DC_WR_CH_ADDR_6,DC Write Channel 6 Configuration Register"
|
|
hexmask.long 0x04 0.--28. 1. " ST_ADDR_6 ,Start address within the display's memory space (Channel 6)"
|
|
line.long 0x08 "DC_RL0_CH_6,DC Routine Link Register 0 Channel 6"
|
|
hexmask.long.byte 0x08 24.--31. 1. " COD_NL_START_CHAN_6 ,Pointer to the address within the microcode memory (NL)"
|
|
bitfld.long 0x08 16.--19. " COD_NL_PRIORITY_CHAN_6 ,Priority of the new line (NL) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x08 8.--15. 1. " COD_NF_START_CHAN_6 ,Pointer to the address within the microcode memory (NF)"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " COD_NF_PRIORITY_CHAN_6 ,Priority of the new frame (NF) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x0c "DC_RL1_CH_6,DC Routine Link Register 1 Channel 6"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " COD_NFIELD_START_CHAN_6 ,Pointer to the address within the microcode memory (new field)"
|
|
bitfld.long 0x0C 16.--19. " COD_NFIELD_PRIORITY_CHAN_6 ,Priority of the new field event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x0C 8.--15. 1. " COD_EOF_START_CHAN_6 ,Pointer to the address within the microcode memory (EOF)"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " COD_EOF_PRIORITY_CHAN_6 ,Priority of the end-of-frame (EOF) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x10 "DC_RL2_CH_6,DC Routine Link Register 2 Channel 6"
|
|
hexmask.long.byte 0x10 24.--31. 1. " COD_EOFIELD_START_CHAN_6 ,Pointer to the address within the microcode memory (end-of-field)"
|
|
bitfld.long 0x10 16.--19. " COD_EOFIELD_PRIORITY_CHAN_6 ,Priority of the end-of-field event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x10 8.--15. 1. " COD_EOL_START_CHAN_6 ,Pointer to the address within the microcode memory (EOL)"
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " COD_EOL_PRIORITY_CHAN_6 ,Priority of the end of line (EOL) event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x14 "DC_RL3_CH_6,DC Routine Link Register 3 Channel 6"
|
|
hexmask.long.byte 0x14 24.--31. 1. " COD_NEW_CHAN_START_CHAN_6 ,Pointer to the address within the microcode memory (new channel)"
|
|
bitfld.long 0x14 16.--19. " COD_NEW_CHAN_PRIORITY_CHAN_6 ,Priority of the new channel event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
hexmask.long.byte 0x14 8.--15. 1. " COD_NEW_ADDR_START_CHAN_6 ,Pointer to the address within the microcode memory (new address)"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " COD_NEW_ADDR_PRIORITY_CHAN_6 ,Priority of the new address event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x18 "DC_RL4_CH_6,DC Routine Link Register 4 Channel 6"
|
|
hexmask.long.byte 0x18 8.--15. 1. " COD_NEW_DATA_START_CHAN_6 ,Pointer to the address within the microcode memory (new data)"
|
|
bitfld.long 0x18 0.--3. " COD_NEW_DATA_PRIORITY_CHAN_6 ,Priority of the new data event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
tree.end
|
|
tree "Channel 8"
|
|
group.long 0x94++0x1f
|
|
line.long 0x00 "DC_WR_CH_CONF1_8,DC Write Channel 8 Configuration 1 Register"
|
|
bitfld.long 0x00 3.--4. " MCU_DISP_ID_8 ,Defines which one of the 4 displays is associated with channel #8" "0,1,2,3"
|
|
bitfld.long 0x00 2. " CHAN_MASK_DEFAULT_8 ,Event mask bit for channel #8" "High. prior. used/rest masked,All used/Not masked"
|
|
bitfld.long 0x00 0.--1. " W_SIZE_8 ,Word Size associated with channel #8" "8 bits,16 LSB,24 MSB,32 bits"
|
|
line.long 0x04 "DC_WR_CH_CONF2_8,DC Write Channel 8 Configuration 2 Register"
|
|
hexmask.long 0x04 0.--28. 1. " NEW_ADDR_SPACE_SA_8 ,Base address of the second region accessible on the display"
|
|
line.long 0x08 "DC_RL1_CH_8,DC Routine Link Register 1 Channel 8"
|
|
hexmask.long.byte 0x08 24.--31. 1. " COD_NEW_ADDR_START_CHAN_W_8_1 ,Pointer to the address within the microcode memory (new address/second region)"
|
|
hexmask.long.byte 0x08 8.--15. 1. " COD_NEW_ADDR_START_CHAN_W_8_0 ,Pointer to the address within the microcode memory (new address/first region)"
|
|
bitfld.long 0x08 0.--3. " COD_NEW_ADDR_PRIORITY_CHAN_8 ,Priority of the new address event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x0c "DC_RL2_CH_8,DC Routine Link Register 2 Channel 8"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " COD_NEW_CHAN_START_CHAN_W_8_1 ,Pointer to the address within the microcode memory (new channel/second region)"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " COD_NEW_CHAN_START_CHAN_W_8_0 ,Pointer to the address within the microcode memory (new channel/second region)"
|
|
bitfld.long 0x0C 0.--3. " COD_NEW_CHAN_PRIORITY_CHAN_8 ,Priority of the new channel event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x10 "DC_RL3_CH_8,DC Routine Link Register 3 Channel 8"
|
|
hexmask.long.byte 0x10 24.--31. 1. " COD_NEW_DATA_START_CHAN_W_8_1 ,Pointer to the address within the microcode memory (new data/second region)"
|
|
hexmask.long.byte 0x10 8.--15. 1. " COD_NEW_DATA_START_CHAN_W_8_0 ,Pointer to the address within the microcode memory (new data/first region)"
|
|
bitfld.long 0x10 0.--3. " COD_NEW_DATA_PRIORITY_CHAN_8 ,Priority of the new data event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x14 "DC_RL4_CH_8,DC Routine Link Register 4 Channel 8"
|
|
hexmask.long.byte 0x14 24.--31. 1. " COD_NEW_ADDR_START_CHAN_R_8_1 ,Pointer to the address within the microcode memory (new address/second region)"
|
|
hexmask.long.byte 0x14 8.--15. 1. " OD_NEW_ADDR_START_CHAN_R_8_0 ,Pointer to the address within the microcode memory (new address/first region)"
|
|
line.long 0x18 "DC_RL5_CH_8,DC Routine Link Register 5 Channel 8"
|
|
hexmask.long.byte 0x18 24.--31. 1. " COD_NEW_CHAN_START_CHAN_R_8_1 ,Pointer to the address within the microcode memory (new channel/second region)"
|
|
hexmask.long.byte 0x18 8.--15. 1. " COD_NEW_CHAN_START_CHAN_R_8_0 ,Pointer to the address within the microcode memory (new channel/first region)"
|
|
line.long 0x1c "DC_RL6_CH_8,DC Routine Link Register 6 Channel 8"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " COD_NEW_DATA_START_CHAN_R_8_1 ,Pointer to the address within the microcode memory (new data/second region)"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " COD_NEW_DATA_START_CHAN_R_8_0 ,Pointer to the address within the microcode memory (new data/first region)"
|
|
tree.end
|
|
tree "Channel 9"
|
|
group.long 0xb4++0x1f
|
|
line.long 0x00 "DC_WR_CH_CONF1_9,DC Write Channel 9 Configuration 1 Register"
|
|
bitfld.long 0x00 3.--4. " MCU_DISP_ID_9 ,Defines which one of the 4 displays is associated with channel #9" "0,1,2,3"
|
|
bitfld.long 0x00 2. " CHAN_MASK_DEFAULT_9 ,Event mask bit for channel #9" "High. prior. used/rest masked,All used/Not masked"
|
|
bitfld.long 0x00 0.--1. " W_SIZE_9 ,Word Size associated with channel #9" "8 bits,16 LSB,24 MSB,32 bits"
|
|
line.long 0x04 "DC_WR_CH_CONF2_9,DC Write Channel 9 Configuration 2 Register"
|
|
hexmask.long 0x04 0.--28. 1. " NEW_ADDR_SPACE_SA_9 ,Base address of the second region accessible on the display"
|
|
line.long 0x08 "DC_RL1_CH_9,DC Routine Link Register 1 Channel 9"
|
|
hexmask.long.byte 0x08 24.--31. 1. " COD_NEW_ADDR_START_CHAN_W_9_1 ,Pointer to the address within the microcode memory (new address/second region)"
|
|
hexmask.long.byte 0x08 8.--15. 1. " COD_NEW_ADDR_START_CHAN_W_9_0 ,Pointer to the address within the microcode memory (new address/first region)"
|
|
bitfld.long 0x08 0.--3. " COD_NEW_ADDR_PRIORITY_CHAN_9 ,Priority of the new address event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x0c "DC_RL2_CH_9,DC Routine Link Register 2 Channel 9"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " COD_NEW_CHAN_START_CHAN_W_9_1 ,Pointer to the address within the microcode memory (new channel/second region)"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " COD_NEW_CHAN_START_CHAN_W_9_0 ,Pointer to the address within the microcode memory (new channel/second region)"
|
|
bitfld.long 0x0C 0.--3. " COD_NEW_CHAN_PRIORITY_CHAN_9 ,Priority of the new channel event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x10 "DC_RL3_CH_9,DC Routine Link Register 3 Channel 9"
|
|
hexmask.long.byte 0x10 24.--31. 1. " COD_NEW_DATA_START_CHAN_W_9_1 ,Pointer to the address within the microcode memory (new data/second region)"
|
|
hexmask.long.byte 0x10 8.--15. 1. " COD_NEW_DATA_START_CHAN_W_9_0 ,Pointer to the address within the microcode memory (new data/first region)"
|
|
bitfld.long 0x10 0.--3. " COD_NEW_DATA_PRIORITY_CHAN_9 ,Priority of the new data event" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
|
|
line.long 0x14 "DC_RL4_CH_9,DC Routine Link Register 4 Channel 9"
|
|
hexmask.long.byte 0x14 24.--31. 1. " COD_NEW_ADDR_START_CHAN_R_9_1 ,Pointer to the address within the microcode memory (new address/second region)"
|
|
hexmask.long.byte 0x14 8.--15. 1. " OD_NEW_ADDR_START_CHAN_R_9_0 ,Pointer to the address within the microcode memory (new address/first region)"
|
|
line.long 0x18 "DC_RL5_CH_9,DC Routine Link Register 5 Channel 9"
|
|
hexmask.long.byte 0x18 24.--31. 1. " COD_NEW_CHAN_START_CHAN_R_9_1 ,Pointer to the address within the microcode memory (new channel/second region)"
|
|
hexmask.long.byte 0x18 8.--15. 1. " COD_NEW_CHAN_START_CHAN_R_9_0 ,Pointer to the address within the microcode memory (new channel/first region)"
|
|
line.long 0x1c "DC_RL6_CH_9,DC Routine Link Register 6 Channel 9"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " COD_NEW_DATA_START_CHAN_R_9_1 ,Pointer to the address within the microcode memory (new data/second region)"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " COD_NEW_DATA_START_CHAN_R_9_0 ,Pointer to the address within the microcode memory (new data/first region)"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xd4++0x03
|
|
line.long 0x00 "DC_GEN,DC General Register"
|
|
bitfld.long 0x00 24. " DC_BK_EN ,Cursor blinking enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DC_BKDIV ,Blinking Rate"
|
|
bitfld.long 0x00 8. " DC_CH5_TYPE ,Channel 5 is used for synchronous flow" "Synchronous,Asynchronous"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYNC_PRIORITY_1 ,Sets the priority of channel #1" "Low,High"
|
|
bitfld.long 0x00 6. " SYNC_PRIORITY_5 ,Sets the priority of channel #5" "Low,High"
|
|
bitfld.long 0x00 5. " MASK4CHAN_5 ,Mask for channel #5" "DC,DP"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MASK_EN ,Enable of the mask channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " SYNC_1_6 ,Channel 1 of the DC async/sync flow handle" "Async flow,,Sync flow,?..."
|
|
if (((per.long(ad:0x5e058000+0xd8+0x0))&0x40)==0x00)
|
|
group.long (0xd8+0x0)++0x03
|
|
line.long 0x00 "DC_DISP_CONF1_0,DC Display Configuration 1 Register 0"
|
|
bitfld.long 0x00 7. " DISP_RD_VALUE_PTR_0 ,Holds a pointer to the corresponding set of mask and value" "VALUE_0 & MASK_0,VALUE_1 & MASK_1"
|
|
bitfld.long 0x00 6. " MCU_ACC_LB_MASK_0 ,Comparing mode" "Compared/ignored ADDR[0],Fully compared"
|
|
bitfld.long 0x00 4.--5. " ADDR_BE_L_INC_0 ,Increment mode when the latest access was done with some of the byte enable signals are low" "No increment,,2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ADDR_INCREMENT_0 ,Increment step for auto increment mode" "1,2,3,4"
|
|
bitfld.long 0x00 0.--1. " DISP_TYP_0 ,Type of the display" "Serial accesses,,Parallel/without byte_enable,Parallel/with byte_enable"
|
|
else
|
|
group.long (0xd8+0x0)++0x03
|
|
line.long 0x00 "DC_DISP_CONF1_0,DC Display Configuration 1 Register 0"
|
|
bitfld.long 0x00 7. " DISP_RD_VALUE_PTR_0 ,Holds a pointer to the corresponding set of mask and value" "VALUE_0 & MASK_0,VALUE_1 & MASK_1"
|
|
bitfld.long 0x00 6. " MCU_ACC_LB_MASK_0 ,Comparing mode" "Compared/ignored ADDR[0],Fully compared"
|
|
bitfld.long 0x00 4.--5. " ADDR_BE_L_INC_0 ,Increment mode when the latest access was done with some of the byte enable signals are low" "No increment,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ADDR_INCREMENT_0 ,Increment step for auto increment mode" "1,2,3,4"
|
|
bitfld.long 0x00 0.--1. " DISP_TYP_0 ,Type of the display" "Serial accesses,,Parallel/without byte_enable,Parallel/with byte_enable"
|
|
endif
|
|
if (((per.long(ad:0x5e058000+0xd8+0x4))&0x40)==0x00)
|
|
group.long (0xd8+0x4)++0x03
|
|
line.long 0x00 "DC_DISP_CONF1_1,DC Display Configuration 1 Register 1"
|
|
bitfld.long 0x00 7. " DISP_RD_VALUE_PTR_1 ,Holds a pointer to the corresponding set of mask and value" "VALUE_0 & MASK_0,VALUE_1 & MASK_1"
|
|
bitfld.long 0x00 6. " MCU_ACC_LB_MASK_1 ,Comparing mode" "Compared/ignored ADDR[0],Fully compared"
|
|
bitfld.long 0x00 4.--5. " ADDR_BE_L_INC_1 ,Increment mode when the latest access was done with some of the byte enable signals are low" "No increment,,2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ADDR_INCREMENT_1 ,Increment step for auto increment mode" "1,2,3,4"
|
|
bitfld.long 0x00 0.--1. " DISP_TYP_1 ,Type of the display" "Serial accesses,,Parallel/without byte_enable,Parallel/with byte_enable"
|
|
else
|
|
group.long (0xd8+0x4)++0x03
|
|
line.long 0x00 "DC_DISP_CONF1_1,DC Display Configuration 1 Register 1"
|
|
bitfld.long 0x00 7. " DISP_RD_VALUE_PTR_1 ,Holds a pointer to the corresponding set of mask and value" "VALUE_0 & MASK_0,VALUE_1 & MASK_1"
|
|
bitfld.long 0x00 6. " MCU_ACC_LB_MASK_1 ,Comparing mode" "Compared/ignored ADDR[0],Fully compared"
|
|
bitfld.long 0x00 4.--5. " ADDR_BE_L_INC_1 ,Increment mode when the latest access was done with some of the byte enable signals are low" "No increment,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ADDR_INCREMENT_1 ,Increment step for auto increment mode" "1,2,3,4"
|
|
bitfld.long 0x00 0.--1. " DISP_TYP_1 ,Type of the display" "Serial accesses,,Parallel/without byte_enable,Parallel/with byte_enable"
|
|
endif
|
|
if (((per.long(ad:0x5e058000+0xd8+0x8))&0x40)==0x00)
|
|
group.long (0xd8+0x8)++0x03
|
|
line.long 0x00 "DC_DISP_CONF1_2,DC Display Configuration 1 Register 2"
|
|
bitfld.long 0x00 7. " DISP_RD_VALUE_PTR_2 ,Holds a pointer to the corresponding set of mask and value" "VALUE_0 & MASK_0,VALUE_1 & MASK_1"
|
|
bitfld.long 0x00 6. " MCU_ACC_LB_MASK_2 ,Comparing mode" "Compared/ignored ADDR[0],Fully compared"
|
|
bitfld.long 0x00 4.--5. " ADDR_BE_L_INC_2 ,Increment mode when the latest access was done with some of the byte enable signals are low" "No increment,,2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ADDR_INCREMENT_2 ,Increment step for auto increment mode" "1,2,3,4"
|
|
bitfld.long 0x00 0.--1. " DISP_TYP_2 ,Type of the display" "Serial accesses,,Parallel/without byte_enable,Parallel/with byte_enable"
|
|
else
|
|
group.long (0xd8+0x8)++0x03
|
|
line.long 0x00 "DC_DISP_CONF1_2,DC Display Configuration 1 Register 2"
|
|
bitfld.long 0x00 7. " DISP_RD_VALUE_PTR_2 ,Holds a pointer to the corresponding set of mask and value" "VALUE_0 & MASK_0,VALUE_1 & MASK_1"
|
|
bitfld.long 0x00 6. " MCU_ACC_LB_MASK_2 ,Comparing mode" "Compared/ignored ADDR[0],Fully compared"
|
|
bitfld.long 0x00 4.--5. " ADDR_BE_L_INC_2 ,Increment mode when the latest access was done with some of the byte enable signals are low" "No increment,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ADDR_INCREMENT_2 ,Increment step for auto increment mode" "1,2,3,4"
|
|
bitfld.long 0x00 0.--1. " DISP_TYP_2 ,Type of the display" "Serial accesses,,Parallel/without byte_enable,Parallel/with byte_enable"
|
|
endif
|
|
if (((per.long(ad:0x5e058000+0xd8+0xC))&0x40)==0x00)
|
|
group.long (0xd8+0xC)++0x03
|
|
line.long 0x00 "DC_DISP_CONF1_3,DC Display Configuration 1 Register 3"
|
|
bitfld.long 0x00 7. " DISP_RD_VALUE_PTR_3 ,Holds a pointer to the corresponding set of mask and value" "VALUE_0 & MASK_0,VALUE_1 & MASK_1"
|
|
bitfld.long 0x00 6. " MCU_ACC_LB_MASK_3 ,Comparing mode" "Compared/ignored ADDR[0],Fully compared"
|
|
bitfld.long 0x00 4.--5. " ADDR_BE_L_INC_3 ,Increment mode when the latest access was done with some of the byte enable signals are low" "No increment,,2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ADDR_INCREMENT_3 ,Increment step for auto increment mode" "1,2,3,4"
|
|
bitfld.long 0x00 0.--1. " DISP_TYP_3 ,Type of the display" "Serial accesses,,Parallel/without byte_enable,Parallel/with byte_enable"
|
|
else
|
|
group.long (0xd8+0xC)++0x03
|
|
line.long 0x00 "DC_DISP_CONF1_3,DC Display Configuration 1 Register 3"
|
|
bitfld.long 0x00 7. " DISP_RD_VALUE_PTR_3 ,Holds a pointer to the corresponding set of mask and value" "VALUE_0 & MASK_0,VALUE_1 & MASK_1"
|
|
bitfld.long 0x00 6. " MCU_ACC_LB_MASK_3 ,Comparing mode" "Compared/ignored ADDR[0],Fully compared"
|
|
bitfld.long 0x00 4.--5. " ADDR_BE_L_INC_3 ,Increment mode when the latest access was done with some of the byte enable signals are low" "No increment,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ADDR_INCREMENT_3 ,Increment step for auto increment mode" "1,2,3,4"
|
|
bitfld.long 0x00 0.--1. " DISP_TYP_3 ,Type of the display" "Serial accesses,,Parallel/without byte_enable,Parallel/with byte_enable"
|
|
endif
|
|
group.long 0xe8--0x1c7
|
|
line.long 0x0 "DC_DISP_CONF2_0,DC Display Configuration 2 Register 0"
|
|
hexmask.long 0x0 0.--28. 1. " SL_0 ,Stride line of display 0"
|
|
line.long 0x4 "DC_DISP_CONF2_1,DC Display Configuration 2 Register 1"
|
|
hexmask.long 0x4 0.--28. 1. " SL_1 ,Stride line of display 1"
|
|
line.long 0x8 "DC_DISP_CONF2_2,DC Display Configuration 2 Register 2"
|
|
hexmask.long 0x8 0.--28. 1. " SL_2 ,Stride line of display 2"
|
|
line.long 0xC "DC_DISP_CONF2_3,DC Display Configuration 2 Register 3"
|
|
hexmask.long 0xC 0.--28. 1. " SL_3 ,Stride line of display 3"
|
|
line.long 0x10 "DC_DI0_CONF_1,DC DI0 Configuration Register 1"
|
|
line.long 0x14 "DC_DI0_CONF_2,DC DI0 Configuration Register 2"
|
|
line.long 0x18 "DC_DI1_CONF_1,DC DI1 Configuration Register 1"
|
|
line.long 0x1C "DC_DI1_CONF_2,DC DI1 Configuration Register 2"
|
|
textline " "
|
|
line.long 0x20 "DC_MAP_CONF_0,DC Mapping Configuration Register 0"
|
|
bitfld.long 0x20 26.--30. " MAPPING_PNTR_BYTE2_1 ,Mapping pointer #1 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 21.--25. " MAPPING_PNTR_BYTE1_1 ,Mapping pointer #1 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 16.--20. " MAPPING_PNTR_BYTE0_1 ,Mapping pointer #1 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 10.--14. " MAPPING_PNTR_BYTE2_0 ,Mapping pointer #0 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " MAPPING_PNTR_BYTE1_0 ,Mapping pointer #0 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 0.--4. " MAPPING_PNTR_BYTE0_0 ,Mapping pointer #0 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x24 "DC_MAP_CONF_1,DC Mapping Configuration Register 1"
|
|
bitfld.long 0x24 26.--30. " MAPPING_PNTR_BYTE2_3 ,Mapping pointer #3 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 21.--25. " MAPPING_PNTR_BYTE1_3 ,Mapping pointer #3 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 16.--20. " MAPPING_PNTR_BYTE0_3 ,Mapping pointer #3 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 10.--14. " MAPPING_PNTR_BYTE2_2 ,Mapping pointer #2 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x24 5.--9. " MAPPING_PNTR_BYTE1_2 ,Mapping pointer #2 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 0.--4. " MAPPING_PNTR_BYTE0_2 ,Mapping pointer #2 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x28 "DC_MAP_CONF_2,DC Mapping Configuration Register 2"
|
|
bitfld.long 0x28 26.--30. " MAPPING_PNTR_BYTE2_5 ,Mapping pointer #5 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 21.--25. " MAPPING_PNTR_BYTE1_5 ,Mapping pointer #5 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 16.--20. " MAPPING_PNTR_BYTE0_5 ,Mapping pointer #5 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 10.--14. " MAPPING_PNTR_BYTE2_4 ,Mapping pointer #4 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x28 5.--9. " MAPPING_PNTR_BYTE1_4 ,Mapping pointer #4 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x28 0.--4. " MAPPING_PNTR_BYTE0_4 ,Mapping pointer #4 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "DC_MAP_CONF_3,DC Mapping Configuration Register 3"
|
|
bitfld.long 0x2C 26.--30. " MAPPING_PNTR_BYTE2_7 ,Mapping pointer #7 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x2C 21.--25. " MAPPING_PNTR_BYTE1_7 ,Mapping pointer #7 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x2C 16.--20. " MAPPING_PNTR_BYTE0_7 ,Mapping pointer #7 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x2C 10.--14. " MAPPING_PNTR_BYTE2_6 ,Mapping pointer #6 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x2C 5.--9. " MAPPING_PNTR_BYTE1_6 ,Mapping pointer #6 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x2C 0.--4. " MAPPING_PNTR_BYTE0_6 ,Mapping pointer #6 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x30 "DC_MAP_CONF_4,DC Mapping Configuration Register 4"
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bitfld.long 0x30 26.--30. " MAPPING_PNTR_BYTE2_9 ,Mapping pointer #9 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 21.--25. " MAPPING_PNTR_BYTE1_9 ,Mapping pointer #9 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 16.--20. " MAPPING_PNTR_BYTE0_9 ,Mapping pointer #9 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 10.--14. " MAPPING_PNTR_BYTE2_8 ,Mapping pointer #8 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x30 5.--9. " MAPPING_PNTR_BYTE1_8 ,Mapping pointer #8 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x30 0.--4. " MAPPING_PNTR_BYTE0_8 ,Mapping pointer #8 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x34 "DC_MAP_CONF_5,DC Mapping Configuration Register 5"
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bitfld.long 0x34 26.--30. " MAPPING_PNTR_BYTE2_11 ,Mapping pointer #11 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 21.--25. " MAPPING_PNTR_BYTE1_11 ,Mapping pointer #11 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 16.--20. " MAPPING_PNTR_BYTE0_11 ,Mapping pointer #11 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 10.--14. " MAPPING_PNTR_BYTE2_10 ,Mapping pointer #10 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x34 5.--9. " MAPPING_PNTR_BYTE1_10 ,Mapping pointer #10 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x34 0.--4. " MAPPING_PNTR_BYTE0_10 ,Mapping pointer #10 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x38 "DC_MAP_CONF_6,DC Mapping Configuration Register 6"
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bitfld.long 0x38 26.--30. " MAPPING_PNTR_BYTE2_13 ,Mapping pointer #13 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 21.--25. " MAPPING_PNTR_BYTE1_13 ,Mapping pointer #13 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 16.--20. " MAPPING_PNTR_BYTE0_13 ,Mapping pointer #13 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 10.--14. " MAPPING_PNTR_BYTE2_12 ,Mapping pointer #12 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x38 5.--9. " MAPPING_PNTR_BYTE1_12 ,Mapping pointer #12 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 0.--4. " MAPPING_PNTR_BYTE0_12 ,Mapping pointer #12 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x3C "DC_MAP_CONF_7,DC Mapping Configuration Register 7"
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bitfld.long 0x3C 26.--30. " MAPPING_PNTR_BYTE2_15 ,Mapping pointer #15 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 21.--25. " MAPPING_PNTR_BYTE1_15 ,Mapping pointer #15 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 16.--20. " MAPPING_PNTR_BYTE0_15 ,Mapping pointer #15 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 10.--14. " MAPPING_PNTR_BYTE2_14 ,Mapping pointer #14 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x3C 5.--9. " MAPPING_PNTR_BYTE1_14 ,Mapping pointer #14 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x3C 0.--4. " MAPPING_PNTR_BYTE0_14 ,Mapping pointer #14 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x40 "DC_MAP_CONF_8,DC Mapping Configuration Register 8"
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bitfld.long 0x40 26.--30. " MAPPING_PNTR_BYTE2_17 ,Mapping pointer #17 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 21.--25. " MAPPING_PNTR_BYTE1_17 ,Mapping pointer #17 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 16.--20. " MAPPING_PNTR_BYTE0_17 ,Mapping pointer #17 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 10.--14. " MAPPING_PNTR_BYTE2_16 ,Mapping pointer #16 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x40 5.--9. " MAPPING_PNTR_BYTE1_16 ,Mapping pointer #16 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 0.--4. " MAPPING_PNTR_BYTE0_16 ,Mapping pointer #16 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x44 "DC_MAP_CONF_9,DC Mapping Configuration Register 9"
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bitfld.long 0x44 26.--30. " MAPPING_PNTR_BYTE2_19 ,Mapping pointer #19 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 21.--25. " MAPPING_PNTR_BYTE1_19 ,Mapping pointer #19 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 16.--20. " MAPPING_PNTR_BYTE0_19 ,Mapping pointer #19 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 10.--14. " MAPPING_PNTR_BYTE2_18 ,Mapping pointer #18 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x44 5.--9. " MAPPING_PNTR_BYTE1_18 ,Mapping pointer #18 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x44 0.--4. " MAPPING_PNTR_BYTE0_18 ,Mapping pointer #18 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x48 "DC_MAP_CONF_10,DC Mapping Configuration Register 10"
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bitfld.long 0x48 26.--30. " MAPPING_PNTR_BYTE2_21 ,Mapping pointer #21 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 21.--25. " MAPPING_PNTR_BYTE1_21 ,Mapping pointer #21 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 16.--20. " MAPPING_PNTR_BYTE0_21 ,Mapping pointer #21 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 10.--14. " MAPPING_PNTR_BYTE2_20 ,Mapping pointer #20 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x48 5.--9. " MAPPING_PNTR_BYTE1_20 ,Mapping pointer #20 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x48 0.--4. " MAPPING_PNTR_BYTE0_20 ,Mapping pointer #20 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x4C "DC_MAP_CONF_11,DC Mapping Configuration Register 11"
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bitfld.long 0x4C 26.--30. " MAPPING_PNTR_BYTE2_23 ,Mapping pointer #23 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 21.--25. " MAPPING_PNTR_BYTE1_23 ,Mapping pointer #23 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 16.--20. " MAPPING_PNTR_BYTE0_23 ,Mapping pointer #23 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 10.--14. " MAPPING_PNTR_BYTE2_22 ,Mapping pointer #22 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x4C 5.--9. " MAPPING_PNTR_BYTE1_22 ,Mapping pointer #22 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x4C 0.--4. " MAPPING_PNTR_BYTE0_22 ,Mapping pointer #22 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x50 "DC_MAP_CONF_12,DC Mapping Configuration Register 12"
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bitfld.long 0x50 26.--30. " MAPPING_PNTR_BYTE2_25 ,Mapping pointer #25 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 21.--25. " MAPPING_PNTR_BYTE1_25 ,Mapping pointer #25 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 16.--20. " MAPPING_PNTR_BYTE0_25 ,Mapping pointer #25 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 10.--14. " MAPPING_PNTR_BYTE2_24 ,Mapping pointer #24 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x50 5.--9. " MAPPING_PNTR_BYTE1_24 ,Mapping pointer #24 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x50 0.--4. " MAPPING_PNTR_BYTE0_24 ,Mapping pointer #24 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x54 "DC_MAP_CONF_13,DC Mapping Configuration Register 13"
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bitfld.long 0x54 26.--30. " MAPPING_PNTR_BYTE2_27 ,Mapping pointer #27 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 21.--25. " MAPPING_PNTR_BYTE1_27 ,Mapping pointer #27 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 16.--20. " MAPPING_PNTR_BYTE0_27 ,Mapping pointer #27 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 10.--14. " MAPPING_PNTR_BYTE2_26 ,Mapping pointer #26 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x54 5.--9. " MAPPING_PNTR_BYTE1_26 ,Mapping pointer #26 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x54 0.--4. " MAPPING_PNTR_BYTE0_26 ,Mapping pointer #26 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x58 "DC_MAP_CONF_14,DC Mapping Configuration Register 14"
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bitfld.long 0x58 26.--30. " MAPPING_PNTR_BYTE2_29 ,Mapping pointer #29 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 21.--25. " MAPPING_PNTR_BYTE1_29 ,Mapping pointer #29 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 16.--20. " MAPPING_PNTR_BYTE0_29 ,Mapping pointer #29 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 10.--14. " MAPPING_PNTR_BYTE2_28 ,Mapping pointer #28 for Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x58 5.--9. " MAPPING_PNTR_BYTE1_28 ,Mapping pointer #28 for Byte 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x58 0.--4. " MAPPING_PNTR_BYTE0_28 ,Mapping pointer #28 for Byte 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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line.long 0x5C "DC_MAP_CONF_15,DC Mapping Configuration Register 15"
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bitfld.long 0x5C 24.--28. " MD_OFFSET_1 ,Mapping unit's offset parameter #1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x5C 16.--23. 1. " MD_MASK_1 ,Mapping unit's mask value #1"
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bitfld.long 0x5C 8.--12. " MD_OFFSET_0 ,Mapping unit's offset parameter #0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x5C 0.--7. 1. " MD_MASK_0 ,Mapping unit's mask value #0"
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line.long 0x60 "DC_MAP_CONF_16,DC Mapping Configuration Register 16"
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bitfld.long 0x60 24.--28. " MD_OFFSET_3 ,Mapping unit's offset parameter #3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x60 16.--23. 1. " MD_MASK_3 ,Mapping unit's mask value #3"
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bitfld.long 0x60 8.--12. " MD_OFFSET_2 ,Mapping unit's offset parameter #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x60 0.--7. 1. " MD_MASK_2 ,Mapping unit's mask value #2"
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line.long 0x64 "DC_MAP_CONF_17,DC Mapping Configuration Register 17"
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bitfld.long 0x64 24.--28. " MD_OFFSET_5 ,Mapping unit's offset parameter #5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x64 16.--23. 1. " MD_MASK_5 ,Mapping unit's mask value #5"
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bitfld.long 0x64 8.--12. " MD_OFFSET_4 ,Mapping unit's offset parameter #4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.byte 0x64 0.--7. 1. " MD_MASK_4 ,Mapping unit's mask value #4"
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line.long 0x68 "DC_MAP_CONF_18,DC Mapping Configuration Register 18"
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bitfld.long 0x68 24.--28. " MD_OFFSET_7 ,Mapping unit's offset parameter #7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x68 16.--23. 1. " MD_MASK_7 ,Mapping unit's mask value #7"
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bitfld.long 0x68 8.--12. " MD_OFFSET_6 ,Mapping unit's offset parameter #6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.byte 0x68 0.--7. 1. " MD_MASK_6 ,Mapping unit's mask value #6"
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line.long 0x6C "DC_MAP_CONF_19,DC Mapping Configuration Register 19"
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|
bitfld.long 0x6C 24.--28. " MD_OFFSET_9 ,Mapping unit's offset parameter #9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x6C 16.--23. 1. " MD_MASK_9 ,Mapping unit's mask value #9"
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bitfld.long 0x6C 8.--12. " MD_OFFSET_8 ,Mapping unit's offset parameter #8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x6C 0.--7. 1. " MD_MASK_8 ,Mapping unit's mask value #8"
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line.long 0x70 "DC_MAP_CONF_20,DC Mapping Configuration Register 20"
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bitfld.long 0x70 24.--28. " MD_OFFSET_11 ,Mapping unit's offset parameter #11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x70 16.--23. 1. " MD_MASK_11 ,Mapping unit's mask value #11"
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bitfld.long 0x70 8.--12. " MD_OFFSET_10 ,Mapping unit's offset parameter #10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x70 0.--7. 1. " MD_MASK_10 ,Mapping unit's mask value #10"
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line.long 0x74 "DC_MAP_CONF_21,DC Mapping Configuration Register 21"
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bitfld.long 0x74 24.--28. " MD_OFFSET_13 ,Mapping unit's offset parameter #13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x74 16.--23. 1. " MD_MASK_13 ,Mapping unit's mask value #13"
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bitfld.long 0x74 8.--12. " MD_OFFSET_12 ,Mapping unit's offset parameter #12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x74 0.--7. 1. " MD_MASK_12 ,Mapping unit's mask value #12"
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line.long 0x78 "DC_MAP_CONF_22,DC Mapping Configuration Register 22"
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bitfld.long 0x78 24.--28. " MD_OFFSET_15 ,Mapping unit's offset parameter #15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x78 16.--23. 1. " MD_MASK_15 ,Mapping unit's mask value #15"
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bitfld.long 0x78 8.--12. " MD_OFFSET_14 ,Mapping unit's offset parameter #14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x78 0.--7. 1. " MD_MASK_14 ,Mapping unit's mask value #14"
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line.long 0x7C "DC_MAP_CONF_23,DC Mapping Configuration Register 23"
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bitfld.long 0x7C 24.--28. " MD_OFFSET_17 ,Mapping unit's offset parameter #17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x7C 16.--23. 1. " MD_MASK_17 ,Mapping unit's mask value #17"
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bitfld.long 0x7C 8.--12. " MD_OFFSET_16 ,Mapping unit's offset parameter #16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x7C 0.--7. 1. " MD_MASK_16 ,Mapping unit's mask value #16"
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line.long 0x80 "DC_MAP_CONF_24,DC Mapping Configuration Register 24"
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bitfld.long 0x80 24.--28. " MD_OFFSET_19 ,Mapping unit's offset parameter #19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x80 16.--23. 1. " MD_MASK_19 ,Mapping unit's mask value #19"
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bitfld.long 0x80 8.--12. " MD_OFFSET_18 ,Mapping unit's offset parameter #18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x80 0.--7. 1. " MD_MASK_18 ,Mapping unit's mask value #18"
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line.long 0x84 "DC_MAP_CONF_25,DC Mapping Configuration Register 25"
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bitfld.long 0x84 24.--28. " MD_OFFSET_21 ,Mapping unit's offset parameter #21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x84 16.--23. 1. " MD_MASK_21 ,Mapping unit's mask value #21"
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bitfld.long 0x84 8.--12. " MD_OFFSET_20 ,Mapping unit's offset parameter #20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.byte 0x84 0.--7. 1. " MD_MASK_20 ,Mapping unit's mask value #20"
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line.long 0x88 "DC_MAP_CONF_26,DC Mapping Configuration Register 26"
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bitfld.long 0x88 24.--28. " MD_OFFSET_23 ,Mapping unit's offset parameter #23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x88 16.--23. 1. " MD_MASK_23 ,Mapping unit's mask value #23"
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bitfld.long 0x88 8.--12. " MD_OFFSET_22 ,Mapping unit's offset parameter #22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x88 0.--7. 1. " MD_MASK_22 ,Mapping unit's mask value #22"
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line.long 0x8C "DC_UGDE0_0,DC User General Data Event 0 Register 0"
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bitfld.long 0x8C 27.--28. " NF_NL_0 ,New-line New-Frame and New-field event" "New Line,New Frame,New Field,?..."
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|
bitfld.long 0x8C 26. " AUTORESTART_0 ,Auto restart mode" "Disabled,Enabled"
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|
bitfld.long 0x8C 25. " ODD_EN_0 ,Odd Mode Enable" "Disabled,Enabled"
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|
hexmask.long.byte 0x8C 16.--23. 1. " COD_ODD_START_0 ,Pointer in the microcode holding the routine to be performed following the user general event #0 (odd events)"
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|
textline " "
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hexmask.long.byte 0x8C 8.--15. 1. " COD_EV_START_0 ,Pointer in the microcode holding the routine to be performed following the user general event #0 (even events)"
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bitfld.long 0x8C 3.--6. " COD_EV_PRIORITY_0 ,Priority of the user general event #0" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
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bitfld.long 0x8C 0.--2. " ID_CODED_0 ,Number of DC channel number" "0,1,2,5,6,?..."
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line.long (0x8C+0x04) "DC_UGDE0_1,DC User General Data Event 0 Register 1"
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hexmask.long (0x8C+0x04) 0.--28. 1. " STEP_0 ,Pre defined value that the counter counts too"
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line.long (0x8C+0x08) "DC_UGDE0_2,DC User General Data Event 0 Register 2"
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hexmask.long (0x8C+0x08) 0.--28. 1. " OFFSET_DT_0 ,Offset value from which the counter of user general event #0 will start counting from"
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line.long (0x8C+0x0c) "DC_UGDE0_3,DC User General Data Event 0 Register 3"
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hexmask.long (0x8C+0x0c) 0.--28. 1. " STEP_REPEAT_0 ,Number of events that will be generated by the user general event #0 mechanism"
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line.long 0x9C "DC_UGDE1_0,DC User General Data Event 1 Register 0"
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bitfld.long 0x9C 27.--28. " NF_NL_1 ,New-line New-Frame and New-field event" "New Line,New Frame,New Field,?..."
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bitfld.long 0x9C 26. " AUTORESTART_1 ,Auto restart mode" "Disabled,Enabled"
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bitfld.long 0x9C 25. " ODD_EN_1 ,Odd Mode Enable" "Disabled,Enabled"
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hexmask.long.byte 0x9C 16.--23. 1. " COD_ODD_START_1 ,Pointer in the microcode holding the routine to be performed following the user general event #1 (odd events)"
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textline " "
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hexmask.long.byte 0x9C 8.--15. 1. " COD_EV_START_1 ,Pointer in the microcode holding the routine to be performed following the user general event #1 (even events)"
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bitfld.long 0x9C 3.--6. " COD_EV_PRIORITY_1 ,Priority of the user general event #1" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
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bitfld.long 0x9C 0.--2. " ID_CODED_1 ,Number of DC channel number" "0,1,2,5,6,?..."
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line.long (0x9C+0x04) "DC_UGDE1_1,DC User General Data Event 1 Register 1"
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hexmask.long (0x9C+0x04) 0.--28. 1. " STEP_1 ,Pre defined value that the counter counts too"
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line.long (0x9C+0x08) "DC_UGDE1_2,DC User General Data Event 1 Register 2"
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hexmask.long (0x9C+0x08) 0.--28. 1. " OFFSET_DT_1 ,Offset value from which the counter of user general event #1 will start counting from"
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line.long (0x9C+0x0c) "DC_UGDE1_3,DC User General Data Event 1 Register 3"
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hexmask.long (0x9C+0x0c) 0.--28. 1. " STEP_REPEAT_1 ,Number of events that will be generated by the user general event #1 mechanism"
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line.long 0xAC "DC_UGDE2_0,DC User General Data Event 2 Register 0"
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bitfld.long 0xAC 27.--28. " NF_NL_2 ,New-line New-Frame and New-field event" "New Line,New Frame,New Field,?..."
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bitfld.long 0xAC 26. " AUTORESTART_2 ,Auto restart mode" "Disabled,Enabled"
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bitfld.long 0xAC 25. " ODD_EN_2 ,Odd Mode Enable" "Disabled,Enabled"
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hexmask.long.byte 0xAC 16.--23. 1. " COD_ODD_START_2 ,Pointer in the microcode holding the routine to be performed following the user general event #2 (odd events)"
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textline " "
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hexmask.long.byte 0xAC 8.--15. 1. " COD_EV_START_2 ,Pointer in the microcode holding the routine to be performed following the user general event #2 (even events)"
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bitfld.long 0xAC 3.--6. " COD_EV_PRIORITY_2 ,Priority of the user general event #2" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
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bitfld.long 0xAC 0.--2. " ID_CODED_2 ,Number of DC channel number" "0,1,2,5,6,?..."
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line.long (0xAC+0x04) "DC_UGDE2_1,DC User General Data Event 2 Register 1"
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hexmask.long (0xAC+0x04) 0.--28. 1. " STEP_2 ,Pre defined value that the counter counts too"
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line.long (0xAC+0x08) "DC_UGDE2_2,DC User General Data Event 2 Register 2"
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hexmask.long (0xAC+0x08) 0.--28. 1. " OFFSET_DT_2 ,Offset value from which the counter of user general event #2 will start counting from"
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line.long (0xAC+0x0c) "DC_UGDE2_3,DC User General Data Event 2 Register 3"
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hexmask.long (0xAC+0x0c) 0.--28. 1. " STEP_REPEAT_2 ,Number of events that will be generated by the user general event #2 mechanism"
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line.long 0xBC "DC_UGDE3_0,DC User General Data Event 3 Register 0"
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bitfld.long 0xBC 27.--28. " NF_NL_3 ,New-line New-Frame and New-field event" "New Line,New Frame,New Field,?..."
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bitfld.long 0xBC 26. " AUTORESTART_3 ,Auto restart mode" "Disabled,Enabled"
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bitfld.long 0xBC 25. " ODD_EN_3 ,Odd Mode Enable" "Disabled,Enabled"
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hexmask.long.byte 0xBC 16.--23. 1. " COD_ODD_START_3 ,Pointer in the microcode holding the routine to be performed following the user general event #3 (odd events)"
|
|
textline " "
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hexmask.long.byte 0xBC 8.--15. 1. " COD_EV_START_3 ,Pointer in the microcode holding the routine to be performed following the user general event #3 (even events)"
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bitfld.long 0xBC 3.--6. " COD_EV_PRIORITY_3 ,Priority of the user general event #3" "Disabled,1(lowest),2,3,4,5,6,7,8,9,10,11,12,13(highest),?..."
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bitfld.long 0xBC 0.--2. " ID_CODED_3 ,Number of DC channel number" "0,1,2,5,6,?..."
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line.long (0xBC+0x04) "DC_UGDE3_1,DC User General Data Event 3 Register 1"
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hexmask.long (0xBC+0x04) 0.--28. 1. " STEP_3 ,Pre defined value that the counter counts too"
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line.long (0xBC+0x08) "DC_UGDE3_2,DC User General Data Event 3 Register 2"
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hexmask.long (0xBC+0x08) 0.--28. 1. " OFFSET_DT_3 ,Offset value from which the counter of user general event #3 will start counting from"
|
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line.long (0xBC+0x0c) "DC_UGDE3_3,DC User General Data Event 3 Register 3"
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hexmask.long (0xBC+0x0c) 0.--28. 1. " STEP_REPEAT_3 ,Number of events that will be generated by the user general event #3 mechanism"
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line.long 0xCC "DC_LLA0,DC Low Level Access Control Register 0"
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hexmask.long.byte 0xCC 24.--31. 1. " MCU_RS_3_0 ,Pointer in the microcode handling the RS_3 routine for the display defined at DISP_ID_8 (Low level)"
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hexmask.long.byte 0xCC 16.--23. 1. " MCU_RS_2_0 ,Pointer in the microcode handling the RS_2 routine for the display defined at DISP_ID_8 (Low level)"
|
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hexmask.long.byte 0xCC 8.--15. 1. " MCU_RS_1_0 ,Pointer in the microcode handling the RS_1 routine for the display defined at DISP_ID_8 (Low level)"
|
|
textline " "
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hexmask.long.byte 0xCC 0.--7. 1. " MCU_RS_0_0 ,Pointer in the microcode handling the RS_0 routine for the display defined at DISP_ID_8 (Low level)"
|
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line.long 0xD0 "DC_LLA1,DC Low Level Access Control Register 1"
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hexmask.long.byte 0xD0 24.--31. 1. " MCU_RS_3_1 ,Pointer in the microcode handling the RS_3 routine for the display defined at DISP_ID_9 (Low level)"
|
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hexmask.long.byte 0xD0 16.--23. 1. " MCU_RS_2_1 ,Pointer in the microcode handling the RS_2 routine for the display defined at DISP_ID_9 (Low level)"
|
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hexmask.long.byte 0xD0 8.--15. 1. " MCU_RS_1_1 ,Pointer in the microcode handling the RS_1 routine for the display defined at DISP_ID_9 (Low level)"
|
|
textline " "
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hexmask.long.byte 0xD0 0.--7. 1. " MCU_RS_0_1 ,Pointer in the microcode handling the RS_0 routine for the display defined at DISP_ID_9 (Low level)"
|
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line.long 0xD4 "DC_R_LLA0,DC Low Level Read Access Control Register 0"
|
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hexmask.long.byte 0xD4 24.--31. 1. " MCU_RS_R_3_0 ,Pointer in the microcode handling the RS_3 routine for the display defined at DISP_ID_8 (Read Low level)"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " MCU_RS_R_2_0 ,Pointer in the microcode handling the RS_2 routine for the display defined at DISP_ID_8 (Read Low level)"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " MCU_RS_R_1_0 ,Pointer in the microcode handling the RS_1 routine for the display defined at DISP_ID_8 (Read Low level)"
|
|
textline " "
|
|
hexmask.long.byte 0xD4 0.--7. 1. " MCU_RS_R_0_0 ,Pointer in the microcode handling the RS_0 routine for the display defined at DISP_ID_8 (Read Low level)"
|
|
line.long 0xD8 "DC_R_LLA1,DC Low Level Read Access Control Register 1"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " MCU_RS_R_3_1 ,Pointer in the microcode handling the RS_3 routine for the display defined at DISP_ID_9 (Read Low level)"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " MCU_RS_R_2_1 ,Pointer in the microcode handling the RS_2 routine for the display defined at DISP_ID_9 (Read Low level)"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " MCU_RS_R_1_1 ,Pointer in the microcode handling the RS_1 routine for the display defined at DISP_ID_9 (Read Low level)"
|
|
textline " "
|
|
hexmask.long.byte 0xD8 0.--7. 1. " MCU_RS_R_0_1 ,Pointer in the microcode handling the RS_0 routine for the display defined at DISP_ID_9 (Read Low level)"
|
|
width 21.
|
|
textline " "
|
|
line.long 0xdc "DC_WR_CH_ADDR_5_ALT,DC Write Channel 5 Configuration Register"
|
|
hexmask.long 0xdc 0.--28. 1. " ST_ADDR_5_ALT ,Start address within the display's memory space (channel #5)"
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|
rgroup.long 0x1c8++0x03
|
|
line.long 0x00 "DC_STAT,DC Status Register"
|
|
bitfld.long 0x00 7. " DC_TRIPLE_BUF_DATA_EMPTY_1 ,DC_TRIPLE_BUF_DATA_EMPTY_1" "Not empty,Empty"
|
|
bitfld.long 0x00 6. " DC_TRIPLE_BUF_DATA_FULL_1 ,DC_TRIPLE_BUF_DATA_FULL_1" "Not full,Full"
|
|
bitfld.long 0x00 5. " DC_TRIPLE_BUF_CNT_EMPTY_1 ,DC_TRIPLE_BUF_CNT_EMPTY_1" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DC_TRIPLE_BUF_CNT_FULL_1 ,DC_TRIPLE_BUF_CNT_FULL_1" "Not full,Full"
|
|
bitfld.long 0x00 3. " DC_TRIPLE_BUF_DATA_EMPTY_0 ,DC_TRIPLE_BUF_DATA_EMPTY_0" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " DC_TRIPLE_BUF_DATA_FULL_0 ,DC_TRIPLE_BUF_DATA_FULL_0" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DC_TRIPLE_BUF_CNT_EMPTY_0 ,DC_TRIPLE_BUF_CNT_EMPTY_0" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " DC_TRIPLE_BUF_CNT_FULL_0 ,DC_TRIPLE_BUF_CNT_FULL_0" "Not full,Full"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMFC registers"
|
|
base ad:0x5e060000
|
|
width 22.
|
|
group.long 0x00++0x33
|
|
line.long 0x00 "DMFC_RD_CHAN,DMFC Read Channel Register"
|
|
bitfld.long 0x00 24.--25. " DMFC_PPW_C ,Pixel Per Word coded" "8,16,24,?..."
|
|
bitfld.long 0x00 21.--23. " DMFC_WM_CLR_0 ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DMFC_WM_SET_0 ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 17. " DMFC_WM_EN_0 ,Watermark enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " DMFC_BURST_SIZE_0 ,Read burst Size" "32,16,8,4"
|
|
line.long 0x04 "DMFC_WR_CHAN,DMFC Write Channel Register"
|
|
bitfld.long 0x04 30.--31. " DMFC_BURST_SIZE_2C ,Burst size of IDMAC's channel 43" "32,16,8,4"
|
|
bitfld.long 0x04 27.--29. " DMFC_FIFO_SIZE_2C ,DMFC FIFO size for IDMAC's channel 43" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
textline " "
|
|
bitfld.long 0x04 24.--26. " DMFC_ST_ADDR_2C ,DMFC Start Address for IDMAC's channel 43" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
bitfld.long 0x04 22.--23. " DMFC_BURST_SIZE_1C ,Burst size of IDMAC's channel 42" "32,16,8,4"
|
|
textline " "
|
|
bitfld.long 0x04 19.--21. " DMFC_FIFO_SIZE_1C ,DMFC FIFO size for IDMAC's channel 42" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
bitfld.long 0x04 16.--18. " DMFC_ST_ADDR_1C ,DMFC Start Address for IDMAC's channel 42" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " DMFC_BURST_SIZE_2 ,Burst size of IDMAC's channel 41" "32,16,8,4"
|
|
bitfld.long 0x04 11.--13. " DMFC_FIFO_SIZE_2 ,DMFC FIFO size for IDMAC's channel 41" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " DMFC_ST_ADDR_2 ,DMFC Start Address for IDMAC's channel 41" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
bitfld.long 0x04 6.--7. " DMFC_BURST_SIZE_1 ,Burst size of IDMAC's channel 28" "32,16,8,4"
|
|
textline " "
|
|
bitfld.long 0x04 3.--5. " DMFC_FIFO_SIZE_1 ,DMFC FIFO size for IDMAC's channel 28" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
bitfld.long 0x04 0.--2. " DMFC_ST_ADDR_1 ,DMFC Start Address for IDMAC's channel 28" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
line.long 0x08 "DMFC_WR_CHAN_DEF,DMFC Write Channel Definition Register"
|
|
bitfld.long 0x08 29.--31. " DMFC_WM_CLR_2C ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 26.--28. " DMFC_WM_SET_2C ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 25. " DMFC_WM_EN_2C ,Watermark enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21.--23. " DMFC_WM_CLR_1C ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 18.--20. " DMFC_WM_SET_1C ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 17. " DMFC_WM_EN_1C ,Watermark enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13.--15. " DMFC_WM_CLR_2 ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 10.--12. " DMFC_WM_SET_2 ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 9. " DMFC_WM_EN_2 ,Watermark enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5.--7. " DMFC_WM_CLR_1 ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 2.--4. " DMFC_WM_SET_1 ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 1. " DMFC_WM_EN_1 ,Watermark enable" "Disabled,Enabled"
|
|
line.long 0x0c "DMFC_DP_CHAN,DMFC Display Processor Channel Register"
|
|
bitfld.long 0x0c 30.--31. " DMFC_BURST_SIZE_6F ,Burst size of IDMAC's channel 29" "32,16,8,4"
|
|
bitfld.long 0x0c 27.--29. " DMFC_FIFO_SIZE_6F ,DMFC FIFO size for IDMAC's channel 29" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
textline " "
|
|
bitfld.long 0x0c 24.--26. " DMFC_ST_ADDR_6F ,DMFC Start Address for IDMAC's channel 29" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
bitfld.long 0x0c 22.--23. " DMFC_BURST_SIZE_6B ,Burst size of IDMAC's channel 24" "32,16,8,4"
|
|
textline " "
|
|
bitfld.long 0x0c 19.--21. " DMFC_FIFO_SIZE_6B ,DMFC FIFO size for IDMAC's channel 24" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
bitfld.long 0x0c 16.--18. " DMFC_ST_ADDR_6B ,DMFC Start Address for IDMAC's channel 24" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
textline " "
|
|
bitfld.long 0x0c 14.--15. " DMFC_BURST_SIZE_5F ,Burst size of IDMAC's channel 27" "32,16,8,4"
|
|
bitfld.long 0x0c 11.--13. " DMFC_FIFO_SIZE_5F ,DMFC FIFO size for IDMAC's channel 27" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--10. " DMFC_ST_ADDR_5F ,DMFC Start Address for IDMAC's channel 27" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
bitfld.long 0x0c 6.--7. " DMFC_BURST_SIZE_5B ,Burst size of IDMAC's channel 23" "32,16,8,4"
|
|
textline " "
|
|
bitfld.long 0x0c 3.--5. " DMFC_FIFO_SIZE_5B ,DMFC FIFO size for IDMAC's channel 23" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
bitfld.long 0x0c 0.--2. " DMFC_ST_ADDR_5B ,DMFC Start Address for IDMAC's channel 23" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
line.long 0x10 "DMFC_DP_CHAN_DEF,DMFC Display Channel Definition Register"
|
|
bitfld.long 0x10 29.--31. " DMFC_WM_CLR_6F ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 26.--28. " DMFC_WM_SET_6F ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 25. " DMFC_WM_EN_6F ,Watermark enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 21.--23. " DMFC_WM_CLR_6B ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 18.--20. " DMFC_WM_SET_6B ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 17. " DMFC_WM_EN_6B ,Watermark enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13.--15. " DMFC_WM_CLR_5F ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 10.--12. " DMFC_WM_SET_5F ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 9. " DMFC_WM_EN_5F ,Watermark enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5.--7. " DMFC_WM_CLR_5B ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 2.--4. " DMFC_WM_SET_5B ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 1. " DMFC_WM_EN_5B ,Watermark enable" "Disabled,Enabled"
|
|
line.long 0x14 "DMFC_GENERAL1,DMFC General 1 Register"
|
|
bitfld.long 0x14 24. " WAIT4EOT_9 ,FIFO #9 operation mode" "Normal,Wait4eot"
|
|
bitfld.long 0x14 23. " WAIT4EOT_6F ,FIFO #6F operation mode" "Normal,Wait4eot"
|
|
textline " "
|
|
bitfld.long 0x14 22. " WAIT4EOT_6B ,FIFO #6B operation mode" "Normal,Wait4eot"
|
|
bitfld.long 0x14 21. " WAIT4EOT_5F ,FIFO #5F operation mode" "Normal,Wait4eot"
|
|
textline " "
|
|
bitfld.long 0x14 20. " WAIT4EOT_5B ,FIFO #5B operation mode" "Normal,Wait4eot"
|
|
bitfld.long 0x14 19. " WAIT4EOT_4 ,FIFO #4 operation mode" "Normal,Wait4eot"
|
|
textline " "
|
|
bitfld.long 0x14 18. " WAIT4EOT_3 ,FIFO #3 operation mode" "Normal,Wait4eot"
|
|
bitfld.long 0x14 17. " WAIT4EOT_2 ,FIFO #2 operation mode" "Normal,Wait4eot"
|
|
textline " "
|
|
bitfld.long 0x14 16. " WAIT4EOT_1 ,FIFO #1 operation mode" "Normal,Wait4eot"
|
|
bitfld.long 0x14 13.--15. " DMFC_WM_CLR_9 ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 10.--12. " DMFC_WM_SET_9 ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 9. " DMFC_WM_EN_9 ,Watermark enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5.--6. " DMFC_BURST_SIZE_9 ,Burst size of IDMAC's channel 44" "32,16,8,4"
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
bitfld.long 0x14 0.--1. " DMFC_DCDP_SYNC_PR ,Burst size of IDMAC's channel 44" "Forbidden,DC over DP,DP over DC,Round Robin"
|
|
else
|
|
bitfld.long 0x14 0.--1. " DMFC_DCDP_SYNC_PR ,DMFC's memory access priority" "Forbidden,DC over DP,DP over DC,Round Robin"
|
|
endif
|
|
line.long 0x18 "DMFC_GENERAL2,DMFC General Register 2"
|
|
hexmask.long.word 0x18 16.--28. 1. " DMFC_FRAME_HEIGHT_RD ,Frame height for read channel from the display to the IDMAC"
|
|
hexmask.long.word 0x18 0.--12. 1. " DMFC_FRAME_WIDTH_RD ,Frame width for read channel from the display to the IDMAC"
|
|
line.long 0x1c "DMFC_IC_CTRL,DMFC IC Interface Control Register"
|
|
hexmask.long.word 0x1c 19.--31. 1. " DMFC_IC_FRAME_HEIGHT_RD ,Frame's height for the channel coming from IC"
|
|
hexmask.long.word 0x1c 6.--18. 1. " DMFC_IC_FRAME_WIDTH_RD ,Frame's width for the channel coming from IC"
|
|
textline " "
|
|
bitfld.long 0x1c 4.--5. " DMFC_IC_PPW_C ,Pixel Per Word coded from IC" "8,16,24,?..."
|
|
bitfld.long 0x1c 0.--2. " DMFC_IC_IN_PORT ,DMFC input port" "CH28,CH41,,,CH23,CH27,CH24,CH29"
|
|
line.long 0x20 "DMFC_WR_CHAN_ALT,DMFC Write Channel Alternate Register"
|
|
bitfld.long 0x20 14.--15. " DMFC_BURST_SIZE_2_ALT ,Burst size of IDMAC's channel 41" "32,16,8,4"
|
|
bitfld.long 0x20 11.--13. " DMFC_FIFO_SIZE_2_ALT ,DMFC FIFO size for IDMAC's channel 41 (for alternate flow)" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
textline " "
|
|
bitfld.long 0x20 8.--10. " DMFC_FIFO_SIZE_2_ALT ,DMFC Start Address for IDMAC's channel 41 (for alternate flow)" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
line.long 0x24 "DMFC_WR_CHAN_DEF_ALT,DMFC Write Channel Definition Alternate Register"
|
|
bitfld.long 0x24 13.--15. " DMFC_WM_CLR_2_ALT ,Watermark Clear (for alternate flow)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x24 10.--12. " DMFC_WM_SET_2_ALT ,Watermark Set (for alternate flow)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 9. " DMFC_WM_EN_2_ALT ,Watermark enable (for alternate flow)" "Disabled,Enabled"
|
|
line.long 0x28 "DMFC_DP_CHAN_ALT,DMFC Display Processor Channel Alternate Register"
|
|
bitfld.long 0x28 30.--31. " DMFC_BURST_SIZE_6F_ALT ,Burst size of IDMAC's channel 29" "32,16,8,4"
|
|
bitfld.long 0x28 27.--29. " DMFC_FIFO_SIZE_6F_ALT ,DMFC FIFO size for IDMAC's channel 29" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
textline " "
|
|
bitfld.long 0x28 24.--26. " DMFC_ST_ADDR_6F_ALT ,DMFC Start Address for IDMAC's channel 29" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
bitfld.long 0x28 22.--23. " DMFC_BURST_SIZE_6B_ALT ,Burst size of IDMAC's channel 24" "32,16,8,4"
|
|
textline " "
|
|
bitfld.long 0x28 19.--21. " DMFC_FIFO_SIZE_6B_ALT ,DMFC FIFO size for IDMAC's channel 24" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
bitfld.long 0x28 16.--18. " DMFC_ST_ADDR_6B_ALT ,DMFC Start Address for IDMAC's channel 24" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
textline " "
|
|
bitfld.long 0x28 6.--7. " DMFC_BURST_SIZE_5B_ALT ,Burst size of IDMAC's channel 23" "32,16,8,4"
|
|
bitfld.long 0x28 3.--5. " DMFC_FIFO_SIZE_5B_ALT ,DMFC FIFO size for IDMAC's channel 23" "512X128,256X128,128X128,64X128,32X128,16X128,8X128,4X128"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " DMFC_ST_ADDR_5B_ALT ,DMFC Start Address for IDMAC's channel 23" "Segment 0,Segment 1,Segment 2,Segment 3,Segment 4,Segment 5,Segment 6,Segment 7"
|
|
line.long 0x2c "DMFC_DP_CHAN_DEF_ALT,DMFC Display Channel Definition Alternate Register"
|
|
bitfld.long 0x2c 29.--31. " DMFC_WM_CLR_6F_ALT ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2c 26.--28. " DMFC_WM_SET_6F_ALT ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2c 25. " DMFC_WM_EN_6F_ALT ,Watermark enable" "Disabled,Enabled"
|
|
bitfld.long 0x2c 21.--23. " DMFC_WM_CLR_6B_ALT ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2c 18.--20. " DMFC_WM_SET_6B_ALT ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2c 17. " DMFC_WM_EN_6B_ALT ,Watermark enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2c 5.--7. " DMFC_WM_CLR_5B_ALT ,Watermark Clear" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2c 2.--4. " DMFC_WM_SET_5B_ALT ,Watermark Set" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2c 1. " DMFC_WM_EN_5B_ALT ,Watermark enable" "Disabled,Enabled"
|
|
line.long 0x30 "DMFC_GENERAL1_ALT,DMFC General 1 Altenate Register"
|
|
bitfld.long 0x30 23. " WAIT4EOT_6F_ALT ,FIFO #6F operation mode" "Normal,Wait4eot"
|
|
bitfld.long 0x30 22. " WAIT4EOT_6B_ALT ,FIFO #6B operation mode" "Normal,Wait4eot"
|
|
textline " "
|
|
bitfld.long 0x30 20. " WAIT4EOT_5B_ALT ,FIFO #5B operation mode" "Normal,Wait4eot"
|
|
bitfld.long 0x30 17. " WAIT4EOT_2_ALT ,FIFO #2 operation mode" "Normal,Wait4eot"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "DMFC_STAT,DMFC Status Register"
|
|
bitfld.long 0x00 25. " DMFC_IC_BUFFER_EMPTY ,Indicates on a IC FIFO empty condition" "Not empty,Empty"
|
|
bitfld.long 0x00 24. " DMFC_IC_BUFFER_FULL ,Indicates on a IC FIFO full condition" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DMFC_FIFO_EMPTY_11 ,Indicates on a DMFC FIFO 11 empty condition" "Not empty,Empty"
|
|
bitfld.long 0x00 22. " DMFC_FIFO_EMPTY_10 ,Indicates on a DMFC FIFO 10 empty condition" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DMFC_FIFO_EMPTY_9 ,Indicates on a DMFC FIFO 9 empty condition" "Not empty,Empty"
|
|
bitfld.long 0x00 20. " DMFC_FIFO_EMPTY_8 ,Indicates on a DMFC FIFO 8 (6F) empty condition" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DMFC_FIFO_EMPTY_7 ,Indicates on a DMFC FIFO 7 (6b) empty condition" "Not empty,Empty"
|
|
bitfld.long 0x00 18. " DMFC_FIFO_EMPTY_6 ,Indicates on a DMFC FIFO 6 (5f) empty condition" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DMFC_FIFO_EMPTY_5 ,Indicates on a DMFC FIFO 5 (5b) empty condition" "Not empty,Empty"
|
|
bitfld.long 0x00 16. " DMFC_FIFO_EMPTY_4 ,Indicates on a DMFC FIFO 4 (2c) empty condition" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DMFC_FIFO_EMPTY_3 ,Indicates on a DMFC FIFO 3 (1c) empty condition" "Not empty,Empty"
|
|
bitfld.long 0x00 14. " DMFC_FIFO_EMPTY_2 ,Indicates on a DMFC FIFO 2 empty condition" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMFC_FIFO_EMPTY_1 ,Indicates on a DMFC FIFO 1 empty condition" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " DMFC_FIFO_EMPTY_0 ,Indicates on a DMFC FIFO 0 empty condition" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DMFC_FIFO_FULL_11 ,Indicates on a DMFC FIFO 11 full condition" "Not full,Full"
|
|
bitfld.long 0x00 10. " DMFC_FIFO_FULL_10 ,Indicates on a DMFC FIFO 10 full condition" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DMFC_FIFO_FULL_9 ,Indicates on a DMFC FIFO 9 full condition" "Not full,Full"
|
|
bitfld.long 0x00 8. " DMFC_FIFO_FULL_8 ,Indicates on a DMFC FIFO 8 (6f) full condition" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMFC_FIFO_FULL_7 ,Indicates on a DMFC FIFO 7 (6b) full condition" "Not full,Full"
|
|
bitfld.long 0x00 6. " DMFC_FIFO_FULL_6 ,Indicates on a DMFC FIFO 6 (5f) full condition" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DMFC_FIFO_FULL_5 ,Indicates on a DMFC FIFO 5 (5b) full condition" "Not full,Full"
|
|
bitfld.long 0x00 4. " DMFC_FIFO_FULL_4 ,Indicates on a DMFC FIFO 4 (2c) full condition" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMFC_FIFO_FULL_3 ,Indicates on a DMFC FIFO 3 (1c) full condition" "Not full,Full"
|
|
bitfld.long 0x00 2. " DMFC_FIFO_FULL_2 ,Indicates on a DMFC FIFO 2 full condition" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DMFC_FIFO_FULL_1 ,Indicates on a DMFC FIFO 1 full condition" "Not full,Full"
|
|
bitfld.long 0x00 0. " DMFC_FIFO_FULL_0 ,Indicates on a DMFC FIFO 0 full condition" "Not full,Full"
|
|
width 0x0B
|
|
tree.end
|
|
tree "VDI Registers"
|
|
base ad:0x5e068000
|
|
width 12.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "VDI_FSIZE,VDI Field Size Register"
|
|
sif ((!cpuis("IMX6*"))&&cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
hexmask.long.word 0x00 16.--25. 1. " VDI_FHEIGHT ,Frame height"
|
|
hexmask.long.word 0x00 0.--9. 1. " VDI_FWIDTH ,Frame width"
|
|
else
|
|
hexmask.long.word 0x00 16.--26. 1. " VDI_FHEIGHT ,Frame height"
|
|
hexmask.long.word 0x00 0.--10. 1. " VDI_FWIDTH ,Frame width"
|
|
endif
|
|
line.long 0x04 "VDI_C,VDI Control Register"
|
|
bitfld.long 0x04 31. " VDI_TOP_FIELD_AUTO ,VDI top filed (automatic)" "0,1"
|
|
bitfld.long 0x04 30. " VDI_TOP_FIELD_MAN ,VDI top filed (manual)" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 25.--27. " VDI_VWM3_CLR ,VDI WaterMark clear level for channel 3" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
|
|
bitfld.long 0x04 22.--24. " VDI_VWM3_SET ,VDI WaterMark set level for channel 3" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
|
|
textline " "
|
|
sif (cpu()!="IMX53"&&(!cpuis("IMX6*"))&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538")
|
|
bitfld.long 0x04 19.--21. " VDI_VWM1_CLR ,VDI WaterMark clear level for channel 1 or channel 2" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
|
|
else
|
|
bitfld.long 0x04 19.--21. " VDI_VWM1_CLR ,VDI WaterMark clear level for channel 1 or channel 4" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
|
|
endif
|
|
bitfld.long 0x04 16.--18. " VDI_VWM1_SET ,VDI WaterMark set level for channel 1 or channel 2" "Full on 1/8,Full on 2/8,Full on 3/8,Full on 4/8,Full on 5/8,Full on 6/8,Full on 7/8,Full"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " VDI_BURST_SIZE3 ,Burst Size for channel 3" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x04 8.--11. " VDI_BURST_SIZE2 ,Burst Size for channel 2" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " VDI_BURST_SIZE1 ,Burst Size for channels 1 or 4" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x04 2.--3. " VDI_MOT_SEL ,Motion select" "ROM 1,ROM 2,Full motion,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x04 1. " VDI_CH_422 ,Chroma format at input and output of VDI" "420,422"
|
|
sif (cpu()=="IMX53"||cpuis("IMX6*")||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
group.long 0x08++0x1B
|
|
line.long 0x00 "VDI_C2,VDI Control Register 2"
|
|
bitfld.long 0x00 3. " PLANE_1_EN ,Plane 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " GLB_A_EN ,Global alpha enable" "Local,Global"
|
|
bitfld.long 0x00 1. " KEY_COLOR_EN ,Key Color Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMB_EN ,Combining enable" "Disabled,Enabled"
|
|
line.long 0x04 "VDI_CMDP_1,VDI Combining Parameters Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ALPHA ,Global Alpha"
|
|
hexmask.long.byte 0x04 16.--23. 1. " KEY_COLOR_R ,Red component of Key Color"
|
|
hexmask.long.byte 0x04 8.--15. 1. " KEY_COLOR_G ,Green component of Key Color"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " KEY_COLOR_B ,Blue component of Key Color"
|
|
line.long 0x08 "VDI_CMDP_2,VDI Combining Parameters Register 2"
|
|
hexmask.long.byte 0x08 16.--23. 1. " VDI_KEY_COLOR_R ,Red component of background Color"
|
|
hexmask.long.byte 0x08 8.--15. 1. " VDI_KEY_COLOR_G ,Green component of background Color"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " VDI_KEY_COLOR_B ,Blue component of background Color"
|
|
line.long 0x0C "VDI_PS_1,VDI Plane Size Register 1"
|
|
hexmask.long.word 0x0C 16.--26. 1. " VDI_FHEIGHT1 ,Plane 1 height"
|
|
hexmask.long.word 0x0C 0.--10. 1. " VDI_FWIDTH1 ,Plane 1 width"
|
|
line.long 0x10 "VDI_PS_2,VDI Plane Size Register 2"
|
|
hexmask.long.word 0x10 16.--26. 1. " VDI_OFFSET_VER1 ,Vertical offset of plane 1"
|
|
hexmask.long.word 0x10 0.--10. 1. " VDI_OFFSET_HOR1 ,Horizontal offset of plane 1"
|
|
line.long 0x14 "VDI_PS_3,VDI Plane Size Register 3"
|
|
hexmask.long.word 0x14 16.--26. 1. " VDI_FHEIGHT3 ,Plane 3 height"
|
|
hexmask.long.word 0x14 0.--10. 1. " VDI_FWIDTH3 ,Plane 3 width"
|
|
line.long 0x18 "VDI_PS_4,VDI Plane Size Register 4"
|
|
hexmask.long.word 0x18 16.--26. 1. " VDI_OFFSET_VER3 ,Vertical offset of plane 3"
|
|
hexmask.long.word 0x18 0.--10. 1. " VDI_OFFSET_HOR3 ,Horizontal offset of plane 3"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "KPP (Keypad Port)"
|
|
base ad:0x73f94000
|
|
width 6.
|
|
group.word 0x00++0x7
|
|
line.word 0x00 "KPCR,Keypad Control Register"
|
|
bitfld.word 0x00 15. " KCO7 ,Keypad Column Strobe Open-Drain Enable 7" "Totem pole,Open drain"
|
|
bitfld.word 0x00 14. " KCO6 ,Keypad Column Strobe Open-Drain Enable 6" "Totem pole,Open drain"
|
|
bitfld.word 0x00 13. " KCO5 ,Keypad Column Strobe Open-Drain Enable 5" "Totem pole,Open drain"
|
|
bitfld.word 0x00 12. " KCO4 ,Keypad Column Strobe Open-Drain Enable 4" "Totem pole,Open drain"
|
|
bitfld.word 0x00 11. " KCO3 ,Keypad Column Strobe Open-Drain Enable 3" "Totem pole,Open drain"
|
|
bitfld.word 0x00 10. " KCO2 ,Keypad Column Strobe Open-Drain Enable 2" "Totem pole,Open drain"
|
|
bitfld.word 0x00 9. " KCO1 ,Keypad Column Strobe Open-Drain Enable 1" "Totem pole,Open drain"
|
|
bitfld.word 0x00 8. " KCO0 ,Keypad Column Strobe Open-Drain Enable 0" "Totem pole,Open drain"
|
|
textline " "
|
|
bitfld.word 0x00 7. " KRE7 ,Keypad Row Enable 7" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " KRE6 ,Keypad Row Enable 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " KRE5 ,Keypad Row Enable 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " KRE4 ,Keypad Row Enable 4" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " KRE3 ,Keypad Row Enable 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " KRE2 ,Keypad Row Enable 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " KRE1 ,Keypad Row Enable 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " KRE0 ,Keypad Row Enable 0" "Disabled,Enabled"
|
|
line.word 0x02 "KPSR,Keypad Status Register"
|
|
bitfld.word 0x02 9. " KRIE ,Keypad Release Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " KDIE ,Keypad Key Depress Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x02 3. " KRSS ,Key Release Synchronizer Set" "No effect,Set"
|
|
bitfld.word 0x02 2. " KDSC ,Key Depress Synchronizer Clear" "No effect,Clear"
|
|
eventfld.word 0x02 1. " KPKR ,Keypad Key Release" "Not released,Released"
|
|
eventfld.word 0x02 0. " KPKD ,Keypad Key Depress" "Not depressed,Depressed"
|
|
line.word 0x04 "KDDR,Keypad Data Direction Register"
|
|
bitfld.word 0x04 15. " KCDD7 ,Keypad Column Data Direction 7" "Input,Output"
|
|
bitfld.word 0x04 14. " KCDD6 ,Keypad Column Data Direction 6" "Input,Output"
|
|
bitfld.word 0x04 13. " KCDD5 ,Keypad Column Data Direction 5" "Input,Output"
|
|
bitfld.word 0x04 12. " KCDD4 ,Keypad Column Data Direction 4" "Input,Output"
|
|
bitfld.word 0x04 11. " KCDD3 ,Keypad Column Data Direction 3" "Input,Output"
|
|
bitfld.word 0x04 10. " KCDD2 ,Keypad Column Data Direction 2" "Input,Output"
|
|
bitfld.word 0x04 9. " KCDD1 ,Keypad Column Data Direction 1" "Input,Output"
|
|
bitfld.word 0x04 8. " KCDD0 ,Keypad Column Data Direction 0" "Input,Output"
|
|
textline " "
|
|
bitfld.word 0x04 7. " KRDD7 ,Keypad Row Data Direction 7" "Input,Output"
|
|
bitfld.word 0x04 6. " KRDD6 ,Keypad Row Data Direction 6" "Input,Output"
|
|
bitfld.word 0x04 5. " KRDD5 ,Keypad Row Data Direction 5" "Input,Output"
|
|
bitfld.word 0x04 4. " KRDD4 ,Keypad Row Data Direction 4" "Input,Output"
|
|
bitfld.word 0x04 3. " KRDD3 ,Keypad Row Data Direction 3" "Input,Output"
|
|
bitfld.word 0x04 2. " KRDD2 ,Keypad Row Data Direction 2" "Input,Output"
|
|
bitfld.word 0x04 1. " KRDD1 ,Keypad Row Data Direction 1" "Input,Output"
|
|
bitfld.word 0x04 0. " KRDD0 ,Keypad Row Data Direction 0" "Input,Output"
|
|
line.word 0x06 "KPDR,Keypad Data Register"
|
|
bitfld.word 0x06 15. " KCD7 ,Keypad Column Data 7" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 14. " KCD6 ,Keypad Column Data 6" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 13. " KCD5 ,Keypad Column Data 5" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 12. " KCD4 ,Keypad Column Data 4" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 11. " KCD3 ,Keypad Column Data 3" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 10. " KCD2 ,Keypad Column Data 2" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 9. " KCD1 ,Keypad Column Data 1" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 8. " KCD0 ,Keypad Column Data 0" "Pin=0,Pin=1"
|
|
textline " "
|
|
bitfld.word 0x06 7. " KRD7 ,Keypad Row Data 7" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 6. " KRD6 ,Keypad Row Data 6" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 5. " KRD5 ,Keypad Row Data 5" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 4. " KRD4 ,Keypad Row Data 4" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 3. " KRD3 ,Keypad Row Data 3" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 2. " KRD2 ,Keypad Row Data 2" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 1. " KRD1 ,Keypad Row Data 1" "Pin=0,Pin=1"
|
|
bitfld.word 0x06 0. " KRD0 ,Keypad Row Data 0" "Pin=0,Pin=1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "One-Wire (1-Wire)"
|
|
base ad:0x83fa4000
|
|
width 14.
|
|
group.byte 0x00++0x1
|
|
line.word 0x00 "CONTROL,Control Register"
|
|
bitfld.word 0x00 7. " RPP ,Reset Presence Pulse" "No Pulse,Pulse"
|
|
bitfld.word 0x00 6. " PST ,Presence Status" "Not present,Present"
|
|
bitfld.word 0x00 5. " WR0 ,Write 0" "No effect,Written"
|
|
textline " "
|
|
bitfld.word 0x00 4. " WR1 ,Write 1 / Read" "No effect,Written"
|
|
bitfld.word 0x00 3. " RDST ,Read Status" "0,1"
|
|
group.byte 0x02++0x1
|
|
line.word 0x00 "TIME_DIVIDER,Time Divider Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DVDR ,Pre-divider Factor"
|
|
group.byte 0x04++0x1
|
|
line.word 0x00 "RESET,Reset Register"
|
|
bitfld.word 0x00 0. " RST ,Software Reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree.open "PATA (Parallel Advanced Technology Attachment)"
|
|
tree "UDMA"
|
|
base ad:0x70030000
|
|
width 18.
|
|
tree "Timing Registers"
|
|
group.byte 0x00--0x18
|
|
line.byte 0x00 "TIME_OFF,TIME OFF Register"
|
|
hexmask.byte 0x00 0.--7. 1. " TIME_OFF[7:0] ,Transceiver Timing Parameter Controls TOFF"
|
|
line.byte 0x01 "TIME_ON,TIME ON Register"
|
|
hexmask.byte 0x01 0.--7. 1. " TIME_ON[7:0] ,Transceiver Timing Parameter Controls TON"
|
|
line.byte 0x02 "TIME_1,TIME 1 Register"
|
|
hexmask.byte 0x02 0.--7. 1. " TIME_1[7:0] ,PIO Timing Parameter Controls T1"
|
|
line.byte 0x03 "TIME_2W,TIME 2W Register"
|
|
hexmask.byte 0x03 0.--7. 1. " TIME_2W[7:0] ,PIO Timing Parameter Controls T2 During Write Cycles"
|
|
line.byte 0x04 "TIME_2R,TIME 2R Register"
|
|
hexmask.byte 0x04 0.--7. 1. " TIME_2R[7:0] ,PIO Timing Parameter Controls T2 During Read Cycles"
|
|
line.byte 0x05 "TIME_AX,TIME AX Register"
|
|
hexmask.byte 0x05 0.--7. 1. " TIME_AX[7:0] ,PIO Timing Parameter Controls TA"
|
|
line.byte 0x0f "TIME_PIO_RDX,TIME PIO RDX Register"
|
|
hexmask.byte 0x0f 0.--7. 1. " TIME_RDX[7:0] ,PIO Timing Parameter Controls TRD"
|
|
line.byte 0x07 "TIME_4,TIME 4 Register"
|
|
hexmask.byte 0x07 0.--7. 1. " TIME_4[7:0] ,PIO Timing Parameter Controls T4"
|
|
line.byte 0x08 "TIME_9,TIME 9 Register"
|
|
hexmask.byte 0x08 0.--7. 1. " TIME_9[7:0] ,PIO Timing Parameter Controls T9"
|
|
line.byte 0x09 "TIME_M,TIME M Register"
|
|
hexmask.byte 0x09 0.--7. 1. " TIME_M[7:0] ,MDMA Timing Parameter Controls TM"
|
|
line.byte 0x0a "TIME_JN,TIME JN Register"
|
|
hexmask.byte 0x0a 0.--7. 1. " TIME_JN[7:0] ,MDMA Timing Parameter Controls TN and TJ"
|
|
line.byte 0x0b "TIME_D,TIME D Register"
|
|
hexmask.byte 0x0b 0.--7. 1. " TIME_D[7:0] ,MDMA Timing Parameter Controls TD"
|
|
line.byte 0x0c "TIME_K,TIME K Register"
|
|
hexmask.byte 0x0c 0.--7. 1. " TIME_K[7:0] ,MDMA Timing Parameter Controls TK"
|
|
line.byte 0x0d "TIME_ACK,TIME ACK Register"
|
|
hexmask.byte 0x0d 0.--7. 1. " TIME_ACK[7:0] ,UDMA Timing Parameter Controls TACK"
|
|
line.byte 0x0e "TIME_ENV,TIME ENV Register"
|
|
hexmask.byte 0x0e 0.--7. 1. " TIME_ENV[7:0] ,UDMA Timing Parameter Controls TENV"
|
|
line.byte 0x0f "TIME_RPX,TIME RPX Register"
|
|
hexmask.byte 0x0f 0.--7. 1. " TIME_RPX[7:0] ,UDMA Timing Parameter Controls TRP"
|
|
line.byte 0x10 "TIME_ZAH,TIME ZAH Register"
|
|
hexmask.byte 0x10 0.--7. 1. " TIME_ZAH[7:0] ,UDMA Timing Parameter Controls TZAH"
|
|
line.byte 0x11 "TIME_MLIX,TIME MLIX Register"
|
|
hexmask.byte 0x11 0.--7. 1. " TIME_MLIX[7:0] ,UDMA Timing Parameter Controls TMLI"
|
|
line.byte 0x12 "TIME_DVH,TIME DVH Register"
|
|
hexmask.byte 0x12 0.--7. 1. " TIME_DVH[7:0] ,UDMA Timing Parameter Controls TDVH"
|
|
line.byte 0x13 "TIME_DZFS,TIME DZFS Register"
|
|
hexmask.byte 0x13 0.--7. 1. " TIME_DZFS[7:0] ,UDMA Timing Parameter Controls TDZFS"
|
|
line.byte 0x14 "TIME_DVS,TIME DVS Register"
|
|
hexmask.byte 0x14 0.--7. 1. " TIME_D[7:0] ,UDMA Timing Parameter Controls TDVS"
|
|
line.byte 0x15 "TIME_CVH,Time CVH Register"
|
|
hexmask.byte 0x15 0.--7. 1. " TIME_CVH[7:0] ,UDMA Timing Parameter Controls TCVH"
|
|
line.byte 0x16 "TIME_SS,TIME SS Register"
|
|
hexmask.byte 0x16 0.--7. 1. " TIME_SS[7:0] ,UDMA Timing Parameter Controls TSS"
|
|
line.byte 0x17 "TIME_CYC,TIME CYC Register"
|
|
hexmask.byte 0x17 0.--7. 1. " TIME_CYC[7:0] ,TIME_CYC Register"
|
|
tree.end
|
|
width 20.
|
|
sif cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FIFO_DATA_32,FIFO_DATA Register In 32-bit Mode"
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "FIFO_DATA_16,FIFO DATA Register In 16-bit Mode"
|
|
else
|
|
hgroup.word 0x1c++0x01
|
|
hide.word 0x00 "FIFO_DATA_16,FIFO DATA Register In 16-bit Mode"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "FIFO_DATA_32,FIFO_DATA Register In 32-bit Mode"
|
|
in
|
|
endif
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "FIFO_FILL,FIFO_FILL Register"
|
|
sif cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "PATA_CONTROL,PATA Interface Control Register"
|
|
bitfld.byte 0x00 7. " FIFO_RST_B ,FIFO Reset or Enable" "Reset,Normal"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " PATA_RST_B ,Control The Reset Of The Internal PATA" "Reset,Normal"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FIFO_TX_EN ,FIFO Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FIFO_RCV_EN ,FIFO Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DMA_PENDING ,DMA Pending Bit" "Not start,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DMA_ULTRA_SELECTED ,UDMA Or MDMA Protocol Is used" "MDMA,UDMA"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DMA_WRITE ,Data Direction On Any DMA" "In burst,Out burst"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IORDY_EN ,IORDY Handshake Or Disregarded" "Disregarded,Handshake"
|
|
else
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "ATA_CONTROL,ATA Control Register"
|
|
bitfld.byte 0x00 7. " FIFO_RST_B ,FIFO Reset or Enable" "Reset,Normal"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " ATA_RST_B ,Control The Reset Of The Internal ATA" "Reset,Normal"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FIFO_TX_EN ,FIFO Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FIFO_RCV_EN ,FIFO Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DMA_PENDING ,DMA Pending Bit" "Not start,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DMA_ULTRA_SELECTED ,UDMA Or MDMA Protocol Is used" "MDMA,UDMA"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DMA_WRITE ,Data Direction On Any DMA" "In burst,Out burst"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IORDY_EN ,IORDY Handshake Or Disregarded" "Disregarded,Handshake"
|
|
endif
|
|
rgroup.byte 0x28++0x00
|
|
line.byte 0x00 "INT_PENDING,Interrupt Pending Register"
|
|
bitfld.byte 0x00 7. " ATA_INTRQ1 ,ATA Interrupt Request 1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " FIFO_UNDERFLOW ,FIFO Underflow" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FIFO_OVERFLOW ,FIFO Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CONTROLLER_IDLE ,Controller Idle" "Active,Idle"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ATA_INTRQ2 ,ATA interrupt request 2" "Not pending,Pending"
|
|
group.byte 0x2c++0x00
|
|
line.byte 0x00 "INT_ENABLE,Interrupt_Enable Register"
|
|
bitfld.byte 0x00 7. " ATA_INTRQ1 ,ATA Interrupt Request 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " FIFO_UNDERFLOW ,FIFO Underflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FIFO_OVERFLOW ,FIFO Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CONTROLLER_IDLE ,Controller Idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ATA_INTRQ2 ,ATA Interrupt Request 2" "Disabled,Enabled"
|
|
wgroup.byte 0x30++0x00
|
|
line.byte 0x00 "INTERRUPT_CLEAR,Interrupt Clear Register"
|
|
bitfld.byte 0x00 6. " FIFO_UNDERFLOW ,FIFO Underflow Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FIFO_OVERFLOW ,FIFO Overflow Interrupt Clear" "No effect,Clear"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "FIFO_ALARM,FIFO Alarm Register"
|
|
hexmask.byte 0x00 0.--7. 1. " FIFO_ALARM[7:0] , FIFO Alarm Threshold"
|
|
group.word 0xa0++0x01
|
|
line.word 0x00 "DRIVE_DATA,Drive Data Register"
|
|
group.byte 0xa4++0x00
|
|
line.byte 0x00 "DRIVE_FEATURES,Drive Features Register"
|
|
group.byte 0xa8++0x00
|
|
line.byte 0x00 "DRIVE_SECTOR_COUNT,Drive Sector Count Register"
|
|
group.byte 0xac++0x00
|
|
line.byte 0x00 "DRIVE_SECTOR_NUM,Drive Sector Number Register"
|
|
group.byte 0xb0++0x00
|
|
line.byte 0x00 "DRIVE_CYL_LOW,Drive Cylinder Low Register"
|
|
group.byte 0xb4++0x00
|
|
line.byte 0x00 "DRIVE_CYL_HIGH,Drive Cylinder High Register"
|
|
group.byte 0xb8++0x00
|
|
line.byte 0x00 "DRIVE_DEV_HEAD,Drive Device Head Register"
|
|
sif cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"
|
|
group.byte 0xbc++0x00
|
|
line.byte 0x00 "DRIVE_COMMAND_STS,Drive Command/Status Register"
|
|
group.byte 0xd8++0x00
|
|
line.byte 0x00 "DRIVE_ALT_STS_CTRL,Drive Alternate Status/Control Register"
|
|
else
|
|
wgroup.byte 0xbc++0x00
|
|
line.byte 0x00 "DRIVE_COMMAND,Drive Command Register"
|
|
rgroup.byte 0xc0--0xc8
|
|
line.byte 0x00 "DRIVE_STATUS,Drive Status Register"
|
|
line.byte 0x04 "DRIVE_ALT_STATUS,Drive Alternate Status Register"
|
|
wgroup.byte 0xc8++0x00
|
|
line.byte 0x00 "DRIVE_CONTROL,Drive Control Register"
|
|
endif
|
|
width 0x14
|
|
tree.end
|
|
tree "PIO"
|
|
base ad:0x83fe0000
|
|
width 18.
|
|
tree "Timing Registers"
|
|
group.byte 0x00--0x18
|
|
line.byte 0x00 "TIME_OFF,TIME OFF Register"
|
|
hexmask.byte 0x00 0.--7. 1. " TIME_OFF[7:0] ,Transceiver Timing Parameter Controls TOFF"
|
|
line.byte 0x01 "TIME_ON,TIME ON Register"
|
|
hexmask.byte 0x01 0.--7. 1. " TIME_ON[7:0] ,Transceiver Timing Parameter Controls TON"
|
|
line.byte 0x02 "TIME_1,TIME 1 Register"
|
|
hexmask.byte 0x02 0.--7. 1. " TIME_1[7:0] ,PIO Timing Parameter Controls T1"
|
|
line.byte 0x03 "TIME_2W,TIME 2W Register"
|
|
hexmask.byte 0x03 0.--7. 1. " TIME_2W[7:0] ,PIO Timing Parameter Controls T2 During Write Cycles"
|
|
line.byte 0x04 "TIME_2R,TIME 2R Register"
|
|
hexmask.byte 0x04 0.--7. 1. " TIME_2R[7:0] ,PIO Timing Parameter Controls T2 During Read Cycles"
|
|
line.byte 0x05 "TIME_AX,TIME AX Register"
|
|
hexmask.byte 0x05 0.--7. 1. " TIME_AX[7:0] ,PIO Timing Parameter Controls TA"
|
|
line.byte 0x0f "TIME_PIO_RDX,TIME PIO RDX Register"
|
|
hexmask.byte 0x0f 0.--7. 1. " TIME_RDX[7:0] ,PIO Timing Parameter Controls TRD"
|
|
line.byte 0x07 "TIME_4,TIME 4 Register"
|
|
hexmask.byte 0x07 0.--7. 1. " TIME_4[7:0] ,PIO Timing Parameter Controls T4"
|
|
line.byte 0x08 "TIME_9,TIME 9 Register"
|
|
hexmask.byte 0x08 0.--7. 1. " TIME_9[7:0] ,PIO Timing Parameter Controls T9"
|
|
line.byte 0x09 "TIME_M,TIME M Register"
|
|
hexmask.byte 0x09 0.--7. 1. " TIME_M[7:0] ,MDMA Timing Parameter Controls TM"
|
|
line.byte 0x0a "TIME_JN,TIME JN Register"
|
|
hexmask.byte 0x0a 0.--7. 1. " TIME_JN[7:0] ,MDMA Timing Parameter Controls TN and TJ"
|
|
line.byte 0x0b "TIME_D,TIME D Register"
|
|
hexmask.byte 0x0b 0.--7. 1. " TIME_D[7:0] ,MDMA Timing Parameter Controls TD"
|
|
line.byte 0x0c "TIME_K,TIME K Register"
|
|
hexmask.byte 0x0c 0.--7. 1. " TIME_K[7:0] ,MDMA Timing Parameter Controls TK"
|
|
line.byte 0x0d "TIME_ACK,TIME ACK Register"
|
|
hexmask.byte 0x0d 0.--7. 1. " TIME_ACK[7:0] ,UDMA Timing Parameter Controls TACK"
|
|
line.byte 0x0e "TIME_ENV,TIME ENV Register"
|
|
hexmask.byte 0x0e 0.--7. 1. " TIME_ENV[7:0] ,UDMA Timing Parameter Controls TENV"
|
|
line.byte 0x0f "TIME_RPX,TIME RPX Register"
|
|
hexmask.byte 0x0f 0.--7. 1. " TIME_RPX[7:0] ,UDMA Timing Parameter Controls TRP"
|
|
line.byte 0x10 "TIME_ZAH,TIME ZAH Register"
|
|
hexmask.byte 0x10 0.--7. 1. " TIME_ZAH[7:0] ,UDMA Timing Parameter Controls TZAH"
|
|
line.byte 0x11 "TIME_MLIX,TIME MLIX Register"
|
|
hexmask.byte 0x11 0.--7. 1. " TIME_MLIX[7:0] ,UDMA Timing Parameter Controls TMLI"
|
|
line.byte 0x12 "TIME_DVH,TIME DVH Register"
|
|
hexmask.byte 0x12 0.--7. 1. " TIME_DVH[7:0] ,UDMA Timing Parameter Controls TDVH"
|
|
line.byte 0x13 "TIME_DZFS,TIME DZFS Register"
|
|
hexmask.byte 0x13 0.--7. 1. " TIME_DZFS[7:0] ,UDMA Timing Parameter Controls TDZFS"
|
|
line.byte 0x14 "TIME_DVS,TIME DVS Register"
|
|
hexmask.byte 0x14 0.--7. 1. " TIME_D[7:0] ,UDMA Timing Parameter Controls TDVS"
|
|
line.byte 0x15 "TIME_CVH,Time CVH Register"
|
|
hexmask.byte 0x15 0.--7. 1. " TIME_CVH[7:0] ,UDMA Timing Parameter Controls TCVH"
|
|
line.byte 0x16 "TIME_SS,TIME SS Register"
|
|
hexmask.byte 0x16 0.--7. 1. " TIME_SS[7:0] ,UDMA Timing Parameter Controls TSS"
|
|
line.byte 0x17 "TIME_CYC,TIME CYC Register"
|
|
hexmask.byte 0x17 0.--7. 1. " TIME_CYC[7:0] ,TIME_CYC Register"
|
|
tree.end
|
|
width 20.
|
|
sif cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FIFO_DATA_32,FIFO_DATA Register In 32-bit Mode"
|
|
group.word 0x1c++0x01
|
|
line.word 0x00 "FIFO_DATA_16,FIFO DATA Register In 16-bit Mode"
|
|
else
|
|
hgroup.word 0x1c++0x01
|
|
hide.word 0x00 "FIFO_DATA_16,FIFO DATA Register In 16-bit Mode"
|
|
in
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "FIFO_DATA_32,FIFO_DATA Register In 32-bit Mode"
|
|
in
|
|
endif
|
|
rgroup.byte 0x20++0x00
|
|
line.byte 0x00 "FIFO_FILL,FIFO_FILL Register"
|
|
sif cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "PATA_CONTROL,PATA Interface Control Register"
|
|
bitfld.byte 0x00 7. " FIFO_RST_B ,FIFO Reset or Enable" "Reset,Normal"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " PATA_RST_B ,Control The Reset Of The Internal PATA" "Reset,Normal"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FIFO_TX_EN ,FIFO Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FIFO_RCV_EN ,FIFO Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DMA_PENDING ,DMA Pending Bit" "Not start,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DMA_ULTRA_SELECTED ,UDMA Or MDMA Protocol Is used" "MDMA,UDMA"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DMA_WRITE ,Data Direction On Any DMA" "In burst,Out burst"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IORDY_EN ,IORDY Handshake Or Disregarded" "Disregarded,Handshake"
|
|
else
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "ATA_CONTROL,ATA Control Register"
|
|
bitfld.byte 0x00 7. " FIFO_RST_B ,FIFO Reset or Enable" "Reset,Normal"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " ATA_RST_B ,Control The Reset Of The Internal ATA" "Reset,Normal"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FIFO_TX_EN ,FIFO Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FIFO_RCV_EN ,FIFO Receive Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DMA_PENDING ,DMA Pending Bit" "Not start,Start"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DMA_ULTRA_SELECTED ,UDMA Or MDMA Protocol Is used" "MDMA,UDMA"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DMA_WRITE ,Data Direction On Any DMA" "In burst,Out burst"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IORDY_EN ,IORDY Handshake Or Disregarded" "Disregarded,Handshake"
|
|
endif
|
|
rgroup.byte 0x28++0x00
|
|
line.byte 0x00 "INT_PENDING,Interrupt Pending Register"
|
|
bitfld.byte 0x00 7. " ATA_INTRQ1 ,ATA Interrupt Request 1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " FIFO_UNDERFLOW ,FIFO Underflow" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FIFO_OVERFLOW ,FIFO Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CONTROLLER_IDLE ,Controller Idle" "Active,Idle"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ATA_INTRQ2 ,ATA interrupt request 2" "Not pending,Pending"
|
|
group.byte 0x2c++0x00
|
|
line.byte 0x00 "INT_ENABLE,Interrupt_Enable Register"
|
|
bitfld.byte 0x00 7. " ATA_INTRQ1 ,ATA Interrupt Request 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 6. " FIFO_UNDERFLOW ,FIFO Underflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FIFO_OVERFLOW ,FIFO Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CONTROLLER_IDLE ,Controller Idle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " ATA_INTRQ2 ,ATA Interrupt Request 2" "Disabled,Enabled"
|
|
wgroup.byte 0x30++0x00
|
|
line.byte 0x00 "INTERRUPT_CLEAR,Interrupt Clear Register"
|
|
bitfld.byte 0x00 6. " FIFO_UNDERFLOW ,FIFO Underflow Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " FIFO_OVERFLOW ,FIFO Overflow Interrupt Clear" "No effect,Clear"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "FIFO_ALARM,FIFO Alarm Register"
|
|
hexmask.byte 0x00 0.--7. 1. " FIFO_ALARM[7:0] , FIFO Alarm Threshold"
|
|
group.word 0xa0++0x01
|
|
line.word 0x00 "DRIVE_DATA,Drive Data Register"
|
|
group.byte 0xa4++0x00
|
|
line.byte 0x00 "DRIVE_FEATURES,Drive Features Register"
|
|
group.byte 0xa8++0x00
|
|
line.byte 0x00 "DRIVE_SECTOR_COUNT,Drive Sector Count Register"
|
|
group.byte 0xac++0x00
|
|
line.byte 0x00 "DRIVE_SECTOR_NUM,Drive Sector Number Register"
|
|
group.byte 0xb0++0x00
|
|
line.byte 0x00 "DRIVE_CYL_LOW,Drive Cylinder Low Register"
|
|
group.byte 0xb4++0x00
|
|
line.byte 0x00 "DRIVE_CYL_HIGH,Drive Cylinder High Register"
|
|
group.byte 0xb8++0x00
|
|
line.byte 0x00 "DRIVE_DEV_HEAD,Drive Device Head Register"
|
|
sif cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"
|
|
group.byte 0xbc++0x00
|
|
line.byte 0x00 "DRIVE_COMMAND_STS,Drive Command/Status Register"
|
|
group.byte 0xd8++0x00
|
|
line.byte 0x00 "DRIVE_ALT_STS_CTRL,Drive Alternate Status/Control Register"
|
|
else
|
|
wgroup.byte 0xbc++0x00
|
|
line.byte 0x00 "DRIVE_COMMAND,Drive Command Register"
|
|
rgroup.byte 0xc0--0xc8
|
|
line.byte 0x00 "DRIVE_STATUS,Drive Status Register"
|
|
line.byte 0x04 "DRIVE_ALT_STATUS,Drive Alternate Status Register"
|
|
wgroup.byte 0xc8++0x00
|
|
line.byte 0x00 "DRIVE_CONTROL,Drive Control Register"
|
|
endif
|
|
width 0x14
|
|
tree.end
|
|
tree.end
|
|
tree.open "PWM (Pulse-Width Modulator)"
|
|
tree "PWM 1"
|
|
base ad:0x73fb4000
|
|
width 8.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots"
|
|
bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped"
|
|
bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped"
|
|
bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k"
|
|
hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value"
|
|
bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PWMSR,PWM Status Register"
|
|
eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark"
|
|
textline " "
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..."
|
|
else
|
|
bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..."
|
|
endif
|
|
line.long 0x08 "PWMIR,PWM Interrupt Register"
|
|
bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
if (((per.l(ad:0x73fb4000+0x00))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PWMPR,PWM Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "PWMCNR,PWM Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM 2"
|
|
base ad:0x73fb8000
|
|
width 8.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 26.--27. " FWM ,FIFO Water Mark" "1 slot,2 slots,3 slots,4 slots"
|
|
bitfld.long 0x00 25. " STOPEN ,Stop Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DOZEN ,Doze Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " WAITEN ,Wait Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DBGEN ,Debug Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " BCTR ,Byte Data Swap Control" "Not swapped,Swapped"
|
|
bitfld.long 0x00 20. " HCTR ,Half-word Data Swap Control" "Not swapped,Swapped"
|
|
bitfld.long 0x00 18.--19. " POUTC ,PWM Output Configuration" "Output set/Rollover cleared,Output cleared/Rollover set,Disconnected,Disconnected"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CLKSRC ,Select Clock Source" "Off,ipg_clk,ipg_clk_highfreq,ipg_clk_32k"
|
|
hexmask.long.word 0x00 4.--15. 1. " PRESCALER ,Counter Clock Prescaler Value"
|
|
bitfld.long 0x00 3. " SWR ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1.--2. " REPEAT ,Sample Repeat" "Once,Twice,Four times,Eight times"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,PWM Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PWMSR,PWM Status Register"
|
|
eventfld.long 0x04 6. " FWE ,FIFO Write Error Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " CMP ,Compare Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 4. " ROV ,Roll-over Status" "Not occurred,Occurred"
|
|
eventfld.long 0x04 3. " FE ,FIFO Empty Status" "Above mark,Below mark"
|
|
textline " "
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rbitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..."
|
|
else
|
|
bitfld.long 0x04 0.--2. " FIFOAV ,FIFO Available" "No available,1 word,2 words,3 words,4 words,?..."
|
|
endif
|
|
line.long 0x08 "PWMIR,PWM Interrupt Register"
|
|
bitfld.long 0x08 2. " CIE ,Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " RIE ,Roll-over Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " FIE ,FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
if (((per.l(ad:0x73fb8000+0x00))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
endif
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMSAR,PWM Sample Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SAMPLE ,Sample Value"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PWMPR,PWM Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " PERIOD ,Period Value"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "PWMCNR,PWM Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter Value"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SIM (Subscriber Identification Module)"
|
|
base ad:0x83fe4000
|
|
width 15.
|
|
group.long 0x00++0xf
|
|
line.long 0x00 "PORT1_CNTL,Port1 Control Register"
|
|
bitfld.long 0x00 7. " SFPD1 ,Auto Power Down port1" "No effect,Started"
|
|
bitfld.long 0x00 6. " 3VOLT1 ,3 Volt SIM Card port1" "RCV/XMT,XMT"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCSP1 ,SIM Card Clock Stop Polarity port1" "Low,High"
|
|
bitfld.long 0x00 4. " SCEN1 ,SIM card Clock Enable Port 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SRST1 ,SIM card Reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " STEN1 ,SIM card Transmit Enable Port 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SVEN1 ,SIM card Vcc Enable Port 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAPD1 ,SIM card Auto Power Down Port 1" "Disabled,Enabled"
|
|
line.long 0x04 "SETUP,Setup Register"
|
|
bitfld.long 0x04 1. " SPS ,SIM card Port Select" "Port 0,Port 1"
|
|
bitfld.long 0x04 0. " AMODE ,Alternate SIM Card Mode enable" "Disabled,Enabled"
|
|
line.long 0x08 "PORT1_DETECT,Port1 Detect Register"
|
|
bitfld.long 0x08 3. " SPDS1 ,SIM Presence Detect Select Port 1" "Falling edge,Rising edge"
|
|
bitfld.long 0x08 2. " SPDP1 ,SIMPD1 input pin status" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x08 1. " SDI1 ,SIM Detect Interrupt flag Port 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " SDIM1 ,SIM Detect Interrupt Mask Port 1" "Not masked,Masked"
|
|
line.long 0x0c "PORT1_XMT_BUF,Port1 Transmit Buffer Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " PORT1_XMT ,Port1 Transmit Buffer"
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "PORT1_RCV_BUF,Port1 Receive Buffer Register"
|
|
in
|
|
group.long 0x14++0x1f
|
|
line.long 0x00 "PORT0_CNTL,Port0 Control Register"
|
|
bitfld.long 0x00 7. " SFPD0 ,Auto Power Down port0" "No effect,Started"
|
|
bitfld.long 0x00 6. " 3VOLT0 ,3 Volt SIM Card port0" "RCV/XMT,XMT"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCSP0 ,SIM Card Clock Stop Polarity port0" "Low,High"
|
|
bitfld.long 0x00 4. " SCEN0 ,SIM card Clock Enable Port 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SRST0 ,SIM card Reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " STEN0 ,SIM card Transmit Enable Port 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SVEN0 ,SIM card Vcc Enable Port 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SAPD0 ,SIM card Auto Power Down Port 0" "Disabled,Enabled"
|
|
line.long 0x04 "CNTL,SIM Control Register"
|
|
bitfld.long 0x04 15. " BWTEN ,Block wait time enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XMT_CRC_LRC ,Transmit CRC or LRC" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CRCEN ,CRC Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LRCEN ,LRC Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CWTEN ,Character Wait Time Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9.--10. " GPCNT_CLK_SEL[1:0] ,General Purpose Counter Clock Select" "Disabled,Card,Receive,ETU"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " BAUD_SEL[2:0] ,SIM Baud Rate Select" "31,32,16,8,4,2,1,DIVISOR reg"
|
|
bitfld.long 0x04 4. " SAMPLE12 ,Sample12" "Div by 8,Div by 12"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ONACK ,Overrun NACK Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ANACK ,Automatic NACK Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ICM ,Initial Character Mode" "Disabled,Enabled"
|
|
line.long 0x08 "CLK_PRESCALER,SIM Clock Prescaler Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CLK_PRESCALER[7:0] ,Clock Prescaler Divisor Register"
|
|
line.long 0x0c "RCV_THRESHOLD,Receive Threshold Register"
|
|
bitfld.long 0x0c 9.--12. " RTH[3:0] ,Receive NackThreshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x0c 0.--8. 1. " RDT[8:0] ,Receive Data Threshold"
|
|
line.long 0x10 "ENABLE,Enable Register"
|
|
bitfld.long 0x10 3. " TXDMA_EN ,Transmitter DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " RXDMA_EN ,Receiver DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " XMT_EN ,SIM Transmit Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " RCV_EN ,SIM Receiver Enable" "Disabled,Enabled"
|
|
line.long 0x14 "XMT_STATUS,Transmit Status Register"
|
|
eventfld.long 0x14 8. " GPCNT ,General purpose Counter Flag" "Not reached,Reached"
|
|
eventfld.long 0x14 7. " TDTF ,Transmit FIFO Threshold Flag" "> TDT[3:0] / cleared,< = TDT[3:0]"
|
|
textline " "
|
|
eventfld.long 0x14 6. " TFO ,Transmit FIFO Overfill Error" "No error,Error"
|
|
eventfld.long 0x14 5. " TC ,Transmit Complete" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x14 4. " ETC ,Early Transmit Complete" "Not completed,Completed"
|
|
eventfld.long 0x14 3. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x14 0. " XTE ,Transmit Threshold Error" "Not reached,Reached"
|
|
line.long 0x18 "RCV_STATUS,Receive Status Register"
|
|
eventfld.long 0x18 11. " BGT ,Block guard time error flag" "No error,Error"
|
|
eventfld.long 0x18 10. " BWT ,Block wait time error flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x18 9. " RTE ,Receive NACK threshold error flag" "< RTH[3:0],= RTH[3:0]"
|
|
eventfld.long 0x18 8. " CWT ,Character Wait Time Counter Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x18 7. " CRCOK ,Cyclic Redundancy Check Okay flag" "Not matched,Matched"
|
|
bitfld.long 0x18 6. " LRCOK ,Linear Redundancy Check Okay flag" "Not matched,Matched"
|
|
textline " "
|
|
bitfld.long 0x18 5. " RDRF ,Receive Data Register Full" "< RDT[8:0],>= RDT[8:0]"
|
|
bitfld.long 0x18 4. " RFD ,Receive FIFO has unread Data" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x18 1. " RFE ,Receive FIFO Empty" "Not empty,Empty"
|
|
eventfld.long 0x18 0. " OEF ,Overrun Error Flag" "No overrun,Overrun"
|
|
line.long 0x1c "INT_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x1c 13. " RFEM ,Receive fifo empty interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1c 12. " BGTM ,Block guard time interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x1c 11. " BWTM ,Block wait time interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1c 10. " RTM ,Receive Nack threshold interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x1c 9. " CWTM ,Character Wait Time Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1c 8. " GPCNTM ,General Purpose Counter Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x1c 7. " TDTFM ,Transmit Data Threshold Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1c 6. " TFOM ,Transmit FIFO Overfill Error Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x1c 5. " XTM ,Transmit Threshold Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1c 4. " TFEIM ,Transmit FIFO Empty Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x1c 3. " ETCIM ,Early Transmit Complete Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1c 2. " OIM ,Overrun Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x1c 1. " TCIM ,Transmit Complete Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x1c 0. " RIM ,Receive Interrupt Mask" "Not masked,Masked"
|
|
group.long 0x3c++0x2f
|
|
line.long 0x00 "PORT0_DETECT,Port0 Detect Register"
|
|
bitfld.long 0x00 3. " SPDS0 ,SIM Presence Detect Select Port 0" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 2. " SPDP0 ,SIMPD0 input pin status" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 1. " SDI0 ,SIM Detect Interrupt flag Port 0" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " SDIM0 ,SIM Detect Interrupt Mask Port 0" "Not masked,Masked"
|
|
line.long 0x04 "DATA_FORMAT,Data Format Register"
|
|
bitfld.long 0x04 0. " IC ,Inverse Conversion" "Direct,Inverted"
|
|
line.long 0x08 "XMT_THRESHOLD,Transmit Threshold Register"
|
|
bitfld.long 0x08 4.--7. " XTH[3:0] ,Transmit NACK Threshold" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " TDT[3:0] ,Transmit Data Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0c "GUARD_CNTL,Transmit Guard Control Register"
|
|
bitfld.long 0x0c 8. " RCVR11 ,Receiver use 11 ETUs" "12 ETU,11 EUT"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " GETU[7:0] ,Transmit Guard ETUs"
|
|
line.long 0x10 "OD_CONFIG,Open Drain Configuration Control Register"
|
|
bitfld.long 0x10 1. " OD_P1 ,Open Drain Control for Port 1" "Push-pull,Open-drain"
|
|
bitfld.long 0x10 0. " OD_P0 ,Open Drain Control for Port 0" "Push-pull,Open-drain"
|
|
width 15.
|
|
line.long 0x14 "RESET_CNTL,Reset Control Register"
|
|
bitfld.long 0x14 6. " DBUG ,DEBUG" "No effect,Read pointer frozen"
|
|
bitfld.long 0x14 5. " STOP ,STOP" "All,Except baud_clk"
|
|
textline " "
|
|
bitfld.long 0x14 4. " DOZE ,DOZE" "No effect,Clocks gated"
|
|
bitfld.long 0x14 3. " KILL_CLOCK ,Kill SIM Clock" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " SOFT_RST ,Software Reset" "Normal,Reset"
|
|
bitfld.long 0x14 1. " FLUSH_XMT ,Flush Transmitter" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 0. " FLUSH_RCV ,Flush Receiver" "Normal,Reset"
|
|
line.long 0x18 "CHAR_WAIT,Character Wait Time Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " CWT ,Character Wait Time"
|
|
line.long 0x1c "GPCNT,General Purpose Counter Register"
|
|
hexmask.long.word 0x1c 0.--15. 1. " GPCNT ,General Purpose Counter"
|
|
line.long 0x20 "DIVISOR,DIVISOR Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " DIVISOR ,Divisor"
|
|
line.long 0x24 "BWT,Block Wait Time Register"
|
|
hexmask.long.word 0x24 0.--15. 1. " BWT ,BWT Register 16 LSB"
|
|
line.long 0x28 "BGT,Block Guard Time Register"
|
|
hexmask.long.word 0x28 0.--15. 1. " BGT ,Block Wait Guard Time"
|
|
line.long 0x2c "BWT_H,Block Wait Time Register High"
|
|
hexmask.long.word 0x2c 0.--15. 1. " BWT_H ,BWT Register 16 MSB"
|
|
rgroup.long 0x6c++0xf
|
|
line.long 0x00 "XMT_FIFO_STAT,SIM Transmit FIFO Status Register"
|
|
bitfld.long 0x00 8.--11. " XMT_CNT[3:0] ,Transmit FIFO Byte Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " XMT_WPTR[3:0] ,Transmit FIFO Write Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " XMT_RPTR[3:0] ,Transmit FIFO Read Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "RCV_FIFO_CNT,SIM Receive FIFO Counter Register"
|
|
hexmask.long.word 0x04 0.--8. 1. " RCV_CNT[8:0] ,Receive FIFO Byte Number"
|
|
line.long 0x08 "RCV_FIFO_WPTR,SIM Receive FIFO Write Pointer Register"
|
|
hexmask.long.word 0x08 0.--8. 1. " RCV_WPTR[8:0] ,Receive FIFO Write Pointer"
|
|
line.long 0x0c "RCV_FIFO_RPTR,SIM Receive FIFO Read Pointer Register"
|
|
hexmask.long.word 0x0c 0.--8. 1. " RCV_RPTR[8:0] ,Receive FIFO Read Pointer"
|
|
width 0xb
|
|
tree.end
|
|
tree "SDMA (Smart Direct Memory Access Controller)"
|
|
base ad:0x83fb0000
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "MC0PTR,AP Channel 0 Pointer Register"
|
|
line.long 0x04 "INTR,Channel Interrupts Register"
|
|
eventfld.long 0x04 31. " HI[31] ,AP HI[31] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 30. " HI[30] ,AP HI[30] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 29. " HI[29] ,AP HI[29] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 28. " HI[28] ,AP HI[28] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 27. " HI[27] ,AP HI[27] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 26. " HI[26] ,AP HI[26] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 25. " HI[25] ,AP HI[25] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 24. " HI[24] ,AP HI[24] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 23. " HI[23] ,AP HI[23] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 22. " HI[22] ,AP HI[22] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 21. " HI[21] ,AP HI[21] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 20. " HI[20] ,AP HI[20] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 19. " HI[19] ,AP HI[19] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 18. " HI[18] ,AP HI[18] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 17. " HI[17] ,AP HI[17] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 16. " HI[16] ,AP HI[16] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 15. " HI[15] ,AP HI[15] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " HI[14] ,AP HI[14] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 13. " HI[13] ,AP HI[13] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " HI[12] ,AP HI[12] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 11. " HI[11] ,AP HI[11] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 10. " HI[10] ,AP HI[10] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " HI[9] ,AP HI[9] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " HI[8] ,AP HI[8] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 7. " HI[7] ,AP HI[7] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " HI[6] ,AP HI[6] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " HI[5] ,AP HI[5] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " HI[4] ,AP HI[4] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " HI[3] ,AP HI[3] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " HI[2] ,AP HI[2] Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 1. " HI[1] ,AP HI[1] Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " HI[0] ,AP HI[0] Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "STOP_STAT,Channel Stop/Channel Status Register"
|
|
eventfld.long 0x08 31. " HE[31] ,HE[31] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 30. " HE[30] ,HE[30] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 29. " HE[29] ,HE[29] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 28. " HE[28] ,HE[28] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 27. " HE[27] ,HE[27] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 26. " HE[26] ,HE[26] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 25. " HE[25] ,HE[25] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 24. " HE[24] ,HE[24] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 23. " HE[23] ,HE[23] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 22. " HE[22] ,HE[22] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 21. " HE[21] ,HE[21] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 20. " HE[20] ,HE[20] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 19. " HE[19] ,HE[19] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 18. " HE[18] ,HE[18] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 17. " HE[17] ,HE[17] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 16. " HE[16] ,HE[16] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 15. " HE[15] ,HE[15] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 14. " HE[14] ,HE[14] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 13. " HE[13] ,HE[13] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 12. " HE[12] ,HE[12] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 11. " HE[11] ,HE[11] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 10. " HE[10] ,HE[10] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 9. " HE[9] ,HE[9] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 8. " HE[8] ,HE[8] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 7. " HE[7] ,HE[7] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 6. " HE[6] ,HE[6] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 5. " HE[5] ,HE[5] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 4. " HE[4] ,HE[4] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 3. " HE[3] ,HE[3] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 2. " HE[2] ,HE[2] Stop/Status" "No access,Access"
|
|
textline " "
|
|
eventfld.long 0x08 1. " HE[1] ,HE[1] Stop/Status" "No access,Access"
|
|
eventfld.long 0x08 0. " HE[0] ,HE[0] Stop/Status" "No access,Access"
|
|
line.long 0x0C "HSTART,Channel Start Register"
|
|
eventfld.long 0x0C 31. " HSTART[31] ,Channel 31 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 30. " HSTART[30] ,Channel 30 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 29. " HSTART[29] ,Channel 29 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 28. " HSTART[28] ,Channel 28 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 27. " HSTART[27] ,Channel 27 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 26. " HSTART[26] ,Channel 26 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " HSTART[25] ,Channel 25 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 24. " HSTART[24] ,Channel 24 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 23. " HSTART[23] ,Channel 23 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 22. " HSTART[22] ,Channel 22 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 21. " HSTART[21] ,Channel 21 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 20. " HSTART[20] ,Channel 20 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " HSTART[19] ,Channel 19 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 18. " HSTART[18] ,Channel 18 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 17. " HSTART[17] ,Channel 17 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 16. " HSTART[16] ,Channel 16 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 15. " HSTART[15] ,Channel 15 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 14. " HSTART[14] ,Channel 14 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " HSTART[13] ,Channel 13 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 12. " HSTART[12] ,Channel 12 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 11. " HSTART[11] ,Channel 11 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 10. " HSTART[10] ,Channel 10 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 9. " HSTART[9] ,Channel 9 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 8. " HSTART[8] ,Channel 8 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " HSTART[7] ,Channel 7 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 6. " HSTART[6] ,Channel 6 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 5. " HSTART[5] ,Channel 5 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 4. " HSTART[4] ,Channel 4 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 3. " HSTART[3] ,Channel 3 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 2. " HSTART[2] ,Channel 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " HSTART[1] ,Channel 1 Enable" "Disabled,Enabled"
|
|
eventfld.long 0x0C 0. " HSTART[0] ,Channel 0 Enable" "Disabled,Enabled"
|
|
line.long 0x10 "EVTOVR,Channel Event Override Register"
|
|
bitfld.long 0x10 31. " EO[31] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 30. " EO[30] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 29. " EO[29] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 28. " EO[28] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 27. " EO[27] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 26. " EO[26] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EO[25] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 24. " EO[24] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 23. " EO[23] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 22. " EO[22] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 21. " EO[21] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 20. " EO[20] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 19. " EO[19] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 18. " EO[18] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 17. " EO[17] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 16. " EO[16] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 15. " EO[15] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 14. " EO[14] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 13. " EO[13] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 12. " EO[12] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 11. " EO[11] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 10. " EO[10] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 9. " EO[9] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 8. " EO[8] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 7. " EO[7] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 6. " EO[6] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 5. " EO[5] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EO[4] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 3. " EO[3] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 2. " EO[2] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x10 1. " EO[1] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x10 0. " EO[0] ,DMA Request Ignored by SDMA" "Not ignored,Ignored"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "DSPOVR,Channel BP Override Register"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "HOSTOVR,Channel AP Override Register"
|
|
bitfld.long 0x00 31. " HO[31] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 30. " HO[30] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 29. " HO[29] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 28. " HO[28] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 27. " HO[27] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 26. " HO[26] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HO[25] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 24. " HO[24] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 23. " HO[23] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 22. " HO[22] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 21. " HO[21] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 20. " HO[20] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HO[19] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 18. " HO[18] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 17. " HO[17] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HO[16] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 15. " HO[15] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 14. " HO[14] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HO[13] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 12. " HO[12] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 11. " HO[11] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HO[10] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " HO[9] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 8. " HO[8] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HO[7] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 6. " HO[6] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 5. " HO[5] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HO[4] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 3. " HO[3] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 2. " HO[2] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HO[1] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
bitfld.long 0x00 0. " HO[0] ,AP Enable Ignored by SDMA" "Not ignored,Ignored"
|
|
sif (cpuis("IMX6*"))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "EVTPEND,Channel Event Pending Register"
|
|
eventfld.long 0x00 31. " EP[31] ,Channel 31 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " EP[30] ,Channel 30 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " EP[29] ,Channel 29 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 28. " EP[28] ,Channel 28 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 27. " EP[27] ,Channel 27 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " EP[26] ,Channel 26 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 25. " EP[25] ,Channel 25 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " EP[24] ,Channel 24 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 23. " EP[23] ,Channel 23 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 22. " EP[22] ,Channel 22 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " EP[21] ,Channel 21 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " EP[20] ,Channel 20 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 19. " EP[19] ,Channel 19 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " EP[18] ,Channel 18 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " EP[17] ,Channel 17 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " EP[16] ,Channel 16 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 15. " EP[15] ,Channel 15 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " EP[14] ,Channel 14 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " EP[13] ,Channel 13 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " EP[12] ,Channel 12 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 11. " EP[11] ,Channel 11 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " EP[10] ,Channel 10 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " EP[9] ,Channel 9 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " EP[8] ,Channel 8 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 7. " EP[7] ,Channel 7 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " EP[6] ,Channel 6 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " EP[5] ,Channel 5 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 4. " EP[4] ,Channel 4 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 3. " EP[3] ,Channel 3 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " EP[2] ,Channel 2 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EP[1] ,Channel 1 Event Pending" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " EP[0] ,Channel 0 Event Pending" "Not pending,Pending"
|
|
else
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "EVTPEND,Channel Event Pending Register"
|
|
bitfld.long 0x00 31. " EP[31] ,Channel 31 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " EP[30] ,Channel 30 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " EP[29] ,Channel 29 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EP[28] ,Channel 28 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " EP[27] ,Channel 27 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " EP[26] ,Channel 26 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EP[25] ,Channel 25 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " EP[24] ,Channel 24 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " EP[23] ,Channel 23 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " EP[22] ,Channel 22 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " EP[21] ,Channel 21 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " EP[20] ,Channel 20 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EP[19] ,Channel 19 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " EP[18] ,Channel 18 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " EP[17] ,Channel 17 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EP[16] ,Channel 16 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " EP[15] ,Channel 15 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " EP[14] ,Channel 14 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EP[13] ,Channel 13 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " EP[12] ,Channel 12 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " EP[11] ,Channel 11 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EP[10] ,Channel 10 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " EP[9] ,Channel 9 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " EP[8] ,Channel 8 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EP[7] ,Channel 7 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " EP[6] ,Channel 6 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " EP[5] ,Channel 5 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EP[4] ,Channel 4 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " EP[3] ,Channel 3 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " EP[2] ,Channel 2 Event Pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EP[1] ,Channel 1 Event Pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " EP[0] ,Channel 0 Event Pending" "Not pending,Pending"
|
|
endif
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x00 "RESET,Reset Register"
|
|
bitfld.long 0x00 1. " RESCHED ,SDMA Reschedule as If a Script had Executed a Done Instruction" "Off,On"
|
|
bitfld.long 0x00 0. " RESET ,Software Reset" "No effect,Reset"
|
|
sif (cpuis("IMX6*"))
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "EVTERR,DMA Request Error Register"
|
|
in
|
|
else
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "EVTERR,DMA Request Error Register"
|
|
bitfld.long 0x00 31. " CHNERR[31] ,Channel 31 Error" "No error,Error"
|
|
bitfld.long 0x00 30. " CHNERR[30] ,Channel 30 Error" "No error,Error"
|
|
bitfld.long 0x00 29. " CHNERR[29] ,Channel 29 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CHNERR[28] ,Channel 28 Error" "No error,Error"
|
|
bitfld.long 0x00 27. " CHNERR[27] ,Channel 27 Error" "No error,Error"
|
|
bitfld.long 0x00 26. " CHNERR[26] ,Channel 26 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CHNERR[25] ,Channel 25 Error" "No error,Error"
|
|
bitfld.long 0x00 24. " CHNERR[24] ,Channel 24 Error" "No error,Error"
|
|
bitfld.long 0x00 23. " CHNERR[23] ,Channel 23 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CHNERR[22] ,Channel 22 Error" "No error,Error"
|
|
bitfld.long 0x00 21. " CHNERR[21] ,Channel 21 Error" "No error,Error"
|
|
bitfld.long 0x00 20. " CHNERR[20] ,Channel 20 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CHNERR[19] ,Channel 19 Error" "No error,Error"
|
|
bitfld.long 0x00 18. " CHNERR[18] ,Channel 18 Error" "No error,Error"
|
|
bitfld.long 0x00 17. " CHNERR[17] ,Channel 17 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CHNERR[16] ,Channel 16 Error" "No error,Error"
|
|
bitfld.long 0x00 15. " CHNERR[15] ,Channel 15 Error" "No error,Error"
|
|
bitfld.long 0x00 14. " CHNERR[14] ,Channel 14 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CHNERR[13] ,Channel 13 Error" "No error,Error"
|
|
bitfld.long 0x00 12. " CHNERR[12] ,Channel 12 Error" "No error,Error"
|
|
bitfld.long 0x00 11. " CHNERR[11] ,Channel 11 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CHNERR[10] ,Channel 10 Error" "No error,Error"
|
|
bitfld.long 0x00 9. " CHNERR[9] ,Channel 9 Error" "No error,Error"
|
|
bitfld.long 0x00 8. " CHNERR[8] ,Channel 8 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CHNERR[7] ,Channel 7 Error" "No error,Error"
|
|
bitfld.long 0x00 6. " CHNERR[6] ,Channel 6 Error" "No error,Error"
|
|
bitfld.long 0x00 5. " CHNERR[5] ,Channel 5 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CHNERR[4] ,Channel 4 Error" "No error,Error"
|
|
bitfld.long 0x00 3. " CHNERR[3] ,Channel 3 Error" "No error,Error"
|
|
bitfld.long 0x00 2. " CHNERR[2] ,Channel 2 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHNERR[1] ,Channel 1 Error" "No error,Error"
|
|
bitfld.long 0x00 0. " CHNERR[0] ,Channel 0 Error" "No error,Error"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTRMASK,Channel AP Interrupt Mask Flags Register"
|
|
bitfld.long 0x00 31. " HIMASK[31] ,Channel 31 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " HIMASK[30] ,Channel 30 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " HIMASK[29] ,Channel 29 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " HIMASK[28] ,Channel 28 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 27. " HIMASK[27] ,Channel 27 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " HIMASK[26] ,Channel 26 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HIMASK[25] ,Channel 25 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " HIMASK[24] ,Channel 24 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 23. " HIMASK[23] ,Channel 23 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " HIMASK[22] ,Channel 22 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " HIMASK[21] ,Channel 21 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " HIMASK[20] ,Channel 20 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HIMASK[19] ,Channel 19 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " HIMASK[18] ,Channel 18 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " HIMASK[17] ,Channel 17 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " HIMASK[16] ,Channel 16 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 15. " HIMASK[15] ,Channel 15 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " HIMASK[14] ,Channel 14 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HIMASK[13] ,Channel 13 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " HIMASK[12] ,Channel 12 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 11. " HIMASK[11] ,Channel 11 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HIMASK[10] ,Channel 10 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " HIMASK[9] ,Channel 9 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " HIMASK[8] ,Channel 8 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIMASK[7] ,Channel 7 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " HIMASK[6] ,Channel 6 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " HIMASK[5] ,Channel 5 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " HIMASK[4] ,Channel 4 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " HIMASK[3] ,Channel 3 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " HIMASK[2] ,Channel 2 Interrupt Mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIMASK[1] ,Channel 1 Interrupt Mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " HIMASK[0] ,Channel 0 Interrupt Mask" "Masked,Not masked"
|
|
textline ""
|
|
rgroup.long 0x30++0x7
|
|
sif (cpuis("IMX6*"))
|
|
line.long 0x00 "PSW,Schedule Status Register"
|
|
bitfld.long 0x00 13.--15. " NCP[2:0] ,Next Channel Priority" "No running channel,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " NCR[4:0] ,Next Channel Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " CCP[2:0] ,Current Channel Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CCR[4:0] ,Current Channel Register" "No running channel,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
line.long 0x00 "PSW,Schedule Status Register"
|
|
bitfld.long 0x00 13.--15. " NCP[2:0] ,Next Channel Priority" "No running channel,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--12. " NCR[4:0] ,Next Channel Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CCP[2:0] ,Current Channel Priority" "No running channel,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CCR[4:0] ,Current Channel Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
line.long 0x04 "EVTERRDBG,DMA Request Error Register for Debug"
|
|
bitfld.long 0x04 31. " CHNERR[31] ,Channel 31 Error" "No error,Error"
|
|
bitfld.long 0x04 30. " CHNERR[30] ,Channel 30 Error" "No error,Error"
|
|
bitfld.long 0x04 29. " CHNERR[29] ,Channel 29 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 28. " CHNERR[28] ,Channel 28 Error" "No error,Error"
|
|
bitfld.long 0x04 27. " CHNERR[27] ,Channel 27 Error" "No error,Error"
|
|
bitfld.long 0x04 26. " CHNERR[26] ,Channel 26 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 25. " CHNERR[25] ,Channel 25 Error" "No error,Error"
|
|
bitfld.long 0x04 24. " CHNERR[24] ,Channel 24 Error" "No error,Error"
|
|
bitfld.long 0x04 23. " CHNERR[23] ,Channel 23 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 22. " CHNERR[22] ,Channel 22 Error" "No error,Error"
|
|
bitfld.long 0x04 21. " CHNERR[21] ,Channel 21 Error" "No error,Error"
|
|
bitfld.long 0x04 20. " CHNERR[20] ,Channel 20 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CHNERR[19] ,Channel 19 Error" "No error,Error"
|
|
bitfld.long 0x04 18. " CHNERR[18] ,Channel 18 Error" "No error,Error"
|
|
bitfld.long 0x04 17. " CHNERR[17] ,Channel 17 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 16. " CHNERR[16] ,Channel 16 Error" "No error,Error"
|
|
bitfld.long 0x04 15. " CHNERR[15] ,Channel 15 Error" "No error,Error"
|
|
bitfld.long 0x04 14. " CHNERR[14] ,Channel 14 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CHNERR[13] ,Channel 13 Error" "No error,Error"
|
|
bitfld.long 0x04 12. " CHNERR[12] ,Channel 12 Error" "No error,Error"
|
|
bitfld.long 0x04 11. " CHNERR[11] ,Channel 11 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CHNERR[10] ,Channel 10 Error" "No error,Error"
|
|
bitfld.long 0x04 9. " CHNERR[9] ,Channel 9 Error" "No error,Error"
|
|
bitfld.long 0x04 8. " CHNERR[8] ,Channel 8 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CHNERR[7] ,Channel 7 Error" "No error,Error"
|
|
bitfld.long 0x04 6. " CHNERR[6] ,Channel 6 Error" "No error,Error"
|
|
bitfld.long 0x04 5. " CHNERR[5] ,Channel 5 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CHNERR[4] ,Channel 4 Error" "No error,Error"
|
|
bitfld.long 0x04 3. " CHNERR[3] ,Channel 3 Error" "No error,Error"
|
|
bitfld.long 0x04 2. " CHNERR[2] ,Channel 2 Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CHNERR[1] ,Channel 1 Error" "No error,Error"
|
|
bitfld.long 0x04 0. " CHNERR[0] ,Channel 0 Error" "No error,Error"
|
|
textline ""
|
|
group.long 0x38++0x13
|
|
line.long 0x00 "CONFIG,Configuration Register"
|
|
sif (!cpuis("IMX6*"))
|
|
bitfld.long 0x00 12. " DSPCTRL ,SDMA control mode" "Dual core,Single core"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " RTDOBS ,Real-Time Debug Pins are Used" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACR ,AHB/SDMA Core Clock Ratio" "2x core freq,Core freq"
|
|
bitfld.long 0x00 0.--1. " CSM ,Selects the Context Switch Mode" "Static,Dynamic low power,Dynamic with no loop,Dynamic"
|
|
line.long 0x04 "SDMA_LOCK,SDMA Lock Register"
|
|
bitfld.long 0x04 1. " SRESET_LOCK_CLR ,LOCK bit is cleared on a software reset" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " LOCK ,Access to update SDMA script memory" "Not locked,Locked"
|
|
line.long 0x08 "ONCE_ENB,OnCE Enable Register"
|
|
bitfld.long 0x08 0. " ENB ,OnCE Enable" "Disabled,Enabled"
|
|
line.long 0x0c "ONCE_DATA,OnCE Data Register"
|
|
line.long 0x10 "ONCE_INSTR,OnCE Instruction Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " INSTR ,Instruction Register of the OnCE JTAG Controller"
|
|
rgroup.long 0x4c++0x03
|
|
line.long 0x00 "ONCE_STAT,OnCE Status Register"
|
|
bitfld.long 0x00 12.--15. " PST[3:0] ,Processor Status" "Program,Data,Change of flow,Change of flow in loop,Debug,Functional unit,Sleep,Save,Program in sleep,Data in sleep,Change of flow in sleep,Change flow in loop in sleep,Debug in sleep,Functional unit in sleep,Sleep after reset,Restore"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCV ,RCV Flag" "Cleared,Set"
|
|
bitfld.long 0x00 10. " EDR ,SDMA has Entered Debug Mode After an External Debug Request" "Normal,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ODR ,SDMA has Entered Debug Mode After a OnCE Debug Request" "Normal,Debug"
|
|
bitfld.long 0x00 8. " SWB ,SDMA has Entered Debug Mode After a Software Breakpoint" "Normal,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MST ,OnCE is Controlled from the AP Peripheral Interface" "JTAG,AP"
|
|
bitfld.long 0x00 2. " ECDR[2] ,Event Cell Debug Request from data_cond" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ECDR[1] ,Event Cell Debug Request from addrb_cond" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " ECDR[0] ,Event Cell Debug Request from addra_cond" "Not requested,Requested"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ONCE_CMD,OnCE Command Register"
|
|
bitfld.long 0x00 0.--3. " CMD ,Command" "Rstatus,Dmov,Exec_once,Run_core,Exec_core,Debug_rqst,Rbuffer,?..."
|
|
group.long 0x58++0x7
|
|
line.long 0x00 "ILLINSTADDR,Illegal Instruction Trap Address Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " ILLINSTADDR ,Illegal Instruction Trap Address"
|
|
line.long 0x04 "CHN0ADDR,Channel 0 Boot Address Register"
|
|
bitfld.long 0x04 14. " SMSZ ,Scratch Memory Size" "24,32"
|
|
hexmask.long.word 0x04 0.--13. 1. " CHN0ADDR ,Channel 0 Boot Address"
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "EVT_MIRROR,DMA Requests Register"
|
|
bitfld.long 0x00 31. " EVENTS[31] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " EVENTS[30] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 29. " EVENTS[29] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " EVENTS[28] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 27. " EVENTS[27] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 26. " EVENTS[26] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EVENTS[25] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " EVENTS[24] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EVENTS[23] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " EVENTS[22] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EVENTS[21] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " EVENTS[20] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EVENTS[19] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " EVENTS[18] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EVENTS[17] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " EVENTS[16] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EVENTS[15] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " EVENTS[14] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EVENTS[13] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " EVENTS[12] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EVENTS[11] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " EVENTS[10] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EVENTS[9] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " EVENTS[8] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EVENTS[7] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " EVENTS[6] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EVENTS[5] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " EVENTS[4] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EVENTS[3] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " EVENTS[2] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EVENTS[1] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " EVENTS[0] ,DMA Request" "Not requested,Requested"
|
|
line.long 0x04 "EVT_MIRROR2,DMA Requests 2 Register"
|
|
bitfld.long 0x04 15. " EVENTS[47] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " EVENTS[46] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 13. " EVENTS[45] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " EVENTS[44] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EVENTS[43] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " EVENTS[42] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EVENTS[41] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " EVENTS[40] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EVENTS[39] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " EVENTS[38] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EVENTS[37] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " EVENTS[36] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EVENTS[35] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " EVENTS[34] ,DMA Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EVENTS[33] ,DMA Request" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " EVENTS[32] ,DMA Request" "Not requested,Requested"
|
|
textline ""
|
|
group.long 0x70++0x7
|
|
line.long 0x00 "XTRIG_CONF1,Cross-Trigger Events Configuration Register 1"
|
|
bitfld.long 0x00 30. " CNF3 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x00 24.--29. " NUM3[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22. " CNF2 ,Configuration of the SDMA" "Channel,DMA request"
|
|
textline " "
|
|
bitfld.long 0x00 16.--21. " NUM2[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 14. " CNF1 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x00 8.--13. " NUM1[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CNF0 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x00 0.--5. " NUM0[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "XTRIG_CONF2,Cross-Trigger Events Configuration Register 2"
|
|
bitfld.long 0x04 30. " CNF7 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x04 24.--29. " NUM7[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 22. " CNF6 ,Configuration of the SDMA" "Channel,DMA request"
|
|
textline " "
|
|
bitfld.long 0x04 16.--21. " NUM6[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 14. " CNF5 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x04 8.--13. " NUM5[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 6. " CNF4 ,Configuration of the SDMA" "Channel,DMA request"
|
|
bitfld.long 0x04 0.--5. " NUM4[5:0] ,Number of the DMA Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif (cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&(!cpuis("IMX6*")))
|
|
group.long 0x7c++0x23
|
|
line.long 0x0 "PRF_CNT_1,Profile Counter 1 Register"
|
|
hexmask.long.word 0x0 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0x0 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0x0 0.--21. 1. " COUNTER ,Counter field"
|
|
line.long 0x4 "PRF_CNT_2,Profile Counter 2 Register"
|
|
hexmask.long.word 0x4 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0x4 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0x4 0.--21. 1. " COUNTER ,Counter field"
|
|
line.long 0x8 "PRF_CNT_3,Profile Counter 3 Register"
|
|
hexmask.long.word 0x8 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0x8 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0x8 0.--21. 1. " COUNTER ,Counter field"
|
|
line.long 0xC "PRF_CNT_4,Profile Counter 4 Register"
|
|
hexmask.long.word 0xC 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0xC 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0xC 0.--21. 1. " COUNTER ,Counter field"
|
|
line.long 0x10 "PRF_CNT_5,Profile Counter 5 Register"
|
|
hexmask.long.word 0x10 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0x10 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0x10 0.--21. 1. " COUNTER ,Counter field"
|
|
line.long 0x14 "PRF_CNT_6,Profile Counter 6 Register"
|
|
hexmask.long.word 0x14 23.--31. 1. " COUNTER_CONFIG ,Counter configure field"
|
|
bitfld.long 0x14 22. " OFL ,Overflow flag" "No overflow,Overflow"
|
|
hexmask.long.tbyte 0x14 0.--21. 1. " COUNTER ,Counter field"
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "PRF_CFG,Profile Config/Status Register"
|
|
eventfld.long 0x00 13. " ISR ,Profile counter overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 12. " OFL6 ,Profile counter 6 overflow status" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFL5 ,Profile counter 5 overflow status" "No overflow,Overflow"
|
|
bitfld.long 0x00 10. " OFL4 ,Profile counter 4 overflow status" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFL3 ,Profile counter 3 overflow status" "No overflow,Overflow"
|
|
bitfld.long 0x00 8. " OFL2 ,Profile counter 2 overflow status" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OFL1 ,Profile counter 1 overflow status" "No overflow,Overflow"
|
|
bitfld.long 0x00 6. " INT_EN_6 ,Interrupt enabled for profile counter 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INT_EN_5 ,Interrupt enabled for profile counter 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INT_EN_4 ,Interrupt enabled for profile counter 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INT_EN_3 ,Interrupt enabled for profile counter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INT_EN_2 ,Interrupt enabled for profile counter 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INT_EN_1 ,Interrupt enabled for profile counter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Bit enables the profile counters" "Disabled,Enabled"
|
|
endif
|
|
textline ""
|
|
width 23.
|
|
sif (cpuis("IMX6*"))
|
|
group.long 0x100++0x7F
|
|
line.long 0x0 "SDMAARM_SDMA_CHNPRI0 ,Channel Priority 0 Register"
|
|
bitfld.long 0x0 0.--2. " CHNPRI0 ,Channel 0 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x4 "SDMAARM_SDMA_CHNPRI1 ,Channel Priority 1 Register"
|
|
bitfld.long 0x4 0.--2. " CHNPRI1 ,Channel 1 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x8 "SDMAARM_SDMA_CHNPRI2 ,Channel Priority 2 Register"
|
|
bitfld.long 0x8 0.--2. " CHNPRI2 ,Channel 2 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0xC "SDMAARM_SDMA_CHNPRI3 ,Channel Priority 3 Register"
|
|
bitfld.long 0xC 0.--2. " CHNPRI3 ,Channel 3 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x10 "SDMAARM_SDMA_CHNPRI4 ,Channel Priority 4 Register"
|
|
bitfld.long 0x10 0.--2. " CHNPRI4 ,Channel 4 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x14 "SDMAARM_SDMA_CHNPRI5 ,Channel Priority 5 Register"
|
|
bitfld.long 0x14 0.--2. " CHNPRI5 ,Channel 5 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x18 "SDMAARM_SDMA_CHNPRI6 ,Channel Priority 6 Register"
|
|
bitfld.long 0x18 0.--2. " CHNPRI6 ,Channel 6 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x1C "SDMAARM_SDMA_CHNPRI7 ,Channel Priority 7 Register"
|
|
bitfld.long 0x1C 0.--2. " CHNPRI7 ,Channel 7 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x20 "SDMAARM_SDMA_CHNPRI8 ,Channel Priority 8 Register"
|
|
bitfld.long 0x20 0.--2. " CHNPRI8 ,Channel 8 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x24 "SDMAARM_SDMA_CHNPRI9 ,Channel Priority 9 Register"
|
|
bitfld.long 0x24 0.--2. " CHNPRI9 ,Channel 9 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x28 "SDMAARM_SDMA_CHNPRI10,Channel Priority 10 Register"
|
|
bitfld.long 0x28 0.--2. " CHNPRI10 ,Channel 10 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x2C "SDMAARM_SDMA_CHNPRI11,Channel Priority 11 Register"
|
|
bitfld.long 0x2C 0.--2. " CHNPRI11 ,Channel 11 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x30 "SDMAARM_SDMA_CHNPRI12,Channel Priority 12 Register"
|
|
bitfld.long 0x30 0.--2. " CHNPRI12 ,Channel 12 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x34 "SDMAARM_SDMA_CHNPRI13,Channel Priority 13 Register"
|
|
bitfld.long 0x34 0.--2. " CHNPRI13 ,Channel 13 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x38 "SDMAARM_SDMA_CHNPRI14,Channel Priority 14 Register"
|
|
bitfld.long 0x38 0.--2. " CHNPRI14 ,Channel 14 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x3C "SDMAARM_SDMA_CHNPRI15,Channel Priority 15 Register"
|
|
bitfld.long 0x3C 0.--2. " CHNPRI15 ,Channel 15 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x40 "SDMAARM_SDMA_CHNPRI16,Channel Priority 16 Register"
|
|
bitfld.long 0x40 0.--2. " CHNPRI16 ,Channel 16 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x44 "SDMAARM_SDMA_CHNPRI17,Channel Priority 17 Register"
|
|
bitfld.long 0x44 0.--2. " CHNPRI17 ,Channel 17 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x48 "SDMAARM_SDMA_CHNPRI18,Channel Priority 18 Register"
|
|
bitfld.long 0x48 0.--2. " CHNPRI18 ,Channel 18 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x4C "SDMAARM_SDMA_CHNPRI19,Channel Priority 19 Register"
|
|
bitfld.long 0x4C 0.--2. " CHNPRI19 ,Channel 19 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x50 "SDMAARM_SDMA_CHNPRI20,Channel Priority 20 Register"
|
|
bitfld.long 0x50 0.--2. " CHNPRI20 ,Channel 20 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x54 "SDMAARM_SDMA_CHNPRI21,Channel Priority 21 Register"
|
|
bitfld.long 0x54 0.--2. " CHNPRI21 ,Channel 21 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x58 "SDMAARM_SDMA_CHNPRI22,Channel Priority 22 Register"
|
|
bitfld.long 0x58 0.--2. " CHNPRI22 ,Channel 22 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x5C "SDMAARM_SDMA_CHNPRI23,Channel Priority 23 Register"
|
|
bitfld.long 0x5C 0.--2. " CHNPRI23 ,Channel 23 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x60 "SDMAARM_SDMA_CHNPRI24,Channel Priority 24 Register"
|
|
bitfld.long 0x60 0.--2. " CHNPRI24 ,Channel 24 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x64 "SDMAARM_SDMA_CHNPRI25,Channel Priority 25 Register"
|
|
bitfld.long 0x64 0.--2. " CHNPRI25 ,Channel 25 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x68 "SDMAARM_SDMA_CHNPRI26,Channel Priority 26 Register"
|
|
bitfld.long 0x68 0.--2. " CHNPRI26 ,Channel 26 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x6C "SDMAARM_SDMA_CHNPRI27,Channel Priority 27 Register"
|
|
bitfld.long 0x6C 0.--2. " CHNPRI27 ,Channel 27 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x70 "SDMAARM_SDMA_CHNPRI28,Channel Priority 28 Register"
|
|
bitfld.long 0x70 0.--2. " CHNPRI28 ,Channel 28 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x74 "SDMAARM_SDMA_CHNPRI29,Channel Priority 29 Register"
|
|
bitfld.long 0x74 0.--2. " CHNPRI29 ,Channel 29 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x78 "SDMAARM_SDMA_CHNPRI30,Channel Priority 30 Register"
|
|
bitfld.long 0x78 0.--2. " CHNPRI30 ,Channel 30 priority" ",1,2,3,4,5,6,7"
|
|
line.long 0x7C "SDMAARM_SDMA_CHNPRI31,Channel Priority 31 Register"
|
|
bitfld.long 0x7C 0.--2. " CHNPRI31 ,Channel 31 priority" ",1,2,3,4,5,6,7"
|
|
endif
|
|
width 11.
|
|
tree "Channel Enable RAM Registers"
|
|
group.long 0x200++0xbf
|
|
line.long 0x0 "CHNENBL0 ,Channel 0 Enable RAM"
|
|
bitfld.long 0x0 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 0 " "Disabled,Enabled"
|
|
line.long 0x4 "CHNENBL1 ,Channel 1 Enable RAM"
|
|
bitfld.long 0x4 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 1 " "Disabled,Enabled"
|
|
line.long 0x8 "CHNENBL2 ,Channel 2 Enable RAM"
|
|
bitfld.long 0x8 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 2 " "Disabled,Enabled"
|
|
line.long 0xC "CHNENBL3 ,Channel 3 Enable RAM"
|
|
bitfld.long 0xC 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 3 " "Disabled,Enabled"
|
|
line.long 0x10 "CHNENBL4 ,Channel 4 Enable RAM"
|
|
bitfld.long 0x10 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 4 " "Disabled,Enabled"
|
|
line.long 0x14 "CHNENBL5 ,Channel 5 Enable RAM"
|
|
bitfld.long 0x14 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 5 " "Disabled,Enabled"
|
|
line.long 0x18 "CHNENBL6 ,Channel 6 Enable RAM"
|
|
bitfld.long 0x18 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 6 " "Disabled,Enabled"
|
|
line.long 0x1C "CHNENBL7 ,Channel 7 Enable RAM"
|
|
bitfld.long 0x1C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 7 " "Disabled,Enabled"
|
|
line.long 0x20 "CHNENBL8 ,Channel 8 Enable RAM"
|
|
bitfld.long 0x20 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 8 " "Disabled,Enabled"
|
|
line.long 0x24 "CHNENBL9 ,Channel 9 Enable RAM"
|
|
bitfld.long 0x24 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 9 " "Disabled,Enabled"
|
|
line.long 0x28 "CHNENBL10,Channel 10 Enable RAM"
|
|
bitfld.long 0x28 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
bitfld.long 0x28 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 10" "Disabled,Enabled"
|
|
line.long 0x2C "CHNENBL11,Channel 11 Enable RAM"
|
|
bitfld.long 0x2C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
bitfld.long 0x2C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 11" "Disabled,Enabled"
|
|
line.long 0x30 "CHNENBL12,Channel 12 Enable RAM"
|
|
bitfld.long 0x30 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 12" "Disabled,Enabled"
|
|
line.long 0x34 "CHNENBL13,Channel 13 Enable RAM"
|
|
bitfld.long 0x34 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
bitfld.long 0x34 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 13" "Disabled,Enabled"
|
|
line.long 0x38 "CHNENBL14,Channel 14 Enable RAM"
|
|
bitfld.long 0x38 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 14" "Disabled,Enabled"
|
|
line.long 0x3C "CHNENBL15,Channel 15 Enable RAM"
|
|
bitfld.long 0x3C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
bitfld.long 0x3C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 15" "Disabled,Enabled"
|
|
line.long 0x40 "CHNENBL16,Channel 16 Enable RAM"
|
|
bitfld.long 0x40 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
bitfld.long 0x40 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 16" "Disabled,Enabled"
|
|
line.long 0x44 "CHNENBL17,Channel 17 Enable RAM"
|
|
bitfld.long 0x44 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
bitfld.long 0x44 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 17" "Disabled,Enabled"
|
|
line.long 0x48 "CHNENBL18,Channel 18 Enable RAM"
|
|
bitfld.long 0x48 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
bitfld.long 0x48 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 18" "Disabled,Enabled"
|
|
line.long 0x4C "CHNENBL19,Channel 19 Enable RAM"
|
|
bitfld.long 0x4C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
bitfld.long 0x4C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 19" "Disabled,Enabled"
|
|
line.long 0x50 "CHNENBL20,Channel 20 Enable RAM"
|
|
bitfld.long 0x50 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x50 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
bitfld.long 0x50 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 20" "Disabled,Enabled"
|
|
line.long 0x54 "CHNENBL21,Channel 21 Enable RAM"
|
|
bitfld.long 0x54 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
bitfld.long 0x54 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 21" "Disabled,Enabled"
|
|
line.long 0x58 "CHNENBL22,Channel 22 Enable RAM"
|
|
bitfld.long 0x58 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x58 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
bitfld.long 0x58 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 22" "Disabled,Enabled"
|
|
line.long 0x5C "CHNENBL23,Channel 23 Enable RAM"
|
|
bitfld.long 0x5C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x5C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
bitfld.long 0x5C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 23" "Disabled,Enabled"
|
|
line.long 0x60 "CHNENBL24,Channel 24 Enable RAM"
|
|
bitfld.long 0x60 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x60 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
bitfld.long 0x60 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 24" "Disabled,Enabled"
|
|
line.long 0x64 "CHNENBL25,Channel 25 Enable RAM"
|
|
bitfld.long 0x64 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x64 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
bitfld.long 0x64 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 25" "Disabled,Enabled"
|
|
line.long 0x68 "CHNENBL26,Channel 26 Enable RAM"
|
|
bitfld.long 0x68 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x68 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
bitfld.long 0x68 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 26" "Disabled,Enabled"
|
|
line.long 0x6C "CHNENBL27,Channel 27 Enable RAM"
|
|
bitfld.long 0x6C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x6C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
bitfld.long 0x6C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 27" "Disabled,Enabled"
|
|
line.long 0x70 "CHNENBL28,Channel 28 Enable RAM"
|
|
bitfld.long 0x70 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x70 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
bitfld.long 0x70 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 28" "Disabled,Enabled"
|
|
line.long 0x74 "CHNENBL29,Channel 29 Enable RAM"
|
|
bitfld.long 0x74 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x74 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
bitfld.long 0x74 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 29" "Disabled,Enabled"
|
|
line.long 0x78 "CHNENBL30,Channel 30 Enable RAM"
|
|
bitfld.long 0x78 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x78 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
bitfld.long 0x78 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 30" "Disabled,Enabled"
|
|
line.long 0x7C "CHNENBL31,Channel 31 Enable RAM"
|
|
bitfld.long 0x7C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x7C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
bitfld.long 0x7C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 31" "Disabled,Enabled"
|
|
line.long 0x80 "CHNENBL32,Channel 32 Enable RAM"
|
|
bitfld.long 0x80 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x80 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
bitfld.long 0x80 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 32" "Disabled,Enabled"
|
|
line.long 0x84 "CHNENBL33,Channel 33 Enable RAM"
|
|
bitfld.long 0x84 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x84 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
bitfld.long 0x84 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 33" "Disabled,Enabled"
|
|
line.long 0x88 "CHNENBL34,Channel 34 Enable RAM"
|
|
bitfld.long 0x88 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x88 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
bitfld.long 0x88 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 34" "Disabled,Enabled"
|
|
line.long 0x8C "CHNENBL35,Channel 35 Enable RAM"
|
|
bitfld.long 0x8C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
bitfld.long 0x8C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 35" "Disabled,Enabled"
|
|
line.long 0x90 "CHNENBL36,Channel 36 Enable RAM"
|
|
bitfld.long 0x90 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x90 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
bitfld.long 0x90 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 36" "Disabled,Enabled"
|
|
line.long 0x94 "CHNENBL37,Channel 37 Enable RAM"
|
|
bitfld.long 0x94 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x94 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
bitfld.long 0x94 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 37" "Disabled,Enabled"
|
|
line.long 0x98 "CHNENBL38,Channel 38 Enable RAM"
|
|
bitfld.long 0x98 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x98 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
bitfld.long 0x98 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 38" "Disabled,Enabled"
|
|
line.long 0x9C "CHNENBL39,Channel 39 Enable RAM"
|
|
bitfld.long 0x9C 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x9C 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
bitfld.long 0x9C 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 39" "Disabled,Enabled"
|
|
line.long 0xA0 "CHNENBL40,Channel 40 Enable RAM"
|
|
bitfld.long 0xA0 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA0 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
bitfld.long 0xA0 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 40" "Disabled,Enabled"
|
|
line.long 0xA4 "CHNENBL41,Channel 41 Enable RAM"
|
|
bitfld.long 0xA4 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA4 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
bitfld.long 0xA4 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 41" "Disabled,Enabled"
|
|
line.long 0xA8 "CHNENBL42,Channel 42 Enable RAM"
|
|
bitfld.long 0xA8 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xA8 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
bitfld.long 0xA8 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 42" "Disabled,Enabled"
|
|
line.long 0xAC "CHNENBL43,Channel 43 Enable RAM"
|
|
bitfld.long 0xAC 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xAC 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
bitfld.long 0xAC 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 43" "Disabled,Enabled"
|
|
line.long 0xB0 "CHNENBL44,Channel 44 Enable RAM"
|
|
bitfld.long 0xB0 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB0 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
bitfld.long 0xB0 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 44" "Disabled,Enabled"
|
|
line.long 0xB4 "CHNENBL45,Channel 45 Enable RAM"
|
|
bitfld.long 0xB4 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB4 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
bitfld.long 0xB4 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 45" "Disabled,Enabled"
|
|
line.long 0xB8 "CHNENBL46,Channel 46 Enable RAM"
|
|
bitfld.long 0xB8 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xB8 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
bitfld.long 0xB8 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 46" "Disabled,Enabled"
|
|
line.long 0xBC "CHNENBL47,Channel 47 Enable RAM"
|
|
bitfld.long 0xBC 31. " ENBL[31] ,Channel 31 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 30. " ENBL[30] ,Channel 30 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 29. " ENBL[29] ,Channel 29 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 28. " ENBL[28] ,Channel 28 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 27. " ENBL[27] ,Channel 27 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 26. " ENBL[26] ,Channel 26 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 25. " ENBL[25] ,Channel 25 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 24. " ENBL[24] ,Channel 24 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 23. " ENBL[23] ,Channel 23 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 22. " ENBL[22] ,Channel 22 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 21. " ENBL[21] ,Channel 21 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 20. " ENBL[20] ,Channel 20 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 19. " ENBL[19] ,Channel 19 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 18. " ENBL[18] ,Channel 18 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 17. " ENBL[17] ,Channel 17 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 16. " ENBL[16] ,Channel 16 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 15. " ENBL[15] ,Channel 15 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 14. " ENBL[14] ,Channel 14 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 13. " ENBL[13] ,Channel 13 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 12. " ENBL[12] ,Channel 12 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 11. " ENBL[11] ,Channel 11 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 10. " ENBL[10] ,Channel 10 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 9. " ENBL[09] ,Channel 9 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 8. " ENBL[08] ,Channel 8 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 7. " ENBL[07] ,Channel 7 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 6. " ENBL[06] ,Channel 6 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 5. " ENBL[05] ,Channel 5 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 4. " ENBL[04] ,Channel 4 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 3. " ENBL[03] ,Channel 3 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 2. " ENBL[02] ,Channel 2 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xBC 1. " ENBL[01] ,Channel 1 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
bitfld.long 0xBC 0. " ENBL[00] ,Channel 0 Enable triggered by DMA request number 47" "Disabled,Enabled"
|
|
tree.end
|
|
width 10.
|
|
sif (!cpuis("IMX6*"))
|
|
tree "Channel Priority Registers"
|
|
group.long 0x100++0x7f
|
|
line.long 0x0 "CHNPRI0 ,Channel 0 Priority Register"
|
|
bitfld.long 0x0 0.--2. " CHNPRI0 ,Priority of Channel Number 0 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CHNPRI1 ,Channel 1 Priority Register"
|
|
bitfld.long 0x4 0.--2. " CHNPRI1 ,Priority of Channel Number 1 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CHNPRI2 ,Channel 2 Priority Register"
|
|
bitfld.long 0x8 0.--2. " CHNPRI2 ,Priority of Channel Number 2 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0xC "CHNPRI3 ,Channel 3 Priority Register"
|
|
bitfld.long 0xC 0.--2. " CHNPRI3 ,Priority of Channel Number 3 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CHNPRI4 ,Channel 4 Priority Register"
|
|
bitfld.long 0x10 0.--2. " CHNPRI4 ,Priority of Channel Number 4 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CHNPRI5 ,Channel 5 Priority Register"
|
|
bitfld.long 0x14 0.--2. " CHNPRI5 ,Priority of Channel Number 5 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CHNPRI6 ,Channel 6 Priority Register"
|
|
bitfld.long 0x18 0.--2. " CHNPRI6 ,Priority of Channel Number 6 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x1C "CHNPRI7 ,Channel 7 Priority Register"
|
|
bitfld.long 0x1C 0.--2. " CHNPRI7 ,Priority of Channel Number 7 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x20 "CHNPRI8 ,Channel 8 Priority Register"
|
|
bitfld.long 0x20 0.--2. " CHNPRI8 ,Priority of Channel Number 8 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x24 "CHNPRI9 ,Channel 9 Priority Register"
|
|
bitfld.long 0x24 0.--2. " CHNPRI9 ,Priority of Channel Number 9 " "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x28 "CHNPRI10,Channel 10 Priority Register"
|
|
bitfld.long 0x28 0.--2. " CHNPRI10 ,Priority of Channel Number 10" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x2C "CHNPRI11,Channel 11 Priority Register"
|
|
bitfld.long 0x2C 0.--2. " CHNPRI11 ,Priority of Channel Number 11" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x30 "CHNPRI12,Channel 12 Priority Register"
|
|
bitfld.long 0x30 0.--2. " CHNPRI12 ,Priority of Channel Number 12" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x34 "CHNPRI13,Channel 13 Priority Register"
|
|
bitfld.long 0x34 0.--2. " CHNPRI13 ,Priority of Channel Number 13" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x38 "CHNPRI14,Channel 14 Priority Register"
|
|
bitfld.long 0x38 0.--2. " CHNPRI14 ,Priority of Channel Number 14" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x3C "CHNPRI15,Channel 15 Priority Register"
|
|
bitfld.long 0x3C 0.--2. " CHNPRI15 ,Priority of Channel Number 15" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x40 "CHNPRI16,Channel 16 Priority Register"
|
|
bitfld.long 0x40 0.--2. " CHNPRI16 ,Priority of Channel Number 16" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x44 "CHNPRI17,Channel 17 Priority Register"
|
|
bitfld.long 0x44 0.--2. " CHNPRI17 ,Priority of Channel Number 17" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x48 "CHNPRI18,Channel 18 Priority Register"
|
|
bitfld.long 0x48 0.--2. " CHNPRI18 ,Priority of Channel Number 18" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x4C "CHNPRI19,Channel 19 Priority Register"
|
|
bitfld.long 0x4C 0.--2. " CHNPRI19 ,Priority of Channel Number 19" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x50 "CHNPRI20,Channel 20 Priority Register"
|
|
bitfld.long 0x50 0.--2. " CHNPRI20 ,Priority of Channel Number 20" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x54 "CHNPRI21,Channel 21 Priority Register"
|
|
bitfld.long 0x54 0.--2. " CHNPRI21 ,Priority of Channel Number 21" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x58 "CHNPRI22,Channel 22 Priority Register"
|
|
bitfld.long 0x58 0.--2. " CHNPRI22 ,Priority of Channel Number 22" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x5C "CHNPRI23,Channel 23 Priority Register"
|
|
bitfld.long 0x5C 0.--2. " CHNPRI23 ,Priority of Channel Number 23" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x60 "CHNPRI24,Channel 24 Priority Register"
|
|
bitfld.long 0x60 0.--2. " CHNPRI24 ,Priority of Channel Number 24" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x64 "CHNPRI25,Channel 25 Priority Register"
|
|
bitfld.long 0x64 0.--2. " CHNPRI25 ,Priority of Channel Number 25" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x68 "CHNPRI26,Channel 26 Priority Register"
|
|
bitfld.long 0x68 0.--2. " CHNPRI26 ,Priority of Channel Number 26" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x6C "CHNPRI27,Channel 27 Priority Register"
|
|
bitfld.long 0x6C 0.--2. " CHNPRI27 ,Priority of Channel Number 27" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x70 "CHNPRI28,Channel 28 Priority Register"
|
|
bitfld.long 0x70 0.--2. " CHNPRI28 ,Priority of Channel Number 28" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x74 "CHNPRI29,Channel 29 Priority Register"
|
|
bitfld.long 0x74 0.--2. " CHNPRI29 ,Priority of Channel Number 29" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x78 "CHNPRI30,Channel 30 Priority Register"
|
|
bitfld.long 0x78 0.--2. " CHNPRI30 ,Priority of Channel Number 30" "No running channel,1,2,3,4,5,6,7"
|
|
line.long 0x7C "CHNPRI31,Channel 31 Priority Register"
|
|
bitfld.long 0x7C 0.--2. " CHNPRI31 ,Priority of Channel Number 31" "No running channel,1,2,3,4,5,6,7"
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "SPDIF (Sony/Philips Digital Interface)"
|
|
base ad:0x70028000
|
|
width 9.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "SCR,Configuration Register"
|
|
bitfld.long 0x0 17. " TXAUTOSYNC ,Transmit FIFO Auto Sync Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 15.--16. " TXFIFOEMPTY_SEL ,Transmit FIFO Empty interrupt select" "0,4,8,12"
|
|
textline " "
|
|
bitfld.long 0x0 13. " LOW_POWER ,SPDIF low-power mode" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " SW_RESET ,SPDIF software reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " TXFIFO_CTRL ,Transmit FIFO Control" "Tx Digital 0,Normal,Reset to 1 samp,?..."
|
|
bitfld.long 0x0 8. " PDIR_TX ,DMA Transmit Request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " VALCTRL ,Outingoing Validity" "Set,Clear"
|
|
bitfld.long 0x0 2.--4. " TXSEL ,Transmit Select" "0ff and output 0,Reserved,Reserved,Reserved,Reserved,Normal,?..."
|
|
group.long 0x0c++0x7
|
|
line.long 0x0 "SIE,Interrupt Enable Register"
|
|
bitfld.long 0x0 19. " TXUNOV_EN ,SPDIF transmit FIFO under/overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " TXRESYN_EN ,SPDIF transmit FIFO resync interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TXEM_EN ,SPDIF transmit FIFO empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x4 "SIS/SIC,Interrupt Status Register"
|
|
eventfld.long 0x4 19. " TXUNOV ,SPDIF transmit FIFO under/overrun" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 18. " TXRESYN ,SPDIF transmit FIFO resync" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 1. " TXEM ,SPDIF transmit FIFO empty interrupt bit" "No interrupt,Interrupt"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "STL,SPDIF Left Channel Data Transmitter"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " TXDATALEFT ,SPDIF transmit left channel data"
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x0 "STR,SPDIF Right Channel Data Transmitter"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " TXDATARIGHT ,SPDIF transmit right channel data"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "STCSCH,SPDIF Tx Consumer Channel Status High Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " TXCCHANNELCONS_H ,SPDIF transmit Cons. C channel data"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "STCSCL,SPDIF Tx Consumer Channel Status Low Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " TXCCHANNELCONS_L ,SPDIF transmit Cons. C channel data"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "STC,Transmit Clock Control Register"
|
|
bitfld.long 0x0 8.--10. " TXCLK_SRC , Transmit Clock Source" "CAMP1_CMAP_OUT,SPDIF0_CLK_ROOT,SPDIF1_CLK_ROOT,AUDMUX_Port3_TXCLK input,AUDMUX_Port5_TXCLK input,Reserved,AUDMUX_Port6_TXCLK input,CAMP2_CMAP_OUT"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--6. 1. " TXCLK_DF ,Divider factor"
|
|
width 0xb
|
|
tree.end
|
|
tree "SRC (System Reset Controller)"
|
|
base ad:0x73fd0000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCR,System Reset Controller"
|
|
sif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 25. " DBG_RST_MSK_PG ,Debug reset mask" "Unmasked,Masked"
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 24. " CORE3_ENABLE ,CPU core3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CORE2_ENABLE ,CPU core2 enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 22. " CORE1_ENABLE ,CPU core1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CORES_DBG_RST ,Software reset for debug of arm platform only" "Not asserted,Asserted"
|
|
else
|
|
bitfld.long 0x00 21. " CORES_DBG_RST ,Software reset for debug of arm platform only" "Not asserted,Asserted"
|
|
endif
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 20. " CORE3_DBG_RST ,Software reset for core3 debug only" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " CORE2_DBG_RST ,Software reset for core2 debug only" "Not asserted,Asserted"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMXSOLOLITE")
|
|
bitfld.long 0x00 18. " CORE1_DBG_RST ,Software reset for core1 debug only" "Not asserted,Asserted"
|
|
bitfld.long 0x00 17. " CORE0_DBG_RST ,Software reset for core0 debug only" "Not asserted,Asserted"
|
|
else
|
|
bitfld.long 0x00 17. " CORE0_DBG_RST ,Software reset for core0 debug only" "Not asserted,Asserted"
|
|
endif
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMXSOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 16. " CORE3_RST ,Software reset for core3 only" "Not asserted,Asserted"
|
|
bitfld.long 0x00 15. " CORE2_RST ,Software reset for core2 only" "Not asserted,Asserted"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 14. " CORE1_RST ,Software reset for core1 only" "Not asserted,Asserted"
|
|
bitfld.long 0x00 13. " CORE0_RST ,Software reset for core0 only" "Not asserted,Asserted"
|
|
else
|
|
bitfld.long 0x00 13. " CORE0_RST ,Software reset for core0 only" "Not asserted,Asserted"
|
|
endif
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 12. " SW_IPU2_RST ,Software reset for ipu2" "Not asserted,Asserted"
|
|
endif
|
|
endif
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpuis("IMX6*")||cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
textline " "
|
|
bitfld.long 0x00 11. " EIM_RST ,EIM Reset" "No reset,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7.--10. " MASK_WDOG_RST ,Mask wdog_rst_b source" "Not masked,Not masked,Not masked,Not masked,Not masked,Masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked,Not masked"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " WARM_RST_BYPASS_COUNT ,Ckil cycles to count before bypassing the MMDC ack for warm reset" "Disabled,16 ckil,32 ckil,64 ckil"
|
|
elif (cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " WARM_RST_BYPASS_COUNT ,XTALI cycles to count before bypassing the MMDC ack for warm reset" "Disabled,16 XTALI,32 XTALI,64 XTALI"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " WARM_RST_BYPASS_COUNT ,Ckil cycles to count before bypassing the emi ack for warm reset" "Disabled,16 ckil,32 ckil,64 ckil"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " SW_OPEN_VG_RST ,Software reset for open_vg" "Not asserted,Asserted"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
textline " "
|
|
bitfld.long 0x00 0. " WARM_RESET_ENABLE ,Warm reset enable bit" "Disabled,Enabled"
|
|
elif (cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 2. " SW_VPU_RST ,Software reset for vpu" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SW_GPU_RST ,Software reset for gpu" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " WARM_RESET_ENABLE ,Warm reset enable bit" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 3. " SW_IPU_RST ,Software reset for ipu" "Not asserted,Asserted"
|
|
bitfld.long 0x00 2. " SW_VPU_RST ,Software reset for vpu" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SW_GPU_RST ,Software reset for gpu" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " WARM_RESET_ENABLE ,Warm reset enable bit" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpu()=="IMX61"||cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpuis("IMX6*"))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SBMR,SRC Boot Mode Register"
|
|
sif cpuis("IMX50*")
|
|
bitfld.long 0x00 27.--29. " TEST_MODE[2:0] ,Test Mode Fuse Select" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
elif (!cpuis("IMX6*"))
|
|
bitfld.long 0x00 26. " BT_FUSE_SEL ,Boot fuse select" "0,1"
|
|
bitfld.long 0x00 24.--25. " BMOD[1:0] ,Boot mode" "0,1,2,3"
|
|
textline " "
|
|
elif (cpuis("IMX6*"))
|
|
hexmask.long.byte 0x00 24.--31. 1. " BOOT_CFG4 ,Boot configuration4"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x00 16.--23. 1. " BOOT_CFG3 ,Boot configuration3"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BOOT_CFG2 ,Boot configuration2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " BOOT_CFG1 ,Boot configuration1"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SBMR,SRC Boot Mode Register"
|
|
bitfld.long 0x00 29.--31. " BT_LPB_FREQ[2:0] ,BT_LPB_FREQ[2:0]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 28. " BT_HPN_EN ,BT_HPN_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " BT_USB_SRC ,BT_USB_SRC" "0,1"
|
|
bitfld.long 0x00 25.--26. " BT_UART_SRC[1:0] ,BT_UART_SRC" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " BT_LPB[1:0] ,BT_LPB" "0,1,2,3"
|
|
bitfld.long 0x00 21.--22. " BT_OSC_FREQ_SEL[1:0] ,BT_OSC_FREQ_SEL" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " BT_SRC[1:0] ,BT_SDMMC_SRC" "0,1,2,3"
|
|
bitfld.long 0x00 18. " BT_LPB_EN ,BT_LPB_EN" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " BT_WEIM_MUXED ,Multiplexed address mode" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " BMOD[1:0] ,Sample of boot mode pins after reset" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIR_BT_DIS ,Value of dir_bt_dis fuse" "0,1"
|
|
bitfld.long 0x00 12. " BT_EEPROM_CFG ,EEPROM device used for load of configuration DCD data" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BT_MLC_SEL ,BT_MLC_SEL" "0,1"
|
|
bitfld.long 0x00 7.--8. " BT_MEM_TYPE[1:0] ,Boot Memory Type" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BT_SPARE_SIZE ,Specifies the size of spare bytes, for Nand Flash devices" "0,1"
|
|
bitfld.long 0x00 3.--4. " BT_PAGE_SIZE[1:0] ,BT_PAGE_SIZE" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BT_BUS_WIDTH ,NAND Bus width" "0,1"
|
|
bitfld.long 0x00 0.--1. " BT_MEM_CTL[1:0] ,Boot memory control type" "0,1,2,3"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SRSR,SRC Reset Status Register"
|
|
bitfld.long 0x00 16. " WARM_BOOT ,Warm boot indication" "Not initiated,Initiated"
|
|
textline " "
|
|
eventfld.long 0x00 6. " JTAG_SW_RST ,Reset via JTAG SW" "Not software,Software"
|
|
eventfld.long 0x00 5. " JTAG_RST_B ,Reset via HIGH-Z JTAG" "Not HIGH-Z,HIGH-Z"
|
|
textline " "
|
|
eventfld.long 0x00 4. " WDOG_RST_B ,IC Watchdog Time-out reset" "Not WD time-out,WD time-out"
|
|
eventfld.long 0x00 3. " IPP_USER_RESET_B ,Reset via ipp_user_reset_b qulified" "Not ipp_user_reset_b,Ipp_user_reset_b"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
textline " "
|
|
eventfld.long 0x00 0. " IPP_RESET_B ,Reset via ipp_reset_b pin" "Not ipp_reset_b,Ipp_reset_b"
|
|
else
|
|
textline " "
|
|
eventfld.long 0x00 2. " CSU_RESET_B ,Reset via csu_reset_b input" "Not csu_reset_b,Csu_reset_b"
|
|
eventfld.long 0x00 0. " IPP_RESET_B ,Reset via ipp_reset_b pin" "Not ipp_reset_b,Ipp_reset_b"
|
|
endif
|
|
sif (cpuis("IMX6*"))
|
|
rgroup.long 0x014++0x03
|
|
line.long 0x00 "SISR,SRC Interrupt Status Register"
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 8. " CORE3_WDOG_RST_REQ ,Wdog reset request from CPU core3" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " CORE2_WDOG_RST_REQ ,Wdog reset request from CPU core2" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 6. " CORE1_WDOG_RST_REQ ,Wdog reset request from CPU core1" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " CORE0_WDOG_RST_REQ ,Wdog reset request from CPU core0" "Not requested,Requested"
|
|
else
|
|
bitfld.long 0x00 5. " CORE0_WDOG_RST_REQ ,Wdog reset request from CPU core0" "Not requested,Requested"
|
|
endif
|
|
sif (cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 4. " IPU2_PASSED_RESET ,Interrupt generated to indicate that ipu2 passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " OPEN_VG_PASSED_RESET ,Interrupt generated to indicate that open_vg passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 2. " IPU1_PASSED_RESET ,Interrupt generated to indicate that ipu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " VPU_PASSED_RESET ,Interrupt generated to indicate that vpu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " GPU_PASSED_RESET ,Interrupt generated to indicate that gpu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x014++0x03
|
|
line.long 0x00 "SISR,SRC Interrupt Status Register"
|
|
rbitfld.long 0x00 3. " OPEN_VG_PASSED_RESET ,Open_vg passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
sif (cpu()!="IMX50"&&cpu()!="IMX502"&&cpu()!="IMX503"&&cpu()!="IMX507"&&cpu()!="IMX508")
|
|
textline " "
|
|
bitfld.long 0x00 2. " IPU_PASSED_RESET ,Ipu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " VPU_PASSED_RESET ,Vpu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPU_PASSED_RESET ,Gpu passed software reset and is ready to be used" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
group.long 0x018++0x03
|
|
line.long 0x00 "SIMR,SRC Interrupt Mask Register"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")
|
|
bitfld.long 0x00 4. " MASK_IPU2_PASSED_RESET ,Mask interrupt generation due to ipu2 passed reset" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " MASK_OPEN_VG_PASSED_RESET ,Mask interrupt generation due to open_vg passed reset" "Not masked,Masked"
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 2. " MASK_IPU_PASSED_RESET ,Mask interrupt generation due to ipu passed reset" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " MASK_VPU_PASSED_RESET ,Mask interrupt generation due to vpu passed reset" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MASK_GPU_PASSED_RESET ,Mask interrupt generation due to gpu passed reset" "Not masked,Masked"
|
|
sif (cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&cpu()!="IMX50"&&cpu()!="IMX502"&&cpu()!="IMX503"&&cpu()!="IMX507"&&cpu()!="IMX508")
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SBMR2,SRC Boot Mode Register 2"
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 27.--29. " TEST_MODE ,Test mode" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--25. " BMOD ,Boot mode" "0,1,2,3"
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " RESERVED_FUSES ,Reversed fuses" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " BT_FUSE_SEL ,Boot fuse selection" "0,1"
|
|
bitfld.long 0x00 3. " DIR_BT_DIS ,DIR_BT_DIS" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SEC_CONFIG ,SEC_CONFIG" "0,1,2,3"
|
|
group.long 0x20++0x1F
|
|
line.long 0x0 "GPR1,SRC General Purpose Register 1"
|
|
line.long 0x4 "GPR2,SRC General Purpose Register 2"
|
|
line.long 0x8 "GPR3,SRC General Purpose Register 3"
|
|
line.long 0xC "GPR4,SRC General Purpose Register 4"
|
|
line.long 0x10 "GPR5,SRC General Purpose Register 5"
|
|
line.long 0x14 "GPR6,SRC General Purpose Register 6"
|
|
line.long 0x18 "GPR7,SRC General Purpose Register 7"
|
|
line.long 0x1C "GPR8,SRC General Purpose Register 8"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "GPR10,SRC General Purpose Register 10"
|
|
bitfld.long 0x00 30. " PERSIST_SECONDARY_BOOT ,Identifies which image must be used" "0,1"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "GPR10,SRC General Purpose Register 10"
|
|
sif (cpu()!="IMX6SOLO"||cpu()!="IMX6DUALLITE"||cpu()!="IMX6DUAL")
|
|
bitfld.long 0x00 27. " CORE3_ERROR_STATUS ,Core 3 error status bit" "No error,Error"
|
|
bitfld.long 0x00 26. " CORE2_ERROR_STATUS ,Core 2 error status bit" "No error,Error"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " CORE1_ERROR_STATUS ,Core 1 error status bit" "No error,Error"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "SSI (Synchronous Serial Interface)"
|
|
tree "SSI1"
|
|
base ad:0x83fcc000
|
|
width 8.
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
if (((per.l((ad:0x83fcc000)+0x10))&0x01)==0x01)
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
else
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
endif
|
|
else
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
endif
|
|
hgroup.long 0x08++0x7
|
|
hide.long 0x00 "SRX0,Receive Data Register 0"
|
|
in
|
|
hide.long 0x04 "SRX1,Receive Data Register 1"
|
|
in
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SCR,SSI Control Register"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes"
|
|
bitfld.long 0x0 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "Low,High"
|
|
bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
in
|
|
elif (cpuis("IMX6*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
bitfld.long 0x00 24. " RFRC ,Receive Frame Complete" "Not reached,Reached"
|
|
bitfld.long 0x00 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached"
|
|
bitfld.long 0x00 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated"
|
|
bitfld.long 0x00 16. " RXT ,Receive Tag Updated" "Not updated,Updated"
|
|
bitfld.long 0x00 15. " RDR1 ,Receive Data Ready 1" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RDR0 ,Receive Data Ready 0" "No new data,New data"
|
|
bitfld.long 0x00 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error"
|
|
eventfld.long 0x00 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error"
|
|
eventfld.long 0x00 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error"
|
|
bitfld.long 0x00 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLS ,Transmit Last Time Slot" "No,Yes"
|
|
bitfld.long 0x00 4. " RLS ,Receive Last Time Slot" "No,Yes"
|
|
bitfld.long 0x00 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full"
|
|
bitfld.long 0x00 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty"
|
|
else
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
in
|
|
endif
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "SIER,SSI Interrupt Enable Register"
|
|
bitfld.long 0x00 24. " RFRC_EN ,Receive Frame Complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TFRC_EN ,Transmit Frame Complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CMDAU_EN ,Command Address Register Updated" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CMDDU_EN ,Command Data Register Updated" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXT_EN ,Receive Tag Updated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RDR1_EN ,Receive Data Ready 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RDR0_EN ,Receive Data Ready 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TDE1_EN ,Transmit Data Register Empty 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TDE0_EN ,Transmit Data Register Empty 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ROE1_EN ,Receiver Overrun Error 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ROE0_EN ,Receiver Overrun Error 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TUE1_EN ,Transmitter Underrun Error 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TUE0_EN ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TFS_EN ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RFS_EN ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rbitfld.long 0x00 5. " TLS_EN ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 5. " TLS_EN ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 4. " RLS_EN ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RFF1_EN ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RFF0_EN ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFE1_EN ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "STCR,SSI Transmit Configuration Register"
|
|
bitfld.long 0x04 9. " TXBIT0 ,Transmit Bit 0" "Bit 31|15,Bit 0"
|
|
bitfld.long 0x04 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TFDIR ,Transmit Frame Direction" "External,Internal"
|
|
bitfld.long 0x04 5. " TXDIR ,Transmit Clock Direction" "External,Internal"
|
|
bitfld.long 0x04 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x04 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low"
|
|
bitfld.long 0x04 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before"
|
|
line.long 0x08 "SRCR,SSI Receive Configuration Register"
|
|
bitfld.long 0x8 10. " RXEXT ,Receive Data Extension" "Not extended,Extended"
|
|
bitfld.long 0x08 9. " RXBIT0 ,Receive Bit 0" "Bit 31|15,Bit 0"
|
|
bitfld.long 0x08 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RFDIR ,Receive Frame Direction" "External,Internal"
|
|
bitfld.long 0x08 5. " RXDIR ,Receive Clock Direction" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x08 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first"
|
|
bitfld.long 0x08 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x08 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit"
|
|
bitfld.long 0x08 0. " REFS ,Receive Early Frame Sync" "First bit,One before"
|
|
line.long 0x0c "STCCR,SSI Transmit Clock Control Register"
|
|
bitfld.long 0x0c 18. " DIV2 ,Divide By 2" "Bypassed,Div by 2"
|
|
bitfld.long 0x0c 17. " PSR ,Prescaler Range" "Bypassed,Div by 8"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x0C 13.--16. " WL[3:0] ,Word Length Control" "-,-,-,8,10,12,-,16,18,20,22,24,-,?..."
|
|
else
|
|
bitfld.long 0x0C 13.--16. " WL[3:0] ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 8.--12. " DC[4:0] ,Frame Rate Divider Control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " PM[7:0] ,Prescaler Modulus Select"
|
|
line.long 0x10 "SRCCR,SSI Receive Clock Control Register"
|
|
bitfld.long 0x10 18. " DIV2 ,Divide By 2" "Bypassed,Div by 2"
|
|
bitfld.long 0x10 17. " PSR ,Prescaler Range" "Bypassed,Div by 8"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x10 13.--16. " WL[3:0] ,Word Length Control" "-,-,-,8,10,12,-,16,18,20,22,24,-,?..."
|
|
else
|
|
bitfld.long 0x10 13.--16. " WL[3:0] ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 8.--12. " DC[4:0] ,Frame Rate Divider Control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PM[7:0] ,Prescaler Modulus Select"
|
|
line.long 0x14 "SFCSR,SSI FIFO Control/Status Register"
|
|
bitfld.long 0x14 28.--31. " RFCNT1[3:0] ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " TFCNT1[3:0] ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " RFWM1[3:0] ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
textline " "
|
|
bitfld.long 0x14 16.--19. " TFWM1[3:0] ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
bitfld.long 0x14 12.--15. " RFCNT0[3:0] ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " TFCNT0[3:0] ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " RFWM0[3:0] ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
bitfld.long 0x14 0.--3. " TFWM0[3:0] ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
sif (!cpuis("IMX6*")&&cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&!cpuis("IMX50*"))
|
|
group.long 0x30++0x7
|
|
line.long 0x00 "STR,SSI Test Register"
|
|
bitfld.long 0x00 15. " TEST ,Test Mode" "No effect,Test Mode"
|
|
bitfld.long 0x00 14. " RCK2TCK ,Receive Clock to Transmit Clock Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 13. " RFS2TFS ,Receive Frame to Transmit Frame Loop Back" "No effect,Loop back"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RXSTATE ,Receiver State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " TXD2RXD ,Transmit Data to Receive Data Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 6. " TCK2RCK ,Transmit Clock to Receive Clock Loop Back" "No effect,Loop back"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TFS2RFS ,Transmit Frame to Receive Frame Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 0.--4. " TXSTATE ,Transmitter State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "SOR,SSI Option Register"
|
|
bitfld.long 0x04 6. " CLKOFF ,Clock Off" "No effect,Off"
|
|
bitfld.long 0x04 5. " RX_CLR ,Receiver Clear" "No effect,Flushed"
|
|
bitfld.long 0x04 4. " TX_CLR ,Transmitter Clear" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INIT ,Initialize" "No effect,Initialized"
|
|
bitfld.long 0x04 1.--2. " WAIT ,Number wait states" "0,1,2,3"
|
|
bitfld.long 0x04 0. " SYNRST ,Frame Sync Reset" "No reset,Reset"
|
|
endif
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "SACNT,SSI AC97 Control Register"
|
|
hexmask.long.byte 0x00 5.--10. 1. " FRDIV[5:0] ,Frame Rate Divider"
|
|
bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached"
|
|
bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0"
|
|
bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
hgroup.long 0x3c++0x0B
|
|
hide.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
in
|
|
hide.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
in
|
|
hide.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
in
|
|
elif (cpuis("IMX6*"))
|
|
group.long 0x3c++0x0B
|
|
line.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " SACADD ,AC97 Command Address"
|
|
line.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " SACDAT ,AC97 Command Data"
|
|
line.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SATAG ,AC97 Tag Value"
|
|
else
|
|
hgroup.long 0x3c++0x0B
|
|
hide.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
in
|
|
hide.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
in
|
|
hide.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
in
|
|
endif
|
|
textline " "
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "STMSK,SSI Transmit Time Slot Mask Register"
|
|
bitfld.long 0x00 31. " STMSK ,Transmit Mask Bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Transmit Mask Bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Transmit Mask Bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Transmit Mask Bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Transmit Mask Bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Transmit Mask Bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Transmit Mask Bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Transmit Mask Bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Transmit Mask Bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Transmit Mask Bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Transmit Mask Bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Transmit Mask Bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Transmit Mask Bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Transmit Mask Bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Transmit Mask Bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Transmit Mask Bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Transmit Mask Bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Transmit Mask Bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Transmit Mask Bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Transmit Mask Bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Transmit Mask Bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Transmit Mask Bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Transmit Mask Bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Transmit Mask Bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Transmit Mask Bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Transmit Mask Bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Transmit Mask Bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Transmit Mask Bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Transmit Mask Bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Transmit Mask Bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Transmit Mask Bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Transmit Mask Bit 0" "0,1"
|
|
line.long 0x04 "SRMSK,SSI Receive Time Slot Mask Register"
|
|
bitfld.long 0x04 31. " SRMSK ,Receive Mask Bit 31" "0,1"
|
|
bitfld.long 0x04 30. ",Receive Mask Bit 30" "0,1"
|
|
bitfld.long 0x04 29. ",Receive Mask Bit 29" "0,1"
|
|
bitfld.long 0x04 28. ",Receive Mask Bit 28" "0,1"
|
|
bitfld.long 0x04 27. ",Receive Mask Bit 27" "0,1"
|
|
bitfld.long 0x04 26. ",Receive Mask Bit 26" "0,1"
|
|
bitfld.long 0x04 25. ",Receive Mask Bit 25" "0,1"
|
|
bitfld.long 0x04 24. ",Receive Mask Bit 24" "0,1"
|
|
bitfld.long 0x04 23. ",Receive Mask Bit 23" "0,1"
|
|
bitfld.long 0x04 22. ",Receive Mask Bit 22" "0,1"
|
|
bitfld.long 0x04 21. ",Receive Mask Bit 21" "0,1"
|
|
bitfld.long 0x04 20. ",Receive Mask Bit 20" "0,1"
|
|
bitfld.long 0x04 19. ",Receive Mask Bit 19" "0,1"
|
|
bitfld.long 0x04 18. ",Receive Mask Bit 18" "0,1"
|
|
bitfld.long 0x04 17. ",Receive Mask Bit 17" "0,1"
|
|
bitfld.long 0x04 16. ",Receive Mask Bit 16" "0,1"
|
|
bitfld.long 0x04 15. ",Receive Mask Bit 15" "0,1"
|
|
bitfld.long 0x04 14. ",Receive Mask Bit 14" "0,1"
|
|
bitfld.long 0x04 13. ",Receive Mask Bit 13" "0,1"
|
|
bitfld.long 0x04 12. ",Receive Mask Bit 12" "0,1"
|
|
bitfld.long 0x04 11. ",Receive Mask Bit 11" "0,1"
|
|
bitfld.long 0x04 10. ",Receive Mask Bit 10" "0,1"
|
|
bitfld.long 0x04 9. ",Receive Mask Bit 9" "0,1"
|
|
bitfld.long 0x04 8. ",Receive Mask Bit 8" "0,1"
|
|
bitfld.long 0x04 7. ",Receive Mask Bit 7" "0,1"
|
|
bitfld.long 0x04 6. ",Receive Mask Bit 6" "0,1"
|
|
bitfld.long 0x04 5. ",Receive Mask Bit 5" "0,1"
|
|
bitfld.long 0x04 4. ",Receive Mask Bit 4" "0,1"
|
|
bitfld.long 0x04 3. ",Receive Mask Bit 3" "0,1"
|
|
bitfld.long 0x04 2. ",Receive Mask Bit 2" "0,1"
|
|
bitfld.long 0x04 1. ",Receive Mask Bit 1" "0,1"
|
|
bitfld.long 0x04 0. ",Receive Mask Bit 0" "0,1"
|
|
textline " "
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "SACCST,SSI AC97 Channel Status Register"
|
|
setclrfld.long 0x0 9. 0x4 9. 0x8 9. " SACCST9_set/clr ,AC97 Channel Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. 0x4 8. 0x8 8. " SACCST8_set/clr ,AC97 Channel Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x4 7. 0x8 7. " SACCST7_set/clr ,AC97 Channel Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. 0x4 6. 0x8 6. " SACCST6_set/clr ,AC97 Channel Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x4 5. 0x8 5. " SACCST5_set/clr ,AC97 Channel Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. 0x4 4. 0x8 4. " SACCST4_set/clr ,AC97 Channel Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x4 3. 0x8 3. " SACCST3_set/clr ,AC97 Channel Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. 0x4 2. 0x8 2. " SACCST2_set/clr ,AC97 Channel Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x4 1. 0x8 1. " SACCST1_set/clr ,AC97 Channel Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. 0x4 0. 0x8 0. " SACCST0_set/clr ,AC97 Channel Status 0" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SSI2"
|
|
base ad:0x70014000
|
|
width 8.
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
if (((per.l((ad:0x70014000)+0x10))&0x01)==0x01)
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
else
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
endif
|
|
else
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
endif
|
|
hgroup.long 0x08++0x7
|
|
hide.long 0x00 "SRX0,Receive Data Register 0"
|
|
in
|
|
hide.long 0x04 "SRX1,Receive Data Register 1"
|
|
in
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SCR,SSI Control Register"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes"
|
|
bitfld.long 0x0 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "Low,High"
|
|
bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
in
|
|
elif (cpuis("IMX6*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
bitfld.long 0x00 24. " RFRC ,Receive Frame Complete" "Not reached,Reached"
|
|
bitfld.long 0x00 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached"
|
|
bitfld.long 0x00 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated"
|
|
bitfld.long 0x00 16. " RXT ,Receive Tag Updated" "Not updated,Updated"
|
|
bitfld.long 0x00 15. " RDR1 ,Receive Data Ready 1" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RDR0 ,Receive Data Ready 0" "No new data,New data"
|
|
bitfld.long 0x00 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error"
|
|
eventfld.long 0x00 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error"
|
|
eventfld.long 0x00 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error"
|
|
bitfld.long 0x00 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLS ,Transmit Last Time Slot" "No,Yes"
|
|
bitfld.long 0x00 4. " RLS ,Receive Last Time Slot" "No,Yes"
|
|
bitfld.long 0x00 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full"
|
|
bitfld.long 0x00 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty"
|
|
else
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
in
|
|
endif
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "SIER,SSI Interrupt Enable Register"
|
|
bitfld.long 0x00 24. " RFRC_EN ,Receive Frame Complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TFRC_EN ,Transmit Frame Complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CMDAU_EN ,Command Address Register Updated" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CMDDU_EN ,Command Data Register Updated" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXT_EN ,Receive Tag Updated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RDR1_EN ,Receive Data Ready 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RDR0_EN ,Receive Data Ready 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TDE1_EN ,Transmit Data Register Empty 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TDE0_EN ,Transmit Data Register Empty 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ROE1_EN ,Receiver Overrun Error 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ROE0_EN ,Receiver Overrun Error 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TUE1_EN ,Transmitter Underrun Error 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TUE0_EN ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TFS_EN ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RFS_EN ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rbitfld.long 0x00 5. " TLS_EN ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 5. " TLS_EN ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 4. " RLS_EN ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RFF1_EN ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RFF0_EN ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFE1_EN ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "STCR,SSI Transmit Configuration Register"
|
|
bitfld.long 0x04 9. " TXBIT0 ,Transmit Bit 0" "Bit 31|15,Bit 0"
|
|
bitfld.long 0x04 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TFDIR ,Transmit Frame Direction" "External,Internal"
|
|
bitfld.long 0x04 5. " TXDIR ,Transmit Clock Direction" "External,Internal"
|
|
bitfld.long 0x04 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x04 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low"
|
|
bitfld.long 0x04 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before"
|
|
line.long 0x08 "SRCR,SSI Receive Configuration Register"
|
|
bitfld.long 0x8 10. " RXEXT ,Receive Data Extension" "Not extended,Extended"
|
|
bitfld.long 0x08 9. " RXBIT0 ,Receive Bit 0" "Bit 31|15,Bit 0"
|
|
bitfld.long 0x08 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RFDIR ,Receive Frame Direction" "External,Internal"
|
|
bitfld.long 0x08 5. " RXDIR ,Receive Clock Direction" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x08 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first"
|
|
bitfld.long 0x08 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x08 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit"
|
|
bitfld.long 0x08 0. " REFS ,Receive Early Frame Sync" "First bit,One before"
|
|
line.long 0x0c "STCCR,SSI Transmit Clock Control Register"
|
|
bitfld.long 0x0c 18. " DIV2 ,Divide By 2" "Bypassed,Div by 2"
|
|
bitfld.long 0x0c 17. " PSR ,Prescaler Range" "Bypassed,Div by 8"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x0C 13.--16. " WL[3:0] ,Word Length Control" "-,-,-,8,10,12,-,16,18,20,22,24,-,?..."
|
|
else
|
|
bitfld.long 0x0C 13.--16. " WL[3:0] ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 8.--12. " DC[4:0] ,Frame Rate Divider Control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " PM[7:0] ,Prescaler Modulus Select"
|
|
line.long 0x10 "SRCCR,SSI Receive Clock Control Register"
|
|
bitfld.long 0x10 18. " DIV2 ,Divide By 2" "Bypassed,Div by 2"
|
|
bitfld.long 0x10 17. " PSR ,Prescaler Range" "Bypassed,Div by 8"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x10 13.--16. " WL[3:0] ,Word Length Control" "-,-,-,8,10,12,-,16,18,20,22,24,-,?..."
|
|
else
|
|
bitfld.long 0x10 13.--16. " WL[3:0] ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 8.--12. " DC[4:0] ,Frame Rate Divider Control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PM[7:0] ,Prescaler Modulus Select"
|
|
line.long 0x14 "SFCSR,SSI FIFO Control/Status Register"
|
|
bitfld.long 0x14 28.--31. " RFCNT1[3:0] ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " TFCNT1[3:0] ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " RFWM1[3:0] ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
textline " "
|
|
bitfld.long 0x14 16.--19. " TFWM1[3:0] ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
bitfld.long 0x14 12.--15. " RFCNT0[3:0] ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " TFCNT0[3:0] ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " RFWM0[3:0] ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
bitfld.long 0x14 0.--3. " TFWM0[3:0] ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
sif (!cpuis("IMX6*")&&cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&!cpuis("IMX50*"))
|
|
group.long 0x30++0x7
|
|
line.long 0x00 "STR,SSI Test Register"
|
|
bitfld.long 0x00 15. " TEST ,Test Mode" "No effect,Test Mode"
|
|
bitfld.long 0x00 14. " RCK2TCK ,Receive Clock to Transmit Clock Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 13. " RFS2TFS ,Receive Frame to Transmit Frame Loop Back" "No effect,Loop back"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RXSTATE ,Receiver State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " TXD2RXD ,Transmit Data to Receive Data Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 6. " TCK2RCK ,Transmit Clock to Receive Clock Loop Back" "No effect,Loop back"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TFS2RFS ,Transmit Frame to Receive Frame Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 0.--4. " TXSTATE ,Transmitter State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "SOR,SSI Option Register"
|
|
bitfld.long 0x04 6. " CLKOFF ,Clock Off" "No effect,Off"
|
|
bitfld.long 0x04 5. " RX_CLR ,Receiver Clear" "No effect,Flushed"
|
|
bitfld.long 0x04 4. " TX_CLR ,Transmitter Clear" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INIT ,Initialize" "No effect,Initialized"
|
|
bitfld.long 0x04 1.--2. " WAIT ,Number wait states" "0,1,2,3"
|
|
bitfld.long 0x04 0. " SYNRST ,Frame Sync Reset" "No reset,Reset"
|
|
endif
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "SACNT,SSI AC97 Control Register"
|
|
hexmask.long.byte 0x00 5.--10. 1. " FRDIV[5:0] ,Frame Rate Divider"
|
|
bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached"
|
|
bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0"
|
|
bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
hgroup.long 0x3c++0x0B
|
|
hide.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
in
|
|
hide.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
in
|
|
hide.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
in
|
|
elif (cpuis("IMX6*"))
|
|
group.long 0x3c++0x0B
|
|
line.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " SACADD ,AC97 Command Address"
|
|
line.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " SACDAT ,AC97 Command Data"
|
|
line.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SATAG ,AC97 Tag Value"
|
|
else
|
|
hgroup.long 0x3c++0x0B
|
|
hide.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
in
|
|
hide.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
in
|
|
hide.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
in
|
|
endif
|
|
textline " "
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "STMSK,SSI Transmit Time Slot Mask Register"
|
|
bitfld.long 0x00 31. " STMSK ,Transmit Mask Bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Transmit Mask Bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Transmit Mask Bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Transmit Mask Bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Transmit Mask Bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Transmit Mask Bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Transmit Mask Bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Transmit Mask Bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Transmit Mask Bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Transmit Mask Bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Transmit Mask Bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Transmit Mask Bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Transmit Mask Bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Transmit Mask Bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Transmit Mask Bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Transmit Mask Bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Transmit Mask Bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Transmit Mask Bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Transmit Mask Bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Transmit Mask Bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Transmit Mask Bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Transmit Mask Bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Transmit Mask Bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Transmit Mask Bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Transmit Mask Bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Transmit Mask Bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Transmit Mask Bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Transmit Mask Bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Transmit Mask Bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Transmit Mask Bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Transmit Mask Bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Transmit Mask Bit 0" "0,1"
|
|
line.long 0x04 "SRMSK,SSI Receive Time Slot Mask Register"
|
|
bitfld.long 0x04 31. " SRMSK ,Receive Mask Bit 31" "0,1"
|
|
bitfld.long 0x04 30. ",Receive Mask Bit 30" "0,1"
|
|
bitfld.long 0x04 29. ",Receive Mask Bit 29" "0,1"
|
|
bitfld.long 0x04 28. ",Receive Mask Bit 28" "0,1"
|
|
bitfld.long 0x04 27. ",Receive Mask Bit 27" "0,1"
|
|
bitfld.long 0x04 26. ",Receive Mask Bit 26" "0,1"
|
|
bitfld.long 0x04 25. ",Receive Mask Bit 25" "0,1"
|
|
bitfld.long 0x04 24. ",Receive Mask Bit 24" "0,1"
|
|
bitfld.long 0x04 23. ",Receive Mask Bit 23" "0,1"
|
|
bitfld.long 0x04 22. ",Receive Mask Bit 22" "0,1"
|
|
bitfld.long 0x04 21. ",Receive Mask Bit 21" "0,1"
|
|
bitfld.long 0x04 20. ",Receive Mask Bit 20" "0,1"
|
|
bitfld.long 0x04 19. ",Receive Mask Bit 19" "0,1"
|
|
bitfld.long 0x04 18. ",Receive Mask Bit 18" "0,1"
|
|
bitfld.long 0x04 17. ",Receive Mask Bit 17" "0,1"
|
|
bitfld.long 0x04 16. ",Receive Mask Bit 16" "0,1"
|
|
bitfld.long 0x04 15. ",Receive Mask Bit 15" "0,1"
|
|
bitfld.long 0x04 14. ",Receive Mask Bit 14" "0,1"
|
|
bitfld.long 0x04 13. ",Receive Mask Bit 13" "0,1"
|
|
bitfld.long 0x04 12. ",Receive Mask Bit 12" "0,1"
|
|
bitfld.long 0x04 11. ",Receive Mask Bit 11" "0,1"
|
|
bitfld.long 0x04 10. ",Receive Mask Bit 10" "0,1"
|
|
bitfld.long 0x04 9. ",Receive Mask Bit 9" "0,1"
|
|
bitfld.long 0x04 8. ",Receive Mask Bit 8" "0,1"
|
|
bitfld.long 0x04 7. ",Receive Mask Bit 7" "0,1"
|
|
bitfld.long 0x04 6. ",Receive Mask Bit 6" "0,1"
|
|
bitfld.long 0x04 5. ",Receive Mask Bit 5" "0,1"
|
|
bitfld.long 0x04 4. ",Receive Mask Bit 4" "0,1"
|
|
bitfld.long 0x04 3. ",Receive Mask Bit 3" "0,1"
|
|
bitfld.long 0x04 2. ",Receive Mask Bit 2" "0,1"
|
|
bitfld.long 0x04 1. ",Receive Mask Bit 1" "0,1"
|
|
bitfld.long 0x04 0. ",Receive Mask Bit 0" "0,1"
|
|
textline " "
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "SACCST,SSI AC97 Channel Status Register"
|
|
setclrfld.long 0x0 9. 0x4 9. 0x8 9. " SACCST9_set/clr ,AC97 Channel Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. 0x4 8. 0x8 8. " SACCST8_set/clr ,AC97 Channel Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x4 7. 0x8 7. " SACCST7_set/clr ,AC97 Channel Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. 0x4 6. 0x8 6. " SACCST6_set/clr ,AC97 Channel Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x4 5. 0x8 5. " SACCST5_set/clr ,AC97 Channel Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. 0x4 4. 0x8 4. " SACCST4_set/clr ,AC97 Channel Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x4 3. 0x8 3. " SACCST3_set/clr ,AC97 Channel Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. 0x4 2. 0x8 2. " SACCST2_set/clr ,AC97 Channel Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x4 1. 0x8 1. " SACCST1_set/clr ,AC97 Channel Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. 0x4 0. 0x8 0. " SACCST0_set/clr ,AC97 Channel Status 0" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SSI3"
|
|
base ad:0x83fe8000
|
|
width 8.
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
if (((per.l((ad:0x83fe8000)+0x10))&0x01)==0x01)
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
else
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
endif
|
|
else
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "STX0,Transmit Data Register 0"
|
|
line.long 0x04 "STX1,Transmit Data Register 1"
|
|
endif
|
|
hgroup.long 0x08++0x7
|
|
hide.long 0x00 "SRX0,Receive Data Register 0"
|
|
in
|
|
hide.long 0x04 "SRX1,Receive Data Register 1"
|
|
in
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SCR,SSI Control Register"
|
|
sif (cpuis("IMX6*")||cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538"||cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508")
|
|
bitfld.long 0x00 12. " SYNC_TX_FS ,TE latch" "Not latched,Latched"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 11. " RFR_CLK_DIS ,Receive Frame Clock Disable" "No,Yes"
|
|
bitfld.long 0x0 10. " TFR_CLK_DIS ,Transmit Frame Clock Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLK_IST ,Clock Idle State" "Low,High"
|
|
bitfld.long 0x00 8. " TCH_EN ,Two Channel Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SYS_CLK_EN ,Network Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5.--6. " I2S_MODE[1:0] ,I2S Mode Select" "Normal,I2S master,I2S slave,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYN ,Synchronous Mode" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 3. " NET ,Network Mode" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSIEN ,SSI Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
in
|
|
elif (cpuis("IMX6*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
bitfld.long 0x00 24. " RFRC ,Receive Frame Complete" "Not reached,Reached"
|
|
bitfld.long 0x00 23. " TFRC ,Transmit Frame Complete" "Not reached,Reached"
|
|
bitfld.long 0x00 18. " CMDAU ,Command Address Register Updated" "Not updated,Updated"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMDDU ,Command Data Register Updated" "Not updated,Updated"
|
|
bitfld.long 0x00 16. " RXT ,Receive Tag Updated" "Not updated,Updated"
|
|
bitfld.long 0x00 15. " RDR1 ,Receive Data Ready 1" "No new data,New data"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RDR0 ,Receive Data Ready 0" "No new data,New data"
|
|
bitfld.long 0x00 13. " TDE1 ,Transmit Data Register Empty 1" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " TDE0 ,Transmit Data Register Empty 0" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ROE1 ,Receiver Overrun Error 1" "No error,Error"
|
|
eventfld.long 0x00 10. " ROE0 ,Receiver Overrun Error 0" "No error,Error"
|
|
eventfld.long 0x00 9. " TUE1 ,Transmitter Underrun Error 1" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TUE0 ,Transmitter Underrun Error 0" "No error,Error"
|
|
bitfld.long 0x00 7. " TFS ,Transmit Frame Sync" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " RFS ,Receive Frame Sync" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLS ,Transmit Last Time Slot" "No,Yes"
|
|
bitfld.long 0x00 4. " RLS ,Receive Last Time Slot" "No,Yes"
|
|
bitfld.long 0x00 3. " RFF1 ,Receive FIFO Full 1" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RFF0 ,Receive FIFO Full 0" "Not full,Full"
|
|
bitfld.long 0x00 1. " TFE1 ,Transmit FIFO Empty 1" "Not empty,Empty"
|
|
bitfld.long 0x00 0. " TFE0 ,Transmit FIFO Empty 0" "Not empty,Empty"
|
|
else
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x00 "SISR,SSI Interrupt Status Register"
|
|
in
|
|
endif
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "SIER,SSI Interrupt Enable Register"
|
|
bitfld.long 0x00 24. " RFRC_EN ,Receive Frame Complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TFRC_EN ,Transmit Frame Complete" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RDMAE ,Receive DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDMAE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CMDAU_EN ,Command Address Register Updated" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CMDDU_EN ,Command Data Register Updated" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RXT_EN ,Receive Tag Updated" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RDR1_EN ,Receive Data Ready 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RDR0_EN ,Receive Data Ready 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TDE1_EN ,Transmit Data Register Empty 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TDE0_EN ,Transmit Data Register Empty 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ROE1_EN ,Receiver Overrun Error 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ROE0_EN ,Receiver Overrun Error 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TUE1_EN ,Transmitter Underrun Error 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TUE0_EN ,Transmitter Underrun Error 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TFS_EN ,Transmit Frame Sync Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RFS_EN ,Receive Frame Sync Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rbitfld.long 0x00 5. " TLS_EN ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 5. " TLS_EN ,Transmit Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 4. " RLS_EN ,Receive Last Time Slot Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RFF1_EN ,Receive FIFO Full 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RFF0_EN ,Receive FIFO Full 0 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TFE1_EN ,Transmit FIFO Empty 1 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TFE0_EN ,Transmit FIFO Empty 0 Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "STCR,SSI Transmit Configuration Register"
|
|
bitfld.long 0x04 9. " TXBIT0 ,Transmit Bit 0" "Bit 31|15,Bit 0"
|
|
bitfld.long 0x04 8. " TFEN1 ,Transmit FIFO Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " TFEN0 ,Transmit FIFO Enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " TFDIR ,Transmit Frame Direction" "External,Internal"
|
|
bitfld.long 0x04 5. " TXDIR ,Transmit Clock Direction" "External,Internal"
|
|
bitfld.long 0x04 4. " TSHFD ,Transmit Shift Direction" "MSB first,LSB first"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TSCKP ,Transmit Clock Polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x04 2. " TFSI ,Transmit Frame Sync Invert" "Active high,Active low"
|
|
bitfld.long 0x04 1. " TFSL ,Transmit Frame Sync Length" "One-word,One-clock-bit"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TEFS ,Transmit Early Frame Sync" "First bit,One before"
|
|
line.long 0x08 "SRCR,SSI Receive Configuration Register"
|
|
bitfld.long 0x8 10. " RXEXT ,Receive Data Extension" "Not extended,Extended"
|
|
bitfld.long 0x08 9. " RXBIT0 ,Receive Bit 0" "Bit 31|15,Bit 0"
|
|
bitfld.long 0x08 8. " RFEN1 ,Receive FIFO Enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " RFEN0 ,Receive FIFO Enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " RFDIR ,Receive Frame Direction" "External,Internal"
|
|
bitfld.long 0x08 5. " RXDIR ,Receive Clock Direction" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x08 4. " RSHFD ,Receive Shift Direction" "MSB first,LSB first"
|
|
bitfld.long 0x08 3. " RSCKP ,Receive Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x08 2. " RFSI ,Receive Frame Sync Invert" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSL ,Receive Frame Sync Length" "One-word,One-clock-bit"
|
|
bitfld.long 0x08 0. " REFS ,Receive Early Frame Sync" "First bit,One before"
|
|
line.long 0x0c "STCCR,SSI Transmit Clock Control Register"
|
|
bitfld.long 0x0c 18. " DIV2 ,Divide By 2" "Bypassed,Div by 2"
|
|
bitfld.long 0x0c 17. " PSR ,Prescaler Range" "Bypassed,Div by 8"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x0C 13.--16. " WL[3:0] ,Word Length Control" "-,-,-,8,10,12,-,16,18,20,22,24,-,?..."
|
|
else
|
|
bitfld.long 0x0C 13.--16. " WL[3:0] ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0c 8.--12. " DC[4:0] ,Frame Rate Divider Control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " PM[7:0] ,Prescaler Modulus Select"
|
|
line.long 0x10 "SRCCR,SSI Receive Clock Control Register"
|
|
bitfld.long 0x10 18. " DIV2 ,Divide By 2" "Bypassed,Div by 2"
|
|
bitfld.long 0x10 17. " PSR ,Prescaler Range" "Bypassed,Div by 8"
|
|
sif (cpu()=="IMX50"||cpu()=="IMX502"||cpu()=="IMX503"||cpu()=="IMX507"||cpu()=="IMX508"||cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x10 13.--16. " WL[3:0] ,Word Length Control" "-,-,-,8,10,12,-,16,18,20,22,24,-,?..."
|
|
else
|
|
bitfld.long 0x10 13.--16. " WL[3:0] ,Word Length Control" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 8.--12. " DC[4:0] ,Frame Rate Divider Control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PM[7:0] ,Prescaler Modulus Select"
|
|
line.long 0x14 "SFCSR,SSI FIFO Control/Status Register"
|
|
bitfld.long 0x14 28.--31. " RFCNT1[3:0] ,Receive FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " TFCNT1[3:0] ,Transmit FIFO Counter 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 20.--23. " RFWM1[3:0] ,Receive FIFO Full WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
textline " "
|
|
bitfld.long 0x14 16.--19. " TFWM1[3:0] ,Transmit FIFO Empty WaterMark 1" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
bitfld.long 0x14 12.--15. " RFCNT0[3:0] ,Receive FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " TFCNT0[3:0] ,Transmit FIFO Counter 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " RFWM0[3:0] ,Receive FIFO Full WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
bitfld.long 0x14 0.--3. " TFWM0[3:0] ,Transmit FIFO Empty WaterMark 0" ",>=1,>=2,>=3,>=4,>=5,>=6,>=7,>=8,>=9,>=10,>=11,>=12,>=13,>=14,=15"
|
|
sif (!cpuis("IMX6*")&&cpu()!="IMX53"&&cpu()!="IMX534"&&cpu()!="IMX535"&&cpu()!="IMX536"&&cpu()!="IMX537"&&cpu()!="IMX538"&&!cpuis("IMX50*"))
|
|
group.long 0x30++0x7
|
|
line.long 0x00 "STR,SSI Test Register"
|
|
bitfld.long 0x00 15. " TEST ,Test Mode" "No effect,Test Mode"
|
|
bitfld.long 0x00 14. " RCK2TCK ,Receive Clock to Transmit Clock Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 13. " RFS2TFS ,Receive Frame to Transmit Frame Loop Back" "No effect,Loop back"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " RXSTATE ,Receiver State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " TXD2RXD ,Transmit Data to Receive Data Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 6. " TCK2RCK ,Transmit Clock to Receive Clock Loop Back" "No effect,Loop back"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TFS2RFS ,Transmit Frame to Receive Frame Loop Back" "No effect,Loop back"
|
|
bitfld.long 0x00 0.--4. " TXSTATE ,Transmitter State Machine Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "SOR,SSI Option Register"
|
|
bitfld.long 0x04 6. " CLKOFF ,Clock Off" "No effect,Off"
|
|
bitfld.long 0x04 5. " RX_CLR ,Receiver Clear" "No effect,Flushed"
|
|
bitfld.long 0x04 4. " TX_CLR ,Transmitter Clear" "No effect,Flushed"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INIT ,Initialize" "No effect,Initialized"
|
|
bitfld.long 0x04 1.--2. " WAIT ,Number wait states" "0,1,2,3"
|
|
bitfld.long 0x04 0. " SYNRST ,Frame Sync Reset" "No reset,Reset"
|
|
endif
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "SACNT,SSI AC97 Control Register"
|
|
hexmask.long.byte 0x00 5.--10. 1. " FRDIV[5:0] ,Frame Rate Divider"
|
|
bitfld.long 0x00 4. " WR ,Write Command" "Not attached,Attached"
|
|
bitfld.long 0x00 3. " RD ,Read Command" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIF ,Tag in FIFO" "SATAG,Rx FIFO 0"
|
|
bitfld.long 0x00 1. " FV ,Fixed/Variable Operation" "Fixed,Variable"
|
|
bitfld.long 0x00 0. " AC97EN ,AC97 Mode Enable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
hgroup.long 0x3c++0x0B
|
|
hide.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
in
|
|
hide.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
in
|
|
hide.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
in
|
|
elif (cpuis("IMX6*"))
|
|
group.long 0x3c++0x0B
|
|
line.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. " SACADD ,AC97 Command Address"
|
|
line.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
hexmask.long.tbyte 0x04 0.--19. 1. " SACDAT ,AC97 Command Data"
|
|
line.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " SATAG ,AC97 Tag Value"
|
|
else
|
|
hgroup.long 0x3c++0x0B
|
|
hide.long 0x00 "SACADD,SSI AC97 Command Address Register"
|
|
in
|
|
hide.long 0x04 "SACDAT,SSI AC97 Command Data Register"
|
|
in
|
|
hide.long 0x08 "SATAG,SSI AC97 Tag Register"
|
|
in
|
|
endif
|
|
textline " "
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "STMSK,SSI Transmit Time Slot Mask Register"
|
|
bitfld.long 0x00 31. " STMSK ,Transmit Mask Bit 31" "0,1"
|
|
bitfld.long 0x00 30. ",Transmit Mask Bit 30" "0,1"
|
|
bitfld.long 0x00 29. ",Transmit Mask Bit 29" "0,1"
|
|
bitfld.long 0x00 28. ",Transmit Mask Bit 28" "0,1"
|
|
bitfld.long 0x00 27. ",Transmit Mask Bit 27" "0,1"
|
|
bitfld.long 0x00 26. ",Transmit Mask Bit 26" "0,1"
|
|
bitfld.long 0x00 25. ",Transmit Mask Bit 25" "0,1"
|
|
bitfld.long 0x00 24. ",Transmit Mask Bit 24" "0,1"
|
|
bitfld.long 0x00 23. ",Transmit Mask Bit 23" "0,1"
|
|
bitfld.long 0x00 22. ",Transmit Mask Bit 22" "0,1"
|
|
bitfld.long 0x00 21. ",Transmit Mask Bit 21" "0,1"
|
|
bitfld.long 0x00 20. ",Transmit Mask Bit 20" "0,1"
|
|
bitfld.long 0x00 19. ",Transmit Mask Bit 19" "0,1"
|
|
bitfld.long 0x00 18. ",Transmit Mask Bit 18" "0,1"
|
|
bitfld.long 0x00 17. ",Transmit Mask Bit 17" "0,1"
|
|
bitfld.long 0x00 16. ",Transmit Mask Bit 16" "0,1"
|
|
bitfld.long 0x00 15. ",Transmit Mask Bit 15" "0,1"
|
|
bitfld.long 0x00 14. ",Transmit Mask Bit 14" "0,1"
|
|
bitfld.long 0x00 13. ",Transmit Mask Bit 13" "0,1"
|
|
bitfld.long 0x00 12. ",Transmit Mask Bit 12" "0,1"
|
|
bitfld.long 0x00 11. ",Transmit Mask Bit 11" "0,1"
|
|
bitfld.long 0x00 10. ",Transmit Mask Bit 10" "0,1"
|
|
bitfld.long 0x00 9. ",Transmit Mask Bit 9" "0,1"
|
|
bitfld.long 0x00 8. ",Transmit Mask Bit 8" "0,1"
|
|
bitfld.long 0x00 7. ",Transmit Mask Bit 7" "0,1"
|
|
bitfld.long 0x00 6. ",Transmit Mask Bit 6" "0,1"
|
|
bitfld.long 0x00 5. ",Transmit Mask Bit 5" "0,1"
|
|
bitfld.long 0x00 4. ",Transmit Mask Bit 4" "0,1"
|
|
bitfld.long 0x00 3. ",Transmit Mask Bit 3" "0,1"
|
|
bitfld.long 0x00 2. ",Transmit Mask Bit 2" "0,1"
|
|
bitfld.long 0x00 1. ",Transmit Mask Bit 1" "0,1"
|
|
bitfld.long 0x00 0. ",Transmit Mask Bit 0" "0,1"
|
|
line.long 0x04 "SRMSK,SSI Receive Time Slot Mask Register"
|
|
bitfld.long 0x04 31. " SRMSK ,Receive Mask Bit 31" "0,1"
|
|
bitfld.long 0x04 30. ",Receive Mask Bit 30" "0,1"
|
|
bitfld.long 0x04 29. ",Receive Mask Bit 29" "0,1"
|
|
bitfld.long 0x04 28. ",Receive Mask Bit 28" "0,1"
|
|
bitfld.long 0x04 27. ",Receive Mask Bit 27" "0,1"
|
|
bitfld.long 0x04 26. ",Receive Mask Bit 26" "0,1"
|
|
bitfld.long 0x04 25. ",Receive Mask Bit 25" "0,1"
|
|
bitfld.long 0x04 24. ",Receive Mask Bit 24" "0,1"
|
|
bitfld.long 0x04 23. ",Receive Mask Bit 23" "0,1"
|
|
bitfld.long 0x04 22. ",Receive Mask Bit 22" "0,1"
|
|
bitfld.long 0x04 21. ",Receive Mask Bit 21" "0,1"
|
|
bitfld.long 0x04 20. ",Receive Mask Bit 20" "0,1"
|
|
bitfld.long 0x04 19. ",Receive Mask Bit 19" "0,1"
|
|
bitfld.long 0x04 18. ",Receive Mask Bit 18" "0,1"
|
|
bitfld.long 0x04 17. ",Receive Mask Bit 17" "0,1"
|
|
bitfld.long 0x04 16. ",Receive Mask Bit 16" "0,1"
|
|
bitfld.long 0x04 15. ",Receive Mask Bit 15" "0,1"
|
|
bitfld.long 0x04 14. ",Receive Mask Bit 14" "0,1"
|
|
bitfld.long 0x04 13. ",Receive Mask Bit 13" "0,1"
|
|
bitfld.long 0x04 12. ",Receive Mask Bit 12" "0,1"
|
|
bitfld.long 0x04 11. ",Receive Mask Bit 11" "0,1"
|
|
bitfld.long 0x04 10. ",Receive Mask Bit 10" "0,1"
|
|
bitfld.long 0x04 9. ",Receive Mask Bit 9" "0,1"
|
|
bitfld.long 0x04 8. ",Receive Mask Bit 8" "0,1"
|
|
bitfld.long 0x04 7. ",Receive Mask Bit 7" "0,1"
|
|
bitfld.long 0x04 6. ",Receive Mask Bit 6" "0,1"
|
|
bitfld.long 0x04 5. ",Receive Mask Bit 5" "0,1"
|
|
bitfld.long 0x04 4. ",Receive Mask Bit 4" "0,1"
|
|
bitfld.long 0x04 3. ",Receive Mask Bit 3" "0,1"
|
|
bitfld.long 0x04 2. ",Receive Mask Bit 2" "0,1"
|
|
bitfld.long 0x04 1. ",Receive Mask Bit 1" "0,1"
|
|
bitfld.long 0x04 0. ",Receive Mask Bit 0" "0,1"
|
|
textline " "
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "SACCST,SSI AC97 Channel Status Register"
|
|
setclrfld.long 0x0 9. 0x4 9. 0x8 9. " SACCST9_set/clr ,AC97 Channel Status 9" "Disabled,Enabled"
|
|
setclrfld.long 0x0 8. 0x4 8. 0x8 8. " SACCST8_set/clr ,AC97 Channel Status 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x4 7. 0x8 7. " SACCST7_set/clr ,AC97 Channel Status 7" "Disabled,Enabled"
|
|
setclrfld.long 0x0 6. 0x4 6. 0x8 6. " SACCST6_set/clr ,AC97 Channel Status 6" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x4 5. 0x8 5. " SACCST5_set/clr ,AC97 Channel Status 5" "Disabled,Enabled"
|
|
setclrfld.long 0x0 4. 0x4 4. 0x8 4. " SACCST4_set/clr ,AC97 Channel Status 4" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x4 3. 0x8 3. " SACCST3_set/clr ,AC97 Channel Status 3" "Disabled,Enabled"
|
|
setclrfld.long 0x0 2. 0x4 2. 0x8 2. " SACCST2_set/clr ,AC97 Channel Status 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x4 1. 0x8 1. " SACCST1_set/clr ,AC97 Channel Status 1" "Disabled,Enabled"
|
|
setclrfld.long 0x0 0. 0x4 0. 0x8 0. " SACCST0_set/clr ,AC97 Channel Status 0" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "TZIC (TrustZone Interrupt Controller)"
|
|
base ad:0xe0000000
|
|
width 12.
|
|
sif cpuis("IMX50*")
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "INTCTRL,Control Register"
|
|
bitfld.long 0x00 0. " EN ,Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "INTCTRL,Control Register"
|
|
bitfld.long 0x00 31. " NSEN_MASK ,Non-Secure Enable Mask" "Not updated,Updated"
|
|
bitfld.long 0x00 16. " NSEN ,Non-Secure Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "INTTYPE,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 10. " DOM ,Domains" "1 domain,2 domains"
|
|
bitfld.long 0x00 5.--7. " CPUS ,CPU Count" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 0.--4. " ITLINES ,Interrupt Lines" "32,64,96,128,160,192,224,256,288,320,352,384,416,448,480,512,544,576,608,640,672,704,736,768,800,832,864,896,928,960,992,1020"
|
|
group.byte 0x0c++0x3
|
|
line.long 0x00 "PRIOMASK,Priority Mask Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MASK ,Priority Mask"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "SYNCCTRL,Synchronizer Control Register"
|
|
bitfld.long 0x00 0.--1. " SYNCMODE ,Synchronizer Mode" "Low Latency,Low Power,?..."
|
|
line.long 0x04 "DSMINT,DSM Interrupt Holdoff Register"
|
|
bitfld.long 0x04 0. " DSM ,DSM Interrupt Holdoff" "Updated,Not updated"
|
|
sif cpuis("IMX50*")
|
|
group.long 0x80++0xf
|
|
line.long 0x00 "INTSEC0,Interrupt Security 0 Register"
|
|
bitfld.long 0x00 31. " SECURE[31] ,Interrupt 31 Status" "Fast,Normal"
|
|
bitfld.long 0x00 30. " SECURE[30] ,Interrupt 30 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SECURE[29] ,Interrupt 29 Status" "Fast,Normal"
|
|
bitfld.long 0x00 28. " SECURE[28] ,Interrupt 28 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SECURE[27] ,Interrupt 27 Status" "Fast,Normal"
|
|
bitfld.long 0x00 26. " SECURE[26] ,Interrupt 26 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SECURE[25] ,Interrupt 25 Status" "Fast,Normal"
|
|
bitfld.long 0x00 24. " SECURE[24] ,Interrupt 24 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SECURE[23] ,Interrupt 23 Status" "Fast,Normal"
|
|
bitfld.long 0x00 22. " SECURE[22] ,Interrupt 22 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE[21] ,Interrupt 21 Status" "Fast,Normal"
|
|
bitfld.long 0x00 20. " SECURE[20] ,Interrupt 20 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SECURE[19] ,Interrupt 19 Status" "Fast,Normal"
|
|
bitfld.long 0x00 18. " SECURE[18] ,Interrupt 18 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SECURE[17] ,Interrupt 17 Status" "Fast,Normal"
|
|
bitfld.long 0x00 16. " SECURE[16] ,Interrupt 16 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SECURE[15] ,Interrupt 15 Status" "Fast,Normal"
|
|
bitfld.long 0x00 14. " SECURE[14] ,Interrupt 14 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SECURE[13] ,Interrupt 13 Status" "Fast,Normal"
|
|
bitfld.long 0x00 12. " SECURE[12] ,Interrupt 12 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SECURE[11] ,Interrupt 11 Status" "Fast,Normal"
|
|
bitfld.long 0x00 10. " SECURE[10] ,Interrupt 10 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE[9] ,Interrupt 9 Status" "Fast,Normal"
|
|
bitfld.long 0x00 8. " SECURE[8] ,Interrupt 8 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECURE[7] ,Interrupt 7 Status" "Fast,Normal"
|
|
bitfld.long 0x00 6. " SECURE[6] ,Interrupt 6 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SECURE[5] ,Interrupt 5 Status" "Fast,Normal"
|
|
bitfld.long 0x00 4. " SECURE[4] ,Interrupt 4 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SECURE[3] ,Interrupt 3 Status" "Fast,Normal"
|
|
bitfld.long 0x00 2. " SECURE[2] ,Interrupt 2 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SECURE[1] ,Interrupt 1 Status" "Fast,Normal"
|
|
bitfld.long 0x00 0. " SECURE[0] ,Interrupt 0 Status" "Fast,Normal"
|
|
line.long 0x04 "INTSEC1,Interrupt Security 1 Register"
|
|
bitfld.long 0x04 31. " SECURE[63] ,Interrupt 63 Status" "Fast,Normal"
|
|
bitfld.long 0x04 30. " SECURE[62] ,Interrupt 62 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SECURE[61] ,Interrupt 61 Status" "Fast,Normal"
|
|
bitfld.long 0x04 28. " SECURE[60] ,Interrupt 60 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 27. " SECURE[59] ,Interrupt 59 Status" "Fast,Normal"
|
|
bitfld.long 0x04 26. " SECURE[58] ,Interrupt 58 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SECURE[57] ,Interrupt 57 Status" "Fast,Normal"
|
|
bitfld.long 0x04 24. " SECURE[56] ,Interrupt 56 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 23. " SECURE[55] ,Interrupt 55 Status" "Fast,Normal"
|
|
bitfld.long 0x04 22. " SECURE[54] ,Interrupt 54 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SECURE[53] ,Interrupt 53 Status" "Fast,Normal"
|
|
bitfld.long 0x04 20. " SECURE[52] ,Interrupt 52 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SECURE[51] ,Interrupt 51 Status" "Fast,Normal"
|
|
bitfld.long 0x04 18. " SECURE[50] ,Interrupt 50 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 17. " SECURE[49] ,Interrupt 49 Status" "Fast,Normal"
|
|
bitfld.long 0x04 16. " SECURE[48] ,Interrupt 48 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SECURE[47] ,Interrupt 47 Status" "Fast,Normal"
|
|
bitfld.long 0x04 14. " SECURE[46] ,Interrupt 46 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SECURE[45] ,Interrupt 45 Status" "Fast,Normal"
|
|
bitfld.long 0x04 12. " SECURE[44] ,Interrupt 44 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SECURE[43] ,Interrupt 43 Status" "Fast,Normal"
|
|
bitfld.long 0x04 10. " SECURE[42] ,Interrupt 42 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SECURE[41] ,Interrupt 41 Status" "Fast,Normal"
|
|
bitfld.long 0x04 8. " SECURE[40] ,Interrupt 40 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SECURE[39] ,Interrupt 39 Status" "Fast,Normal"
|
|
bitfld.long 0x04 6. " SECURE[38] ,Interrupt 38 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SECURE[37] ,Interrupt 37 Status" "Fast,Normal"
|
|
bitfld.long 0x04 4. " SECURE[36] ,Interrupt 36 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SECURE[35] ,Interrupt 35 Status" "Fast,Normal"
|
|
bitfld.long 0x04 2. " SECURE[34] ,Interrupt 34 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SECURE[33] ,Interrupt 33 Status" "Fast,Normal"
|
|
bitfld.long 0x04 0. " SECURE[32] ,Interrupt 32 Status" "Fast,Normal"
|
|
line.long 0x08 "INTSEC2,Interrupt Security 2 Register"
|
|
bitfld.long 0x08 31. " SECURE[95] ,Interrupt 95 Status" "Fast,Normal"
|
|
bitfld.long 0x08 30. " SECURE[94] ,Interrupt 94 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 29. " SECURE[93] ,Interrupt 93 Status" "Fast,Normal"
|
|
bitfld.long 0x08 28. " SECURE[92] ,Interrupt 92 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 27. " SECURE[91] ,Interrupt 91 Status" "Fast,Normal"
|
|
bitfld.long 0x08 26. " SECURE[90] ,Interrupt 90 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SECURE[89] ,Interrupt 89 Status" "Fast,Normal"
|
|
bitfld.long 0x08 24. " SECURE[88] ,Interrupt 88 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 23. " SECURE[87] ,Interrupt 87 Status" "Fast,Normal"
|
|
bitfld.long 0x08 22. " SECURE[86] ,Interrupt 86 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SECURE[85] ,Interrupt 85 Status" "Fast,Normal"
|
|
bitfld.long 0x08 20. " SECURE[84] ,Interrupt 84 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SECURE[83] ,Interrupt 83 Status" "Fast,Normal"
|
|
bitfld.long 0x08 18. " SECURE[82] ,Interrupt 82 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 17. " SECURE[81] ,Interrupt 81 Status" "Fast,Normal"
|
|
bitfld.long 0x08 16. " SECURE[80] ,Interrupt 80 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 15. " SECURE[79] ,Interrupt 79 Status" "Fast,Normal"
|
|
bitfld.long 0x08 14. " SECURE[78] ,Interrupt 78 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SECURE[77] ,Interrupt 77 Status" "Fast,Normal"
|
|
bitfld.long 0x08 12. " SECURE[76] ,Interrupt 76 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SECURE[75] ,Interrupt 75 Status" "Fast,Normal"
|
|
bitfld.long 0x08 10. " SECURE[74] ,Interrupt 74 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SECURE[73] ,Interrupt 73 Status" "Fast,Normal"
|
|
bitfld.long 0x08 8. " SECURE[72] ,Interrupt 72 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SECURE[71] ,Interrupt 71 Status" "Fast,Normal"
|
|
bitfld.long 0x08 6. " SECURE[70] ,Interrupt 70 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SECURE[69] ,Interrupt 69 Status" "Fast,Normal"
|
|
bitfld.long 0x08 4. " SECURE[68] ,Interrupt 68 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SECURE[67] ,Interrupt 67 Status" "Fast,Normal"
|
|
bitfld.long 0x08 2. " SECURE[66] ,Interrupt 66 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SECURE[65] ,Interrupt 65 Status" "Fast,Normal"
|
|
bitfld.long 0x08 0. " SECURE[64] ,Interrupt 64 Status" "Fast,Normal"
|
|
line.long 0x0c "INTSEC3,Interrupt Security 3 Register"
|
|
bitfld.long 0x0c 31. " SECURE[127] ,Interrupt 127 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 30. " SECURE[126] ,Interrupt 126 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " SECURE[125] ,Interrupt 125 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 28. " SECURE[124] ,Interrupt 124 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " SECURE[123] ,Interrupt 123 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 26. " SECURE[122] ,Interrupt 122 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " SECURE[121] ,Interrupt 121 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 24. " SECURE[120] ,Interrupt 120 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " SECURE[119] ,Interrupt 119 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 22. " SECURE[118] ,Interrupt 118 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " SECURE[117] ,Interrupt 117 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 20. " SECURE[116] ,Interrupt 116 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " SECURE[115] ,Interrupt 115 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 18. " SECURE[114] ,Interrupt 114 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " SECURE[113] ,Interrupt 113 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 16. " SECURE[112] ,Interrupt 112 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " SECURE[111] ,Interrupt 111 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 14. " SECURE[110] ,Interrupt 110 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " SECURE[109] ,Interrupt 109 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 12. " SECURE[108] ,Interrupt 108 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " SECURE[107] ,Interrupt 107 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 10. " SECURE[106] ,Interrupt 106 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " SECURE[105] ,Interrupt 105 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 8. " SECURE[104] ,Interrupt 104 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " SECURE[103] ,Interrupt 103 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 6. " SECURE[102] ,Interrupt 102 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " SECURE[101] ,Interrupt 101 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 4. " SECURE[100] ,Interrupt 100 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " SECURE[99] ,Interrupt 99 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 2. " SECURE[98] ,Interrupt 98 Status" "Fast,Normal"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " SECURE[97] ,Interrupt 97 Status" "Fast,Normal"
|
|
bitfld.long 0x0c 0. " SECURE[96] ,Interrupt 96 Status" "Fast,Normal"
|
|
else
|
|
group.long 0x80++0xf
|
|
line.long 0x00 "INTSEC0,Interrupt Security 0 Register"
|
|
bitfld.long 0x00 31. " SECURE[31] ,Interrupt Secure 31 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 30. " SECURE[30] ,Interrupt Secure 30 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SECURE[29] ,Interrupt Secure 29 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 28. " SECURE[28] ,Interrupt Secure 28 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SECURE[27] ,Interrupt Secure 27 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 26. " SECURE[26] ,Interrupt Secure 26 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SECURE[25] ,Interrupt Secure 25 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 24. " SECURE[24] ,Interrupt Secure 24 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SECURE[23] ,Interrupt Secure 23 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 22. " SECURE[22] ,Interrupt Secure 22 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE[21] ,Interrupt Secure 21 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 20. " SECURE[20] ,Interrupt Secure 20 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SECURE[19] ,Interrupt Secure 19 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 18. " SECURE[18] ,Interrupt Secure 18 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SECURE[17] ,Interrupt Secure 17 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 16. " SECURE[16] ,Interrupt Secure 16 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SECURE[15] ,Interrupt Secure 15 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 14. " SECURE[14] ,Interrupt Secure 14 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SECURE[13] ,Interrupt Secure 13 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 12. " SECURE[12] ,Interrupt Secure 12 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SECURE[11] ,Interrupt Secure 11 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 10. " SECURE[10] ,Interrupt Secure 10 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE[9] ,Interrupt Secure 9 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 8. " SECURE[8] ,Interrupt Secure 8 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SECURE[7] ,Interrupt Secure 7 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 6. " SECURE[6] ,Interrupt Secure 6 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SECURE[5] ,Interrupt Secure 5 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 4. " SECURE[4] ,Interrupt Secure 4 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SECURE[3] ,Interrupt Secure 3 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 2. " SECURE[2] ,Interrupt Secure 2 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SECURE[1] ,Interrupt Secure 1 Status" "Secured,Not secured"
|
|
bitfld.long 0x00 0. " SECURE[0] ,Interrupt Secure 0 Status" "Secured,Not secured"
|
|
line.long 0x04 "INTSEC1,Interrupt Security 1 Register"
|
|
bitfld.long 0x04 31. " SECURE[63] ,Interrupt Secure 63 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 30. " SECURE[62] ,Interrupt Secure 62 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SECURE[61] ,Interrupt Secure 61 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 28. " SECURE[60] ,Interrupt Secure 60 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 27. " SECURE[59] ,Interrupt Secure 59 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 26. " SECURE[58] ,Interrupt Secure 58 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SECURE[57] ,Interrupt Secure 57 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 24. " SECURE[56] ,Interrupt Secure 56 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 23. " SECURE[55] ,Interrupt Secure 55 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 22. " SECURE[54] ,Interrupt Secure 54 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SECURE[53] ,Interrupt Secure 53 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 20. " SECURE[52] ,Interrupt Secure 52 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SECURE[51] ,Interrupt Secure 51 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 18. " SECURE[50] ,Interrupt Secure 50 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 17. " SECURE[49] ,Interrupt Secure 49 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 16. " SECURE[48] ,Interrupt Secure 48 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SECURE[47] ,Interrupt Secure 47 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 14. " SECURE[46] ,Interrupt Secure 46 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SECURE[45] ,Interrupt Secure 45 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 12. " SECURE[44] ,Interrupt Secure 44 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SECURE[43] ,Interrupt Secure 43 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 10. " SECURE[42] ,Interrupt Secure 42 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SECURE[41] ,Interrupt Secure 41 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 8. " SECURE[40] ,Interrupt Secure 40 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SECURE[39] ,Interrupt Secure 39 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 6. " SECURE[38] ,Interrupt Secure 38 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SECURE[37] ,Interrupt Secure 37 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 4. " SECURE[36] ,Interrupt Secure 36 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SECURE[35] ,Interrupt Secure 35 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 2. " SECURE[34] ,Interrupt Secure 34 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SECURE[33] ,Interrupt Secure 33 Status" "Secured,Not secured"
|
|
bitfld.long 0x04 0. " SECURE[32] ,Interrupt Secure 32 Status" "Secured,Not secured"
|
|
line.long 0x08 "INTSEC2,Interrupt Security 2 Register"
|
|
bitfld.long 0x08 31. " SECURE[95] ,Interrupt Secure 95 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 30. " SECURE[94] ,Interrupt Secure 94 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 29. " SECURE[93] ,Interrupt Secure 93 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 28. " SECURE[92] ,Interrupt Secure 92 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 27. " SECURE[91] ,Interrupt Secure 91 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 26. " SECURE[90] ,Interrupt Secure 90 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SECURE[89] ,Interrupt Secure 89 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 24. " SECURE[88] ,Interrupt Secure 88 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 23. " SECURE[87] ,Interrupt Secure 87 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 22. " SECURE[86] ,Interrupt Secure 86 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SECURE[85] ,Interrupt Secure 85 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 20. " SECURE[84] ,Interrupt Secure 84 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SECURE[83] ,Interrupt Secure 83 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 18. " SECURE[82] ,Interrupt Secure 82 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 17. " SECURE[81] ,Interrupt Secure 81 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 16. " SECURE[80] ,Interrupt Secure 80 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 15. " SECURE[79] ,Interrupt Secure 79 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 14. " SECURE[78] ,Interrupt Secure 78 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SECURE[77] ,Interrupt Secure 77 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 12. " SECURE[76] ,Interrupt Secure 76 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SECURE[75] ,Interrupt Secure 75 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 10. " SECURE[74] ,Interrupt Secure 74 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SECURE[73] ,Interrupt Secure 73 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 8. " SECURE[72] ,Interrupt Secure 72 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SECURE[71] ,Interrupt Secure 71 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 6. " SECURE[70] ,Interrupt Secure 70 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SECURE[69] ,Interrupt Secure 69 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 4. " SECURE[68] ,Interrupt Secure 68 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SECURE[67] ,Interrupt Secure 67 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 2. " SECURE[66] ,Interrupt Secure 66 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SECURE[65] ,Interrupt Secure 65 Status" "Secured,Not secured"
|
|
bitfld.long 0x08 0. " SECURE[64] ,Interrupt Secure 64 Status" "Secured,Not secured"
|
|
line.long 0x0c "INTSEC3,Interrupt Security 3 Register"
|
|
bitfld.long 0x0c 31. " SECURE[127] ,Interrupt Secure 127 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 30. " SECURE[126] ,Interrupt Secure 126 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " SECURE[125] ,Interrupt Secure 125 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 28. " SECURE[124] ,Interrupt Secure 124 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " SECURE[123] ,Interrupt Secure 123 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 26. " SECURE[122] ,Interrupt Secure 122 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " SECURE[121] ,Interrupt Secure 121 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 24. " SECURE[120] ,Interrupt Secure 120 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " SECURE[119] ,Interrupt Secure 119 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 22. " SECURE[118] ,Interrupt Secure 118 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " SECURE[117] ,Interrupt Secure 117 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 20. " SECURE[116] ,Interrupt Secure 116 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " SECURE[115] ,Interrupt Secure 115 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 18. " SECURE[114] ,Interrupt Secure 114 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " SECURE[113] ,Interrupt Secure 113 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 16. " SECURE[112] ,Interrupt Secure 112 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " SECURE[111] ,Interrupt Secure 111 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 14. " SECURE[110] ,Interrupt Secure 110 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " SECURE[109] ,Interrupt Secure 109 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 12. " SECURE[108] ,Interrupt Secure 108 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " SECURE[107] ,Interrupt Secure 107 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 10. " SECURE[106] ,Interrupt Secure 106 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " SECURE[105] ,Interrupt Secure 105 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 8. " SECURE[104] ,Interrupt Secure 104 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " SECURE[103] ,Interrupt Secure 103 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 6. " SECURE[102] ,Interrupt Secure 102 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " SECURE[101] ,Interrupt Secure 101 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 4. " SECURE[100] ,Interrupt Secure 100 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " SECURE[99] ,Interrupt Secure 99 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 2. " SECURE[98] ,Interrupt Secure 98 Status" "Secured,Not secured"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " SECURE[97] ,Interrupt Secure 97 Status" "Secured,Not secured"
|
|
bitfld.long 0x0c 0. " SECURE[96] ,Interrupt Secure 96 Status" "Secured,Not secured"
|
|
endif
|
|
group.long 0x100++0xf
|
|
line.long 0x00 "ENSET0,Enable Set 0 Register"
|
|
bitfld.long 0x00 31. " INTENSET[31] ,Interrupt Enable Set 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INTENSET[30] ,Interrupt Enable Set 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTENSET[29] ,Interrupt Enable Set 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INTENSET[28] ,Interrupt Enable Set 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTENSET[27] ,Interrupt Enable Set 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " INTENSET[26] ,Interrupt Enable Set 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTENSET[25] ,Interrupt Enable Set 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " INTENSET[24] ,Interrupt Enable Set 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTENSET[23] ,Interrupt Enable Set 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " INTENSET[22] ,Interrupt Enable Set 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTENSET[21] ,Interrupt Enable Set 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INTENSET[20] ,Interrupt Enable Set 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTENSET[19] ,Interrupt Enable Set 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " INTENSET[18] ,Interrupt Enable Set 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTENSET[17] ,Interrupt Enable Set 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " INTENSET[16] ,Interrupt Enable Set 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTENSET[15] ,Interrupt Enable Set 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTENSET[14] ,Interrupt Enable Set 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTENSET[13] ,Interrupt Enable Set 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTENSET[12] ,Interrupt Enable Set 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTENSET[11] ,Interrupt Enable Set 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " INTENSET[10] ,Interrupt Enable Set 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTENSET[9] ,Interrupt Enable Set 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " INTENSET[8] ,Interrupt Enable Set 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTENSET[7] ,Interrupt Enable Set 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INTENSET[6] ,Interrupt Enable Set 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTENSET[5] ,Interrupt Enable Set 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INTENSET[4] ,Interrupt Enable Set 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTENSET[3] ,Interrupt Enable Set 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " INTENSET[2] ,Interrupt Enable Set 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTENSET[1] ,Interrupt Enable Set 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INTENSET[0] ,Interrupt Enable Set 0" "Disabled,Enabled"
|
|
line.long 0x04 "ENSET1,Enable Set 1 Register"
|
|
bitfld.long 0x04 31. " INTENSET[63] ,Interrupt Enable Set 63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " INTENSET[62] ,Interrupt Enable Set 62" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTENSET[61] ,Interrupt Enable Set 61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " INTENSET[60] ,Interrupt Enable Set 60" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTENSET[59] ,Interrupt Enable Set 59" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " INTENSET[58] ,Interrupt Enable Set 58" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTENSET[57] ,Interrupt Enable Set 57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " INTENSET[56] ,Interrupt Enable Set 56" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTENSET[55] ,Interrupt Enable Set 55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " INTENSET[54] ,Interrupt Enable Set 54" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTENSET[53] ,Interrupt Enable Set 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " INTENSET[52] ,Interrupt Enable Set 52" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTENSET[51] ,Interrupt Enable Set 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " INTENSET[50] ,Interrupt Enable Set 50" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTENSET[49] ,Interrupt Enable Set 49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " INTENSET[48] ,Interrupt Enable Set 48" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTENSET[47] ,Interrupt Enable Set 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " INTENSET[46] ,Interrupt Enable Set 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTENSET[45] ,Interrupt Enable Set 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " INTENSET[44] ,Interrupt Enable Set 44" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTENSET[43] ,Interrupt Enable Set 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " INTENSET[42] ,Interrupt Enable Set 42" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTENSET[41] ,Interrupt Enable Set 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " INTENSET[40] ,Interrupt Enable Set 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTENSET[39] ,Interrupt Enable Set 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " INTENSET[38] ,Interrupt Enable Set 38" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTENSET[37] ,Interrupt Enable Set 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " INTENSET[36] ,Interrupt Enable Set 36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTENSET[35] ,Interrupt Enable Set 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INTENSET[34] ,Interrupt Enable Set 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTENSET[33] ,Interrupt Enable Set 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INTENSET[32] ,Interrupt Enable Set 32" "Disabled,Enabled"
|
|
line.long 0x08 "ENSET2,Enable Set 2 Register"
|
|
bitfld.long 0x08 31. " INTENSET[95] ,Interrupt Enable Set 95" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " INTENSET[94] ,Interrupt Enable Set 94" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " INTENSET[93] ,Interrupt Enable Set 93" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " INTENSET[92] ,Interrupt Enable Set 92" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " INTENSET[91] ,Interrupt Enable Set 91" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " INTENSET[90] ,Interrupt Enable Set 90" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " INTENSET[89] ,Interrupt Enable Set 89" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " INTENSET[88] ,Interrupt Enable Set 88" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " INTENSET[87] ,Interrupt Enable Set 87" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " INTENSET[86] ,Interrupt Enable Set 86" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " INTENSET[85] ,Interrupt Enable Set 85" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " INTENSET[84] ,Interrupt Enable Set 84" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " INTENSET[83] ,Interrupt Enable Set 83" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " INTENSET[82] ,Interrupt Enable Set 82" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " INTENSET[81] ,Interrupt Enable Set 81" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " INTENSET[80] ,Interrupt Enable Set 80" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " INTENSET[79] ,Interrupt Enable Set 79" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " INTENSET[78] ,Interrupt Enable Set 78" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " INTENSET[77] ,Interrupt Enable Set 77" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " INTENSET[76] ,Interrupt Enable Set 76" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " INTENSET[75] ,Interrupt Enable Set 75" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " INTENSET[74] ,Interrupt Enable Set 74" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " INTENSET[73] ,Interrupt Enable Set 73" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " INTENSET[72] ,Interrupt Enable Set 72" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " INTENSET[71] ,Interrupt Enable Set 71" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " INTENSET[70] ,Interrupt Enable Set 70" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " INTENSET[69] ,Interrupt Enable Set 69" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " INTENSET[68] ,Interrupt Enable Set 68" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " INTENSET[67] ,Interrupt Enable Set 67" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " INTENSET[66] ,Interrupt Enable Set 66" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " INTENSET[65] ,Interrupt Enable Set 65" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INTENSET[64] ,Interrupt Enable Set 64" "Disabled,Enabled"
|
|
line.long 0x0c "ENSET3,Enable Set 3 Register"
|
|
bitfld.long 0x0c 31. " INTENSET[127] ,Interrupt Enable Set 127" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " INTENSET[126] ,Interrupt Enable Set 126" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " INTENSET[125] ,Interrupt Enable Set 125" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " INTENSET[124] ,Interrupt Enable Set 124" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " INTENSET[123] ,Interrupt Enable Set 123" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " INTENSET[122] ,Interrupt Enable Set 122" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " INTENSET[121] ,Interrupt Enable Set 121" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " INTENSET[120] ,Interrupt Enable Set 120" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " INTENSET[119] ,Interrupt Enable Set 119" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " INTENSET[118] ,Interrupt Enable Set 118" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " INTENSET[117] ,Interrupt Enable Set 117" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " INTENSET[116] ,Interrupt Enable Set 116" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " INTENSET[115] ,Interrupt Enable Set 115" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " INTENSET[114] ,Interrupt Enable Set 114" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " INTENSET[113] ,Interrupt Enable Set 113" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " INTENSET[112] ,Interrupt Enable Set 112" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " INTENSET[111] ,Interrupt Enable Set 111" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " INTENSET[110] ,Interrupt Enable Set 110" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " INTENSET[109] ,Interrupt Enable Set 109" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " INTENSET[108] ,Interrupt Enable Set 108" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " INTENSET[107] ,Interrupt Enable Set 107" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " INTENSET[106] ,Interrupt Enable Set 106" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " INTENSET[105] ,Interrupt Enable Set 105" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " INTENSET[104] ,Interrupt Enable Set 104" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " INTENSET[103] ,Interrupt Enable Set 103" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " INTENSET[102] ,Interrupt Enable Set 102" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " INTENSET[101] ,Interrupt Enable Set 101" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " INTENSET[100] ,Interrupt Enable Set 100" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " INTENSET[99] ,Interrupt Enable Set 99" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " INTENSET[98] ,Interrupt Enable Set 98" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " INTENSET[97] ,Interrupt Enable Set 97" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " INTENSET[96] ,Interrupt Enable Set 96" "Disabled,Enabled"
|
|
group.long 0x180++0xf
|
|
line.long 0x00 "ENCLEAR0,Enable Clear 0 Register"
|
|
bitfld.long 0x00 31. " INTENCLEAR[31] ,Interrupt Enable Clear 31" "No effect,Cleared"
|
|
bitfld.long 0x00 30. " INTENCLEAR[30] ,Interrupt Enable Clear 30" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTENCLEAR[29] ,Interrupt Enable Clear 29" "No effect,Cleared"
|
|
bitfld.long 0x00 28. " INTENCLEAR[28] ,Interrupt Enable Clear 28" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTENCLEAR[27] ,Interrupt Enable Clear 27" "No effect,Cleared"
|
|
bitfld.long 0x00 26. " INTENCLEAR[26] ,Interrupt Enable Clear 26" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTENCLEAR[25] ,Interrupt Enable Clear 25" "No effect,Cleared"
|
|
bitfld.long 0x00 24. " INTENCLEAR[24] ,Interrupt Enable Clear 24" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTENCLEAR[23] ,Interrupt Enable Clear 23" "No effect,Cleared"
|
|
bitfld.long 0x00 22. " INTENCLEAR[22] ,Interrupt Enable Clear 22" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTENCLEAR[21] ,Interrupt Enable Clear 21" "No effect,Cleared"
|
|
bitfld.long 0x00 20. " INTENCLEAR[20] ,Interrupt Enable Clear 20" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTENCLEAR[19] ,Interrupt Enable Clear 19" "No effect,Cleared"
|
|
bitfld.long 0x00 18. " INTENCLEAR[18] ,Interrupt Enable Clear 18" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTENCLEAR[17] ,Interrupt Enable Clear 17" "No effect,Cleared"
|
|
bitfld.long 0x00 16. " INTENCLEAR[16] ,Interrupt Enable Clear 16" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTENCLEAR[15] ,Interrupt Enable Clear 15" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " INTENCLEAR[14] ,Interrupt Enable Clear 14" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTENCLEAR[13] ,Interrupt Enable Clear 13" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " INTENCLEAR[12] ,Interrupt Enable Clear 12" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTENCLEAR[11] ,Interrupt Enable Clear 11" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " INTENCLEAR[10] ,Interrupt Enable Clear 10" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTENCLEAR[9] ,Interrupt Enable Clear 9" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " INTENCLEAR[8] ,Interrupt Enable Clear 8" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTENCLEAR[7] ,Interrupt Enable Clear 7" "No effect,Cleared"
|
|
bitfld.long 0x00 6. " INTENCLEAR[6] ,Interrupt Enable Clear 6" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTENCLEAR[5] ,Interrupt Enable Clear 5" "No effect,Cleared"
|
|
bitfld.long 0x00 4. " INTENCLEAR[4] ,Interrupt Enable Clear 4" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTENCLEAR[3] ,Interrupt Enable Clear 3" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " INTENCLEAR[2] ,Interrupt Enable Clear 2" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTENCLEAR[1] ,Interrupt Enable Clear 1" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " INTENCLEAR[0] ,Interrupt Enable Clear 0" "No effect,Cleared"
|
|
line.long 0x04 "ENCLEAR1,Enable Clear 1 Register"
|
|
bitfld.long 0x04 31. " INTENCLEAR[63] ,Interrupt Enable Clear 63" "No effect,Cleared"
|
|
bitfld.long 0x04 30. " INTENCLEAR[62] ,Interrupt Enable Clear 62" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTENCLEAR[61] ,Interrupt Enable Clear 61" "No effect,Cleared"
|
|
bitfld.long 0x04 28. " INTENCLEAR[60] ,Interrupt Enable Clear 60" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTENCLEAR[59] ,Interrupt Enable Clear 59" "No effect,Cleared"
|
|
bitfld.long 0x04 26. " INTENCLEAR[58] ,Interrupt Enable Clear 58" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTENCLEAR[57] ,Interrupt Enable Clear 57" "No effect,Cleared"
|
|
bitfld.long 0x04 24. " INTENCLEAR[56] ,Interrupt Enable Clear 56" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTENCLEAR[55] ,Interrupt Enable Clear 55" "No effect,Cleared"
|
|
bitfld.long 0x04 22. " INTENCLEAR[54] ,Interrupt Enable Clear 54" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTENCLEAR[53] ,Interrupt Enable Clear 53" "No effect,Cleared"
|
|
bitfld.long 0x04 20. " INTENCLEAR[52] ,Interrupt Enable Clear 52" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTENCLEAR[51] ,Interrupt Enable Clear 51" "No effect,Cleared"
|
|
bitfld.long 0x04 18. " INTENCLEAR[50] ,Interrupt Enable Clear 50" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTENCLEAR[49] ,Interrupt Enable Clear 49" "No effect,Cleared"
|
|
bitfld.long 0x04 16. " INTENCLEAR[48] ,Interrupt Enable Clear 48" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTENCLEAR[47] ,Interrupt Enable Clear 47" "No effect,Cleared"
|
|
bitfld.long 0x04 14. " INTENCLEAR[46] ,Interrupt Enable Clear 46" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTENCLEAR[45] ,Interrupt Enable Clear 45" "No effect,Cleared"
|
|
bitfld.long 0x04 12. " INTENCLEAR[44] ,Interrupt Enable Clear 44" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTENCLEAR[43] ,Interrupt Enable Clear 43" "No effect,Cleared"
|
|
bitfld.long 0x04 10. " INTENCLEAR[42] ,Interrupt Enable Clear 42" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTENCLEAR[41] ,Interrupt Enable Clear 41" "No effect,Cleared"
|
|
bitfld.long 0x04 8. " INTENCLEAR[40] ,Interrupt Enable Clear 40" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTENCLEAR[39] ,Interrupt Enable Clear 39" "No effect,Cleared"
|
|
bitfld.long 0x04 6. " INTENCLEAR[38] ,Interrupt Enable Clear 38" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTENCLEAR[37] ,Interrupt Enable Clear 37" "No effect,Cleared"
|
|
bitfld.long 0x04 4. " INTENCLEAR[36] ,Interrupt Enable Clear 36" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTENCLEAR[35] ,Interrupt Enable Clear 35" "No effect,Cleared"
|
|
bitfld.long 0x04 2. " INTENCLEAR[34] ,Interrupt Enable Clear 34" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTENCLEAR[33] ,Interrupt Enable Clear 33" "No effect,Cleared"
|
|
bitfld.long 0x04 0. " INTENCLEAR[32] ,Interrupt Enable Clear 32" "No effect,Cleared"
|
|
line.long 0x08 "ENCLEAR2,Enable Clear 2 Register"
|
|
bitfld.long 0x08 31. " INTENCLEAR[95] ,Interrupt Enable Clear 95" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " INTENCLEAR[94] ,Interrupt Enable Clear 94" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " INTENCLEAR[93] ,Interrupt Enable Clear 93" "No effect,Cleared"
|
|
bitfld.long 0x08 28. " INTENCLEAR[92] ,Interrupt Enable Clear 92" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " INTENCLEAR[91] ,Interrupt Enable Clear 91" "No effect,Cleared"
|
|
bitfld.long 0x08 26. " INTENCLEAR[90] ,Interrupt Enable Clear 90" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " INTENCLEAR[89] ,Interrupt Enable Clear 89" "No effect,Cleared"
|
|
bitfld.long 0x08 24. " INTENCLEAR[88] ,Interrupt Enable Clear 88" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " INTENCLEAR[87] ,Interrupt Enable Clear 87" "No effect,Cleared"
|
|
bitfld.long 0x08 22. " INTENCLEAR[86] ,Interrupt Enable Clear 86" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " INTENCLEAR[85] ,Interrupt Enable Clear 85" "No effect,Cleared"
|
|
bitfld.long 0x08 20. " INTENCLEAR[84] ,Interrupt Enable Clear 84" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " INTENCLEAR[83] ,Interrupt Enable Clear 83" "No effect,Cleared"
|
|
bitfld.long 0x08 18. " INTENCLEAR[82] ,Interrupt Enable Clear 82" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " INTENCLEAR[81] ,Interrupt Enable Clear 81" "No effect,Cleared"
|
|
bitfld.long 0x08 16. " INTENCLEAR[80] ,Interrupt Enable Clear 80" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " INTENCLEAR[79] ,Interrupt Enable Clear 79" "No effect,Cleared"
|
|
bitfld.long 0x08 14. " INTENCLEAR[78] ,Interrupt Enable Clear 78" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " INTENCLEAR[77] ,Interrupt Enable Clear 77" "No effect,Cleared"
|
|
bitfld.long 0x08 12. " INTENCLEAR[76] ,Interrupt Enable Clear 76" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " INTENCLEAR[75] ,Interrupt Enable Clear 75" "No effect,Cleared"
|
|
bitfld.long 0x08 10. " INTENCLEAR[74] ,Interrupt Enable Clear 74" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " INTENCLEAR[73] ,Interrupt Enable Clear 73" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " INTENCLEAR[72] ,Interrupt Enable Clear 72" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " INTENCLEAR[71] ,Interrupt Enable Clear 71" "No effect,Cleared"
|
|
bitfld.long 0x08 6. " INTENCLEAR[70] ,Interrupt Enable Clear 70" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " INTENCLEAR[69] ,Interrupt Enable Clear 69" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " INTENCLEAR[68] ,Interrupt Enable Clear 68" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " INTENCLEAR[67] ,Interrupt Enable Clear 67" "No effect,Cleared"
|
|
bitfld.long 0x08 2. " INTENCLEAR[66] ,Interrupt Enable Clear 66" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " INTENCLEAR[65] ,Interrupt Enable Clear 65" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " INTENCLEAR[64] ,Interrupt Enable Clear 64" "No effect,Cleared"
|
|
line.long 0x0c "ENCLEAR3,Enable Clear 3 Register"
|
|
bitfld.long 0x0c 31. " INTENCLEAR[127] ,Interrupt Enable Clear 127" "No effect,Cleared"
|
|
bitfld.long 0x0c 30. " INTENCLEAR[126] ,Interrupt Enable Clear 126" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " INTENCLEAR[125] ,Interrupt Enable Clear 125" "No effect,Cleared"
|
|
bitfld.long 0x0c 28. " INTENCLEAR[124] ,Interrupt Enable Clear 124" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " INTENCLEAR[123] ,Interrupt Enable Clear 123" "No effect,Cleared"
|
|
bitfld.long 0x0c 26. " INTENCLEAR[122] ,Interrupt Enable Clear 122" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " INTENCLEAR[121] ,Interrupt Enable Clear 121" "No effect,Cleared"
|
|
bitfld.long 0x0c 24. " INTENCLEAR[120] ,Interrupt Enable Clear 120" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " INTENCLEAR[119] ,Interrupt Enable Clear 119" "No effect,Cleared"
|
|
bitfld.long 0x0c 22. " INTENCLEAR[118] ,Interrupt Enable Clear 118" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " INTENCLEAR[117] ,Interrupt Enable Clear 117" "No effect,Cleared"
|
|
bitfld.long 0x0c 20. " INTENCLEAR[116] ,Interrupt Enable Clear 116" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " INTENCLEAR[115] ,Interrupt Enable Clear 115" "No effect,Cleared"
|
|
bitfld.long 0x0c 18. " INTENCLEAR[114] ,Interrupt Enable Clear 114" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " INTENCLEAR[113] ,Interrupt Enable Clear 113" "No effect,Cleared"
|
|
bitfld.long 0x0c 16. " INTENCLEAR[112] ,Interrupt Enable Clear 112" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " INTENCLEAR[111] ,Interrupt Enable Clear 111" "No effect,Cleared"
|
|
bitfld.long 0x0c 14. " INTENCLEAR[110] ,Interrupt Enable Clear 110" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " INTENCLEAR[109] ,Interrupt Enable Clear 109" "No effect,Cleared"
|
|
bitfld.long 0x0c 12. " INTENCLEAR[108] ,Interrupt Enable Clear 108" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " INTENCLEAR[107] ,Interrupt Enable Clear 107" "No effect,Cleared"
|
|
bitfld.long 0x0c 10. " INTENCLEAR[106] ,Interrupt Enable Clear 106" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " INTENCLEAR[105] ,Interrupt Enable Clear 105" "No effect,Cleared"
|
|
bitfld.long 0x0c 8. " INTENCLEAR[104] ,Interrupt Enable Clear 104" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " INTENCLEAR[103] ,Interrupt Enable Clear 103" "No effect,Cleared"
|
|
bitfld.long 0x0c 6. " INTENCLEAR[102] ,Interrupt Enable Clear 102" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " INTENCLEAR[101] ,Interrupt Enable Clear 101" "No effect,Cleared"
|
|
bitfld.long 0x0c 4. " INTENCLEAR[100] ,Interrupt Enable Clear 100" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " INTENCLEAR[99] ,Interrupt Enable Clear 99" "No effect,Cleared"
|
|
bitfld.long 0x0c 2. " INTENCLEAR[98] ,Interrupt Enable Clear 98" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " INTENCLEAR[97] ,Interrupt Enable Clear 97" "No effect,Cleared"
|
|
bitfld.long 0x0c 0. " INTENCLEAR[96] ,Interrupt Enable Clear 96" "No effect,Cleared"
|
|
group.long 0x200++0xf
|
|
line.long 0x00 "SRCSET0,Source Set 0 Register"
|
|
bitfld.long 0x00 31. " SRCSET[31] ,Interrupt Source Set 31" "No effect,Set"
|
|
bitfld.long 0x00 30. " SRCSET[30] ,Interrupt Source Set 30" "No effect,Set"
|
|
bitfld.long 0x00 29. " SRCSET[29] ,Interrupt Source Set 29" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SRCSET[28] ,Interrupt Source Set 28" "No effect,Set"
|
|
bitfld.long 0x00 27. " SRCSET[27] ,Interrupt Source Set 27" "No effect,Set"
|
|
bitfld.long 0x00 26. " SRCSET[26] ,Interrupt Source Set 26" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SRCSET[25] ,Interrupt Source Set 25" "No effect,Set"
|
|
bitfld.long 0x00 24. " SRCSET[24] ,Interrupt Source Set 24" "No effect,Set"
|
|
bitfld.long 0x00 23. " SRCSET[23] ,Interrupt Source Set 23" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SRCSET[22] ,Interrupt Source Set 22" "No effect,Set"
|
|
bitfld.long 0x00 21. " SRCSET[21] ,Interrupt Source Set 21" "No effect,Set"
|
|
bitfld.long 0x00 20. " SRCSET[20] ,Interrupt Source Set 20" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SRCSET[19] ,Interrupt Source Set 19" "No effect,Set"
|
|
bitfld.long 0x00 18. " SRCSET[18] ,Interrupt Source Set 18" "No effect,Set"
|
|
bitfld.long 0x00 17. " SRCSET[17] ,Interrupt Source Set 17" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SRCSET[16] ,Interrupt Source Set 16" "No effect,Set"
|
|
bitfld.long 0x00 15. " SRCSET[15] ,Interrupt Source Set 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " SRCSET[14] ,Interrupt Source Set 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SRCSET[13] ,Interrupt Source Set 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " SRCSET[12] ,Interrupt Source Set 12" "No effect,Set"
|
|
bitfld.long 0x00 11. " SRCSET[11] ,Interrupt Source Set 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SRCSET[10] ,Interrupt Source Set 10" "No effect,Set"
|
|
bitfld.long 0x00 9. " SRCSET[9] ,Interrupt Source Set 9" "No effect,Set"
|
|
bitfld.long 0x00 8. " SRCSET[8] ,Interrupt Source Set 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SRCSET[7] ,Interrupt Source Set 7" "No effect,Set"
|
|
bitfld.long 0x00 6. " SRCSET[6] ,Interrupt Source Set 6" "No effect,Set"
|
|
bitfld.long 0x00 5. " SRCSET[5] ,Interrupt Source Set 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SRCSET[4] ,Interrupt Source Set 4" "No effect,Set"
|
|
bitfld.long 0x00 3. " SRCSET[3] ,Interrupt Source Set 3" "No effect,Set"
|
|
bitfld.long 0x00 2. " SRCSET[2] ,Interrupt Source Set 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCSET[1] ,Interrupt Source Set 1" "No effect,Set"
|
|
bitfld.long 0x00 0. " SRCSET[0] ,Interrupt Source Set 0" "No effect,Set"
|
|
line.long 0x04 "SRCSET1,Source Set 1 Register"
|
|
bitfld.long 0x04 31. " SRCSET[63] ,Interrupt Source Set 63" "No effect,Set"
|
|
bitfld.long 0x04 30. " SRCSET[62] ,Interrupt Source Set 62" "No effect,Set"
|
|
bitfld.long 0x04 29. " SRCSET[61] ,Interrupt Source Set 61" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 28. " SRCSET[60] ,Interrupt Source Set 60" "No effect,Set"
|
|
bitfld.long 0x04 27. " SRCSET[59] ,Interrupt Source Set 59" "No effect,Set"
|
|
bitfld.long 0x04 26. " SRCSET[58] ,Interrupt Source Set 58" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SRCSET[57] ,Interrupt Source Set 57" "No effect,Set"
|
|
bitfld.long 0x04 24. " SRCSET[56] ,Interrupt Source Set 56" "No effect,Set"
|
|
bitfld.long 0x04 23. " SRCSET[55] ,Interrupt Source Set 55" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SRCSET[54] ,Interrupt Source Set 54" "No effect,Set"
|
|
bitfld.long 0x04 21. " SRCSET[53] ,Interrupt Source Set 53" "No effect,Set"
|
|
bitfld.long 0x04 20. " SRCSET[52] ,Interrupt Source Set 52" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SRCSET[51] ,Interrupt Source Set 51" "No effect,Set"
|
|
bitfld.long 0x04 18. " SRCSET[50] ,Interrupt Source Set 50" "No effect,Set"
|
|
bitfld.long 0x04 17. " SRCSET[49] ,Interrupt Source Set 49" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 16. " SRCSET[48] ,Interrupt Source Set 48" "No effect,Set"
|
|
bitfld.long 0x04 15. " SRCSET[47] ,Interrupt Source Set 47" "No effect,Set"
|
|
bitfld.long 0x04 14. " SRCSET[46] ,Interrupt Source Set 46" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SRCSET[45] ,Interrupt Source Set 45" "No effect,Set"
|
|
bitfld.long 0x04 12. " SRCSET[44] ,Interrupt Source Set 44" "No effect,Set"
|
|
bitfld.long 0x04 11. " SRCSET[43] ,Interrupt Source Set 43" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 10. " SRCSET[42] ,Interrupt Source Set 42" "No effect,Set"
|
|
bitfld.long 0x04 9. " SRCSET[41] ,Interrupt Source Set 41" "No effect,Set"
|
|
bitfld.long 0x04 8. " SRCSET[40] ,Interrupt Source Set 40" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SRCSET[39] ,Interrupt Source Set 39" "No effect,Set"
|
|
bitfld.long 0x04 6. " SRCSET[38] ,Interrupt Source Set 38" "No effect,Set"
|
|
bitfld.long 0x04 5. " SRCSET[37] ,Interrupt Source Set 37" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SRCSET[36] ,Interrupt Source Set 36" "No effect,Set"
|
|
bitfld.long 0x04 3. " SRCSET[35] ,Interrupt Source Set 35" "No effect,Set"
|
|
bitfld.long 0x04 2. " SRCSET[34] ,Interrupt Source Set 34" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SRCSET[33] ,Interrupt Source Set 33" "No effect,Set"
|
|
bitfld.long 0x04 0. " SRCSET[32] ,Interrupt Source Set 32" "No effect,Set"
|
|
line.long 0x08 "SRCSET2,Source Set 2 Register"
|
|
bitfld.long 0x08 31. " SRCSET[95] ,Interrupt Source Set 95" "No effect,Set"
|
|
bitfld.long 0x08 30. " SRCSET[94] ,Interrupt Source Set 94" "No effect,Set"
|
|
bitfld.long 0x08 29. " SRCSET[93] ,Interrupt Source Set 93" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 28. " SRCSET[92] ,Interrupt Source Set 92" "No effect,Set"
|
|
bitfld.long 0x08 27. " SRCSET[91] ,Interrupt Source Set 91" "No effect,Set"
|
|
bitfld.long 0x08 26. " SRCSET[90] ,Interrupt Source Set 90" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SRCSET[89] ,Interrupt Source Set 89" "No effect,Set"
|
|
bitfld.long 0x08 24. " SRCSET[88] ,Interrupt Source Set 88" "No effect,Set"
|
|
bitfld.long 0x08 23. " SRCSET[87] ,Interrupt Source Set 87" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 22. " SRCSET[86] ,Interrupt Source Set 86" "No effect,Set"
|
|
bitfld.long 0x08 21. " SRCSET[85] ,Interrupt Source Set 85" "No effect,Set"
|
|
bitfld.long 0x08 20. " SRCSET[84] ,Interrupt Source Set 84" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SRCSET[83] ,Interrupt Source Set 83" "No effect,Set"
|
|
bitfld.long 0x08 18. " SRCSET[82] ,Interrupt Source Set 82" "No effect,Set"
|
|
bitfld.long 0x08 17. " SRCSET[81] ,Interrupt Source Set 81" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 16. " SRCSET[80] ,Interrupt Source Set 80" "No effect,Set"
|
|
bitfld.long 0x08 15. " SRCSET[79] ,Interrupt Source Set 79" "No effect,Set"
|
|
bitfld.long 0x08 14. " SRCSET[78] ,Interrupt Source Set 78" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SRCSET[77] ,Interrupt Source Set 77" "No effect,Set"
|
|
bitfld.long 0x08 12. " SRCSET[76] ,Interrupt Source Set 76" "No effect,Set"
|
|
bitfld.long 0x08 11. " SRCSET[75] ,Interrupt Source Set 75" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 10. " SRCSET[74] ,Interrupt Source Set 74" "No effect,Set"
|
|
bitfld.long 0x08 9. " SRCSET[73] ,Interrupt Source Set 73" "No effect,Set"
|
|
bitfld.long 0x08 8. " SRCSET[72] ,Interrupt Source Set 72" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SRCSET[71] ,Interrupt Source Set 71" "No effect,Set"
|
|
bitfld.long 0x08 6. " SRCSET[70] ,Interrupt Source Set 70" "No effect,Set"
|
|
bitfld.long 0x08 5. " SRCSET[69] ,Interrupt Source Set 69" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 4. " SRCSET[68] ,Interrupt Source Set 68" "No effect,Set"
|
|
bitfld.long 0x08 3. " SRCSET[67] ,Interrupt Source Set 67" "No effect,Set"
|
|
bitfld.long 0x08 2. " SRCSET[66] ,Interrupt Source Set 66" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SRCSET[65] ,Interrupt Source Set 65" "No effect,Set"
|
|
bitfld.long 0x08 0. " SRCSET[64] ,Interrupt Source Set 64" "No effect,Set"
|
|
line.long 0x0c "SRCSET3,Source Set 3 Register"
|
|
bitfld.long 0x0c 31. " SRCSET[127] ,Interrupt Source Set 127" "No effect,Set"
|
|
bitfld.long 0x0c 30. " SRCSET[126] ,Interrupt Source Set 126" "No effect,Set"
|
|
bitfld.long 0x0c 29. " SRCSET[125] ,Interrupt Source Set 125" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " SRCSET[124] ,Interrupt Source Set 124" "No effect,Set"
|
|
bitfld.long 0x0c 27. " SRCSET[123] ,Interrupt Source Set 123" "No effect,Set"
|
|
bitfld.long 0x0c 26. " SRCSET[122] ,Interrupt Source Set 122" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " SRCSET[121] ,Interrupt Source Set 121" "No effect,Set"
|
|
bitfld.long 0x0c 24. " SRCSET[120] ,Interrupt Source Set 120" "No effect,Set"
|
|
bitfld.long 0x0c 23. " SRCSET[119] ,Interrupt Source Set 119" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " SRCSET[118] ,Interrupt Source Set 118" "No effect,Set"
|
|
bitfld.long 0x0c 21. " SRCSET[117] ,Interrupt Source Set 117" "No effect,Set"
|
|
bitfld.long 0x0c 20. " SRCSET[116] ,Interrupt Source Set 116" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " SRCSET[115] ,Interrupt Source Set 115" "No effect,Set"
|
|
bitfld.long 0x0c 18. " SRCSET[114] ,Interrupt Source Set 114" "No effect,Set"
|
|
bitfld.long 0x0c 17. " SRCSET[113] ,Interrupt Source Set 113" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " SRCSET[112] ,Interrupt Source Set 112" "No effect,Set"
|
|
bitfld.long 0x0c 15. " SRCSET[111] ,Interrupt Source Set 111" "No effect,Set"
|
|
bitfld.long 0x0c 14. " SRCSET[110] ,Interrupt Source Set 110" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " SRCSET[109] ,Interrupt Source Set 109" "No effect,Set"
|
|
bitfld.long 0x0c 12. " SRCSET[108] ,Interrupt Source Set 108" "No effect,Set"
|
|
bitfld.long 0x0c 11. " SRCSET[107] ,Interrupt Source Set 107" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " SRCSET[106] ,Interrupt Source Set 106" "No effect,Set"
|
|
bitfld.long 0x0c 9. " SRCSET[105] ,Interrupt Source Set 105" "No effect,Set"
|
|
bitfld.long 0x0c 8. " SRCSET[104] ,Interrupt Source Set 104" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " SRCSET[103] ,Interrupt Source Set 103" "No effect,Set"
|
|
bitfld.long 0x0c 6. " SRCSET[102] ,Interrupt Source Set 102" "No effect,Set"
|
|
bitfld.long 0x0c 5. " SRCSET[101] ,Interrupt Source Set 101" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " SRCSET[100] ,Interrupt Source Set 100" "No effect,Set"
|
|
bitfld.long 0x0c 3. " SRCSET[99] ,Interrupt Source Set 99" "No effect,Set"
|
|
bitfld.long 0x0c 2. " SRCSET[98] ,Interrupt Source Set 98" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " SRCSET[97] ,Interrupt Source Set 97" "No effect,Set"
|
|
bitfld.long 0x0c 0. " SRCSET[96] ,Interrupt Source Set 96" "No effect,Set"
|
|
group.long 0x280++0xf
|
|
line.long 0x00 "SRCCLEAR0,Source Clear 0 Register"
|
|
bitfld.long 0x00 31. " SRCCLEAR[31] ,Interrupt Source Clear 31" "No effect,Cleared"
|
|
bitfld.long 0x00 30. " SRCCLEAR[30] ,Interrupt Source Clear 30" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SRCCLEAR[29] ,Interrupt Source Clear 29" "No effect,Cleared"
|
|
bitfld.long 0x00 28. " SRCCLEAR[28] ,Interrupt Source Clear 28" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SRCCLEAR[27] ,Interrupt Source Clear 27" "No effect,Cleared"
|
|
bitfld.long 0x00 26. " SRCCLEAR[26] ,Interrupt Source Clear 26" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SRCCLEAR[25] ,Interrupt Source Clear 25" "No effect,Cleared"
|
|
bitfld.long 0x00 24. " SRCCLEAR[24] ,Interrupt Source Clear 24" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SRCCLEAR[23] ,Interrupt Source Clear 23" "No effect,Cleared"
|
|
bitfld.long 0x00 22. " SRCCLEAR[22] ,Interrupt Source Clear 22" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SRCCLEAR[21] ,Interrupt Source Clear 21" "No effect,Cleared"
|
|
bitfld.long 0x00 20. " SRCCLEAR[20] ,Interrupt Source Clear 20" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SRCCLEAR[19] ,Interrupt Source Clear 19" "No effect,Cleared"
|
|
bitfld.long 0x00 18. " SRCCLEAR[18] ,Interrupt Source Clear 18" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SRCCLEAR[17] ,Interrupt Source Clear 17" "No effect,Cleared"
|
|
bitfld.long 0x00 16. " SRCCLEAR[16] ,Interrupt Source Clear 16" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRCCLEAR[15] ,Interrupt Source Clear 15" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " SRCCLEAR[14] ,Interrupt Source Clear 14" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SRCCLEAR[13] ,Interrupt Source Clear 13" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " SRCCLEAR[12] ,Interrupt Source Clear 12" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SRCCLEAR[11] ,Interrupt Source Clear 11" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " SRCCLEAR[10] ,Interrupt Source Clear 10" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SRCCLEAR[9] ,Interrupt Source Clear 9" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " SRCCLEAR[8] ,Interrupt Source Clear 8" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SRCCLEAR[7] ,Interrupt Source Clear 7" "No effect,Cleared"
|
|
bitfld.long 0x00 6. " SRCCLEAR[6] ,Interrupt Source Clear 6" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SRCCLEAR[5] ,Interrupt Source Clear 5" "No effect,Cleared"
|
|
bitfld.long 0x00 4. " SRCCLEAR[4] ,Interrupt Source Clear 4" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SRCCLEAR[3] ,Interrupt Source Clear 3" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " SRCCLEAR[2] ,Interrupt Source Clear 2" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRCCLEAR[1] ,Interrupt Source Clear 1" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " SRCCLEAR[0] ,Interrupt Source Clear 0" "No effect,Cleared"
|
|
line.long 0x04 "SRCCLEAR1,Source Clear 1 Register"
|
|
bitfld.long 0x04 31. " SRCCLEAR[63] ,Interrupt Source Clear 63" "No effect,Cleared"
|
|
bitfld.long 0x04 30. " SRCCLEAR[62] ,Interrupt Source Clear 62" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SRCCLEAR[61] ,Interrupt Source Clear 61" "No effect,Cleared"
|
|
bitfld.long 0x04 28. " SRCCLEAR[60] ,Interrupt Source Clear 60" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 27. " SRCCLEAR[59] ,Interrupt Source Clear 59" "No effect,Cleared"
|
|
bitfld.long 0x04 26. " SRCCLEAR[58] ,Interrupt Source Clear 58" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 25. " SRCCLEAR[57] ,Interrupt Source Clear 57" "No effect,Cleared"
|
|
bitfld.long 0x04 24. " SRCCLEAR[56] ,Interrupt Source Clear 56" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 23. " SRCCLEAR[55] ,Interrupt Source Clear 55" "No effect,Cleared"
|
|
bitfld.long 0x04 22. " SRCCLEAR[54] ,Interrupt Source Clear 54" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SRCCLEAR[53] ,Interrupt Source Clear 53" "No effect,Cleared"
|
|
bitfld.long 0x04 20. " SRCCLEAR[52] ,Interrupt Source Clear 52" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SRCCLEAR[51] ,Interrupt Source Clear 51" "No effect,Cleared"
|
|
bitfld.long 0x04 18. " SRCCLEAR[50] ,Interrupt Source Clear 50" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 17. " SRCCLEAR[49] ,Interrupt Source Clear 49" "No effect,Cleared"
|
|
bitfld.long 0x04 16. " SRCCLEAR[48] ,Interrupt Source Clear 48" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SRCCLEAR[47] ,Interrupt Source Clear 47" "No effect,Cleared"
|
|
bitfld.long 0x04 14. " SRCCLEAR[46] ,Interrupt Source Clear 46" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 13. " SRCCLEAR[45] ,Interrupt Source Clear 45" "No effect,Cleared"
|
|
bitfld.long 0x04 12. " SRCCLEAR[44] ,Interrupt Source Clear 44" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SRCCLEAR[43] ,Interrupt Source Clear 43" "No effect,Cleared"
|
|
bitfld.long 0x04 10. " SRCCLEAR[42] ,Interrupt Source Clear 42" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SRCCLEAR[41] ,Interrupt Source Clear 41" "No effect,Cleared"
|
|
bitfld.long 0x04 8. " SRCCLEAR[40] ,Interrupt Source Clear 40" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SRCCLEAR[39] ,Interrupt Source Clear 39" "No effect,Cleared"
|
|
bitfld.long 0x04 6. " SRCCLEAR[38] ,Interrupt Source Clear 38" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SRCCLEAR[37] ,Interrupt Source Clear 37" "No effect,Cleared"
|
|
bitfld.long 0x04 4. " SRCCLEAR[36] ,Interrupt Source Clear 36" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SRCCLEAR[35] ,Interrupt Source Clear 35" "No effect,Cleared"
|
|
bitfld.long 0x04 2. " SRCCLEAR[34] ,Interrupt Source Clear 34" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SRCCLEAR[33] ,Interrupt Source Clear 33" "No effect,Cleared"
|
|
bitfld.long 0x04 0. " SRCCLEAR[32] ,Interrupt Source Clear 32" "No effect,Cleared"
|
|
line.long 0x08 "SRCCLEAR2,Source Clear 2 Register"
|
|
bitfld.long 0x08 31. " SRCCLEAR[95] ,Interrupt Source Clear 95" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " SRCCLEAR[94] ,Interrupt Source Clear 94" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " SRCCLEAR[93] ,Interrupt Source Clear 93" "No effect,Cleared"
|
|
bitfld.long 0x08 28. " SRCCLEAR[92] ,Interrupt Source Clear 92" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " SRCCLEAR[91] ,Interrupt Source Clear 91" "No effect,Cleared"
|
|
bitfld.long 0x08 26. " SRCCLEAR[90] ,Interrupt Source Clear 90" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SRCCLEAR[89] ,Interrupt Source Clear 89" "No effect,Cleared"
|
|
bitfld.long 0x08 24. " SRCCLEAR[88] ,Interrupt Source Clear 88" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " SRCCLEAR[87] ,Interrupt Source Clear 87" "No effect,Cleared"
|
|
bitfld.long 0x08 22. " SRCCLEAR[86] ,Interrupt Source Clear 86" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SRCCLEAR[85] ,Interrupt Source Clear 85" "No effect,Cleared"
|
|
bitfld.long 0x08 20. " SRCCLEAR[84] ,Interrupt Source Clear 84" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SRCCLEAR[83] ,Interrupt Source Clear 83" "No effect,Cleared"
|
|
bitfld.long 0x08 18. " SRCCLEAR[82] ,Interrupt Source Clear 82" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " SRCCLEAR[81] ,Interrupt Source Clear 81" "No effect,Cleared"
|
|
bitfld.long 0x08 16. " SRCCLEAR[80] ,Interrupt Source Clear 80" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " SRCCLEAR[79] ,Interrupt Source Clear 79" "No effect,Cleared"
|
|
bitfld.long 0x08 14. " SRCCLEAR[78] ,Interrupt Source Clear 78" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SRCCLEAR[77] ,Interrupt Source Clear 77" "No effect,Cleared"
|
|
bitfld.long 0x08 12. " SRCCLEAR[76] ,Interrupt Source Clear 76" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SRCCLEAR[75] ,Interrupt Source Clear 75" "No effect,Cleared"
|
|
bitfld.long 0x08 10. " SRCCLEAR[74] ,Interrupt Source Clear 74" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SRCCLEAR[73] ,Interrupt Source Clear 73" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " SRCCLEAR[72] ,Interrupt Source Clear 72" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SRCCLEAR[71] ,Interrupt Source Clear 71" "No effect,Cleared"
|
|
bitfld.long 0x08 6. " SRCCLEAR[70] ,Interrupt Source Clear 70" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SRCCLEAR[69] ,Interrupt Source Clear 69" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " SRCCLEAR[68] ,Interrupt Source Clear 68" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SRCCLEAR[67] ,Interrupt Source Clear 67" "No effect,Cleared"
|
|
bitfld.long 0x08 2. " SRCCLEAR[66] ,Interrupt Source Clear 66" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SRCCLEAR[65] ,Interrupt Source Clear 65" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " SRCCLEAR[64] ,Interrupt Source Clear 64" "No effect,Cleared"
|
|
line.long 0x0c "SRCCLEAR3,Source Clear 3 Register"
|
|
bitfld.long 0x0c 31. " SRCCLEAR[127] ,Interrupt Source Clear 127" "No effect,Cleared"
|
|
bitfld.long 0x0c 30. " SRCCLEAR[126] ,Interrupt Source Clear 126" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " SRCCLEAR[125] ,Interrupt Source Clear 125" "No effect,Cleared"
|
|
bitfld.long 0x0c 28. " SRCCLEAR[124] ,Interrupt Source Clear 124" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " SRCCLEAR[123] ,Interrupt Source Clear 123" "No effect,Cleared"
|
|
bitfld.long 0x0c 26. " SRCCLEAR[122] ,Interrupt Source Clear 122" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " SRCCLEAR[121] ,Interrupt Source Clear 121" "No effect,Cleared"
|
|
bitfld.long 0x0c 24. " SRCCLEAR[120] ,Interrupt Source Clear 120" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " SRCCLEAR[119] ,Interrupt Source Clear 119" "No effect,Cleared"
|
|
bitfld.long 0x0c 22. " SRCCLEAR[118] ,Interrupt Source Clear 118" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " SRCCLEAR[117] ,Interrupt Source Clear 117" "No effect,Cleared"
|
|
bitfld.long 0x0c 20. " SRCCLEAR[116] ,Interrupt Source Clear 116" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " SRCCLEAR[115] ,Interrupt Source Clear 115" "No effect,Cleared"
|
|
bitfld.long 0x0c 18. " SRCCLEAR[114] ,Interrupt Source Clear 114" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " SRCCLEAR[113] ,Interrupt Source Clear 113" "No effect,Cleared"
|
|
bitfld.long 0x0c 16. " SRCCLEAR[112] ,Interrupt Source Clear 112" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " SRCCLEAR[111] ,Interrupt Source Clear 111" "No effect,Cleared"
|
|
bitfld.long 0x0c 14. " SRCCLEAR[110] ,Interrupt Source Clear 110" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " SRCCLEAR[109] ,Interrupt Source Clear 109" "No effect,Cleared"
|
|
bitfld.long 0x0c 12. " SRCCLEAR[108] ,Interrupt Source Clear 108" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " SRCCLEAR[107] ,Interrupt Source Clear 107" "No effect,Cleared"
|
|
bitfld.long 0x0c 10. " SRCCLEAR[106] ,Interrupt Source Clear 106" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " SRCCLEAR[105] ,Interrupt Source Clear 105" "No effect,Cleared"
|
|
bitfld.long 0x0c 8. " SRCCLEAR[104] ,Interrupt Source Clear 104" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " SRCCLEAR[103] ,Interrupt Source Clear 103" "No effect,Cleared"
|
|
bitfld.long 0x0c 6. " SRCCLEAR[102] ,Interrupt Source Clear 102" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " SRCCLEAR[101] ,Interrupt Source Clear 101" "No effect,Cleared"
|
|
bitfld.long 0x0c 4. " SRCCLEAR[100] ,Interrupt Source Clear 100" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " SRCCLEAR[99] ,Interrupt Source Clear 99" "No effect,Cleared"
|
|
bitfld.long 0x0c 2. " SRCCLEAR[98] ,Interrupt Source Clear 98" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " SRCCLEAR[97] ,Interrupt Source Clear 97" "No effect,Cleared"
|
|
bitfld.long 0x0c 0. " SRCCLEAR[96] ,Interrupt Source Clear 96" "No effect,Cleared"
|
|
group.byte 0x400++0x7f
|
|
line.long 0x0 "PRIORITY0 ,Priority 0 Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRIO3 ,Interrupt Priority 3 "
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRIO2 ,Interrupt Priority 2 "
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRIO1 ,Interrupt Priority 1 "
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRIO0 ,Interrupt Priority 0 "
|
|
line.long 0x4 "PRIORITY1 ,Priority 1 Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRIO7 ,Interrupt Priority 7 "
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRIO6 ,Interrupt Priority 6 "
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRIO5 ,Interrupt Priority 5 "
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRIO4 ,Interrupt Priority 4 "
|
|
line.long 0x8 "PRIORITY2 ,Priority 2 Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRIO11 ,Interrupt Priority 11 "
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRIO10 ,Interrupt Priority 10 "
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRIO9 ,Interrupt Priority 9 "
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRIO8 ,Interrupt Priority 8 "
|
|
line.long 0xC "PRIORITY3 ,Priority 3 Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRIO15 ,Interrupt Priority 15 "
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRIO14 ,Interrupt Priority 14 "
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRIO13 ,Interrupt Priority 13 "
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRIO12 ,Interrupt Priority 12 "
|
|
line.long 0x10 "PRIORITY4 ,Priority 4 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRIO19 ,Interrupt Priority 19 "
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRIO18 ,Interrupt Priority 18 "
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRIO17 ,Interrupt Priority 17 "
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRIO16 ,Interrupt Priority 16 "
|
|
line.long 0x14 "PRIORITY5 ,Priority 5 Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRIO23 ,Interrupt Priority 23 "
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRIO22 ,Interrupt Priority 22 "
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRIO21 ,Interrupt Priority 21 "
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRIO20 ,Interrupt Priority 20 "
|
|
line.long 0x18 "PRIORITY6 ,Priority 6 Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRIO27 ,Interrupt Priority 27 "
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRIO26 ,Interrupt Priority 26 "
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRIO25 ,Interrupt Priority 25 "
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRIO24 ,Interrupt Priority 24 "
|
|
line.long 0x1C "PRIORITY7 ,Priority 7 Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRIO31 ,Interrupt Priority 31 "
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRIO30 ,Interrupt Priority 30 "
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRIO29 ,Interrupt Priority 29 "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRIO28 ,Interrupt Priority 28 "
|
|
line.long 0x20 "PRIORITY8 ,Priority 8 Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRIO35 ,Interrupt Priority 35 "
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRIO34 ,Interrupt Priority 34 "
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRIO33 ,Interrupt Priority 33 "
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRIO32 ,Interrupt Priority 32 "
|
|
line.long 0x24 "PRIORITY9 ,Priority 9 Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRIO39 ,Interrupt Priority 39 "
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRIO38 ,Interrupt Priority 38 "
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRIO37 ,Interrupt Priority 37 "
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRIO36 ,Interrupt Priority 36 "
|
|
line.long 0x28 "PRIORITY10,Priority 10 Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRIO43 ,Interrupt Priority 43 "
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRIO42 ,Interrupt Priority 42 "
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRIO41 ,Interrupt Priority 41 "
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRIO40 ,Interrupt Priority 40 "
|
|
line.long 0x2C "PRIORITY11,Priority 11 Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRIO47 ,Interrupt Priority 47 "
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRIO46 ,Interrupt Priority 46 "
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRIO45 ,Interrupt Priority 45 "
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRIO44 ,Interrupt Priority 44 "
|
|
line.long 0x30 "PRIORITY12,Priority 12 Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRIO51 ,Interrupt Priority 51 "
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRIO50 ,Interrupt Priority 50 "
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRIO49 ,Interrupt Priority 49 "
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRIO48 ,Interrupt Priority 48 "
|
|
line.long 0x34 "PRIORITY13,Priority 13 Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRIO55 ,Interrupt Priority 55 "
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRIO54 ,Interrupt Priority 54 "
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRIO53 ,Interrupt Priority 53 "
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRIO52 ,Interrupt Priority 52 "
|
|
line.long 0x38 "PRIORITY14,Priority 14 Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRIO59 ,Interrupt Priority 59 "
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRIO58 ,Interrupt Priority 58 "
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRIO57 ,Interrupt Priority 57 "
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRIO56 ,Interrupt Priority 56 "
|
|
line.long 0x3C "PRIORITY15,Priority 15 Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRIO63 ,Interrupt Priority 63 "
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRIO62 ,Interrupt Priority 62 "
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRIO61 ,Interrupt Priority 61 "
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRIO60 ,Interrupt Priority 60 "
|
|
line.long 0x40 "PRIORITY16,Priority 16 Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRIO67 ,Interrupt Priority 67 "
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRIO66 ,Interrupt Priority 66 "
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRIO65 ,Interrupt Priority 65 "
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRIO64 ,Interrupt Priority 64 "
|
|
line.long 0x44 "PRIORITY17,Priority 17 Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRIO71 ,Interrupt Priority 71 "
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRIO70 ,Interrupt Priority 70 "
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRIO69 ,Interrupt Priority 69 "
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRIO68 ,Interrupt Priority 68 "
|
|
line.long 0x48 "PRIORITY18,Priority 18 Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRIO75 ,Interrupt Priority 75 "
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRIO74 ,Interrupt Priority 74 "
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRIO73 ,Interrupt Priority 73 "
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRIO72 ,Interrupt Priority 72 "
|
|
line.long 0x4C "PRIORITY19,Priority 19 Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRIO79 ,Interrupt Priority 79 "
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRIO78 ,Interrupt Priority 78 "
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRIO77 ,Interrupt Priority 77 "
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRIO76 ,Interrupt Priority 76 "
|
|
line.long 0x50 "PRIORITY20,Priority 20 Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRIO83 ,Interrupt Priority 83 "
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRIO82 ,Interrupt Priority 82 "
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRIO81 ,Interrupt Priority 81 "
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRIO80 ,Interrupt Priority 80 "
|
|
line.long 0x54 "PRIORITY21,Priority 21 Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRIO87 ,Interrupt Priority 87 "
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRIO86 ,Interrupt Priority 86 "
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRIO85 ,Interrupt Priority 85 "
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRIO84 ,Interrupt Priority 84 "
|
|
line.long 0x58 "PRIORITY22,Priority 22 Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRIO91 ,Interrupt Priority 91 "
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRIO90 ,Interrupt Priority 90 "
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRIO89 ,Interrupt Priority 89 "
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRIO88 ,Interrupt Priority 88 "
|
|
line.long 0x5C "PRIORITY23,Priority 23 Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRIO95 ,Interrupt Priority 95 "
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRIO94 ,Interrupt Priority 94 "
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRIO93 ,Interrupt Priority 93 "
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRIO92 ,Interrupt Priority 92 "
|
|
line.long 0x60 "PRIORITY24,Priority 24 Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRIO99 ,Interrupt Priority 99 "
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRIO98 ,Interrupt Priority 98 "
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRIO97 ,Interrupt Priority 97 "
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRIO96 ,Interrupt Priority 96 "
|
|
line.long 0x64 "PRIORITY25,Priority 25 Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRIO103 ,Interrupt Priority 103"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRIO102 ,Interrupt Priority 102"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRIO101 ,Interrupt Priority 101"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRIO100 ,Interrupt Priority 100"
|
|
line.long 0x68 "PRIORITY26,Priority 26 Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRIO107 ,Interrupt Priority 107"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRIO106 ,Interrupt Priority 106"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRIO105 ,Interrupt Priority 105"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRIO104 ,Interrupt Priority 104"
|
|
line.long 0x6C "PRIORITY27,Priority 27 Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRIO111 ,Interrupt Priority 111"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRIO110 ,Interrupt Priority 110"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRIO109 ,Interrupt Priority 109"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRIO108 ,Interrupt Priority 108"
|
|
line.long 0x70 "PRIORITY28,Priority 28 Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRIO115 ,Interrupt Priority 115"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRIO114 ,Interrupt Priority 114"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRIO113 ,Interrupt Priority 113"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRIO112 ,Interrupt Priority 112"
|
|
line.long 0x74 "PRIORITY29,Priority 29 Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRIO119 ,Interrupt Priority 119"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRIO118 ,Interrupt Priority 118"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRIO117 ,Interrupt Priority 117"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRIO116 ,Interrupt Priority 116"
|
|
line.long 0x78 "PRIORITY30,Priority 30 Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRIO123 ,Interrupt Priority 123"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRIO122 ,Interrupt Priority 122"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRIO121 ,Interrupt Priority 121"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRIO120 ,Interrupt Priority 120"
|
|
line.long 0x7C "PRIORITY31,Priority 31 Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRIO127 ,Interrupt Priority 127"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRIO126 ,Interrupt Priority 126"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRIO125 ,Interrupt Priority 125"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRIO124 ,Interrupt Priority 124"
|
|
rgroup.long 0xd00++0xf
|
|
line.long 0x00 "PND0,Pending 0 Register"
|
|
bitfld.long 0x00 31. " PND[31] ,Interrupt Pending 31 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PND[30] ,Interrupt Pending 30 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " PND[29] ,Interrupt Pending 29 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PND[28] ,Interrupt Pending 28 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PND[27] ,Interrupt Pending 27 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PND[26] ,Interrupt Pending 26 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PND[25] ,Interrupt Pending 25 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PND[24] ,Interrupt Pending 24 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " PND[23] ,Interrupt Pending 23 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PND[22] ,Interrupt Pending 22 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " PND[21] ,Interrupt Pending 21 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PND[20] ,Interrupt Pending 20 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PND[19] ,Interrupt Pending 19 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PND[18] ,Interrupt Pending 18 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " PND[17] ,Interrupt Pending 17 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PND[16] ,Interrupt Pending 16 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " PND[15] ,Interrupt Pending 15 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PND[14] ,Interrupt Pending 14 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PND[13] ,Interrupt Pending 13 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PND[12] ,Interrupt Pending 12 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " PND[11] ,Interrupt Pending 11 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PND[10] ,Interrupt Pending 10 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " PND[9] ,Interrupt Pending 9 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PND[8] ,Interrupt Pending 8 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PND[7] ,Interrupt Pending 7 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PND[6] ,Interrupt Pending 6 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " PND[5] ,Interrupt Pending 5 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PND[4] ,Interrupt Pending 4 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " PND[3] ,Interrupt Pending 3 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PND[2] ,Interrupt Pending 2 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PND[1] ,Interrupt Pending 1 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PND[0] ,Interrupt Pending 0 Status" "Not pending,Pending"
|
|
line.long 0x04 "PND1,Pending 1 Register"
|
|
bitfld.long 0x04 31. " PND[63] ,Interrupt Pending 63 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 30. " PND[62] ,Interrupt Pending 62 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 29. " PND[61] ,Interrupt Pending 61 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 28. " PND[60] ,Interrupt Pending 60 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 27. " PND[59] ,Interrupt Pending 59 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 26. " PND[58] ,Interrupt Pending 58 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 25. " PND[57] ,Interrupt Pending 57 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PND[56] ,Interrupt Pending 56 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 23. " PND[55] ,Interrupt Pending 55 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 22. " PND[54] ,Interrupt Pending 54 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 21. " PND[53] ,Interrupt Pending 53 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " PND[52] ,Interrupt Pending 52 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PND[51] ,Interrupt Pending 51 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " PND[50] ,Interrupt Pending 50 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 17. " PND[49] ,Interrupt Pending 49 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 16. " PND[48] ,Interrupt Pending 48 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 15. " PND[47] ,Interrupt Pending 47 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 14. " PND[46] ,Interrupt Pending 46 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 13. " PND[45] ,Interrupt Pending 45 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 12. " PND[44] ,Interrupt Pending 44 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 11. " PND[43] ,Interrupt Pending 43 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 10. " PND[42] ,Interrupt Pending 42 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 9. " PND[41] ,Interrupt Pending 41 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " PND[40] ,Interrupt Pending 40 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " PND[39] ,Interrupt Pending 39 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " PND[38] ,Interrupt Pending 38 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 5. " PND[37] ,Interrupt Pending 37 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PND[36] ,Interrupt Pending 36 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 3. " PND[35] ,Interrupt Pending 35 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " PND[34] ,Interrupt Pending 34 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PND[33] ,Interrupt Pending 33 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " PND[32] ,Interrupt Pending 32 Status" "Not pending,Pending"
|
|
line.long 0x08 "PND2,Pending 2 Register"
|
|
bitfld.long 0x08 31. " PND[95] ,Interrupt Pending 95 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 30. " PND[94] ,Interrupt Pending 94 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 29. " PND[93] ,Interrupt Pending 93 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 28. " PND[92] ,Interrupt Pending 92 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 27. " PND[91] ,Interrupt Pending 91 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 26. " PND[90] ,Interrupt Pending 90 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 25. " PND[89] ,Interrupt Pending 89 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 24. " PND[88] ,Interrupt Pending 88 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 23. " PND[87] ,Interrupt Pending 87 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 22. " PND[86] ,Interrupt Pending 86 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 21. " PND[85] ,Interrupt Pending 85 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 20. " PND[84] ,Interrupt Pending 84 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PND[83] ,Interrupt Pending 83 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 18. " PND[82] ,Interrupt Pending 82 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 17. " PND[81] ,Interrupt Pending 81 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 16. " PND[80] ,Interrupt Pending 80 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 15. " PND[79] ,Interrupt Pending 79 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 14. " PND[78] ,Interrupt Pending 78 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 13. " PND[77] ,Interrupt Pending 77 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 12. " PND[76] ,Interrupt Pending 76 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 11. " PND[75] ,Interrupt Pending 75 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 10. " PND[74] ,Interrupt Pending 74 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 9. " PND[73] ,Interrupt Pending 73 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 8. " PND[72] ,Interrupt Pending 72 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 7. " PND[71] ,Interrupt Pending 71 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 6. " PND[70] ,Interrupt Pending 70 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 5. " PND[69] ,Interrupt Pending 69 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PND[68] ,Interrupt Pending 68 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 3. " PND[67] ,Interrupt Pending 67 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 2. " PND[66] ,Interrupt Pending 66 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 1. " PND[65] ,Interrupt Pending 65 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 0. " PND[64] ,Interrupt Pending 64 Status" "Not pending,Pending"
|
|
line.long 0x0c "PND3,Pending 3 Register"
|
|
bitfld.long 0x0c 31. " PND[127] ,Interrupt Pending 127 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 30. " PND[126] ,Interrupt Pending 126 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 29. " PND[125] ,Interrupt Pending 125 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " PND[124] ,Interrupt Pending 124 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 27. " PND[123] ,Interrupt Pending 123 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 26. " PND[122] ,Interrupt Pending 122 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " PND[121] ,Interrupt Pending 121 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 24. " PND[120] ,Interrupt Pending 120 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 23. " PND[119] ,Interrupt Pending 119 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 22. " PND[118] ,Interrupt Pending 118 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 21. " PND[117] ,Interrupt Pending 117 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 20. " PND[116] ,Interrupt Pending 116 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " PND[115] ,Interrupt Pending 115 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 18. " PND[114] ,Interrupt Pending 114 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 17. " PND[113] ,Interrupt Pending 113 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " PND[112] ,Interrupt Pending 112 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 15. " PND[111] ,Interrupt Pending 111 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 14. " PND[110] ,Interrupt Pending 110 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " PND[109] ,Interrupt Pending 109 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 12. " PND[108] ,Interrupt Pending 108 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 11. " PND[107] ,Interrupt Pending 107 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " PND[106] ,Interrupt Pending 106 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 9. " PND[105] ,Interrupt Pending 105 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 8. " PND[104] ,Interrupt Pending 104 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " PND[103] ,Interrupt Pending 103 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 6. " PND[102] ,Interrupt Pending 102 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 5. " PND[101] ,Interrupt Pending 101 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " PND[100] ,Interrupt Pending 100 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 3. " PND[99] ,Interrupt Pending 99 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 2. " PND[98] ,Interrupt Pending 98 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " PND[97] ,Interrupt Pending 97 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 0. " PND[96] ,Interrupt Pending 96 Status" "Not pending,Pending"
|
|
rgroup.long 0xd80++0xf
|
|
line.long 0x00 "HIPND0,High Priority Pending 0 Register"
|
|
bitfld.long 0x00 31. " HIPND[31] ,High Priority Interrupt Pending 31 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " HIPND[30] ,High Priority Interrupt Pending 30 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " HIPND[29] ,High Priority Interrupt Pending 29 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " HIPND[28] ,High Priority Interrupt Pending 28 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HIPND[27] ,High Priority Interrupt Pending 27 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " HIPND[26] ,High Priority Interrupt Pending 26 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HIPND[25] ,High Priority Interrupt Pending 25 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " HIPND[24] ,High Priority Interrupt Pending 24 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HIPND[23] ,High Priority Interrupt Pending 23 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " HIPND[22] ,High Priority Interrupt Pending 22 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " HIPND[21] ,High Priority Interrupt Pending 21 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " HIPND[20] ,High Priority Interrupt Pending 20 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HIPND[19] ,High Priority Interrupt Pending 19 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " HIPND[18] ,High Priority Interrupt Pending 18 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HIPND[17] ,High Priority Interrupt Pending 17 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " HIPND[16] ,High Priority Interrupt Pending 16 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HIPND[15] ,High Priority Interrupt Pending 15 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " HIPND[14] ,High Priority Interrupt Pending 14 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HIPND[13] ,High Priority Interrupt Pending 13 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " HIPND[12] ,High Priority Interrupt Pending 12 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HIPND[11] ,High Priority Interrupt Pending 11 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " HIPND[10] ,High Priority Interrupt Pending 10 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HIPND[9] ,High Priority Interrupt Pending 9 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " HIPND[8] ,High Priority Interrupt Pending 8 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIPND[7] ,High Priority Interrupt Pending 7 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " HIPND[6] ,High Priority Interrupt Pending 6 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HIPND[5] ,High Priority Interrupt Pending 5 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " HIPND[4] ,High Priority Interrupt Pending 4 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HIPND[3] ,High Priority Interrupt Pending 3 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " HIPND[2] ,High Priority Interrupt Pending 2 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIPND[1] ,High Priority Interrupt Pending 1 Status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " HIPND[0] ,High Priority Interrupt Pending 0 Status" "Not pending,Pending"
|
|
line.long 0x04 "HIPND1,High Priority Pending 1 Register"
|
|
bitfld.long 0x04 31. " HIPND[63] ,High Priority Interrupt Pending 63 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 30. " HIPND[62] ,High Priority Interrupt Pending 62 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 29. " HIPND[61] ,High Priority Interrupt Pending 61 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 28. " HIPND[60] ,High Priority Interrupt Pending 60 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 27. " HIPND[59] ,High Priority Interrupt Pending 59 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 26. " HIPND[58] ,High Priority Interrupt Pending 58 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 25. " HIPND[57] ,High Priority Interrupt Pending 57 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " HIPND[56] ,High Priority Interrupt Pending 56 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 23. " HIPND[55] ,High Priority Interrupt Pending 55 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 22. " HIPND[54] ,High Priority Interrupt Pending 54 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 21. " HIPND[53] ,High Priority Interrupt Pending 53 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 20. " HIPND[52] ,High Priority Interrupt Pending 52 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 19. " HIPND[51] ,High Priority Interrupt Pending 51 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 18. " HIPND[50] ,High Priority Interrupt Pending 50 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 17. " HIPND[49] ,High Priority Interrupt Pending 49 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 16. " HIPND[48] ,High Priority Interrupt Pending 48 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HIPND[47] ,High Priority Interrupt Pending 47 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 14. " HIPND[46] ,High Priority Interrupt Pending 46 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 13. " HIPND[45] ,High Priority Interrupt Pending 45 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 12. " HIPND[44] ,High Priority Interrupt Pending 44 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 11. " HIPND[43] ,High Priority Interrupt Pending 43 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 10. " HIPND[42] ,High Priority Interrupt Pending 42 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 9. " HIPND[41] ,High Priority Interrupt Pending 41 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 8. " HIPND[40] ,High Priority Interrupt Pending 40 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HIPND[39] ,High Priority Interrupt Pending 39 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 6. " HIPND[38] ,High Priority Interrupt Pending 38 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 5. " HIPND[37] ,High Priority Interrupt Pending 37 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 4. " HIPND[36] ,High Priority Interrupt Pending 36 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HIPND[35] ,High Priority Interrupt Pending 35 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 2. " HIPND[34] ,High Priority Interrupt Pending 34 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " HIPND[33] ,High Priority Interrupt Pending 33 Status" "Not pending,Pending"
|
|
bitfld.long 0x04 0. " HIPND[32] ,High Priority Interrupt Pending 32 Status" "Not pending,Pending"
|
|
line.long 0x08 "HIPND2,High Priority Pending 2 Register"
|
|
bitfld.long 0x08 31. " HIPND[95] ,High Priority Interrupt Pending 95 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 30. " HIPND[94] ,High Priority Interrupt Pending 94 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HIPND[93] ,High Priority Interrupt Pending 93 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 28. " HIPND[92] ,High Priority Interrupt Pending 92 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HIPND[91] ,High Priority Interrupt Pending 91 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 26. " HIPND[90] ,High Priority Interrupt Pending 90 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HIPND[89] ,High Priority Interrupt Pending 89 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 24. " HIPND[88] ,High Priority Interrupt Pending 88 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HIPND[87] ,High Priority Interrupt Pending 87 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 22. " HIPND[86] ,High Priority Interrupt Pending 86 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIPND[85] ,High Priority Interrupt Pending 85 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 20. " HIPND[84] ,High Priority Interrupt Pending 84 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIPND[83] ,High Priority Interrupt Pending 83 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 18. " HIPND[82] ,High Priority Interrupt Pending 82 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 17. " HIPND[81] ,High Priority Interrupt Pending 81 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 16. " HIPND[80] ,High Priority Interrupt Pending 80 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIPND[79] ,High Priority Interrupt Pending 79 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 14. " HIPND[78] ,High Priority Interrupt Pending 78 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIPND[77] ,High Priority Interrupt Pending 77 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 12. " HIPND[76] ,High Priority Interrupt Pending 76 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIPND[75] ,High Priority Interrupt Pending 75 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 10. " HIPND[74] ,High Priority Interrupt Pending 74 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIPND[73] ,High Priority Interrupt Pending 73 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 8. " HIPND[72] ,High Priority Interrupt Pending 72 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIPND[71] ,High Priority Interrupt Pending 71 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 6. " HIPND[70] ,High Priority Interrupt Pending 70 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIPND[69] ,High Priority Interrupt Pending 69 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 4. " HIPND[68] ,High Priority Interrupt Pending 68 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIPND[67] ,High Priority Interrupt Pending 67 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 2. " HIPND[66] ,High Priority Interrupt Pending 66 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIPND[65] ,High Priority Interrupt Pending 65 Status" "Not pending,Pending"
|
|
bitfld.long 0x08 0. " HIPND[64] ,High Priority Interrupt Pending 64 Status" "Not pending,Pending"
|
|
line.long 0x0c "HIPND3,High Priority Pending 3 Register"
|
|
bitfld.long 0x0c 31. " HIPND[127] ,High Priority Interrupt Pending 127 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 30. " HIPND[126] ,High Priority Interrupt Pending 126 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " HIPND[125] ,High Priority Interrupt Pending 125 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 28. " HIPND[124] ,High Priority Interrupt Pending 124 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " HIPND[123] ,High Priority Interrupt Pending 123 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 26. " HIPND[122] ,High Priority Interrupt Pending 122 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " HIPND[121] ,High Priority Interrupt Pending 121 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 24. " HIPND[120] ,High Priority Interrupt Pending 120 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " HIPND[119] ,High Priority Interrupt Pending 119 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 22. " HIPND[118] ,High Priority Interrupt Pending 118 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " HIPND[117] ,High Priority Interrupt Pending 117 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 20. " HIPND[116] ,High Priority Interrupt Pending 116 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " HIPND[115] ,High Priority Interrupt Pending 115 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 18. " HIPND[114] ,High Priority Interrupt Pending 114 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " HIPND[113] ,High Priority Interrupt Pending 113 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 16. " HIPND[112] ,High Priority Interrupt Pending 112 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " HIPND[111] ,High Priority Interrupt Pending 111 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 14. " HIPND[110] ,High Priority Interrupt Pending 110 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " HIPND[109] ,High Priority Interrupt Pending 109 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 12. " HIPND[108] ,High Priority Interrupt Pending 108 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " HIPND[107] ,High Priority Interrupt Pending 107 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 10. " HIPND[106] ,High Priority Interrupt Pending 106 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " HIPND[105] ,High Priority Interrupt Pending 105 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 8. " HIPND[104] ,High Priority Interrupt Pending 104 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " HIPND[103] ,High Priority Interrupt Pending 103 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 6. " HIPND[102] ,High Priority Interrupt Pending 102 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " HIPND[101] ,High Priority Interrupt Pending 101 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 4. " HIPND[100] ,High Priority Interrupt Pending 100 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " HIPND[99] ,High Priority Interrupt Pending 99 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 2. " HIPND[98] ,High Priority Interrupt Pending 98 Status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " HIPND[97] ,High Priority Interrupt Pending 97 Status" "Not pending,Pending"
|
|
bitfld.long 0x0c 0. " HIPND[96] ,High Priority Interrupt Pending 96 Status" "Not pending,Pending"
|
|
group.long 0xe00++0xf
|
|
line.long 0x00 "WAKEUP0,High Priority Pending 0 Register"
|
|
bitfld.long 0x00 31. " WAKEUP[31] ,Wakeup Configuration 31" "Not asserted,Asserted"
|
|
bitfld.long 0x00 30. " WAKEUP[30] ,Wakeup Configuration 30" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 29. " WAKEUP[29] ,Wakeup Configuration 29" "Not asserted,Asserted"
|
|
bitfld.long 0x00 28. " WAKEUP[28] ,Wakeup Configuration 28" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WAKEUP[27] ,Wakeup Configuration 27" "Not asserted,Asserted"
|
|
bitfld.long 0x00 26. " WAKEUP[26] ,Wakeup Configuration 26" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WAKEUP[25] ,Wakeup Configuration 25" "Not asserted,Asserted"
|
|
bitfld.long 0x00 24. " WAKEUP[24] ,Wakeup Configuration 24" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WAKEUP[23] ,Wakeup Configuration 23" "Not asserted,Asserted"
|
|
bitfld.long 0x00 22. " WAKEUP[22] ,Wakeup Configuration 22" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAKEUP[21] ,Wakeup Configuration 21" "Not asserted,Asserted"
|
|
bitfld.long 0x00 20. " WAKEUP[20] ,Wakeup Configuration 20" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WAKEUP[19] ,Wakeup Configuration 19" "Not asserted,Asserted"
|
|
bitfld.long 0x00 18. " WAKEUP[18] ,Wakeup Configuration 18" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " WAKEUP[17] ,Wakeup Configuration 17" "Not asserted,Asserted"
|
|
bitfld.long 0x00 16. " WAKEUP[16] ,Wakeup Configuration 16" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAKEUP[15] ,Wakeup Configuration 15" "Not asserted,Asserted"
|
|
bitfld.long 0x00 14. " WAKEUP[14] ,Wakeup Configuration 14" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAKEUP[13] ,Wakeup Configuration 13" "Not asserted,Asserted"
|
|
bitfld.long 0x00 12. " WAKEUP[12] ,Wakeup Configuration 12" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKEUP[11] ,Wakeup Configuration 11" "Not asserted,Asserted"
|
|
bitfld.long 0x00 10. " WAKEUP[10] ,Wakeup Configuration 10" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " WAKEUP[9] ,Wakeup Configuration 9" "Not asserted,Asserted"
|
|
bitfld.long 0x00 8. " WAKEUP[8] ,Wakeup Configuration 8" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WAKEUP[7] ,Wakeup Configuration 7" "Not asserted,Asserted"
|
|
bitfld.long 0x00 6. " WAKEUP[6] ,Wakeup Configuration 6" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " WAKEUP[5] ,Wakeup Configuration 5" "Not asserted,Asserted"
|
|
bitfld.long 0x00 4. " WAKEUP[4] ,Wakeup Configuration 4" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WAKEUP[3] ,Wakeup Configuration 3" "Not asserted,Asserted"
|
|
bitfld.long 0x00 2. " WAKEUP[2] ,Wakeup Configuration 2" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WAKEUP[1] ,Wakeup Configuration 1" "Not asserted,Asserted"
|
|
bitfld.long 0x00 0. " WAKEUP[0] ,Wakeup Configuration 0" "Not asserted,Asserted"
|
|
line.long 0x04 "WAKEUP1,High Priority Pending 1 Register"
|
|
bitfld.long 0x04 31. " WAKEUP[63] ,Wakeup Configuration 63" "Not asserted,Asserted"
|
|
bitfld.long 0x04 30. " WAKEUP[62] ,Wakeup Configuration 62" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 29. " WAKEUP[61] ,Wakeup Configuration 61" "Not asserted,Asserted"
|
|
bitfld.long 0x04 28. " WAKEUP[60] ,Wakeup Configuration 60" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 27. " WAKEUP[59] ,Wakeup Configuration 59" "Not asserted,Asserted"
|
|
bitfld.long 0x04 26. " WAKEUP[58] ,Wakeup Configuration 58" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 25. " WAKEUP[57] ,Wakeup Configuration 57" "Not asserted,Asserted"
|
|
bitfld.long 0x04 24. " WAKEUP[56] ,Wakeup Configuration 56" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 23. " WAKEUP[55] ,Wakeup Configuration 55" "Not asserted,Asserted"
|
|
bitfld.long 0x04 22. " WAKEUP[54] ,Wakeup Configuration 54" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 21. " WAKEUP[53] ,Wakeup Configuration 53" "Not asserted,Asserted"
|
|
bitfld.long 0x04 20. " WAKEUP[52] ,Wakeup Configuration 52" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 19. " WAKEUP[51] ,Wakeup Configuration 51" "Not asserted,Asserted"
|
|
bitfld.long 0x04 18. " WAKEUP[50] ,Wakeup Configuration 50" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 17. " WAKEUP[49] ,Wakeup Configuration 49" "Not asserted,Asserted"
|
|
bitfld.long 0x04 16. " WAKEUP[48] ,Wakeup Configuration 48" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 15. " WAKEUP[47] ,Wakeup Configuration 47" "Not asserted,Asserted"
|
|
bitfld.long 0x04 14. " WAKEUP[46] ,Wakeup Configuration 46" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 13. " WAKEUP[45] ,Wakeup Configuration 45" "Not asserted,Asserted"
|
|
bitfld.long 0x04 12. " WAKEUP[44] ,Wakeup Configuration 44" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WAKEUP[43] ,Wakeup Configuration 43" "Not asserted,Asserted"
|
|
bitfld.long 0x04 10. " WAKEUP[42] ,Wakeup Configuration 42" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAKEUP[41] ,Wakeup Configuration 41" "Not asserted,Asserted"
|
|
bitfld.long 0x04 8. " WAKEUP[40] ,Wakeup Configuration 40" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 7. " WAKEUP[39] ,Wakeup Configuration 39" "Not asserted,Asserted"
|
|
bitfld.long 0x04 6. " WAKEUP[38] ,Wakeup Configuration 38" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WAKEUP[37] ,Wakeup Configuration 37" "Not asserted,Asserted"
|
|
bitfld.long 0x04 4. " WAKEUP[36] ,Wakeup Configuration 36" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WAKEUP[35] ,Wakeup Configuration 35" "Not asserted,Asserted"
|
|
bitfld.long 0x04 2. " WAKEUP[34] ,Wakeup Configuration 34" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x04 1. " WAKEUP[33] ,Wakeup Configuration 33" "Not asserted,Asserted"
|
|
bitfld.long 0x04 0. " WAKEUP[32] ,Wakeup Configuration 32" "Not asserted,Asserted"
|
|
line.long 0x08 "WAKEUP2,High Priority Pending 2 Register"
|
|
bitfld.long 0x08 31. " WAKEUP[95] ,Wakeup Configuration 95" "Not asserted,Asserted"
|
|
bitfld.long 0x08 30. " WAKEUP[94] ,Wakeup Configuration 94" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 29. " WAKEUP[93] ,Wakeup Configuration 93" "Not asserted,Asserted"
|
|
bitfld.long 0x08 28. " WAKEUP[92] ,Wakeup Configuration 92" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 27. " WAKEUP[91] ,Wakeup Configuration 91" "Not asserted,Asserted"
|
|
bitfld.long 0x08 26. " WAKEUP[90] ,Wakeup Configuration 90" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 25. " WAKEUP[89] ,Wakeup Configuration 89" "Not asserted,Asserted"
|
|
bitfld.long 0x08 24. " WAKEUP[88] ,Wakeup Configuration 88" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 23. " WAKEUP[87] ,Wakeup Configuration 87" "Not asserted,Asserted"
|
|
bitfld.long 0x08 22. " WAKEUP[86] ,Wakeup Configuration 86" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 21. " WAKEUP[85] ,Wakeup Configuration 85" "Not asserted,Asserted"
|
|
bitfld.long 0x08 20. " WAKEUP[84] ,Wakeup Configuration 84" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 19. " WAKEUP[83] ,Wakeup Configuration 83" "Not asserted,Asserted"
|
|
bitfld.long 0x08 18. " WAKEUP[82] ,Wakeup Configuration 82" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 17. " WAKEUP[81] ,Wakeup Configuration 81" "Not asserted,Asserted"
|
|
bitfld.long 0x08 16. " WAKEUP[80] ,Wakeup Configuration 80" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 15. " WAKEUP[79] ,Wakeup Configuration 79" "Not asserted,Asserted"
|
|
bitfld.long 0x08 14. " WAKEUP[78] ,Wakeup Configuration 78" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 13. " WAKEUP[77] ,Wakeup Configuration 77" "Not asserted,Asserted"
|
|
bitfld.long 0x08 12. " WAKEUP[76] ,Wakeup Configuration 76" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 11. " WAKEUP[75] ,Wakeup Configuration 75" "Not asserted,Asserted"
|
|
bitfld.long 0x08 10. " WAKEUP[74] ,Wakeup Configuration 74" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 9. " WAKEUP[73] ,Wakeup Configuration 73" "Not asserted,Asserted"
|
|
bitfld.long 0x08 8. " WAKEUP[72] ,Wakeup Configuration 72" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 7. " WAKEUP[71] ,Wakeup Configuration 71" "Not asserted,Asserted"
|
|
bitfld.long 0x08 6. " WAKEUP[70] ,Wakeup Configuration 70" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 5. " WAKEUP[69] ,Wakeup Configuration 69" "Not asserted,Asserted"
|
|
bitfld.long 0x08 4. " WAKEUP[68] ,Wakeup Configuration 68" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " WAKEUP[67] ,Wakeup Configuration 67" "Not asserted,Asserted"
|
|
bitfld.long 0x08 2. " WAKEUP[66] ,Wakeup Configuration 66" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x08 1. " WAKEUP[65] ,Wakeup Configuration 65" "Not asserted,Asserted"
|
|
bitfld.long 0x08 0. " WAKEUP[64] ,Wakeup Configuration 64" "Not asserted,Asserted"
|
|
line.long 0x0c "WAKEUP3,High Priority Pending 3 Register"
|
|
bitfld.long 0x0c 31. " WAKEUP[127] ,Wakeup Configuration 127" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 30. " WAKEUP[126] ,Wakeup Configuration 126" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " WAKEUP[125] ,Wakeup Configuration 125" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 28. " WAKEUP[124] ,Wakeup Configuration 124" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " WAKEUP[123] ,Wakeup Configuration 123" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 26. " WAKEUP[122] ,Wakeup Configuration 122" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " WAKEUP[121] ,Wakeup Configuration 121" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 24. " WAKEUP[120] ,Wakeup Configuration 120" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " WAKEUP[119] ,Wakeup Configuration 119" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 22. " WAKEUP[118] ,Wakeup Configuration 118" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " WAKEUP[117] ,Wakeup Configuration 117" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 20. " WAKEUP[116] ,Wakeup Configuration 116" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " WAKEUP[115] ,Wakeup Configuration 115" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 18. " WAKEUP[114] ,Wakeup Configuration 114" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " WAKEUP[113] ,Wakeup Configuration 113" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 16. " WAKEUP[112] ,Wakeup Configuration 112" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " WAKEUP[111] ,Wakeup Configuration 111" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 14. " WAKEUP[110] ,Wakeup Configuration 110" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " WAKEUP[109] ,Wakeup Configuration 109" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 12. " WAKEUP[108] ,Wakeup Configuration 108" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " WAKEUP[107] ,Wakeup Configuration 107" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 10. " WAKEUP[106] ,Wakeup Configuration 106" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " WAKEUP[105] ,Wakeup Configuration 105" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 8. " WAKEUP[104] ,Wakeup Configuration 104" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " WAKEUP[103] ,Wakeup Configuration 103" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 6. " WAKEUP[102] ,Wakeup Configuration 102" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " WAKEUP[101] ,Wakeup Configuration 101" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 4. " WAKEUP[100] ,Wakeup Configuration 100" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " WAKEUP[99] ,Wakeup Configuration 99" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 2. " WAKEUP[98] ,Wakeup Configuration 98" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " WAKEUP[97] ,Wakeup Configuration 97" "Not asserted,Asserted"
|
|
bitfld.long 0x0c 0. " WAKEUP[96] ,High Priority Interrupt Pending 96" "Not asserted,Asserted"
|
|
wgroup.long 0xf00++0x3
|
|
line.long 0x00 "SWINT,Software Interrupt Trigger Register"
|
|
bitfld.long 0x00 31. " INTNEG ,Interrupt Negate" "Not negated,Negated"
|
|
hexmask.long.word 0x00 0.--9. 1. " INTID ,Interrupt ID"
|
|
width 0xB
|
|
tree.end
|
|
tree "TVE (TV Encoder)"
|
|
base ad:0x83ff0000
|
|
width 21.
|
|
if ((per.l(ad:0x83ff0000+0x00)&0xf00)==(0x0||0x100||0x200||0x300))
|
|
; SD TV Standard
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COM_CONF_REG,Common Configuration Register"
|
|
bitfld.long 0x00 24.--26. " ACT_LINE_OFFSET ,Offset of the first active video data line relative to a standard value" "No offset,1-line offset,2-line offset,3-line offset,3-line offset,4-line offset,5-line offset,7-line offset"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SYNC_CH_2_EN ,Enable sync on output channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNC_CH_1_EN ,Enable sync on output channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SYNC_CH_0_EN ,Enable sync on output channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SD_PED_AMP_CONT ,Control pedestal (Y/R/G/B black-to-white/sync output amplitude/pedestal)" "714mV/286mV/no pedestal,714mV/286mV/with pedestal,700mV/300mV/no pedestal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " TV_OUT_MODE ,Select the TV output mode" "Disabled,CVBS on ch. #0,CVBS on ch. #2,CVBS on chs. #0 & #2,S-video on chs. #0 & #1,S-video on chs. #0 & #1 and CVBS on ch. #2,YPbPr component,RGB component"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TV_STAND ,Select the TV standards" "SD NTSC,SD PALM,SD Combination PALN,SD PAL (B D G H I),HD 720p60,HD 720p50,HD 720p30,HD 720p25,HD 720p24,HD 1080i60,HD 1080i50,HD 1035i60 (1920x1035),HD 1080p30,HD 1080p25,HD 1080p24,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P2I_CONV_EN ,Enable progressive to interlaced conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INP_VIDEO_FORM ,Select input video format" "YCbCr 4:2:2,YCbCr 4:4:4"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATA_SOURCE_SEL ,Select data source" "Video data bus 1,Video data bus 2,Ext test data bus,Int Color Bar Generator"
|
|
bitfld.long 0x00 3. " IPU_CLK_EN ,Enable clock output for the IPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " TVDAC_SAMP_RATE ,TVDAC sampling rate SD TV" "216 MHz,108 MHz,54 MHz,?..."
|
|
bitfld.long 0x00 0. " TVE_EN ,Enable the TVE" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x83ff0000+0x00)&0xf00)==0xf00)
|
|
; Reserved TV Standard
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COM_CONF_REG,Common Configuration Register"
|
|
bitfld.long 0x00 24.--26. " ACT_LINE_OFFSET ,Offset of the first active video data line relative to a standard value" "No offset,1-line offset,2-line offset,3-line offset,3-line offset,4-line offset,5-line offset,7-line offset"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SYNC_CH_2_EN ,Enable sync on output channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNC_CH_1_EN ,Enable sync on output channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SYNC_CH_0_EN ,Enable sync on output channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SD_PED_AMP_CONT ,Control pedestal (Y/R/G/B black-to-white/sync output amplitude/pedestal)" "714mV/286mV/no pedestal,714mV/286mV/with pedestal,700mV/300mV/no pedestal,?..."
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TV_STAND ,Select the TV standards" "SD NTSC,SD PALM,SD Combination PALN,SD PAL (B D G H I),HD 720p60,HD 720p50,HD 720p30,HD 720p25,HD 720p24,HD 1080i60,HD 1080i50,HD 1035i60 (1920x1035),HD 1080p30,HD 1080p25,HD 1080p24,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P2I_CONV_EN ,Enable progressive to interlaced conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INP_VIDEO_FORM ,Select input video format" "YCbCr 4:2:2,YCbCr 4:4:4"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATA_SOURCE_SEL ,Select data source" "Video data bus 1,Video data bus 2,Ext test data bus,Int Color Bar Generator"
|
|
bitfld.long 0x00 3. " IPU_CLK_EN ,Enable clock output for the IPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TVE_EN ,Enable the TVE" "Disabled,Enabled"
|
|
else
|
|
; HD TV Standard
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "COM_CONF_REG,Common Configuration Register"
|
|
bitfld.long 0x00 24.--26. " ACT_LINE_OFFSET ,Offset of the first active video data line relative to a standard value" "No offset,1-line offset,2-line offset,3-line offset,3-line offset,4-line offset,5-line offset,7-line offset"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SYNC_CH_2_EN ,Enable sync on output channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNC_CH_1_EN ,Enable sync on output channel 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SYNC_CH_0_EN ,Enable sync on output channel 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SD_PED_AMP_CONT ,Control pedestal (black-to-white/sync/pedestal)" "714mV/286mV/no pedestal,714mV/286mV/with pedestal,700mV/300mV/no pedestal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " TV_OUT_MODE ,Select the TV output mode" "Disabled,Reserved,Reserved,Reserved,Reserved,Reserved,YPbPr component,RGB component"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " TV_STAND ,Select the TV standards" "SD NTSC,SD PALM,SD Combination PALN,SD PAL (B D G H I),HD 720p60,HD 720p50,HD 720p30,HD 720p25,HD 720p24,HD 1080i60,HD 1080i50,HD 1035i60 (1920x1035),HD 1080p30,HD 1080p25,HD 1080p24,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P2I_CONV_EN ,Enable progressive to interlaced conversion" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " INP_VIDEO_FORM ,Select input video format" "YCbCr 4:2:2,YCbCr 4:4:4"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DATA_SOURCE_SEL ,Select data source" "Video data bus 1,Video data bus 2,Ext test data bus,Int Color Bar Generator"
|
|
bitfld.long 0x00 3. " IPU_CLK_EN ,Enable clock output for the IPU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " TVDAC_SAMP_RATE ,TVDAC sampling rate HD TV" "297 MHz,148.5 MHz,?..."
|
|
bitfld.long 0x00 0. " TVE_EN ,Enable the TVE" "Disabled,Enabled"
|
|
endif
|
|
width 21.
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "LUMA_FILT_CONT_REG_0,Luma Filter Control Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DEFLICK_LOW_THRESH ,Vertical deflickering/ fine sharpening/high-frequency noise reduction high threshold"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DEFLICK_MID_THRESH ,Vertical deflickering/ fine sharpening/high-frequency noise reduction mid threshold"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " DEFLICK_LOW_THRESH ,Vertical deflickering/ fine sharpening/high-frequency noise reduction low threshold"
|
|
bitfld.long 0x00 4.--6. " DEFLICK_COE ,Vertical deflickering/ fine sharpening/high-frequency noise reduction coefficient" "0.125,0.25,0.375,0.5,0.625,0.75,0.875,1.0"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DEFLICK_MEAS_WIN ,Select vertical deflickering/ fine sharpening/high-frequency noise reduction measurement window" "1 pixel window,3 pixels window"
|
|
bitfld.long 0x00 0. " DEFLICK_EN ,Enable vertical deflickering/ fine sharpening/high-frequency noise reduction filter" "Disabled,Enabled"
|
|
line.long 0x04 "LUMA_FILT_CONT_REG_1,Luma Filter Control Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " V_SHARP_LOW_THRESH ,Vertical coarse sharpening/ mid-frequency noise reduction high threshold"
|
|
hexmask.long.byte 0x04 8.--15. 1. " V_SHARP_LOW_THRESH ,Vertical coarse sharpening/ mid-frequency noise reduction low threshold"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " V_SHARP_COEF ,Vertical coarse sharpening/ mid-frequency noise reduction coefficient" "0.125,0.25,0.375,0.5,0.625,0.75,0.875,1.0"
|
|
bitfld.long 0x04 0. " V_SHARP_EN ,Enable vertical coarse sharpening/ mid-frequency noise reduction filter" "Disabled,Enabled"
|
|
line.long 0x08 "LUMA_FILT_CONT_REG_2,Luma Filter Control Register 2"
|
|
hexmask.long.byte 0x08 24.--31. 1. " H_SHARP_LOW_THRESH ,Horizontal coarse sharpening/ mid-frequency noise reduction high threshold"
|
|
hexmask.long.byte 0x08 8.--15. 1. " H_SHARP_LOW_THRESH ,Horizontal coarse sharpening/ mid-frequency noise reduction low threshold"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " H_SHARP_COEF ,Horizontal coarse sharpening/ mid-frequency noise reduction coefficient" "0.125,0.25,0.375,0.5,0.625,0.75,0.875,1.0"
|
|
bitfld.long 0x08 0. " H_SHARP_EN ,Enable horizontal coarse sharpening/ mid-frequency noise reduction filter" "Disabled,Enabled"
|
|
line.long 0x0c "LUMA_FILT_CONT_REG_3,Luma Filter Control Register 3"
|
|
hexmask.long.byte 0x0c 24.--31. 1. " DERING_LOW_THRESH ,Horizontal deringing/ fine sharpening/high-frequency noise reduction high threshold"
|
|
hexmask.long.byte 0x0c 16.--23. 1. " DERING_MID_THRESH ,Horizontal deringing/ fine sharpening/high-frequency noise reduction mid threshold"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 8.--15. 1. " DERING_LOW_THRESH ,Horizontal deringing/ fine sharpening/high-frequency noise reduction low threshold"
|
|
bitfld.long 0x0c 4.--6. " DERING_COEF ,Horizontal deringing/ fine sharpening/high-frequency noise reduction coefficient" "0.125,0.25,0.375,0.5,0.625,0.75,0.875,1.0"
|
|
textline " "
|
|
bitfld.long 0x0c 1.--2. " SUPP_FILTER_TYPE ,Select supplement filter type" "No supplement filter,Lowpass filter,PAL notch filter (4.43 MHz),NTSC notch filter (3.58 MHz)"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " DERING_EN ,Enable horizontal deringing/ fine sharpening/high-frequency noise reduction filter" "Disabled,Enabled"
|
|
line.long 0x10 "LUMA_SA_CONT_REG_0,Luma Statistic Analysis Control Register 0"
|
|
bitfld.long 0x10 8.--9. " SA_V_POINTS_NUM ,Select number of vertical points (lines) used for statistic analysis" "256 points,128 points,64 points,32 points"
|
|
bitfld.long 0x10 4.--5. " SA_H_POINTS_NUM ,Select number of horizontal points (pixels in a line) used for statistic analysis" "256 points,128 points,64 points,32 points"
|
|
textline " "
|
|
bitfld.long 0x10 0. " LUMA_SA_EN ,Enable luma statistic analysis" "Disabled,Enabled"
|
|
line.long 0x14 "LUMA_SA_CONT_REG_1,Luma Statistic Analysis Control Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. " SA_WIN_V_OFFSET ,Statistic analysis window vertical offset relative to start of an input active video data frame/field"
|
|
hexmask.long.byte 0x14 16.--23. 1. " SA_WIN_H_OFFSET ,Statistic analysis window horizontal offset relative to start of an input active video data line"
|
|
textline " "
|
|
hexmask.long.byte 0x14 8.--15. 1. " SA_WIN_HEIGHT ,Statistic analysis window height"
|
|
hexmask.long.byte 0x14 0.--7. 1. " SA_WIN_WIDTH ,Statistic analysis window width"
|
|
rgroup.long 0x1c++0x07
|
|
line.long 0x00 "LUMA_SA_STAT_REG_0,Luma Statistic Analysis Status Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DERING_MEAS_MEAN ,Mean absolute value of horizontal deringing/ fine sharpening/high-frequency noise reduction measurement filter output"
|
|
hexmask.long.byte 0x00 16.--23. 1. " H_SHARP_MEAS_MEAN ,Mean absolute value of horizontal coarse sharpening/ mid-frequency noise reduction measurement filter output"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " V_SHARP_MEAS_MEAN ,Mean absolute value of vertical coarse sharpening/ mid-frequency noise reduction measurement filter output"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DEFLICK_MEAS_MEAN ,Mean absolute value of vertical deflickering/ fine sharpening/high-frequency noise reduction measurement filter output"
|
|
line.long 0x04 "LUMA_SA_STAT_REG_1,Luma Statistic Analysis Status Register 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LUMA_MEAN ,Mean value of Luma"
|
|
width 21.
|
|
if (((per.l(ad:0x83ff0000+0x00)&0xf00)==(0x0||0x100||0x200||0x300)&&(per.l(ad:0x83ff0000+0x00)&0x40)==0x00))
|
|
; SD YCbCr 4:2:2
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CHROMA_CONT_REG,Chroma Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCH_PHASE ,Subcurrier initial phase offset"
|
|
bitfld.long 0x00 4.--6. " CHROMA_BW ,Select Chroma filter bandwidth" "0.6 MHz,1.0 MHz,1.3 MHz,2.0 MHz,3.0 MHz,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHROMA_V_FILT_EN ,Enable vertical chroma filter" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x83ff0000+0x00)&0xf00)==(0x0||0x100||0x200||0x300)&&(per.l(ad:0x83ff0000+0x00)&0x40)==0x40)
|
|
; SD YCbCr 4:4:4
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CHROMA_CONT_REG,Chroma Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCH_PHASE ,Subcurrier initial phase offset"
|
|
bitfld.long 0x00 4.--6. " CHROMA_BW ,Select Chroma filter bandwidth" "1.2 MHz,2.0 MHz,3.0 MHz,4.0 MHz,6.4 MHz,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHROMA_V_FILT_EN ,Enable vertical chroma filter" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x83ff0000+0x00)&0xf00)==(0x400--0xe00)&&(per.l(ad:0x83ff0000+0x00)&0x40)==0x0)
|
|
; HD YCbCr 4:2:2
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CHROMA_CONT_REG,Chroma Control Register"
|
|
bitfld.long 0x00 4.--6. " CHROMA_BW ,Select Chroma filter bandwidth" "3.3 MHz,5.5 MHz,7.1 MHz,11.0 MHz,16.5 MHz,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHROMA_V_FILT_EN ,Enable vertical chroma filter" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x83ff0000+0x00)&0xf00)==(0x400--0xe00)&&(per.l(ad:0x83ff0000+0x00)&0x40)==0x40)
|
|
; HD YCbCr 4:4:4
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CHROMA_CONT_REG,Chroma Control Register"
|
|
bitfld.long 0x00 4.--6. " CHROMA_BW ,Select Chroma filter bandwidth" "6.6 MHz,11.0 MHz,16.5 MHz,22.0 MHz,35.2 MHz,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHROMA_V_FILT_EN ,Enable vertical chroma filter" "Disabled,Enabled"
|
|
else
|
|
; Reserved
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "CHROMA_CONT_REG,Chroma Control Register"
|
|
endif
|
|
width 21.
|
|
group.long 0x28++0x9f
|
|
line.long 0x00 "TVDAC_0_CONT_REG,TVDAC 0 Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BG_RDY_TIME ,TVDAC bandgap reference ready time"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TVDAC_0_OFFSET ,Offset value in the 2 complement format for the TVDAC channel #0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " TVDAC_0_GAIN ,Select gain value for the TVDAC channel #0"
|
|
line.long 0x04 "TVDAC_1_CONT_REG,TVDAC 1 Control Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TVDAC_1_OFFSET ,Offset value in the 2 complement format for the TVDAC channel #1"
|
|
hexmask.long.byte 0x04 0.--5. 1. " TVDAC_1_GAIN ,Select gain value for the TVDAC channel #1"
|
|
line.long 0x08 "TVDAC_2_CONT_REG,TVDAC 2 Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " TVDAC_2_OFFSET ,Offset value in the 2 complement format for the TVDAC channel #2"
|
|
hexmask.long.byte 0x08 0.--5. 1. " TVDAC_2_GAIN ,Select gain value for the TVDAC channel #2"
|
|
line.long 0x0c "CD_CONT_REG,Cable Detection Control Register"
|
|
bitfld.long 0x0C 22. " CD_CH_2_SM_EN ,TVDAC channel #2 short monitoring enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " CD_CH_1_SM_EN ,TVDAC channel #1 short monitoring enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " CD_CH_2_SM_EN ,TVDAC channel #0 short monitoring enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " CD_CH_2_LM_EN ,TVDAC channel #2 load impedance monitoring enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " CD_CH_1_LM_EN ,TVDAC channel #1 load impedance monitoring enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " CD_CH_2_LM_EN ,TVDAC channel #0 load impedance monitoring enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CD_REF_MODE ,CD reference mode" "Automatic,Manual"
|
|
bitfld.long 0x0C 10. " CD_CH_2_REF_LVL ,CD reference level for TVDAC channel #2" "Luma,Chroma"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " CD_CH_1_REF_LVL ,CD reference level for TVDAC channel #1" "Luma,Chroma"
|
|
bitfld.long 0x0C 8. " CD_CH_0_REF_LVL ,CD reference level for TVDAC channel #0" "Luma,Chroma"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--7. " CD_MON_PER ,Cable detection monitoring period" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0C 1. " CD_TRIG_MODE ,CD trigger mode" "Automatic,Manual"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CD_EN ,Enable cable detection" "Disabled,Enabled"
|
|
line.long 0x10 "VBI_DATA_CONT_REG,VBI Data Control Register"
|
|
hexmask.long.byte 0x10 24.--29. 1. " CGMS_HD_B_F2_HEADER ,HD CGMS Type B header for field 2"
|
|
hexmask.long.byte 0x10 16.--21. 1. " CGMS_HD_B_F1_HEADER ,HD CGMS Type B header for field 1"
|
|
textline " "
|
|
bitfld.long 0x10 14. " CGMS_HD_B_SW_CRC_EN ,Enable HD CGMS Type B CRC value calculated by software" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " CGMS_HD_B_F2_EN ,Enable HD CGMS Type B data insertion for field 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 12. " CGMS_HD_B_F1_EN ,Enable HD CGMS Type B data insertion for field 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " CGMS_HD_A_SW_CRC_EN ,Enable HD CGMS Type A CRC value calculated by software" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " CGMS_HD_A_F2_EN ,Enable HD CGMS Type A data insertion for field 2" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " CGMS_HD_A_F1_EN ,Enable HD CGMS Type A data insertion for field 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " WSS_SD_EN ,Enable SD WSS data insertion" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " CGMS_SD_SW_CRC_EN ,Enable SD CGMS CRC value calculated by software" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " CGMS_SD_F2_EN ,Enable SD CGMS data insertion for field 2" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " CGMS_SD_F1_EN ,Enable SD CGMS data insertion for field 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " CC_SD_BOOST_EN ,Enable SD closed caption level boost by a factor of 1.7" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " CC_SD_F2_EN ,Enable SD closed caption data insertion for field 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CC_SD_F1_EN ,Enable SD closed caption data insertion for field 1" "Disabled,Enabled"
|
|
line.long 0x14 "VBI_DATA_REG_0,VBI Data Register 0"
|
|
hexmask.long.tbyte 0x14 0.--19. 1. " CGMS_SD_HD_A_F1_DATA ,CGMS data (in SD mode) or CGMS Type A data (in HD mode) for field 1"
|
|
line.long 0x18 "VBI_DATA_REG_1,VBI Data Register 1"
|
|
hexmask.long.tbyte 0x18 0.--19. 1. " CGMS_SD_HD_A_F2_DATA ,CGMS data (in SD mode) or CGMS Type A data (in HD mode) for field 2"
|
|
line.long 0x1c "VBI_DATA_REG_2,VBI Data Register 2"
|
|
line.long 0x20 "VBI_DATA_REG_3,VBI Data Register 3"
|
|
line.long 0x24 "VBI_DATA_REG_4,VBI Data Register 4"
|
|
line.long 0x28 "VBI_DATA_REG_5,VBI Data Register 5"
|
|
line.long 0x2c "VBI_DATA_REG_6,VBI Data Register 6"
|
|
line.long 0x30 "VBI_DATA_REG_7,VBI Data Register 7"
|
|
line.long 0x34 "VBI_DATA_REG_8,VBI Data Register 8"
|
|
line.long 0x38 "VBI_DATA_REG_9,VBI Data Register 9"
|
|
line.long 0x3c "INT_CONT_REG,Interrupt Control Register"
|
|
bitfld.long 0x3c 14. " SA_MEAS_END_IEN ,Enable Luma statistic measurement end interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x3c 13. " TVE_FRAME_END_IEN ,Enable end-of-field interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 12. " TVE_FIELD_END_IEN ,Enable end-of-frame interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x3c 11. " CGMS_HD_B_F2_DONE_IEN ,Enable HD CGMS Type B done interrupt for field 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 10. " CGMS_HD_B_F1_DONE_IEN ,Enable HD CGMS Type B done interrupt for field 1" "Disabled,Enabled"
|
|
bitfld.long 0x3c 9. " CGMS_HD_A_F2_DONE_IEN ,Enable HD CGMS Type A done interrupt for field 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 8. " CGMS_HD_A_F1_DONE_IEN ,Enable HD CGMS Type A done interrupt for field 1" "Disabled,Enabled"
|
|
bitfld.long 0x3c 7. " WSS_SD_DONE_IEN ,Enable SD WSS done interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 6. " CGMS_SD_F2_DONE_IEN ,Enable SD CGMS done interrupt for field 2" "Disabled,Enabled"
|
|
bitfld.long 0x3c 5. " CGMS_SD_F1_DONE_IEN ,Enable SD CGMS done interrupt for field 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 4. " CC_SD_F2_DONE_IEN ,Enable SD closed caption done interrupt for field 2" "Disabled,Enabled"
|
|
bitfld.long 0x3c 3. " CC_SD_F1_DONE_IEN ,Enable SD closed caption done interrupt for field 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 2. " CD_MON_END_IEN ,Enable CD end-of-monitoring interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x3c 1. " CD_SM_IEN ,Enable CD short monitoring interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3c 0. " CD_LM_IEN ,Enable CD load resistance monitoring interrupt" "Disabled,Enabled"
|
|
line.long 0x40 "STAT_REG,Status Register"
|
|
bitfld.long 0x40 25. " BG_READY ,Status bit of bandgap reference of the TVDAC" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x40 24. " CD_MAN_TRIG ,Control/status bit for manual (single shot) trigger of CD monitors" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x40 22. " CD_CH_2_SM_ST ,Status bit of TVDAC channel #2 short monitoring by CD" "Detected,Not detected"
|
|
bitfld.long 0x40 21. " CD_CH_1_SM_ST ,Status bit of TVDAC channel #1 short monitoring by CD" "Detected,Not detected"
|
|
textline " "
|
|
bitfld.long 0x40 20. " CD_CH_0_SM_ST ,Status bit of TVDAC channel #0 short monitoring by CD" "Detected,Not detected"
|
|
bitfld.long 0x40 18. " CD_CH_2_LM_ST ,Status bit of TVDAC channel #2 load impedance monitoring by CD" "Detected,Not detected"
|
|
textline " "
|
|
bitfld.long 0x40 17. " CD_CH_1_LM_ST ,Status bit of TVDAC channel #1 load impedance monitoring by CD" "Detected,Not detected"
|
|
bitfld.long 0x40 16. " CD_CH_0_LM_ST ,Status bit of TVDAC channel #0 load impedance monitoring by CD" "Detected,Not detected"
|
|
textline " "
|
|
eventfld.long 0x40 14. " SA_MEAS_END_INT ,Status bit of the Luma statistic measurement end interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x40 13. " TVE_FRAME_END_INT ,Status bit of the end-of-frame interrupt" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x40 12. " TVE_FIELD_END_INT ,Status bit of the end-of-field interrupt" "Not occurred,Occurred"
|
|
eventfld.long 0x40 11. " CGMS_HD_B_F2_DONE_IEN ,Status bit of the HD CGMS Type B done interrupt for field 2" "Not done,Done"
|
|
textline " "
|
|
eventfld.long 0x40 10. " CGMS_HD_B_F1_DONE_IEN ,Status bit of the HD CGMS Type B done interrupt for field 1" "Not done,Done"
|
|
eventfld.long 0x40 9. " CGMS_HD_A_F2_DONE_IEN ,Status bit of the HD CGMS Type A done interrupt for field 2" "Not done,Done"
|
|
textline " "
|
|
eventfld.long 0x40 8. " CGMS_HD_A_F1_DONE_IEN ,Status bit of the HD CGMS Type A done interrupt for field 1" "Not done,Done"
|
|
eventfld.long 0x40 7. " WSS_SD_DONE_IEN ,Status bit of the SD WSS done interrupt" "Not done,Done"
|
|
textline " "
|
|
eventfld.long 0x40 6. " CGMS_SD_F2_DONE_IEN ,Status bit of the SD CGMS done interrupt for field 2" "Not done,Done"
|
|
eventfld.long 0x40 5. " CGMS_SD_F1_DONE_IEN ,Status bit of the SD CGMS done interrupt for field 1" "Not done,Done"
|
|
textline " "
|
|
eventfld.long 0x40 4. " CC_SD_F2_DONE_IEN ,Status bit of the SD Closed Caption done interrupt for field 2" "Not done,Done"
|
|
eventfld.long 0x40 3. " CC_SD_F1_DONE_IEN ,Status bit of the SD Closed Caption done interrupt for field 1" "Not done,Done"
|
|
textline " "
|
|
eventfld.long 0x40 2. " CD_MON_END_INT ,Status bit of the end-of-monitoring interrupt by CD" "Not occurred,Occurred"
|
|
eventfld.long 0x40 1. " CD_SM_INT ,Status bit of the short monitoring interrupt by CD" "No detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x40 0. " CD_LM_INT ,Status bit of the load impedance monitoring interrupt by CD" "Not detected,Detected"
|
|
line.long 0x44 "TST_MODE_REG,Test Mode Register"
|
|
bitfld.long 0x44 16. " COLORBAR_TYPE ,Select the type of internally generated color bar" "100%,75%"
|
|
bitfld.long 0x44 12.--13. " TVDAC_TEST_SINE_LEVEL ,Select level of internally generated sine wave pattern" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x44 8.--10. " TVDAC_TEST_SINE_FREQ ,Select frequency of internally generated sine wave pattern" "8,16,32,64,128,256,?..."
|
|
bitfld.long 0x44 6. " TVDAC_2_DATA_FORCE ,Enable forcing input of TVDAC channel #2 by value defined in BLANKING_CH_2_USR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 5. " TVDAC_1_DATA_FORCE ,Enable forcing input of TVDAC channel #1 by value defined in BLANKING_CH_1_USR" "Disabled,Enabled"
|
|
bitfld.long 0x44 4. " TVDAC_0_DATA_FORCE ,Enable forcing input of TVDAC channel #0 by value defined in BLANKING_CH_0_USR" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 0.--2. " TVDAC_TEST_MODE ,Select TVDAC test mode" "Disabled,1,2,3,4,5,?..."
|
|
width 26.
|
|
line.long 0x48 "USER_MODE_CONT_REG,User Mode Control Register"
|
|
bitfld.long 0x48 5. " VBI_DATA_USR_MODE_EN ,Enable user mode for VBI data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 4. " BLANK_LEVEL_USR_MODE_EN ,Enable user mode for blank level" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 3. " CSCM_COEF_USR_MODE_EN ,Enable user mode for color space conversion matrix" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 2. " SC_FREQ_USR_MODE_EN ,Enable user mode for subcarrier frequency" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 1. " LUMA_FILT_USR_MODE_EN ,Enable user mode for Luma filtering" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x48 0. " H_TIMING_USR_MODE_EN ,Enable user mode for horizontal timing" "Disabled,Enabled"
|
|
line.long 0x4c "SD_TIMING_USR_CONT_REG_0,SD Timing User Control Register 0"
|
|
hexmask.long.word 0x4c 20.--29. 1. " SD_VBI_T1_USR ,User defined horizontal timing interval t2 for VBI lines in SD mode"
|
|
hexmask.long.word 0x4c 8.--17. 1. " SD_VBI_T1_USR ,User defined horizontal timing interval t1 for VBI lines in SD mode"
|
|
textline " "
|
|
bitfld.long 0x4c 0.--5. " SD_VBI_T0_USR ,User defined horizontal timing interval t0 for VBI lines in SD mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
line.long 0x50 "SD_TIMING_USR_CONT_REG_1,SD Timing User Control Register 1"
|
|
hexmask.long.byte 0x50 24.--30. 1. " SD_ACT_T3_USR ,User defined horizontal timing interval t3 for active data lines in SD mode"
|
|
hexmask.long.byte 0x50 16.--22. 1. " SD_ACT_T2_USR ,User defined horizontal timing interval t2 for active data lines in SD mode"
|
|
textline " "
|
|
bitfld.long 0x50 8.--12. " SD_ACT_T1_USR ,User defined horizontal timing interval t1 for active data lines in SD mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
hexmask.long.byte 0x50 0.--6. 1. " SD_ACT_T0_USR ,User defined horizontal timing interval t0 for active data lines in SD mode"
|
|
line.long 0x54 "SD_TIMING_USR_CONT_REG_2,SD Timing User Control Register 2"
|
|
bitfld.long 0x54 24.--29. " SD_ACT_T6_USR ,User defined horizontal timing interval t6 for active data lines in SD mode" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
|
|
hexmask.long.word 0x54 12.--21. 1. " SD_ACT_T5_USR ,User defined horizontal timing interval t5 for active data lines in SD mode"
|
|
textline " "
|
|
hexmask.long.word 0x54 0.--10. 1. " SD_ACT_T4_USR ,User defined horizontal timing interval t4 for active data lines in SD mode"
|
|
line.long 0x58 "HD_TIMING_USR_CONT_REG_0,HD Timing User Control Register 0"
|
|
hexmask.long.word 0x58 20.--30. 1. " HD_VBI_T2_USR ,User defined horizontal timing interval t2 for VBI lines in HD mode"
|
|
hexmask.long.word 0x58 8.--16. 1. " HD_VBI_T1_USR ,User defined horizontal timing interval t1 for VBI lines in HD mode"
|
|
textline " "
|
|
hexmask.long.byte 0x58 0.--6. 1. " HD_VBI_ACT_T0_USR ,User defined horizontal timing interval t0 for both VBI and active data lines in HD mode"
|
|
line.long 0x5c "HD_TIMING_USR_CONT_REG_1,HD Timing User Control Register 1"
|
|
hexmask.long.word 0x5c 16.--24. 1. " HD_ACT_T1_USR ,User defined horizontal timing interval t1 for active data lines in HD mode"
|
|
hexmask.long.word 0x5c 0.--12. 1. " HD_VBI_T3_USR ,User defined horizontal timing interval t3 for VBI lines in HD mode"
|
|
line.long 0x60 "HD_TIMING_USR_CONT_REG_2,HD Timing User Control Register 2"
|
|
hexmask.long.word 0x60 16.--28. 1. " HD_ACT_T3_USR ,User defined horizontal timing interval t1 for active data lines in HD mode"
|
|
hexmask.long.word 0x60 0.--11. 1. " HD_ACT_T2_USR ,User defined horizontal timing interval t3 for active data lines in HD mode"
|
|
line.long 0x64 "LUMA_USR_CONT_REG_0,Luma User Control Register 0"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " DEFLICK_MASK_MATRIX_USR ,Matrix for vertical deflickering/ fine sharpening/high-frequency noise reduction luma filter"
|
|
line.long 0x68 "LUMA_USR_CONT_REG_1,Luma User Control Register 1"
|
|
hexmask.long.tbyte 0x68 0.--23. 1. " V_SHARP_MASK_MATRIX_USR ,Matrix for vertical coarse sharpening/mid-frequency noise reduction luma filter"
|
|
line.long 0x6c "LUMA_USR_CONT_REG_2,Luma User Control Register 2"
|
|
hexmask.long.tbyte 0x6c 0.--23. 1. " H_SHARP_MASK_MATRIX_USR ,Matrix for horizontal coarse sharpening/mid-frequency noise reduction luma filter"
|
|
line.long 0x70 "LUMA_USR_CONT_REG_3,Luma User Control Register 3"
|
|
hexmask.long.tbyte 0x70 0.--23. 1. " DERING_MASK_MATRIX_USR ,Matrix for horizontal dringing/ fine sharpening/high-frequency noise reduction luma filter"
|
|
line.long 0x74 "CSC_USR_CONT_REG_0,Color Space Conversion User Control Register 0"
|
|
hexmask.long.word 0x74 16.--26. 1. " CSCM_A_COEF_USR ,User defined CSC coefficient A"
|
|
hexmask.long.byte 0x74 8.--13. 1. " BRIGHT_CORR_USR ,User defined brightness correction offset in 2 complement format"
|
|
textline " "
|
|
sif (cpu()=="IMX53"||cpu()=="IMX534"||cpu()=="IMX535"||cpu()=="IMX536"||cpu()=="IMX537"||cpu()=="IMX538")
|
|
bitfld.long 0x74 0. " DATA_CLIP_USR ,User defined lower clipping level for CSC output data" "128,64"
|
|
else
|
|
bitfld.long 0x74 0. " DATA_CLIP_USR ,User defined lower clipping level for CSC output data" "192,128"
|
|
endif
|
|
line.long 0x78 "CSC_USR_CONT_REG_1,Color Space Conversion User Control Register 1"
|
|
hexmask.long.word 0x78 16.--26. 1. " CSCM_C_COEF_USR ,User defined CSC coefficient C"
|
|
hexmask.long.word 0x78 0.--11. 1. " CSCM_B_COEF_USR ,User defined CSC coefficient B"
|
|
line.long 0x7c "CSC_USR_CONT_REG_2,Color Space Conversion User Control Register 2"
|
|
hexmask.long.word 0x7c 16.--28. 1. " CSCM_E_COEF_USR ,User defined CSC coefficient E"
|
|
hexmask.long.word 0x7c 0.--11. 1. " CSCM_D_COEF_USR ,User defined CSC coefficient D"
|
|
line.long 0x80 "BLANK_USR_CONT_REG,Blanking Level User Control Register"
|
|
hexmask.long.word 0x80 20.--29. 1. " BLANKING_CH_2_USR ,User defined blanking level for channel #2"
|
|
hexmask.long.word 0x80 10.--19. 1. " BLANKING_CH_1_USR ,User defined blanking level for channel #1"
|
|
textline " "
|
|
hexmask.long.word 0x80 0.--9. 1. " BLANKING_CH_0_USR ,User defined blanking level for channel #0"
|
|
line.long 0x84 "SD_MOD_USR_CONT_REG,SD Modulation User Control Register"
|
|
hexmask.long 0x84 0.--29. 1. " SC_FREQ_USR ,User defined subcarrier frequency factor"
|
|
width 26.
|
|
line.long 0x88 "VBI_DATA_USR_CONT_REG_0,VBI Data User Control Register 0"
|
|
hexmask.long.word 0x88 16.--27. 1. " VBI_DATA_STOP_TIME_USR ,User defined stop time for switching from VBI data mode to video mode"
|
|
textline " "
|
|
hexmask.long.word 0x88 0.--11. 1. " VBI_DATA_START_TIME_USR ,User defined start time for switching from video mode to VBI data mode"
|
|
line.long 0x8c "VBI_DATA_USR_CONT_REG_1,VBI Data User Control Register 1"
|
|
hexmask.long.word 0x8c 0.--11. 1. " VBI_PACKET_START_TIME_USR ,User defined VBI data packet start time"
|
|
line.long 0x90 "VBI_DATA_USR_CONT_REG_2,VBI Data User Control Register 2"
|
|
hexmask.long.word 0x90 16.--26. 1. " CC_SD_RUNIN_DIV_NUM_USR ,User defined numerator of the run-in frequency division factor for Closed Caption in SD mode"
|
|
textline " "
|
|
hexmask.long.word 0x90 0.--11. 1. " CC_SD_RUNIN_START_TIME_USR ,User defined run-in sequence start time for Closed Caption in SD mode"
|
|
line.long 0x94 "VBI_DATA_USR_CONT_REG_3,VBI Data User Control Register 3"
|
|
hexmask.long.word 0x94 16.--28. 1. " CC_SD_CGMS_HD_B_DIV_DENOM_USR ,User defined denominator of the data rate division factor for Closed Caption in SD mode and CGMS Type B in HD mode"
|
|
textline " "
|
|
hexmask.long.byte 0x94 0.--6. 1. " CC_SD_CGMS_HD_B_DIV_NUM_USR ,User defined numerator of the data rate division factor for Closed Caption in SD mode and CGMS Type B in HD mode"
|
|
line.long 0x98 "VBI_DATA_USR_CONT_REG_4,VBI Data User Control Register 4"
|
|
hexmask.long.word 0x98 16.--28. 1. " WSS_CGMS_SD_CGMS_HD_A_DIV_DENOM_USR ,User defined denominator of the data rate division factor for WSS/CGMS in SD mode and CGMS Type A in HD mode"
|
|
textline " "
|
|
hexmask.long.byte 0x98 0.--6. 1. " WSS_CGMS_SD_CGMS_HD_A_DIV_NUM_USR ,User defined numerator of the data rate division factor for WSS/CGMS in SD mode and CGMS Type A in HD mode"
|
|
line.long 0x9c "DROP_COMP_USR_CONT_REG,Drop Compensation User Control Register"
|
|
bitfld.long 0x9c 8.--11. " TVDAC_2_DROP_COMP ,User defined frequency response drop compensation coefficient Kdc for the TVDAC channel #2" "0,1/256,2/256,3/256,4/256,5/256,6/256,7/256,8/256,9/256,10/256,11/256,12/256,13/256,14/256,15/256"
|
|
textline " "
|
|
bitfld.long 0x9c 4.--7. " TVDAC_1_DROP_COMP ,User defined frequency response drop compensation coefficient Kdc for the TVDAC channel #1" "0,1/256,2/256,3/256,4/256,5/256,6/256,7/256,8/256,9/256,10/256,11/256,12/256,13/256,14/256,15/256"
|
|
textline " "
|
|
bitfld.long 0x9c 0.--3. " TVDAC_0_DROP_COMP ,User defined frequency response drop compensation coefficient Kdc for the TVDAC channel #0" "0,1/256,2/256,3/256,4/256,5/256,6/256,7/256,8/256,9/256,10/256,11/256,12/256,13/256,14/256,15/256"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
|
|
tree "UART1"
|
|
base ad:0x73fbc000
|
|
width 7.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "URXD,UART Receiver Register"
|
|
in
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x00 "UTXD,UART Transmitter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "UCR1,UART Control Register 1"
|
|
bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames"
|
|
bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent"
|
|
bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UCR2,UART Control Register 2"
|
|
bitfld.long 0x04 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored"
|
|
bitfld.long 0x04 13. " CTSC ,CTS Pin Control" "CTS,Receiver"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CTS ,Clear to Send" "High,Low"
|
|
bitfld.long 0x04 11. " ESCEN ,Escape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PREN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PROE ,Parity Odd/Even" "Even,Odd"
|
|
bitfld.long 0x04 6. " STPB ,Number of stop bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WS ,Word Size" "7-bit,8-bit"
|
|
bitfld.long 0x04 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXEN ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RXEN ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SRST ,Software Reset" "Reset,No reset"
|
|
if (((per.long(ad:0x73fbc000+0x90))&0x40)==0x40)
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "DCDDELT interrupt disabled,DCDDELT interrupt enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "RIDELT interrupt disabled,RIDELT interrupt enabled"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "/DCD logic zero,/DCD logic one"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "/RI logic zero,/RI logic 1"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "UCR4,UART Control Register 4"
|
|
bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 9. " INVR ,Inverted Infrared Reception" "Active low,Active high"
|
|
bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "UFCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "Div by 6,Div by 5,Div by 4,Div by 3,Div by 2,Div by 1,Div by 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE"
|
|
bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "USR1,UART Status Register 1"
|
|
eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low"
|
|
bitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed"
|
|
eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready"
|
|
eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active"
|
|
eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle"
|
|
eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "USR2,UART Status Register 2"
|
|
eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received"
|
|
bitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected"
|
|
eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished"
|
|
eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected"
|
|
eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed"
|
|
bitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected"
|
|
eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready"
|
|
group.long 0x9c++0x3
|
|
line.long 0x00 "UESC,UART Escape Character Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character"
|
|
group.long 0xa0++0x0b
|
|
line.long 0x00 "UTIM,UART Escape Timer Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer"
|
|
line.long 0x04 "UBIR,UART BRM Incremental Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Register"
|
|
line.long 0x08 "UBMR,Modulator Dominator"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator"
|
|
rgroup.long 0xac++0x3
|
|
line.long 0x00 "UBRC,UART Baud Rate Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ONEMS,UART One Millisecond Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "UTS,UART Test Register"
|
|
bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted"
|
|
bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop"
|
|
bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop"
|
|
bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented"
|
|
bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x73fc0000
|
|
width 7.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "URXD,UART Receiver Register"
|
|
in
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x00 "UTXD,UART Transmitter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "UCR1,UART Control Register 1"
|
|
bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames"
|
|
bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent"
|
|
bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UCR2,UART Control Register 2"
|
|
bitfld.long 0x04 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored"
|
|
bitfld.long 0x04 13. " CTSC ,CTS Pin Control" "CTS,Receiver"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CTS ,Clear to Send" "High,Low"
|
|
bitfld.long 0x04 11. " ESCEN ,Escape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PREN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PROE ,Parity Odd/Even" "Even,Odd"
|
|
bitfld.long 0x04 6. " STPB ,Number of stop bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WS ,Word Size" "7-bit,8-bit"
|
|
bitfld.long 0x04 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXEN ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RXEN ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SRST ,Software Reset" "Reset,No reset"
|
|
if (((per.long(ad:0x73fc0000+0x90))&0x40)==0x40)
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "DCDDELT interrupt disabled,DCDDELT interrupt enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "RIDELT interrupt disabled,RIDELT interrupt enabled"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "/DCD logic zero,/DCD logic one"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "/RI logic zero,/RI logic 1"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "UCR4,UART Control Register 4"
|
|
bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 9. " INVR ,Inverted Infrared Reception" "Active low,Active high"
|
|
bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "UFCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "Div by 6,Div by 5,Div by 4,Div by 3,Div by 2,Div by 1,Div by 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE"
|
|
bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "USR1,UART Status Register 1"
|
|
eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low"
|
|
bitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed"
|
|
eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready"
|
|
eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active"
|
|
eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle"
|
|
eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "USR2,UART Status Register 2"
|
|
eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received"
|
|
bitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected"
|
|
eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished"
|
|
eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected"
|
|
eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed"
|
|
bitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected"
|
|
eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready"
|
|
group.long 0x9c++0x3
|
|
line.long 0x00 "UESC,UART Escape Character Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character"
|
|
group.long 0xa0++0x0b
|
|
line.long 0x00 "UTIM,UART Escape Timer Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer"
|
|
line.long 0x04 "UBIR,UART BRM Incremental Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Register"
|
|
line.long 0x08 "UBMR,Modulator Dominator"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator"
|
|
rgroup.long 0xac++0x3
|
|
line.long 0x00 "UBRC,UART Baud Rate Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ONEMS,UART One Millisecond Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "UTS,UART Test Register"
|
|
bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted"
|
|
bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop"
|
|
bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop"
|
|
bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented"
|
|
bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree "UART3"
|
|
base ad:0x7000c000
|
|
width 7.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "URXD,UART Receiver Register"
|
|
in
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x00 "UTXD,UART Transmitter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit Data"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 "UCR1,UART Control Register 1"
|
|
bitfld.long 0x00 15. " ADEN ,Automatic Baud Rate Detection Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADBR ,Automatic Detection of Baud Rate" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TRDYEN ,Transmitter Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDEN ,Idle Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " ICD ,Idle Condition Detect" "4 frames,8 frames,16 frames,32 frames"
|
|
bitfld.long 0x00 9. " RRDYEN ,Receiver Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RXDMAEN ,Receive Ready DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " IREN ,Infrared Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TXMPTYEN ,Transmitter Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RTSDEN ,RTS Delta Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SNDBRK ,Send BREAK" "Not sent,Sent"
|
|
bitfld.long 0x00 3. " TXDMAEN ,Transmitter Ready DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ATDMAEN ,Aging DMA Timer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DOZE ,UART enable condition in the DOZE state" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UCR2,UART Control Register 2"
|
|
bitfld.long 0x04 15. " ESCI ,Escape Sequence Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " IRTS ,Ignore RTS Pin" "Not ignored,Ignored"
|
|
bitfld.long 0x04 13. " CTSC ,CTS Pin Control" "CTS,Receiver"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CTS ,Clear to Send" "High,Low"
|
|
bitfld.long 0x04 11. " ESCEN ,Escape Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9.--10. " RTEC ,Request to Send Edge Control" "Rising,Falling,Any,Any"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PREN ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " PROE ,Parity Odd/Even" "Even,Odd"
|
|
bitfld.long 0x04 6. " STPB ,Number of stop bits" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.long 0x04 5. " WS ,Word Size" "7-bit,8-bit"
|
|
bitfld.long 0x04 4. " RTSEN ,Request to Send Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " ATEN ,Aging Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TXEN ,Transmitter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RXEN ,Receiver Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SRST ,Software Reset" "Reset,No reset"
|
|
if (((per.long(ad:0x7000c000+0x90))&0x40)==0x40)
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "DCDDELT interrupt disabled,DCDDELT interrupt enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "RIDELT interrupt disabled,RIDELT interrupt enabled"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "UCR3,UART Control Register 3"
|
|
bitfld.long 0x00 14.--15. " DPEC ,DTR/DSR Interrupt Edge Control" "Rising,Falling,Any,Any"
|
|
bitfld.long 0x00 13. " DTREN ,Data Terminal Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PARERREN ,Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FRAERREN ,Frame Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSR ,Data Set Ready" "0,1"
|
|
bitfld.long 0x00 9. " DCD ,Data Carrier Detect" "/DCD logic zero,/DCD logic one"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RI ,Ring Indicator" "/RI logic zero,/RI logic 1"
|
|
bitfld.long 0x00 7. " ADNIMP ,Autoband Detection Not improved" "New,Old"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDSEN ,Receive Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AIRINTEN ,Asynchronous IR WAKE Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AWAKEN ,Asynchronous WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DTRDEN ,Data Terminal Ready Delta Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RXDMUXSEL ,RXD Muxed Input Selected" "Not muxed,Muxed"
|
|
bitfld.long 0x00 1. " INVT ,Inverted Infrared Transmission" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACIEN ,Autobaud Counter Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x8c++0x3
|
|
line.long 0x00 "UCR4,UART Control Register 4"
|
|
bitfld.long 0x00 10.--15. " CTSTL ,CTS Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 9. " INVR ,Inverted Infrared Reception" "Active low,Active high"
|
|
bitfld.long 0x00 8. " ENIRI ,Serial Infrared Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WKEN ,WAKE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IDDMAEN ,DMA IDLE Condition Detected Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRSC ,IR Special Case" "Sampling clock,Reference clock"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LPBYP ,Low Power Bypass" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " TCEN ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BKEN ,BREAK Condition Detected Interrupt Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OREN ,Receiver Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DREN ,Receive Data Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "UFCR,UART FIFO Control Register"
|
|
bitfld.long 0x00 10.--15. " TXTL ,Transmitter Trigger Level" "Reserved,Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
bitfld.long 0x00 7.--9. " RFDIV ,Reference Frequency Divider" "Div by 6,Div by 5,Div by 4,Div by 3,Div by 2,Div by 1,Div by 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6. " DCEDTE ,DCE/DTE mode select" "DCE,DTE"
|
|
bitfld.long 0x00 0.--5. " RXTL ,Receiver Trigger Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x94++0x3
|
|
line.long 0x00 "USR1,UART Status Register 1"
|
|
eventfld.long 0x00 15. " PARITYERR ,Parity Error Interrupt Flag" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " RTSS ,/RTS Pin Status" "High,Low"
|
|
bitfld.long 0x00 13. " TRDY ,Transmitter Ready Interrupt /DMA Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " RTSD ,RTS Delta" "Not changed,Changed"
|
|
eventfld.long 0x00 11. " ESCF ,Escape Sequence Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 10. " FRAMERR ,Frame Error Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RRDY ,Receiver Ready Interrupt /DMA Flag" "Not ready,Ready"
|
|
eventfld.long 0x00 8. " AGTIM ,Ageing Timer Interrupt Flag" "Not active,Active"
|
|
eventfld.long 0x00 7. " DTRD ,DTR Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RXDS ,Receiver IDLE Interrupt Flag" "In progress,Idle"
|
|
eventfld.long 0x00 5. " AIRINT ,IR WAKE Pulse Detection" "Not detected,Detected"
|
|
eventfld.long 0x00 4. " AWAKE ,Falling Edge Detection on the RXD Serial pin" "Not detected,Detected"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "USR2,UART Status Register 2"
|
|
eventfld.long 0x00 15. " ADET ,Automatic Baud Rate Detect Complete" "Not received,Received"
|
|
bitfld.long 0x00 14. " TXFE ,Transmit Buffer FIFO Empty" "Not empty,Empty"
|
|
eventfld.long 0x00 13. " DTRF ,DTR edge triggered interrupt flag" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 12. " IDLE ,Idle Condition" "Not detected,Detected"
|
|
eventfld.long 0x00 11. " ACST ,Autobaud Counter Stopped" "Not finished,Finished"
|
|
eventfld.long 0x00 10. " RIDELT ,Ring Indicator Delta" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RIIN ,Ring Indicator Input" "Detected,Not detected"
|
|
eventfld.long 0x00 8. " IRINT ,Serial Infrared Interrupt Flag" "Not detected,Detected"
|
|
eventfld.long 0x00 7. " WAKE ,Wake" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 6. " DCDDELT ,Data Carrier Detect Delta" "Not changed,Changed"
|
|
bitfld.long 0x00 5. " DCDIN ,Data Carrier Detect Input" "Detected,Not detected"
|
|
eventfld.long 0x00 4. " RTSF ,RTS Edge Triggered Interrupt Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TXDC ,Transmitter Complete" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " BRCD ,BREAK Condition Detected" "Not detected,Detected"
|
|
eventfld.long 0x00 1. " ORE ,Overrun Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDR ,Receive Data Ready" "Not ready,Ready"
|
|
group.long 0x9c++0x3
|
|
line.long 0x00 "UESC,UART Escape Character Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ESC_CHAR ,UART Escape Character"
|
|
group.long 0xa0++0x0b
|
|
line.long 0x00 "UTIM,UART Escape Timer Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " TIM ,UART Escape Timer"
|
|
line.long 0x04 "UBIR,UART BRM Incremental Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INC ,UART BRM Incremental Register"
|
|
line.long 0x08 "UBMR,Modulator Dominator"
|
|
hexmask.long.word 0x08 0.--15. 1. " MOD ,Modulator Dominator"
|
|
rgroup.long 0xac++0x3
|
|
line.long 0x00 "UBRC,UART Baud Rate Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,UART Baud Rate Count Register"
|
|
group.long 0xb0++0x3
|
|
line.long 0x00 "ONEMS,UART One Millisecond Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ONEMS ,UART One Millisecond Register"
|
|
group.long 0xb4++0x3
|
|
line.long 0x00 "UTS,UART Test Register"
|
|
bitfld.long 0x00 13. " FRCPERR ,Force Parity Error" "Normal,Inverted"
|
|
bitfld.long 0x00 12. " LOOP ,Loop TX and RX for Test" "Normal,Loop"
|
|
bitfld.long 0x00 11. " DBGEN ,/debug_enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LOOPIR ,Loop Tx and RX for IR Test" "Normal,Loop"
|
|
bitfld.long 0x00 9. " RXDBG ,RX_fifo_debug_mode" "Not incremented,Incremented"
|
|
bitfld.long 0x00 6. " TXEMPTY ,Tx FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXEMPTY ,Rx FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 4. " TXFULL ,Tx FIFO Full" "Not full,Full"
|
|
bitfld.long 0x00 3. " RXFULL ,Rx FIFO Full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SOFTRST ,Software Reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "USBOH3 (Universal Serial Bus OTG HOST3)"
|
|
base ad:0x73f80000
|
|
width 16.
|
|
if ((per.long(ad:0x73f80000+0x800)&0x1)==0x1)
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "USB_CTRL,USB Control Register"
|
|
bitfld.long 0x00 31. " OWIR ,OTG Wake up Interrupt Request" "Not requested,Requested"
|
|
bitfld.long 0x00 29.--30. " OSIC ,OTG Serial Interface Configuration" "Differential / Unidirectional,Differential / Bidirectional,Single Ended / Unidirectional,Single Ended / Unidirectional"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OUIE ,OTG ULPI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " OWIE ,OTG Wake-up Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OBPVAL1 ,OTG Bypass Value for RxDp" "0,1"
|
|
bitfld.long 0x00 25. " OBPVAL0 ,OTG Bypass Value for RxDm" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " OPM ,OTG Power Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " ICVOL ,Host1 IC-USB voltage status" "1.8V class,3.0V class"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICTPIE ,IC USB TP interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UBPCKE ,Bypass clock enable" "Bypass OTG,Bypass Host1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " H1TCKOEN ,Host1 ULPI PHY clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ICTPC ,ICTPC" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " H1WIR ,Host 1 Wake-up Interrupt Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " H1SIC ,Host 1 Serial Interface Configuration" "Differential / Unidirectional,Differential / Bidirectional,Single Ended / Unidirectional,Single Ended / Bidirectional"
|
|
textline " "
|
|
bitfld.long 0x00 12. " H1UIE ,Host 1 ULPI interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " H1WIE ,Host 1 Wake-up Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " H1BPVAL1 ,HOST 1 Bypass Value for RxDp" "0,1"
|
|
bitfld.long 0x00 9. " H1BPVAL0 ,HOST 1 Bypass Value for RxDm" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " H1PM ,Host 1 Power Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " HSTLL ,OTG ULPI TLL Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " H1HSTLL ,Host 1 ULPI TLL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " H1DISFSTLL ,Host 1 Serial TLL disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OTCKOEN ,OTG ULPI PHY clock output enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " BPE ,Bypass Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "USB_CTRL,USB Control Register"
|
|
bitfld.long 0x00 31. " OWIR ,OTG Wake up Interrupt Request" "Not requested,Requested"
|
|
bitfld.long 0x00 29.--30. " OSIC ,OTG Serial Interface Configuration" "Differential / Unidirectional,Differential / Bidirectional,Single Ended / Unidirectional,Single Ended / Unidirectional"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OUIE ,OTG ULPI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " OWIE ,OTG Wake-up Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " OPM ,OTG Power Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " ICVOL ,Host1 IC-USB voltage status" "1.8V class,3.0V class"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICTPIE ,IC USB TP interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " H1TCKOEN ,Host1 ULPI PHY clock output enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 16. " ICTPC ,ICTPC" "0,1"
|
|
bitfld.long 0x00 15. " H1WIR ,Host 1 Wake-up Interrupt Request" "Not requested,Requested"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 13.--14. " H1SIC ,Host 1 Serial Interface Configuration" "Differential / Unidirectional,Differential / Bidirectional,Single Ended / Unidirectional,Single Ended / Bidirectional"
|
|
textline " "
|
|
bitfld.long 0x00 12. " H1UIE ,Host 1 ULPI interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " H1WIE ,Host 1 Wake-up Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 8. " H1PM ,Host 1 Power Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " OHSTLL ,OTG ULPI TLL Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " H1HSTLL ,Host 1 ULPI TLL Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " H1DISFSTLL ,Host 1 Serial TLL disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OTCKOEN ,OTG ULPI PHY clock output enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " BPE ,Bypass Enable" "Disabled,Enabled"
|
|
endif
|
|
width 16.
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "USB_OTG_MIRROR,OTG Port Mirror Register"
|
|
bitfld.long 0x00 8. " UTMIPHYCLK ,OTG UTMI PHY Clock on detection" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ULPIPHYCLK ,OTG ULPI PHY Clock on detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SESEND ,B Device Session End" "Active,End"
|
|
bitfld.long 0x00 3. " VBUSVLD ,Vbus Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BSESVLD ,B Session Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " ASESVLD ,A Session Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDIDG ,OTG ID-pin Status" "Low(A-device),High(B-device)"
|
|
group.long 0x808++0x0b
|
|
line.long 0x00 "PHY_CTRL_0,UTMI PHY Control Register 0"
|
|
bitfld.long 0x00 31. " VLOAD ,Assertion of this signal loads the Vendor Control register" "Loaded,Inactive"
|
|
bitfld.long 0x00 27.--30. " VCONTROL ,Chipidea UTMI PHY Vcontrol" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CONF2 ,Turn on OTG comparators during suspend" "Off,On"
|
|
bitfld.long 0x00 25. " CONF3 ,ChipIdea UTMI PHY CONF3" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CHGRDETEN ,Enable Charger Detector" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CHGRDETON ,Charger Detector Power On Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 15.--22. 1. " VSTATUS ,Vendor Status"
|
|
bitfld.long 0x00 12. " SUSPENDM ,UTMI PHY Suspend" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RESET ,UTMI PHY Reset" "Inactive,Reset"
|
|
bitfld.long 0x00 10. " UTMI_ON_CLOCK ,UTMI PHY On clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OTG_OVER_CUR_POL ,OTG Polarity of Overcurrent" "High active,Low active"
|
|
bitfld.long 0x00 8. " OTG_OVER_CUR_DIS ,OTG Disable Overcurrent Event" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OTG_XCVR_CLK_SEL ,Select the clock source of the xcvr_clk" "Ipg_clk_60Mhz/ipp_ind_otg_clk/sie_clock,Ipg_clk_60Mhz"
|
|
textline " "
|
|
bitfld.long 0x00 4. " H1_XCVR_CLK_SEL ,Select the clock source of the xcvr_clk for HOST1 CORE" "Ipg_clk_60Mhz/ipp_ind_otg_clk/sie_clock,Ipg_clk_60Mhz"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWR_POL ,OTG Power Pin polarity" "Low active,High active"
|
|
bitfld.long 0x00 2. " CHRGDET ,ChipIdea UTMI PHY chrgdet" "Host,Charger"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CHRGDET_INT_EN ,Charger detected interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CHRGDET_INT_FLG ,Charger detected interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x04 "PHY_CTRL_1,UTMI PHY Control Register 1"
|
|
bitfld.long 0x04 31. " HSDRVTIMINGP ,HS driver timing control for PMOS" "2x,8x"
|
|
bitfld.long 0x04 29.--30. " HSDRVTIMINGN ,HS driver timing control for NMOS" "2x,4x,6x,8x"
|
|
textline " "
|
|
bitfld.long 0x04 27.--28. " HSDRVAMPLITUDE ,HS driver amplitude control" "I (I=17.78mA),I+2.5%,I+5%,I+7.5%"
|
|
bitfld.long 0x04 23.--26. " HSDRVSLOPE ,HS driver slope control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 21.--22. " HSDEDVSEL ,Reference voltage for high speed disconnect envelope detector" "556.8mV,568.4mV,580mV,591.6mV"
|
|
bitfld.long 0x04 19.--20. " HSTEDVSEL ,Reference voltage for high speed transmission envelope detector" "104.4mV,116mV,127.6mV,139.2mV"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " FSTUNEVSEL ,Reference voltage control for Calibration circuit" "533.6mV,545.2mV,556.8mV,568.4mV,580mV,591.6mV,603.2mV,614.8mV"
|
|
bitfld.long 0x04 14.--15. " ICPCTRL ,PLL charge pump current control" "Icp (Icp = 40uA),Icp*0.5,Icp*1.5,Icp*2"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " FSRFTSEL ,FS driver rise/fall time control" "Rise time-30%,Rise time,Rise time,Rise time+30%"
|
|
bitfld.long 0x04 10.--11. " LSRFTSEL ,LS driver rise/fall time control" "Rise time-30%,Rise time,Rise time,Rise time+30%"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " PREEMDEPTH/ENPRE ,HS driver pre-emphasis depth" "I (I=17.78mA),I+5%,I+10%,I+20%"
|
|
bitfld.long 0x04 7. " CALBP ,Enables calibration bypass for both dp and dn lines" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2.--6. " EXTCAL ,Controls calibration value externally" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--1. " PLLDIVVALUE ,Selects reference clock" "19.2Mhz,24Mhz,26Mhz,27Mhz"
|
|
line.long 0x08 "USB_CTRL_1,USB Control Register 1"
|
|
bitfld.long 0x08 27. " UH3_EXT_CLK_EN ,Host 3 select the clock which comes from external PHY or internal PLL" "PLL,PHY"
|
|
bitfld.long 0x08 26. " UH2_EXT_CLK_EN ,Host 2select the clock which comes from external PHY or internal PLL" "PLL,PHY"
|
|
textline " "
|
|
bitfld.long 0x08 25. " UH1_EXT_CLK_EN ,Host 1 select the clock which comes from external PHY or internal PLL" "PLL,PHY"
|
|
bitfld.long 0x08 24. " OTG_EXT_CLK_EN ,Otg select the clock which comes from external PHY or internal PLL" "PLL,PHY"
|
|
group.long 0x814++0x07
|
|
line.long 0x00 "USB_UH2_CTRL,USB Host2 Control Register"
|
|
bitfld.long 0x00 20. " OTG_SER_DRVEN ,OTG Serial interface drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " H1_SER_DRVEN ,Host1 Serial interface drive enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ICVOL ,Host 2 IC-USB voltage status" "1.8V class,3.0V class"
|
|
bitfld.long 0x00 17. " H2WIR ,Host 2 Wake-up Interrupt Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICTPIE ,IC USB TP interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " H2TCKKOEN ,Host 2 ULPI PHY clock output enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 11. " ICTPC ,IC USB TP interrupt clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " H2SIC ,Host 2 Serial Interface Configuration" "Differential / Unidirectional,Differential / Bidirectional,Single Ended / Unidirectional,Single Ended / Bidirectional"
|
|
textline " "
|
|
bitfld.long 0x00 8. " H2UIE ,Host 2 ULPI interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " H2WIE ,Host 2 Wake-up Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OVBWK_EN ,OTG VBUS Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OIDWK_EN ,OTG ID Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " H2PM ,Host 2 Power Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " H2HSTLL ,Host 2 ULPI TLL Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " H2DISFSTLL ,Host 2 Serial TLL disable" "No,Yes"
|
|
line.long 0x04 "USB_UH3_CTRL,USB Host 3 Control Register"
|
|
bitfld.long 0x04 20. " H2_SER_DRVEN ,Host2 Serial interface drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " H3_SER_DRVEN ,Host3 Serial interface drive enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ICVOL ,Host 3 IC-USB voltage status" "1.8V class,3.0V class"
|
|
bitfld.long 0x04 17. " H3WIR ,Host 3 Wake-up Interrupt Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ICTPIE ,IC USB TP interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " H3TCKKOEN ,Host 3 ULPI PHY clock output enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 11. " ICTPC ,IC USB TP interrupt clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 9.--10. " H3SIC ,Host 3 Serial Interface Configuration" "Differential / Unidirectional,Differential / Bidirectional,Single Ended / Unidirectional,Single Ended / Bidirectional"
|
|
textline " "
|
|
bitfld.long 0x04 8. " H3UIE ,Host 3 ULPI interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " H3WIE ,Host 3 Wake-up Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " H3BPVAL1 ,HOST 3 Bypass Value for RxDp" "0,1"
|
|
bitfld.long 0x04 5. " H3BPVAL0 ,HOST 3 Bypass Value for RxDm" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 4. " H3PM ,Host 3 Power Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " H3HSTLL ,Host 3 ULPI TLL Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " H3DISFSTLL ,Host 3 Serial TLL disable" "No,Yes"
|
|
tree "OTG"
|
|
width 24.
|
|
rgroup.long (0x00+0x0)++0x03
|
|
line.long 0x00 "UOG_ID,Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " REVISION[7:0] ,Revision Number of the Core"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NID[5:0] ,Ones Complement Version of ID[5:0]"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ID[5:0] ,Configuration Number"
|
|
textline " "
|
|
rgroup.long (0x04+0x0)++0x03
|
|
line.long 0x00 "UOG_HWGENERAL,General Hardware Register"
|
|
sif (cpuis("K70*"))
|
|
bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "0,1,2,3"
|
|
textline " "
|
|
elif (cpuis("RAYLEIGH-CA7")||cpuis("IMX6*"))
|
|
bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "No Serial Engine,Serial Engine,Soft. programmable(parallel),Soft. programmable(serial)"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " SM ,Transciever type" "0,1"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")
|
|
bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "000,001,010,011,100,101,110,111"
|
|
elif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Reset UTMI/UTMI+,Reset ULPI DDR,Reset ULPI,Reset Serial"
|
|
else
|
|
bitfld.long 0x00 6.--8. " PHYM ,VUSB_HS_PHY_TYPE" "000,001,010,011,100,101,110,111"
|
|
endif
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core/Software programmable" "8 bit/Soft. non-programmable,16 bit/Soft. non-programmable,Reset to 8 bit/Soft. programmable,Reset to 16 bit/Soft. programmable"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core" "00,01,10,11"
|
|
endif
|
|
sif (!cpuis("K70*"))&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 3. " BWT ,Reserved for Internal Testing" "0,1"
|
|
bitfld.long 0x00 1.--2. " CLKC ,VUSB_HS_CLOCK_CONFIGURATION" "00,01,10,11"
|
|
bitfld.long 0x00 0. " RT ,VUSB_HS_RESET_TYPE" "0,1"
|
|
endif
|
|
textline " "
|
|
rgroup.long (0x08+0x0)++0x0F
|
|
line.long 0x00 "UOG_HWHOST,Host Hardware Parameters Register"
|
|
sif (!(cpuis("IMX6*")))
|
|
hexmask.long.byte 0x00 24.--31. 1. " TTPER ,VUSB_HS_TT_PERIODIC_CONTEXTS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TTASY ,VUSB_HS_TT_ASYNC_CONTEXTS"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 1.--3. " NPORT ,Number of downstream ports supported by host controller (NPORT+1)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Host operation mode support" "Not supported,Supported"
|
|
else
|
|
bitfld.long 0x00 1.--3. " NPORT ,VUSB_HS_NUM_PORT+1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Operation mode support for device" "Not supported,Supported"
|
|
endif
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
else
|
|
line.long 0x04 "UOG_HWDEVICE,Device Hardware Parameters Register"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x04 1.--5. " DEVEP ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0. " DC ,Device operation mode support" "Not supported,Supported"
|
|
else
|
|
hexmask.long.byte 0x04 1.--5. 1. " DEVEP ,VUSB_HS_DEV_EP"
|
|
bitfld.long 0x04 0. " DC ,VUSB_HS_DEV" "0,1"
|
|
endif
|
|
endif
|
|
line.long 0x08 "UOG_HWTXBUF,TX Buffer Hardware Parameters Register"
|
|
sif (!(cpuis("IMX6*")))
|
|
bitfld.long 0x08 31. " TXLCR ,VUSB_HS_TX_LOCAL_CONTEXT_REGISTERS" "0,1"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x08 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint"
|
|
sif (!(cpuis("IMX6*")))
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXADD ,Buffer total size for all transmit endpoints"
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer"
|
|
line.long 0x0C "UOG_HWRXBUF,RX Buffer Hardware Parameters Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer"
|
|
textline " "
|
|
group.long (0x80+0x0)++0xf "Device/Host Timer Registers"
|
|
line.long 0x00 "UOG_GPTIMER0LD,General Purpose Timer #0 Load Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General Purpose Timer Load Value"
|
|
line.long 0x04 "UOG_GPTIMER0CTRL,General Purpose Timer #0 Controller"
|
|
bitfld.long 0x04 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Running"
|
|
bitfld.long 0x04 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x04 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General Purpose Timer Counter"
|
|
line.long 0x08 "UOG_GPTIMER1LD,General Purpose Timer #1 Load Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General Purpose Timer Load Value"
|
|
line.long 0x0C "UOG_GPTIMER1CTRL,General Purpose Timer #1 Controller"
|
|
bitfld.long 0x0C 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Running"
|
|
bitfld.long 0x0C 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General Purpose Timer Counter"
|
|
textline " "
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "UOG_SBUSCFG,System Bus Config"
|
|
bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface Burst configuration" "Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified"
|
|
else
|
|
group.long 0x90++0x03 "UOG_SBUSCFG"
|
|
line.long 0x00 "UOG_WRXBUF, RX Buffer Hardware Parameters"
|
|
bitfld.long 0x00 0.--2. " AHBBRST ,AHB Burst" "Unspecified,INCR4/Singles,INCR8/Singles,INCR16/Singles,,INCR4/Unspecified,INCR8/Unspecified,INCR16/Unspecified"
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
rgroup.word (0x100+0x0)++0x01
|
|
line.word 0x00 "UOG_HCIVERSION,EHCI Compliant Register"
|
|
hexmask.word 0x00 0.--15. 1. " HCIVERSION[15:0] ,Host Interface Version Number"
|
|
rgroup.byte (0x103+0x0)++0x00
|
|
line.byte 0x00 "UOG_CAPLENGTH,EHCI Compliant Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CAPLENGTH[7:0] ,Capability Length"
|
|
elif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
rgroup.byte (0x100+0x0)++0x00
|
|
line.byte 0x00 "UOG_CAPLENGTH,Capability Registers Length"
|
|
rgroup.word (0x102+0x0)++0x01
|
|
line.word 0x00 "UOG_HCIVERSION,Host Controller Interface Version"
|
|
else
|
|
rgroup.byte (0x100+0x0)++0x00 "Device/Host Capability Registers"
|
|
line.byte 0x00 "UOG_CAPLENGTH,EHCI Compliant Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CAPLENGTH[7:0] ,Capability Length"
|
|
rgroup.word (0x102+0x0)++0x01
|
|
line.word 0x00 "UOG_HCIVERSION,EHCI Compliant Register"
|
|
hexmask.word 0x00 0.--15. 1. " HCIVERSION[15:0] ,Host Interface Version Number"
|
|
endif
|
|
rgroup.long (0x104+0x0)++0x07
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6SOLOLITE")
|
|
line.long 0x00 "UOG_HCSPARAMS,Host Controller Structural Parameters"
|
|
else
|
|
line.long 0x00 "UOG_HCSPARAMS,EHCI Compliant With Extensions Register"
|
|
endif
|
|
bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " PI ,Port Indicators" "0,1"
|
|
bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,?..."
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
line.long 0x04 "UOG_HCCPARAMS,Host Controller Capability Parameters"
|
|
else
|
|
line.long 0x04 "UOG_HCCPARAMS,EHCI Compliant Register"
|
|
endif
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Disabled,Enabled"
|
|
sif (cpuis("K70*"))
|
|
rgroup.word (0x122+0x0)++0x1
|
|
line.word 0x00 "UOG_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
rgroup.long (0x124+0x0)++0x3
|
|
line.long 0x00 "UOG_DCCPARAMS,Device Control Capability Parameters Register"
|
|
bitfld.long 0x00 8. " HC ,Host Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DC ,Device Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
else
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rgroup.word (0x120+0x0)++0x1
|
|
line.word 0x00 "UOG_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
else
|
|
rgroup.word (0x120+0x0)++0x1
|
|
line.word 0x00 "UOG_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
endif
|
|
rgroup.long (0x124+0x0)++0x3
|
|
line.long 0x00 "UOG_DCCPARAMS,Device Control Capability Parameters Register"
|
|
bitfld.long 0x00 8. " HC ,Host Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DC ,Device Capable" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..."
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
endif
|
|
endif
|
|
group.long (0x140+0x0)++0x03
|
|
line.long 0x00 "UOG_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control"
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard"
|
|
sif (!cpuis("K70*"))&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")
|
|
textline " "
|
|
bitfld.long 0x00 12. " ATDTW ,ATDTW" "Cleared,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" ",1,2,3"
|
|
sif (!cpuis("IMX6*"))
|
|
textline " "
|
|
bitfld.long 0x00 7. " LR ,Light Host/Device Controller Reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stopped,Running"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
else
|
|
if ((per.l((0x0+ad:0x73f80000+0x1a8))&0x3)==0x3)
|
|
group.long (0x144+0x0)++0x03
|
|
line.long 0x00 "UOG_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
sif (cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPI ,USB host Periodic Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " UAI ,USB host Asynchronous Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRI ,Frame List Rollover" "No rollover,Rollover"
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
elif ((per.l(0x0+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x144+0x0)++0x03
|
|
line.long 0x00 "UOG_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
sif (cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPI ,USB host Periodic Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " UAI ,USB host Asynchronous Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 7. " SRI ,SOF Received" "Not received,Received"
|
|
eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
hgroup.long (0x144+0x0)++0x03
|
|
hide.long 0x00 "UOG_USBSTS,USB Status Register"
|
|
endif
|
|
endif
|
|
group.long (0x148+0x0)++0x07
|
|
line.long 0x00 "UOG_USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("K70*")||cpuis("IMX6*"))||(cpuis("RAYLEIGH-CA7"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPIE ,USB host Periodic Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host Asynchronous Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " NAKIE ,NAK Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " URE ,USB Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UOG_FRINDEX,USB Frame Index Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index"
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*")&&!cpuis("RAYLEIGH-CA7"))
|
|
hgroup.long (0x150+0x0)++0x03
|
|
hide.long 0x00 "UOG_CTRLDSSEGMENT,CTRLDSSEGMENT"
|
|
endif
|
|
if ((per.l((0x0+ad:0x73f80000+0x1a8))&0x3)==0x3)
|
|
group.long (0x154+0x0)++0x03
|
|
line.long 0x00 "UOG_PERIODICLISTBASE,Host Controller Frame List Base Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)"
|
|
elif ((per.l(0x0+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x154+0x0)++0x03
|
|
line.long 0x00 "UOG_DEVICEADDR,Device Controller USB Device Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x02 " USBADR ,Device Address"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 24. " USBADRA ,Device Address Advance" "0,1"
|
|
endif
|
|
else
|
|
hgroup.long (0x154+0x0)++0x03
|
|
hide.long 0x00 "UOG_DEVICEADDR,Device Controller USB Device Address Register"
|
|
endif
|
|
if ((per.l(0x0+ad:0x73f80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x158+0x0)++0x03
|
|
line.long 0x00 "UOG_ASYNCLISTADDR,Host Controller Next Asynch Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low"
|
|
elif ((per.l(0x0+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x158+0x0)++0x03
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")
|
|
line.long 0x00 "UOG_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
else
|
|
line.long 0x00 "UOG_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
endif
|
|
hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address"
|
|
else
|
|
hgroup.long (0x158+0x0)++0x03
|
|
hide.long 0x00 "UOG_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
group.long 0x15c++0x3
|
|
line.long 0x00 "USBHS_TTCTRL,Host TT Asynchronous Buffer Control"
|
|
hexmask.long.byte 0x00 24.--30. 1. " TTHA ,TT Hub Address"
|
|
endif
|
|
group.long (0x160+0x0)++0x7
|
|
line.long 0x00 "UOG_BURSTSIZE,Programmable Burst Size"
|
|
hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length"
|
|
line.long 0x04 "UOG_TXFILLTUNING,TX FIFO Fill Tuning Register"
|
|
bitfld.long 0x04 16.--21. " TXFIFOTHRES ,FIFO Burst Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 8.--12. " TXSCHEALTH ,Scheduler Health Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead"
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(!cpuis("K70*"))&&(cpu()!="IMX6SOLOLITE")
|
|
group.long (0x16C+0x0)++0x03
|
|
line.long 0x00 "IC_USB,IC_USB Enable"
|
|
bitfld.long 0x00 31. " IC8 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " IC_VDD8 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 27. " IC7 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " IC_VDD7 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " IC6 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " IC_VDD6 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 19. " IC5 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " IC_VDD5 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " IC4 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " IC_VDD4 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 11. " IC3 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " IC_VDD3 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " IC2 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " IC_VDD2 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
endif
|
|
sif (!cpuis("IMX6*"))
|
|
group.long (0x170+0x0)++0x03
|
|
line.long 0x00 "UOG_ULPIVIEW,ULPI Vieport Register"
|
|
bitfld.long 0x00 31. " ULPIWU ,ULPI Wakeup" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "No effect,Read/write"
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Not normal,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,ULPI Data Write"
|
|
endif
|
|
sif (cpuis("IMX6*")||cpuis("RAYLEIGH-CA7"))
|
|
group.long 0x178++0x07
|
|
line.long 0x00 "UOG_ENDPTNAK,Endpoint NAK register"
|
|
bitfld.long 0x00 23. " EPTN[7] ,TX Endpoint NAK 7" "Low,High"
|
|
bitfld.long 0x00 22. " EPTN[6] ,TX Endpoint NAK 6" "Low,High"
|
|
bitfld.long 0x00 21. " EPTN[5] ,TX Endpoint NAK 5" "Low,High"
|
|
bitfld.long 0x00 20. " EPTN[4] ,TX Endpoint NAK 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EPTN[3] ,TX Endpoint NAK 3" "Low,High"
|
|
bitfld.long 0x00 18. " EPTN[2] ,TX Endpoint NAK 2" "Low,High"
|
|
bitfld.long 0x00 17. " EPTN[1] ,TX Endpoint NAK 1" "Low,High"
|
|
bitfld.long 0x00 16. " EPTN[0] ,TX Endpoint NAK 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EPRN[7] ,RX Endpoint NAK 7" "Low,High"
|
|
bitfld.long 0x00 6. " EPRN[6] ,RX Endpoint NAK 6" "Low,High"
|
|
bitfld.long 0x00 5. " EPRN[5] ,RX Endpoint NAK 5" "Low,High"
|
|
bitfld.long 0x00 4. " EPRN[4] ,RX Endpoint NAK 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EPRN[3] ,RX Endpoint NAK 3" "Low,High"
|
|
bitfld.long 0x00 2. " EPRN[2] ,RX Endpoint NAK 2" "Low,High"
|
|
bitfld.long 0x00 1. " EPRN[1] ,RX Endpoint NAK 1" "Low,High"
|
|
bitfld.long 0x00 0. " EPRN[0] ,RX Endpoint NAK 0" "Low,High"
|
|
line.long 0x04 "UOG_ENDPTNAKEN,Endpoint NAK Enable register"
|
|
bitfld.long 0x04 23. " EPTN[7] ,TX Endpoint NAK 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " EPTN[6] ,TX Endpoint NAK 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " EPTN[5] ,TX Endpoint NAK 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " EPTN[4] ,TX Endpoint NAK 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " EPTN[3] ,TX Endpoint NAK 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " EPTN[2] ,TX Endpoint NAK 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " EPTN[1] ,TX Endpoint NAK 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " EPTN[0] ,TX Endpoint NAK 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EPRN[7] ,RX Endpoint NAK 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " EPRN[6] ,RX Endpoint NAK 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " EPRN[5] ,RX Endpoint NAK 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " EPRN[4] ,RX Endpoint NAK 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EPRN[3] ,RX Endpoint NAK 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " EPRN[2] ,RX Endpoint NAK 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EPRN[1] ,RX Endpoint NAK 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EPRN[0] ,RX Endpoint NAK 0" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("K70*")&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE"))
|
|
rgroup.long (0x180+0x0)++0x03
|
|
line.long 0x00 "UOG_CFGFLAG,Config Flag Register (Reserved)"
|
|
else
|
|
rgroup.long (0x180+0x0)++0x03
|
|
line.long 0x00 "UOG_CONFIGFLAG,Configure Flag Register"
|
|
bitfld.long 0x00 0. " CF ,Configure Flag" "Low,High"
|
|
endif
|
|
if ((per.l(0x0+ad:0x73f80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x184+0x0)++0x03
|
|
line.long 0x00 "UOG_PORTSC1,Port 1 Status and Control Register"
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial,HSIC,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("K70*"))
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Undefined"
|
|
textline " "
|
|
sif (cpuis("IMX6*"))&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,Undefined"
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device"
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*")&&!cpuis("RAYLEIGH-CA7"))
|
|
group.long (0x184+0x0+0x04)++0x1B
|
|
line.long 0x00 "UOG_PORTSC2,Port 2 Status and Control Register"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x04 "UOG_PORTSC3,Port 3 Status and Control Register"
|
|
bitfld.long 0x04 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x04 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x04 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x04 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x04 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x04 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x04 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x04 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x04 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x04 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x04 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x04 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x04 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x04 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x04 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x04 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x04 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x08 "UOG_PORTSC4,Port 4 Status and Control Register"
|
|
bitfld.long 0x08 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x08 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x08 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x08 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x08 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x08 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x08 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x08 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x08 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x08 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x08 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x08 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x08 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x08 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x08 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x08 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x08 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x08 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x08 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x0C "UOG_PORTSC5,Port 5 Status and Control Register"
|
|
bitfld.long 0x0C 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x0C 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x0C 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x0C 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x0C 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x0C 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x0C 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x0C 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x0C 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x0C 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x0C 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x0C 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x0C 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x10 "UOG_PORTSC6,Port 6 Status and Control Register"
|
|
bitfld.long 0x10 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x10 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x10 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x10 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x10 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x10 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x10 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x10 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x10 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
textline " "
|
|
bitfld.long 0x10 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
bitfld.long 0x10 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x10 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x10 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
textline " "
|
|
bitfld.long 0x10 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x10 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x10 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x10 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
eventfld.long 0x10 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x10 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x10 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x14 "UOG_PORTSC7,Port 7 Status and Control Register"
|
|
bitfld.long 0x14 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x14 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x14 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x14 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x14 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x14 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x14 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x14 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x14 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
textline " "
|
|
bitfld.long 0x14 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
bitfld.long 0x14 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x14 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x14 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
textline " "
|
|
bitfld.long 0x14 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x14 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x14 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x14 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x14 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
eventfld.long 0x14 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x14 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x14 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x18 "UOG_PORTSC8,Port 8 Status and Control Register"
|
|
bitfld.long 0x18 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x18 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x18 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x18 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x18 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x18 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x18 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x18 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x18 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x18 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x18 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x18 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x18 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x18 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x18 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x18 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x18 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x18 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x18 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x18 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x18 0. " CCS ,Current Connect Status" "No device,Device"
|
|
endif
|
|
elif ((per.l(0x0+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x184+0x0)++0x03
|
|
line.long 0x00 "UOG_PORTSC1,Port 1 Status and Control Register"
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial,HSIC,?..."
|
|
textline " "
|
|
elif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
textline " "
|
|
elif (!cpuis("K70*"))
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
textline " "
|
|
elif (cpuis("IMX6*"))&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,Undefined"
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
rbitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " CCS ,Current Connect Status" "Not attached,Attached"
|
|
else
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*"))
|
|
hgroup.long (0x184+0x0)++0x1f
|
|
hide.long 0x00 "UOG_PORTSC1,Port 1 Status and Control Register"
|
|
hide.long 0x04 "UOG_PORTSC2,Port 2 Status and Control Register"
|
|
hide.long 0x08 "UOG_PORTSC3,Port 3 Status and Control Register"
|
|
hide.long 0x0c "UOG_PORTSC4,Port 4 Status and Control Register"
|
|
hide.long 0x10 "UOG_PORTSC5,Port 5 Status and Control Register"
|
|
hide.long 0x14 "UOG_PORTSC6,Port 6 Status and Control Register"
|
|
hide.long 0x18 "UOG_PORTSC7,Port 7 Status and Control Register"
|
|
hide.long 0x1c "UOG_PORTSC8,Port 8 Status and Control Register"
|
|
endif
|
|
endif
|
|
textline " "
|
|
group.long 0x1a4++0x03
|
|
line.long 0x00 "UOG_OTGSC,OTG Status Control Register"
|
|
bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " 1MSE ,1 Milisecond Timer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " 1MSS ,1 Milisecond Timer Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "No interrupt,Interrupt"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rbitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected"
|
|
rbitfld.long 0x00 13. " 1MST ,1 Milisecond Timer Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended"
|
|
rbitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid"
|
|
rbitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " ID ,USB ID" "A device,B device"
|
|
else
|
|
bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " 1MST ,1 Milisecond Timer Toggle" "Not toggled,Toggled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended"
|
|
bitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ID ,USB ID" "A device,B device"
|
|
endif
|
|
bitfld.long 0x00 5. " IDPU ,ID Pullup" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DP ,Data Pulsing" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OT ,OTG Termination" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VC ,VBUS Charge" "Not charged,Charged"
|
|
bitfld.long 0x00 0. " VD ,VBUS Discharge" "Not discharged,Discharged"
|
|
textline " "
|
|
group.long (0x1a8+0x0)++0x03
|
|
line.long 0x00 "UOG_USBMODE,USB Device Mode Register"
|
|
bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big"
|
|
bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,,Device,Host"
|
|
textline " "
|
|
if ((per.l(0x0+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long 0x1ac++0x0b
|
|
line.long 0x00 "UOG_ENDPTSETUPSTAT,Endpoint Setup Status Register"
|
|
sif (!cpuis("K70*"))
|
|
bitfld.long 0x00 15. " ENDPTSETUPSTAT[15] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 14. " ENDPTSETUPSTAT[14] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 13. " ENDPTSETUPSTAT[13] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 12. " ENDPTSETUPSTAT[12] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ENDPTSETUPSTAT[11] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 10. " ENDPTSETUPSTAT[10] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 9. " ENDPTSETUPSTAT[09] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 8. " ENDPTSETUPSTAT[08] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENDPTSETUPSTAT[07] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 6. " ENDPTSETUPSTAT[06] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 5. " ENDPTSETUPSTAT[05] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 4. " ENDPTSETUPSTAT[04] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " ENDPTSETUPSTAT[03] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 2. " ENDPTSETUPSTAT[02] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 1. " ENDPTSETUPSTAT[01] ,Setup Endpoint Status" "Not received,Received"
|
|
bitfld.long 0x00 0. " ENDPTSETUPSTAT[00] ,Setup Endpoint Status" "Not received,Received"
|
|
textline " "
|
|
line.long 0x04 "UOG_ENDPTPRIME,Endpoint Prime Register"
|
|
sif (!cpuis("K70*"))
|
|
bitfld.long 0x04 23. " PETB7 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 22. " PETB6 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 21. " PETB5 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 20. " PETB4 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 19. " PETB3 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 18. " PETB2 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 17. " PETB1 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 16. " PETB0 ,Prime Endpoint Transmit Buffer" "Not prime,Prime"
|
|
sif (!cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x04 7. " PERB7 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 6. " PERB6 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 5. " PERB5 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 4. " PERB4 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 3. " PERB3 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 2. " PERB2 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 1. " PERB1 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
bitfld.long 0x04 0. " PERB0 ,Prime Endpoint Receive Buffer" "Not prime,Prime"
|
|
line.long 0x08 "UOG_ENDPTFLUSH,Endpoint Flush Register"
|
|
sif (!cpuis("K70*"))
|
|
bitfld.long 0x08 23. " FETB7 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 22. " FETB6 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 21. " FETB5 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 20. " FETB4 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 19. " FETB3 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 18. " FETB2 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 17. " FETB1 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 16. " FETB0 ,Flush Endpoint Transmit Buffer" "Not flushed,Flushed"
|
|
sif (!cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x08 7. " FERB7 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 6. " FERB6 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 5. " FERB5 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 4. " FERB4 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 3. " FERB3 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 2. " FERB2 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 1. " FERB1 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
bitfld.long 0x08 0. " FERB0 ,Flush Endpoint Receive Buffer" "Not flushed,Flushed"
|
|
rgroup.long 0x1b8++0x03
|
|
line.long 0x00 "UOG_ENDPTSTAT,Endpoint Status Register"
|
|
sif (!cpuis("K70*"))
|
|
bitfld.long 0x00 23. " ETBR7 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 22. " ETBR6 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 21. " ETBR5 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " ETBR4 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " ETBR3 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 18. " ETBR2 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 17. " ETBR1 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " ETBR0 ,Endpoint Transmit Buffer Ready" "Not ready,Ready"
|
|
sif (!cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERBR7 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 6. " ERBR6 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 5. " ERBR5 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 4. " ERBR4 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERBR3 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 2. " ERBR2 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " ERBR1 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " ERBR0 ,Endpoint Receive Buffer Ready" "Not ready,Ready"
|
|
group.long 0x1bc++0x03
|
|
sif (cpuis("K70*"))
|
|
line.long 0x00 "UOG_ENDPTCOMPLETE,Endpoint Complete Register"
|
|
eventfld.long 0x00 19. " ETCE3 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " ETCE2 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 17. " ETCE1 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " ETCE0 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ERCE3 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " ERCE2 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " ERCE1 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " ERCE0 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
elif (cpuis("RAYLEIGH-CA7"))
|
|
line.long 0x00 "UOG_ENDPTCOMPLETE,Endpoint Complete Register"
|
|
eventfld.long 0x00 23. " ETCE23 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 22. " ETCE22 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 21. " ETCE21 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " ETCE20 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ETCE3 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " ETCE2 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 17. " ETCE1 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 16. " ETCE0 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ERCE7 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " ERCE6 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " ERCE5 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " ERCE3 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ERCE2 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " ERCE1 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " ERCE0 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
else
|
|
line.long 0x00 "UOG_ENDPTCOMPLETE,Endpoint Complete Register"
|
|
sif (!cpuis("IMX6*"))
|
|
bitfld.long 0x00 31. " ETCE15 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " ETCE14 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " ETCE13 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " ETCE12 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ETCE11 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " ETCE10 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " ETCE9 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " ETCE8 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " ETCE7 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " ETCE6 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " ETCE5 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " ETCE4 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ETCE3 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " ETCE2 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " ETCE1 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " ETCE0 ,Endpoint Transmit Complete Event" "Not occurred,Occurred"
|
|
sif (!cpuis("IMX6*"))
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERCE15 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " ERCE14 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " ERCE13 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " ERCE12 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ERCE11 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " ERCE10 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " ERCE9 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " ERCE8 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERCE7 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " ERCE6 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " ERCE5 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " ERCE4 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ERCE3 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " ERCE2 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ERCE1 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ERCE0 ,Endpoint Receive Complete Event" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
else
|
|
hgroup.long 0x1ac++0x13
|
|
hide.long 0x00 "UOG_ENDPTSETUPSTAT,Endpoint Setup Status Register"
|
|
hide.long 0x04 "UOG_ENDPTPRIME,Endpoint Prime Register"
|
|
hide.long 0x08 "UOG_ENDPTFLUSH,Endpoint Flush Register"
|
|
hide.long 0x0c "UOG_ENDPTSTAT,Endpoint Status Register"
|
|
hide.long 0x10 "UOG_ENDPTCOMPLETE,Endpoint Complete Register"
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
group.long 0x1c0--0x1CF
|
|
line.long 0x00 "UOG_ENDPTCTRL0,Endpoint Control 0 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,,,"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,,,"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
line.long 0x4 "UOG_ENDPTCTRL1,Endpoint Control 1 Register"
|
|
bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x4 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,"
|
|
bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
line.long 0x8 "UOG_ENDPTCTRL2,Endpoint Control 2 Register"
|
|
bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x8 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,"
|
|
bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
line.long 0xC "UOG_ENDPTCTRL3,Endpoint Control 3 Register"
|
|
bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0xC 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,"
|
|
bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
elif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
group.long 0x1c0++0x03
|
|
line.long 0x00 "UOG_ENDPTCTRL0,Endpoint Control 0 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,?..."
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "OK,Stalled"
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" ",Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,?..."
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "OK,Stalled"
|
|
if ((per.l(0x0+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long 0x1c4++0x1B
|
|
line.long 0x0 "UOG_ENDPTCTRL1,Endpoint Control 1 Register"
|
|
bitfld.long 0x0 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x0 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x0 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x0 16. " TXS ,TX Endpoint Stall" "OK,Stalled"
|
|
bitfld.long 0x0 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x0 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x0 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x0 0. " RXS ,RX Endpoint Stall" "OK,Stalled"
|
|
line.long 0x4 "UOG_ENDPTCTRL2,Endpoint Control 2 Register"
|
|
bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x4 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "OK,Stalled"
|
|
bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "OK,Stalled"
|
|
line.long 0x8 "UOG_ENDPTCTRL3,Endpoint Control 3 Register"
|
|
bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x8 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "OK,Stalled"
|
|
bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "OK,Stalled"
|
|
line.long 0xC "UOG_ENDPTCTRL4,Endpoint Control 4 Register"
|
|
bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0xC 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "OK,Stalled"
|
|
bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "OK,Stalled"
|
|
line.long 0x10 "UOG_ENDPTCTRL5,Endpoint Control 5 Register"
|
|
bitfld.long 0x10 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x10 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x10 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x10 16. " TXS ,TX Endpoint Stall" "OK,Stalled"
|
|
bitfld.long 0x10 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x10 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x10 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x10 0. " RXS ,RX Endpoint Stall" "OK,Stalled"
|
|
line.long 0x14 "UOG_ENDPTCTRL6,Endpoint Control 6 Register"
|
|
bitfld.long 0x14 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x14 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x14 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x14 16. " TXS ,TX Endpoint Stall" "OK,Stalled"
|
|
bitfld.long 0x14 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x14 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x14 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x14 0. " RXS ,RX Endpoint Stall" "OK,Stalled"
|
|
line.long 0x18 "UOG_ENDPTCTRL7,Endpoint Control 7 Register"
|
|
bitfld.long 0x18 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x18 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x18 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x18 16. " TXS ,TX Endpoint Stall" "OK,Stalled"
|
|
bitfld.long 0x18 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x18 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,?..."
|
|
bitfld.long 0x18 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer/DMA Engine,Undefined"
|
|
bitfld.long 0x18 0. " RXS ,RX Endpoint Stall" "OK,Stalled"
|
|
else
|
|
hgroup.long 0x1c4++0x1B
|
|
hide.long 0x4 "UOG_ENDPTCTRL1,Endpoint Control 1 Register"
|
|
hide.long 0x8 "UOG_ENDPTCTRL2,Endpoint Control 2 Register"
|
|
hide.long 0xC "UOG_ENDPTCTRL3,Endpoint Control 3 Register"
|
|
hide.long 0x10 "UOG_ENDPTCTRL4,Endpoint Control 4 Register"
|
|
hide.long 0x14 "UOG_ENDPTCTRL5,Endpoint Control 5 Register"
|
|
hide.long 0x18 "UOG_ENDPTCTRL6,Endpoint Control 6 Register"
|
|
hide.long 0x1C "UOG_ENDPTCTRL7,Endpoint Control 7 Register"
|
|
endif
|
|
else
|
|
group.long 0x1c0++0x23
|
|
line.long 0x00 "UOG_ENDPTCTRL0,Endpoint Control 0 Register"
|
|
bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Type" "Control,,,"
|
|
bitfld.long 0x00 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Type" "Control,,,"
|
|
bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
line.long 0x4 "UOG_ENDPTCTRL1,Endpoint Control 1 Register"
|
|
bitfld.long 0x4 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x4 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x4 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x4 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0x4 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,"
|
|
bitfld.long 0x4 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x4 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
line.long 0x8 "UOG_ENDPTCTRL2,Endpoint Control 2 Register"
|
|
bitfld.long 0x8 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x8 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x8 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x8 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x8 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0x8 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x8 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x8 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,"
|
|
bitfld.long 0x8 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x8 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
line.long 0xC "UOG_ENDPTCTRL3,Endpoint Control 3 Register"
|
|
bitfld.long 0xC 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0xC 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0xC 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0xC 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0xC 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0xC 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0xC 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0xC 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,"
|
|
bitfld.long 0xC 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0xC 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
line.long 0x10 "UOG_ENDPTCTRL4,Endpoint Control 4 Register"
|
|
bitfld.long 0x10 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x10 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x10 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x10 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0x10 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x10 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,"
|
|
bitfld.long 0x10 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x10 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
line.long 0x14 "UOG_ENDPTCTRL5,Endpoint Control 5 Register"
|
|
bitfld.long 0x14 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x14 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x14 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x14 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0x14 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x14 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,"
|
|
bitfld.long 0x14 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x14 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
line.long 0x18 "UOG_ENDPTCTRL6,Endpoint Control 6 Register"
|
|
bitfld.long 0x18 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x18 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x18 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x18 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0x18 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x18 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,"
|
|
bitfld.long 0x18 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x18 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
line.long 0x1C "UOG_ENDPTCTRL7,Endpoint Control 7 Register"
|
|
bitfld.long 0x1C 23. " TXE ,TX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " TXR ,TX Data Toggle Reset" "No effect,Reset"
|
|
bitfld.long 0x1C 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled"
|
|
bitfld.long 0x1C 18.--19. " TXT ,TX Endpoint Type" "Control,Isochronous,Bulk,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 17. " TXD ,TX Endpoint Data Source" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x1C 16. " TXS ,TX Endpoint Stall" "Not stalled,Stalled"
|
|
bitfld.long 0x1C 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " RXR ,RX Data Toggle Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled"
|
|
bitfld.long 0x1C 2.--3. " RXT ,RX Endpoint Type" "Control,Isochronous,Bulk,"
|
|
bitfld.long 0x1C 1. " RXD ,RX Endpoint Data Sink" "Dual port memory buffer,Undefined"
|
|
bitfld.long 0x1C 0. " RXS ,RX Endpoint Stall" "Not stalled,Stalled"
|
|
endif
|
|
textline " "
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
group.long (0x770+0x0)++0x03
|
|
line.long 0x00 "USB_UOG_ULPIVIEW,ULPI Viewport"
|
|
eventfld.long 0x00 31. " ULPIWU ,ULPI wake-up" "No,Yes"
|
|
eventfld.long 0x00 30. " ULPIRUN ,ULPI Run " "No,Yes"
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Wrtie"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Different state,Sync state"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,ULPI Data Write "
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Host 1"
|
|
width 24.
|
|
rgroup.long (0x00+0x200)++0x03
|
|
line.long 0x00 "UH1_ID,Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " REVISION[7:0] ,Revision Number of the Core"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NID[5:0] ,Ones Complement Version of ID[5:0]"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ID[5:0] ,Configuration Number"
|
|
textline " "
|
|
rgroup.long (0x04+0x200)++0x03
|
|
line.long 0x00 "UH1_HWGENERAL,General Hardware Register"
|
|
sif (cpuis("K70*"))
|
|
bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "0,1,2,3"
|
|
textline " "
|
|
elif (cpuis("RAYLEIGH-CA7")||cpuis("IMX6*"))
|
|
bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "No Serial Engine,Serial Engine,Soft. programmable(parallel),Soft. programmable(serial)"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " SM ,Transciever type" "0,1"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")
|
|
bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "000,001,010,011,100,101,110,111"
|
|
elif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Reset UTMI/UTMI+,Reset ULPI DDR,Reset ULPI,Reset Serial"
|
|
else
|
|
bitfld.long 0x00 6.--8. " PHYM ,VUSB_HS_PHY_TYPE" "000,001,010,011,100,101,110,111"
|
|
endif
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core/Software programmable" "8 bit/Soft. non-programmable,16 bit/Soft. non-programmable,Reset to 8 bit/Soft. programmable,Reset to 16 bit/Soft. programmable"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core" "00,01,10,11"
|
|
endif
|
|
sif (!cpuis("K70*"))&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 3. " BWT ,Reserved for Internal Testing" "0,1"
|
|
bitfld.long 0x00 1.--2. " CLKC ,VUSB_HS_CLOCK_CONFIGURATION" "00,01,10,11"
|
|
bitfld.long 0x00 0. " RT ,VUSB_HS_RESET_TYPE" "0,1"
|
|
endif
|
|
textline " "
|
|
rgroup.long (0x08+0x200)++0x0F
|
|
line.long 0x00 "UH1_HWHOST,Host Hardware Parameters Register"
|
|
sif (!(cpuis("IMX6*")))
|
|
hexmask.long.byte 0x00 24.--31. 1. " TTPER ,VUSB_HS_TT_PERIODIC_CONTEXTS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TTASY ,VUSB_HS_TT_ASYNC_CONTEXTS"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 1.--3. " NPORT ,Number of downstream ports supported by host controller (NPORT+1)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Host operation mode support" "Not supported,Supported"
|
|
else
|
|
bitfld.long 0x00 1.--3. " NPORT ,VUSB_HS_NUM_PORT+1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Operation mode support for device" "Not supported,Supported"
|
|
endif
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
else
|
|
line.long 0x04 "UH1_HWDEVICE,Device Hardware Parameters Register"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x04 1.--5. " DEVEP ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0. " DC ,Device operation mode support" "Not supported,Supported"
|
|
else
|
|
hexmask.long.byte 0x04 1.--5. 1. " DEVEP ,VUSB_HS_DEV_EP"
|
|
bitfld.long 0x04 0. " DC ,VUSB_HS_DEV" "0,1"
|
|
endif
|
|
endif
|
|
line.long 0x08 "UH1_HWTXBUF,TX Buffer Hardware Parameters Register"
|
|
sif (!(cpuis("IMX6*")))
|
|
bitfld.long 0x08 31. " TXLCR ,VUSB_HS_TX_LOCAL_CONTEXT_REGISTERS" "0,1"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x08 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint"
|
|
sif (!(cpuis("IMX6*")))
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXADD ,Buffer total size for all transmit endpoints"
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer"
|
|
line.long 0x0C "UH1_HWRXBUF,RX Buffer Hardware Parameters Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer"
|
|
textline " "
|
|
group.long (0x80+0x200)++0xf "Device/Host Timer Registers"
|
|
line.long 0x00 "UH1_GPTIMER0LD,General Purpose Timer #0 Load Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General Purpose Timer Load Value"
|
|
line.long 0x04 "UH1_GPTIMER0CTRL,General Purpose Timer #0 Controller"
|
|
bitfld.long 0x04 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Running"
|
|
bitfld.long 0x04 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x04 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General Purpose Timer Counter"
|
|
line.long 0x08 "UH1_GPTIMER1LD,General Purpose Timer #1 Load Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General Purpose Timer Load Value"
|
|
line.long 0x0C "UH1_GPTIMER1CTRL,General Purpose Timer #1 Controller"
|
|
bitfld.long 0x0C 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Running"
|
|
bitfld.long 0x0C 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General Purpose Timer Counter"
|
|
textline " "
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "UH1_SBUSCFG,System Bus Config"
|
|
bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface Burst configuration" "Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified"
|
|
else
|
|
group.long 0x90++0x03 "UH1_SBUSCFG"
|
|
line.long 0x00 "UH1_WRXBUF, RX Buffer Hardware Parameters"
|
|
bitfld.long 0x00 0.--2. " AHBBRST ,AHB Burst" "Unspecified,INCR4/Singles,INCR8/Singles,INCR16/Singles,,INCR4/Unspecified,INCR8/Unspecified,INCR16/Unspecified"
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
rgroup.word (0x100+0x200)++0x01
|
|
line.word 0x00 "UH1_HCIVERSION,EHCI Compliant Register"
|
|
hexmask.word 0x00 0.--15. 1. " HCIVERSION[15:0] ,Host Interface Version Number"
|
|
rgroup.byte (0x103+0x200)++0x00
|
|
line.byte 0x00 "UH1_CAPLENGTH,EHCI Compliant Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CAPLENGTH[7:0] ,Capability Length"
|
|
elif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
rgroup.byte (0x100+0x200)++0x00
|
|
line.byte 0x00 "UH1_CAPLENGTH,Capability Registers Length"
|
|
rgroup.word (0x102+0x200)++0x01
|
|
line.word 0x00 "UH1_HCIVERSION,Host Controller Interface Version"
|
|
else
|
|
rgroup.byte (0x100+0x200)++0x00 "Device/Host Capability Registers"
|
|
line.byte 0x00 "UH1_CAPLENGTH,EHCI Compliant Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CAPLENGTH[7:0] ,Capability Length"
|
|
rgroup.word (0x102+0x200)++0x01
|
|
line.word 0x00 "UH1_HCIVERSION,EHCI Compliant Register"
|
|
hexmask.word 0x00 0.--15. 1. " HCIVERSION[15:0] ,Host Interface Version Number"
|
|
endif
|
|
rgroup.long (0x104+0x200)++0x07
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6SOLOLITE")
|
|
line.long 0x00 "UH1_HCSPARAMS,Host Controller Structural Parameters"
|
|
else
|
|
line.long 0x00 "UH1_HCSPARAMS,EHCI Compliant With Extensions Register"
|
|
endif
|
|
bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " PI ,Port Indicators" "0,1"
|
|
bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,?..."
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
line.long 0x04 "UH1_HCCPARAMS,Host Controller Capability Parameters"
|
|
else
|
|
line.long 0x04 "UH1_HCCPARAMS,EHCI Compliant Register"
|
|
endif
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Disabled,Enabled"
|
|
sif (cpuis("K70*"))
|
|
rgroup.word (0x122+0x200)++0x1
|
|
line.word 0x00 "UH1_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
rgroup.long (0x124+0x200)++0x3
|
|
line.long 0x00 "UH1_DCCPARAMS,Device Control Capability Parameters Register"
|
|
bitfld.long 0x00 8. " HC ,Host Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DC ,Device Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
else
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
else
|
|
rgroup.word (0x120+0x200)++0x1
|
|
line.word 0x00 "UH1_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
endif
|
|
endif
|
|
group.long (0x140+0x200)++0x03
|
|
line.long 0x00 "UH1_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control"
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard"
|
|
sif (!cpuis("K70*"))&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")
|
|
textline " "
|
|
bitfld.long 0x00 12. " ATDTW ,ATDTW" "Cleared,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" ",1,2,3"
|
|
sif (!cpuis("IMX6*"))
|
|
textline " "
|
|
bitfld.long 0x00 7. " LR ,Light Host/Device Controller Reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stopped,Running"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
else
|
|
if ((per.l((0x200+ad:0x73f80000+0x1a8))&0x3)==0x3)
|
|
group.long (0x144+0x200)++0x03
|
|
line.long 0x00 "UH1_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
sif (cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPI ,USB host Periodic Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " UAI ,USB host Asynchronous Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRI ,Frame List Rollover" "No rollover,Rollover"
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
elif ((per.l(0x200+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x144+0x200)++0x03
|
|
line.long 0x00 "UH1_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
sif (cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPI ,USB host Periodic Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " UAI ,USB host Asynchronous Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 7. " SRI ,SOF Received" "Not received,Received"
|
|
eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
hgroup.long (0x144+0x200)++0x03
|
|
hide.long 0x00 "UH1_USBSTS,USB Status Register"
|
|
endif
|
|
endif
|
|
group.long (0x148+0x200)++0x07
|
|
line.long 0x00 "UH1_USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("K70*")||cpuis("IMX6*"))||(cpuis("RAYLEIGH-CA7"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPIE ,USB host Periodic Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host Asynchronous Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " NAKIE ,NAK Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " URE ,USB Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UH1_FRINDEX,USB Frame Index Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index"
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*")&&!cpuis("RAYLEIGH-CA7"))
|
|
hgroup.long (0x150+0x200)++0x03
|
|
hide.long 0x00 "UH1_CTRLDSSEGMENT,CTRLDSSEGMENT"
|
|
endif
|
|
if ((per.l((0x200+ad:0x73f80000+0x1a8))&0x3)==0x3)
|
|
group.long (0x154+0x200)++0x03
|
|
line.long 0x00 "UH1_PERIODICLISTBASE,Host Controller Frame List Base Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)"
|
|
elif ((per.l(0x200+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x154+0x200)++0x03
|
|
line.long 0x00 "UH1_DEVICEADDR,Device Controller USB Device Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x02 " USBADR ,Device Address"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 24. " USBADRA ,Device Address Advance" "0,1"
|
|
endif
|
|
else
|
|
hgroup.long (0x154+0x200)++0x03
|
|
hide.long 0x00 "UH1_DEVICEADDR,Device Controller USB Device Address Register"
|
|
endif
|
|
if ((per.l(0x200+ad:0x73f80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x158+0x200)++0x03
|
|
line.long 0x00 "UH1_ASYNCLISTADDR,Host Controller Next Asynch Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low"
|
|
elif ((per.l(0x200+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x158+0x200)++0x03
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")
|
|
line.long 0x00 "UH1_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
else
|
|
line.long 0x00 "UH1_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
endif
|
|
hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address"
|
|
else
|
|
hgroup.long (0x158+0x200)++0x03
|
|
hide.long 0x00 "UH1_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
group.long 0x15c++0x3
|
|
line.long 0x00 "USBHS_TTCTRL,Host TT Asynchronous Buffer Control"
|
|
hexmask.long.byte 0x00 24.--30. 1. " TTHA ,TT Hub Address"
|
|
endif
|
|
group.long (0x160+0x200)++0x7
|
|
line.long 0x00 "UH1_BURSTSIZE,Programmable Burst Size"
|
|
hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length"
|
|
line.long 0x04 "UH1_TXFILLTUNING,TX FIFO Fill Tuning Register"
|
|
bitfld.long 0x04 16.--21. " TXFIFOTHRES ,FIFO Burst Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 8.--12. " TXSCHEALTH ,Scheduler Health Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead"
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(!cpuis("K70*"))&&(cpu()!="IMX6SOLOLITE")
|
|
group.long (0x16C+0x200)++0x03
|
|
line.long 0x00 "IC_USB,IC_USB Enable"
|
|
bitfld.long 0x00 31. " IC8 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " IC_VDD8 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 27. " IC7 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " IC_VDD7 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " IC6 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " IC_VDD6 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 19. " IC5 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " IC_VDD5 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " IC4 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " IC_VDD4 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 11. " IC3 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " IC_VDD3 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " IC2 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " IC_VDD2 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
endif
|
|
sif (!cpuis("IMX6*"))
|
|
group.long (0x170+0x200)++0x03
|
|
line.long 0x00 "UH1_ULPIVIEW,ULPI Vieport Register"
|
|
bitfld.long 0x00 31. " ULPIWU ,ULPI Wakeup" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "No effect,Read/write"
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Not normal,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,ULPI Data Write"
|
|
endif
|
|
sif (cpuis("IMX6*")||cpuis("RAYLEIGH-CA7"))
|
|
endif
|
|
sif (cpuis("K70*")&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE"))
|
|
rgroup.long (0x180+0x200)++0x03
|
|
line.long 0x00 "UH1_CFGFLAG,Config Flag Register (Reserved)"
|
|
else
|
|
rgroup.long (0x180+0x200)++0x03
|
|
line.long 0x00 "UH1_CONFIGFLAG,Configure Flag Register"
|
|
bitfld.long 0x00 0. " CF ,Configure Flag" "Low,High"
|
|
endif
|
|
if ((per.l(0x200+ad:0x73f80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x184+0x200)++0x03
|
|
line.long 0x00 "UH1_PORTSC1,Port 1 Status and Control Register"
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial,HSIC,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("K70*"))
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Undefined"
|
|
textline " "
|
|
sif (cpuis("IMX6*"))&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,Undefined"
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device"
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*")&&!cpuis("RAYLEIGH-CA7"))
|
|
group.long (0x184+0x200+0x04)++0x1B
|
|
line.long 0x00 "UH1_PORTSC2,Port 2 Status and Control Register"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x04 "UH1_PORTSC3,Port 3 Status and Control Register"
|
|
bitfld.long 0x04 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x04 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x04 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x04 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x04 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x04 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x04 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x04 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x04 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x04 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x04 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x04 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x04 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x04 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x04 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x04 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x04 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x08 "UH1_PORTSC4,Port 4 Status and Control Register"
|
|
bitfld.long 0x08 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x08 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x08 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x08 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x08 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x08 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x08 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x08 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x08 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x08 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x08 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x08 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x08 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x08 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x08 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x08 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x08 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x08 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x08 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x0C "UH1_PORTSC5,Port 5 Status and Control Register"
|
|
bitfld.long 0x0C 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x0C 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x0C 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x0C 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x0C 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x0C 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x0C 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x0C 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x0C 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x0C 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x0C 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x0C 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x0C 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x10 "UH1_PORTSC6,Port 6 Status and Control Register"
|
|
bitfld.long 0x10 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x10 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x10 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x10 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x10 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x10 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x10 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x10 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x10 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
textline " "
|
|
bitfld.long 0x10 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
bitfld.long 0x10 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x10 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x10 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
textline " "
|
|
bitfld.long 0x10 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x10 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x10 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x10 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
eventfld.long 0x10 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x10 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x10 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x14 "UH1_PORTSC7,Port 7 Status and Control Register"
|
|
bitfld.long 0x14 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x14 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x14 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x14 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x14 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x14 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x14 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x14 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x14 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
textline " "
|
|
bitfld.long 0x14 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
bitfld.long 0x14 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x14 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x14 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
textline " "
|
|
bitfld.long 0x14 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x14 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x14 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x14 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x14 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
eventfld.long 0x14 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x14 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x14 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x18 "UH1_PORTSC8,Port 8 Status and Control Register"
|
|
bitfld.long 0x18 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x18 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x18 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x18 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x18 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x18 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x18 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x18 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x18 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x18 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x18 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x18 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x18 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x18 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x18 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x18 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x18 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x18 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x18 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x18 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x18 0. " CCS ,Current Connect Status" "No device,Device"
|
|
endif
|
|
elif ((per.l(0x200+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x184+0x200)++0x03
|
|
line.long 0x00 "UH1_PORTSC1,Port 1 Status and Control Register"
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial,HSIC,?..."
|
|
textline " "
|
|
elif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
textline " "
|
|
elif (!cpuis("K70*"))
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
textline " "
|
|
elif (cpuis("IMX6*"))&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,Undefined"
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
rbitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " CCS ,Current Connect Status" "Not attached,Attached"
|
|
else
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*"))
|
|
hgroup.long (0x184+0x200)++0x1f
|
|
hide.long 0x00 "UH1_PORTSC1,Port 1 Status and Control Register"
|
|
hide.long 0x04 "UH1_PORTSC2,Port 2 Status and Control Register"
|
|
hide.long 0x08 "UH1_PORTSC3,Port 3 Status and Control Register"
|
|
hide.long 0x0c "UH1_PORTSC4,Port 4 Status and Control Register"
|
|
hide.long 0x10 "UH1_PORTSC5,Port 5 Status and Control Register"
|
|
hide.long 0x14 "UH1_PORTSC6,Port 6 Status and Control Register"
|
|
hide.long 0x18 "UH1_PORTSC7,Port 7 Status and Control Register"
|
|
hide.long 0x1c "UH1_PORTSC8,Port 8 Status and Control Register"
|
|
endif
|
|
endif
|
|
textline " "
|
|
textline " "
|
|
group.long (0x1a8+0x200)++0x03
|
|
line.long 0x00 "UH1_USBMODE,USB Device Mode Register"
|
|
bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big"
|
|
bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,,,Host"
|
|
textline " "
|
|
textline " "
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
group.long (0x770+0x200)++0x03
|
|
line.long 0x00 "USB_UH1_ULPIVIEW,ULPI Viewport"
|
|
eventfld.long 0x00 31. " ULPIWU ,ULPI wake-up" "No,Yes"
|
|
eventfld.long 0x00 30. " ULPIRUN ,ULPI Run " "No,Yes"
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Wrtie"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Different state,Sync state"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,ULPI Data Write "
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Host 2"
|
|
width 24.
|
|
rgroup.long (0x00+0x400)++0x03
|
|
line.long 0x00 "UH2_ID,Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " REVISION[7:0] ,Revision Number of the Core"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NID[5:0] ,Ones Complement Version of ID[5:0]"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ID[5:0] ,Configuration Number"
|
|
textline " "
|
|
rgroup.long (0x04+0x400)++0x03
|
|
line.long 0x00 "UH2_HWGENERAL,General Hardware Register"
|
|
sif (cpuis("K70*"))
|
|
bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "0,1,2,3"
|
|
textline " "
|
|
elif (cpuis("RAYLEIGH-CA7")||cpuis("IMX6*"))
|
|
bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "No Serial Engine,Serial Engine,Soft. programmable(parallel),Soft. programmable(serial)"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " SM ,Transciever type" "0,1"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")
|
|
bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "000,001,010,011,100,101,110,111"
|
|
elif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Reset UTMI/UTMI+,Reset ULPI DDR,Reset ULPI,Reset Serial"
|
|
else
|
|
bitfld.long 0x00 6.--8. " PHYM ,VUSB_HS_PHY_TYPE" "000,001,010,011,100,101,110,111"
|
|
endif
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core/Software programmable" "8 bit/Soft. non-programmable,16 bit/Soft. non-programmable,Reset to 8 bit/Soft. programmable,Reset to 16 bit/Soft. programmable"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core" "00,01,10,11"
|
|
endif
|
|
sif (!cpuis("K70*"))&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 3. " BWT ,Reserved for Internal Testing" "0,1"
|
|
bitfld.long 0x00 1.--2. " CLKC ,VUSB_HS_CLOCK_CONFIGURATION" "00,01,10,11"
|
|
bitfld.long 0x00 0. " RT ,VUSB_HS_RESET_TYPE" "0,1"
|
|
endif
|
|
textline " "
|
|
rgroup.long (0x08+0x400)++0x0F
|
|
line.long 0x00 "UH2_HWHOST,Host Hardware Parameters Register"
|
|
sif (!(cpuis("IMX6*")))
|
|
hexmask.long.byte 0x00 24.--31. 1. " TTPER ,VUSB_HS_TT_PERIODIC_CONTEXTS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TTASY ,VUSB_HS_TT_ASYNC_CONTEXTS"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 1.--3. " NPORT ,Number of downstream ports supported by host controller (NPORT+1)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Host operation mode support" "Not supported,Supported"
|
|
else
|
|
bitfld.long 0x00 1.--3. " NPORT ,VUSB_HS_NUM_PORT+1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Operation mode support for device" "Not supported,Supported"
|
|
endif
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
else
|
|
line.long 0x04 "UH2_HWDEVICE,Device Hardware Parameters Register"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x04 1.--5. " DEVEP ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0. " DC ,Device operation mode support" "Not supported,Supported"
|
|
else
|
|
hexmask.long.byte 0x04 1.--5. 1. " DEVEP ,VUSB_HS_DEV_EP"
|
|
bitfld.long 0x04 0. " DC ,VUSB_HS_DEV" "0,1"
|
|
endif
|
|
endif
|
|
line.long 0x08 "UH2_HWTXBUF,TX Buffer Hardware Parameters Register"
|
|
sif (!(cpuis("IMX6*")))
|
|
bitfld.long 0x08 31. " TXLCR ,VUSB_HS_TX_LOCAL_CONTEXT_REGISTERS" "0,1"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x08 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint"
|
|
sif (!(cpuis("IMX6*")))
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXADD ,Buffer total size for all transmit endpoints"
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer"
|
|
line.long 0x0C "UH2_HWRXBUF,RX Buffer Hardware Parameters Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer"
|
|
textline " "
|
|
group.long (0x80+0x400)++0xf "Device/Host Timer Registers"
|
|
line.long 0x00 "UH2_GPTIMER0LD,General Purpose Timer #0 Load Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General Purpose Timer Load Value"
|
|
line.long 0x04 "UH2_GPTIMER0CTRL,General Purpose Timer #0 Controller"
|
|
bitfld.long 0x04 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Running"
|
|
bitfld.long 0x04 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x04 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General Purpose Timer Counter"
|
|
line.long 0x08 "UH2_GPTIMER1LD,General Purpose Timer #1 Load Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General Purpose Timer Load Value"
|
|
line.long 0x0C "UH2_GPTIMER1CTRL,General Purpose Timer #1 Controller"
|
|
bitfld.long 0x0C 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Running"
|
|
bitfld.long 0x0C 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General Purpose Timer Counter"
|
|
textline " "
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "UH2_SBUSCFG,System Bus Config"
|
|
bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface Burst configuration" "Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified"
|
|
else
|
|
group.long 0x90++0x03 "UH2_SBUSCFG"
|
|
line.long 0x00 "UH2_WRXBUF, RX Buffer Hardware Parameters"
|
|
bitfld.long 0x00 0.--2. " AHBBRST ,AHB Burst" "Unspecified,INCR4/Singles,INCR8/Singles,INCR16/Singles,,INCR4/Unspecified,INCR8/Unspecified,INCR16/Unspecified"
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
rgroup.word (0x100+0x400)++0x01
|
|
line.word 0x00 "UH2_HCIVERSION,EHCI Compliant Register"
|
|
hexmask.word 0x00 0.--15. 1. " HCIVERSION[15:0] ,Host Interface Version Number"
|
|
rgroup.byte (0x103+0x400)++0x00
|
|
line.byte 0x00 "UH2_CAPLENGTH,EHCI Compliant Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CAPLENGTH[7:0] ,Capability Length"
|
|
elif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
rgroup.byte (0x100+0x400)++0x00
|
|
line.byte 0x00 "UH2_CAPLENGTH,Capability Registers Length"
|
|
rgroup.word (0x102+0x400)++0x01
|
|
line.word 0x00 "UH2_HCIVERSION,Host Controller Interface Version"
|
|
else
|
|
rgroup.byte (0x100+0x400)++0x00 "Device/Host Capability Registers"
|
|
line.byte 0x00 "UH2_CAPLENGTH,EHCI Compliant Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CAPLENGTH[7:0] ,Capability Length"
|
|
rgroup.word (0x102+0x400)++0x01
|
|
line.word 0x00 "UH2_HCIVERSION,EHCI Compliant Register"
|
|
hexmask.word 0x00 0.--15. 1. " HCIVERSION[15:0] ,Host Interface Version Number"
|
|
endif
|
|
rgroup.long (0x104+0x400)++0x07
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6SOLOLITE")
|
|
line.long 0x00 "UH2_HCSPARAMS,Host Controller Structural Parameters"
|
|
else
|
|
line.long 0x00 "UH2_HCSPARAMS,EHCI Compliant With Extensions Register"
|
|
endif
|
|
bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " PI ,Port Indicators" "0,1"
|
|
bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,?..."
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
line.long 0x04 "UH2_HCCPARAMS,Host Controller Capability Parameters"
|
|
else
|
|
line.long 0x04 "UH2_HCCPARAMS,EHCI Compliant Register"
|
|
endif
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Disabled,Enabled"
|
|
sif (cpuis("K70*"))
|
|
rgroup.word (0x122+0x400)++0x1
|
|
line.word 0x00 "UH2_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
rgroup.long (0x124+0x400)++0x3
|
|
line.long 0x00 "UH2_DCCPARAMS,Device Control Capability Parameters Register"
|
|
bitfld.long 0x00 8. " HC ,Host Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DC ,Device Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
else
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rgroup.word (0x120+0x400)++0x1
|
|
line.word 0x00 "UH2_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
else
|
|
rgroup.word (0x120+0x400)++0x1
|
|
line.word 0x00 "UH2_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
endif
|
|
endif
|
|
group.long (0x140+0x400)++0x03
|
|
line.long 0x00 "UH2_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control"
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard"
|
|
sif (!cpuis("K70*"))&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")
|
|
textline " "
|
|
bitfld.long 0x00 12. " ATDTW ,ATDTW" "Cleared,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" ",1,2,3"
|
|
sif (!cpuis("IMX6*"))
|
|
textline " "
|
|
bitfld.long 0x00 7. " LR ,Light Host/Device Controller Reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stopped,Running"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
else
|
|
if ((per.l((0x400+ad:0x73f80000+0x1a8))&0x3)==0x3)
|
|
group.long (0x144+0x400)++0x03
|
|
line.long 0x00 "UH2_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
sif (cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPI ,USB host Periodic Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " UAI ,USB host Asynchronous Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRI ,Frame List Rollover" "No rollover,Rollover"
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
elif ((per.l(0x400+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x144+0x400)++0x03
|
|
line.long 0x00 "UH2_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
sif (cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPI ,USB host Periodic Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " UAI ,USB host Asynchronous Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 7. " SRI ,SOF Received" "Not received,Received"
|
|
eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
hgroup.long (0x144+0x400)++0x03
|
|
hide.long 0x00 "UH2_USBSTS,USB Status Register"
|
|
endif
|
|
endif
|
|
group.long (0x148+0x400)++0x07
|
|
line.long 0x00 "UH2_USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("K70*")||cpuis("IMX6*"))||(cpuis("RAYLEIGH-CA7"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPIE ,USB host Periodic Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host Asynchronous Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " NAKIE ,NAK Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " URE ,USB Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UH2_FRINDEX,USB Frame Index Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index"
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*")&&!cpuis("RAYLEIGH-CA7"))
|
|
hgroup.long (0x150+0x400)++0x03
|
|
hide.long 0x00 "UH2_CTRLDSSEGMENT,CTRLDSSEGMENT"
|
|
endif
|
|
if ((per.l((0x400+ad:0x73f80000+0x1a8))&0x3)==0x3)
|
|
group.long (0x154+0x400)++0x03
|
|
line.long 0x00 "UH2_PERIODICLISTBASE,Host Controller Frame List Base Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)"
|
|
elif ((per.l(0x400+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x154+0x400)++0x03
|
|
line.long 0x00 "UH2_DEVICEADDR,Device Controller USB Device Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x02 " USBADR ,Device Address"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 24. " USBADRA ,Device Address Advance" "0,1"
|
|
endif
|
|
else
|
|
hgroup.long (0x154+0x400)++0x03
|
|
hide.long 0x00 "UH2_DEVICEADDR,Device Controller USB Device Address Register"
|
|
endif
|
|
if ((per.l(0x400+ad:0x73f80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x158+0x400)++0x03
|
|
line.long 0x00 "UH2_ASYNCLISTADDR,Host Controller Next Asynch Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low"
|
|
elif ((per.l(0x400+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x158+0x400)++0x03
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")
|
|
line.long 0x00 "UH2_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
else
|
|
line.long 0x00 "UH2_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
endif
|
|
hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address"
|
|
else
|
|
hgroup.long (0x158+0x400)++0x03
|
|
hide.long 0x00 "UH2_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
group.long 0x15c++0x3
|
|
line.long 0x00 "USBHS_TTCTRL,Host TT Asynchronous Buffer Control"
|
|
hexmask.long.byte 0x00 24.--30. 1. " TTHA ,TT Hub Address"
|
|
endif
|
|
group.long (0x160+0x400)++0x7
|
|
line.long 0x00 "UH2_BURSTSIZE,Programmable Burst Size"
|
|
hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length"
|
|
line.long 0x04 "UH2_TXFILLTUNING,TX FIFO Fill Tuning Register"
|
|
bitfld.long 0x04 16.--21. " TXFIFOTHRES ,FIFO Burst Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 8.--12. " TXSCHEALTH ,Scheduler Health Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead"
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(!cpuis("K70*"))&&(cpu()!="IMX6SOLOLITE")
|
|
group.long (0x16C+0x400)++0x03
|
|
line.long 0x00 "IC_USB,IC_USB Enable"
|
|
bitfld.long 0x00 31. " IC8 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " IC_VDD8 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 27. " IC7 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " IC_VDD7 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " IC6 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " IC_VDD6 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 19. " IC5 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " IC_VDD5 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " IC4 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " IC_VDD4 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 11. " IC3 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " IC_VDD3 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " IC2 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " IC_VDD2 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
endif
|
|
sif (!cpuis("IMX6*"))
|
|
group.long (0x170+0x400)++0x03
|
|
line.long 0x00 "UH2_ULPIVIEW,ULPI Vieport Register"
|
|
bitfld.long 0x00 31. " ULPIWU ,ULPI Wakeup" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "No effect,Read/write"
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Not normal,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,ULPI Data Write"
|
|
endif
|
|
sif (cpuis("IMX6*")||cpuis("RAYLEIGH-CA7"))
|
|
endif
|
|
sif (cpuis("K70*")&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE"))
|
|
rgroup.long (0x180+0x400)++0x03
|
|
line.long 0x00 "UH2_CFGFLAG,Config Flag Register (Reserved)"
|
|
else
|
|
rgroup.long (0x180+0x400)++0x03
|
|
line.long 0x00 "UH2_CONFIGFLAG,Configure Flag Register"
|
|
bitfld.long 0x00 0. " CF ,Configure Flag" "Low,High"
|
|
endif
|
|
if ((per.l(0x400+ad:0x73f80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x184+0x400)++0x03
|
|
line.long 0x00 "UH2_PORTSC1,Port 1 Status and Control Register"
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial,HSIC,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("K70*"))
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Undefined"
|
|
textline " "
|
|
sif (cpuis("IMX6*"))&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,Undefined"
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device"
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*")&&!cpuis("RAYLEIGH-CA7"))
|
|
group.long (0x184+0x400+0x04)++0x1B
|
|
line.long 0x00 "UH2_PORTSC2,Port 2 Status and Control Register"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x04 "UH2_PORTSC3,Port 3 Status and Control Register"
|
|
bitfld.long 0x04 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x04 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x04 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x04 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x04 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x04 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x04 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x04 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x04 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x04 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x04 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x04 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x04 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x04 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x04 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x04 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x04 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x08 "UH2_PORTSC4,Port 4 Status and Control Register"
|
|
bitfld.long 0x08 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x08 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x08 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x08 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x08 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x08 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x08 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x08 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x08 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x08 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x08 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x08 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x08 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x08 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x08 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x08 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x08 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x08 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x08 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x0C "UH2_PORTSC5,Port 5 Status and Control Register"
|
|
bitfld.long 0x0C 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x0C 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x0C 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x0C 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x0C 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x0C 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x0C 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x0C 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x0C 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x0C 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x0C 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x0C 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x0C 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x10 "UH2_PORTSC6,Port 6 Status and Control Register"
|
|
bitfld.long 0x10 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x10 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x10 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x10 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x10 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x10 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x10 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x10 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x10 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
textline " "
|
|
bitfld.long 0x10 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
bitfld.long 0x10 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x10 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x10 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
textline " "
|
|
bitfld.long 0x10 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x10 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x10 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x10 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
eventfld.long 0x10 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x10 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x10 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x14 "UH2_PORTSC7,Port 7 Status and Control Register"
|
|
bitfld.long 0x14 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x14 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x14 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x14 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x14 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x14 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x14 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x14 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x14 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
textline " "
|
|
bitfld.long 0x14 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
bitfld.long 0x14 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x14 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x14 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
textline " "
|
|
bitfld.long 0x14 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x14 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x14 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x14 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x14 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
eventfld.long 0x14 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x14 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x14 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x18 "UH2_PORTSC8,Port 8 Status and Control Register"
|
|
bitfld.long 0x18 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x18 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x18 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x18 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x18 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x18 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x18 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x18 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x18 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x18 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x18 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x18 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x18 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x18 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x18 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x18 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x18 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x18 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x18 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x18 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x18 0. " CCS ,Current Connect Status" "No device,Device"
|
|
endif
|
|
elif ((per.l(0x400+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x184+0x400)++0x03
|
|
line.long 0x00 "UH2_PORTSC1,Port 1 Status and Control Register"
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial,HSIC,?..."
|
|
textline " "
|
|
elif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
textline " "
|
|
elif (!cpuis("K70*"))
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
textline " "
|
|
elif (cpuis("IMX6*"))&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,Undefined"
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
rbitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " CCS ,Current Connect Status" "Not attached,Attached"
|
|
else
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*"))
|
|
hgroup.long (0x184+0x400)++0x1f
|
|
hide.long 0x00 "UH2_PORTSC1,Port 1 Status and Control Register"
|
|
hide.long 0x04 "UH2_PORTSC2,Port 2 Status and Control Register"
|
|
hide.long 0x08 "UH2_PORTSC3,Port 3 Status and Control Register"
|
|
hide.long 0x0c "UH2_PORTSC4,Port 4 Status and Control Register"
|
|
hide.long 0x10 "UH2_PORTSC5,Port 5 Status and Control Register"
|
|
hide.long 0x14 "UH2_PORTSC6,Port 6 Status and Control Register"
|
|
hide.long 0x18 "UH2_PORTSC7,Port 7 Status and Control Register"
|
|
hide.long 0x1c "UH2_PORTSC8,Port 8 Status and Control Register"
|
|
endif
|
|
endif
|
|
textline " "
|
|
textline " "
|
|
group.long (0x1a8+0x400)++0x03
|
|
line.long 0x00 "UH2_USBMODE,USB Device Mode Register"
|
|
bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big"
|
|
bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,,Device,Host"
|
|
textline " "
|
|
textline " "
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
group.long (0x770+0x400)++0x03
|
|
line.long 0x00 "USB_UH2_ULPIVIEW,ULPI Viewport"
|
|
eventfld.long 0x00 31. " ULPIWU ,ULPI wake-up" "No,Yes"
|
|
eventfld.long 0x00 30. " ULPIRUN ,ULPI Run " "No,Yes"
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Wrtie"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Different state,Sync state"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,ULPI Data Write "
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Host 3"
|
|
width 24.
|
|
rgroup.long (0x00+0x600)++0x03
|
|
line.long 0x00 "UH3_ID,Identification Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " REVISION[7:0] ,Revision Number of the Core"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NID[5:0] ,Ones Complement Version of ID[5:0]"
|
|
hexmask.long.byte 0x00 0.--5. 1. " ID[5:0] ,Configuration Number"
|
|
textline " "
|
|
rgroup.long (0x04+0x600)++0x03
|
|
line.long 0x00 "UH3_HWGENERAL,General Hardware Register"
|
|
sif (cpuis("K70*"))
|
|
bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "0,1,2,3"
|
|
textline " "
|
|
elif (cpuis("RAYLEIGH-CA7")||cpuis("IMX6*"))
|
|
bitfld.long 0x00 9.--10. " SM ,Serial interface mode capability" "No Serial Engine,Serial Engine,Soft. programmable(parallel),Soft. programmable(serial)"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9. " SM ,Transciever type" "0,1"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")
|
|
bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "000,001,010,011,100,101,110,111"
|
|
elif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 6.--8. " PHYM ,Transciever type" "UTMI/UMTI+,ULPI DDR,ULPI,Serial Only,Reset UTMI/UTMI+,Reset ULPI DDR,Reset ULPI,Reset Serial"
|
|
else
|
|
bitfld.long 0x00 6.--8. " PHYM ,VUSB_HS_PHY_TYPE" "000,001,010,011,100,101,110,111"
|
|
endif
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core/Software programmable" "8 bit/Soft. non-programmable,16 bit/Soft. non-programmable,Reset to 8 bit/Soft. programmable,Reset to 16 bit/Soft. programmable"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PHYW ,Data width of the transciever connected to the controller core" "00,01,10,11"
|
|
endif
|
|
sif (!cpuis("K70*"))&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 3. " BWT ,Reserved for Internal Testing" "0,1"
|
|
bitfld.long 0x00 1.--2. " CLKC ,VUSB_HS_CLOCK_CONFIGURATION" "00,01,10,11"
|
|
bitfld.long 0x00 0. " RT ,VUSB_HS_RESET_TYPE" "0,1"
|
|
endif
|
|
textline " "
|
|
rgroup.long (0x08+0x600)++0x0F
|
|
line.long 0x00 "UH3_HWHOST,Host Hardware Parameters Register"
|
|
sif (!(cpuis("IMX6*")))
|
|
hexmask.long.byte 0x00 24.--31. 1. " TTPER ,VUSB_HS_TT_PERIODIC_CONTEXTS"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TTASY ,VUSB_HS_TT_ASYNC_CONTEXTS"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 1.--3. " NPORT ,Number of downstream ports supported by host controller (NPORT+1)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Host operation mode support" "Not supported,Supported"
|
|
else
|
|
bitfld.long 0x00 1.--3. " NPORT ,VUSB_HS_NUM_PORT+1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " HC ,Operation mode support for device" "Not supported,Supported"
|
|
endif
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
else
|
|
line.long 0x04 "UH3_HWDEVICE,Device Hardware Parameters Register"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x04 1.--5. " DEVEP ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0. " DC ,Device operation mode support" "Not supported,Supported"
|
|
else
|
|
hexmask.long.byte 0x04 1.--5. 1. " DEVEP ,VUSB_HS_DEV_EP"
|
|
bitfld.long 0x04 0. " DC ,VUSB_HS_DEV" "0,1"
|
|
endif
|
|
endif
|
|
line.long 0x08 "UH3_HWTXBUF,TX Buffer Hardware Parameters Register"
|
|
sif (!(cpuis("IMX6*")))
|
|
bitfld.long 0x08 31. " TXLCR ,VUSB_HS_TX_LOCAL_CONTEXT_REGISTERS" "0,1"
|
|
textline " "
|
|
endif
|
|
hexmask.long.byte 0x08 16.--23. 1. " TXCHANADD ,Buffer size of each transmit endpoint"
|
|
sif (!(cpuis("IMX6*")))
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " TXADD ,Buffer total size for all transmit endpoints"
|
|
endif
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " TXBURST ,Default burst size for memory to TX buffer transfer"
|
|
line.long 0x0C "UH3_HWRXBUF,RX Buffer Hardware Parameters Register"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " RXADD ,Buffer total size for all receive endpoints"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " RXBURST ,Default burst size for memory to RX buffer transfer"
|
|
textline " "
|
|
group.long (0x80+0x600)++0xf "Device/Host Timer Registers"
|
|
line.long 0x00 "UH3_GPTIMER0LD,General Purpose Timer #0 Load Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General Purpose Timer Load Value"
|
|
line.long 0x04 "UH3_GPTIMER0CTRL,General Purpose Timer #0 Controller"
|
|
bitfld.long 0x04 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Running"
|
|
bitfld.long 0x04 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x04 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General Purpose Timer Counter"
|
|
line.long 0x08 "UH3_GPTIMER1LD,General Purpose Timer #1 Load Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General Purpose Timer Load Value"
|
|
line.long 0x0C "UH3_GPTIMER1CTRL,General Purpose Timer #1 Controller"
|
|
bitfld.long 0x0C 31. " GPTRUN ,General Purpose Timer Run" "Stopped,Running"
|
|
bitfld.long 0x0C 30. " GPTRST ,General Purpose Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 24. " GPTMODE ,General Purpose Timer Mode" "One Shot,Repeat"
|
|
textline " "
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General Purpose Timer Counter"
|
|
textline " "
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "UH3_SBUSCFG,System Bus Config"
|
|
bitfld.long 0x00 0.--2. " AHBBRST ,AHB master interface Burst configuration" "Unspecified,INCR4/Singles,INCR8/INCR4/Singles,INCR16/INCR8/INCR4/Singles,,INCR4/Unspecified,INCR8/INCR4/Unspecified,INCR16/INCR8/INCR4/Unspecified"
|
|
else
|
|
group.long 0x90++0x03 "UH3_SBUSCFG"
|
|
line.long 0x00 "UH3_WRXBUF, RX Buffer Hardware Parameters"
|
|
bitfld.long 0x00 0.--2. " AHBBRST ,AHB Burst" "Unspecified,INCR4/Singles,INCR8/Singles,INCR16/Singles,,INCR4/Unspecified,INCR8/Unspecified,INCR16/Unspecified"
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
rgroup.word (0x100+0x600)++0x01
|
|
line.word 0x00 "UH3_HCIVERSION,EHCI Compliant Register"
|
|
hexmask.word 0x00 0.--15. 1. " HCIVERSION[15:0] ,Host Interface Version Number"
|
|
rgroup.byte (0x103+0x600)++0x00
|
|
line.byte 0x00 "UH3_CAPLENGTH,EHCI Compliant Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CAPLENGTH[7:0] ,Capability Length"
|
|
elif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
rgroup.byte (0x100+0x600)++0x00
|
|
line.byte 0x00 "UH3_CAPLENGTH,Capability Registers Length"
|
|
rgroup.word (0x102+0x600)++0x01
|
|
line.word 0x00 "UH3_HCIVERSION,Host Controller Interface Version"
|
|
else
|
|
rgroup.byte (0x100+0x600)++0x00 "Device/Host Capability Registers"
|
|
line.byte 0x00 "UH3_CAPLENGTH,EHCI Compliant Register"
|
|
hexmask.byte 0x00 0.--7. 1. " CAPLENGTH[7:0] ,Capability Length"
|
|
rgroup.word (0x102+0x600)++0x01
|
|
line.word 0x00 "UH3_HCIVERSION,EHCI Compliant Register"
|
|
hexmask.word 0x00 0.--15. 1. " HCIVERSION[15:0] ,Host Interface Version Number"
|
|
endif
|
|
rgroup.long (0x104+0x600)++0x07
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6SOLOLITE")
|
|
line.long 0x00 "UH3_HCSPARAMS,Host Controller Structural Parameters"
|
|
else
|
|
line.long 0x00 "UH3_HCSPARAMS,EHCI Compliant With Extensions Register"
|
|
endif
|
|
bitfld.long 0x00 24.--27. " N_TT[3:0] ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " N_PTT[3:0] ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " PI ,Port Indicators" "0,1"
|
|
bitfld.long 0x00 12.--15. " N_CC[3:0] ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " N_PCC[3:0] ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4. " PPC ,Port Power Control" "Not included,Included"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS[3:0] ,Number of Downstream Ports" ",1,2,3,4,5,6,7,8,?..."
|
|
endif
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
line.long 0x04 "UH3_HCCPARAMS,Host Controller Capability Parameters"
|
|
else
|
|
line.long 0x04 "UH3_HCCPARAMS,EHCI Compliant Register"
|
|
endif
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP[7:0] ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x04 4.--7. " IST[7:4] ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 2. " ASP ,Asynchronous Schedule Park Capability" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PFL ,Programmable Frame List Flag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ADC ,64-bit Addressing Capability" "Disabled,Enabled"
|
|
sif (cpuis("K70*"))
|
|
rgroup.word (0x122+0x600)++0x1
|
|
line.word 0x00 "UH3_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
rgroup.long (0x124+0x600)++0x3
|
|
line.long 0x00 "UH3_DCCPARAMS,Device Control Capability Parameters Register"
|
|
bitfld.long 0x00 8. " HC ,Host Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DC ,Device Capable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--4. " DEN[4:0] ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
else
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
rgroup.word (0x120+0x600)++0x1
|
|
line.word 0x00 "UH3_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
else
|
|
rgroup.word (0x120+0x600)++0x1
|
|
line.word 0x00 "UH3_DCIVERSION,Device Interface Version Number Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCIVERSION[15:0] ,Device Interface Version Number"
|
|
endif
|
|
endif
|
|
group.long (0x140+0x600)++0x03
|
|
line.long 0x00 "UH3_USBCMD,USB Command Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC[7:0] ,Interrupt Threshold Control"
|
|
textline " "
|
|
sif (cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Hazard,No hazard"
|
|
sif (!cpuis("K70*"))&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")
|
|
textline " "
|
|
bitfld.long 0x00 12. " ATDTW ,ATDTW" "Cleared,Set"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" ",1,2,3"
|
|
sif (!cpuis("IMX6*"))
|
|
textline " "
|
|
bitfld.long 0x00 7. " LR ,Light Host/Device Controller Reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. 15. " FS[2:0] ,Frame List Size 1" "1024,512,256,128,64,32,16,8"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST ,Controller Reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stopped,Running"
|
|
sif (cpu()=="IMX6SOLOLITE")
|
|
else
|
|
if ((per.l((0x600+ad:0x73f80000+0x1a8))&0x3)==0x3)
|
|
group.long (0x144+0x600)++0x03
|
|
line.long 0x00 "UH3_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
sif (cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPI ,USB host Periodic Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " UAI ,USB host Asynchronous Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RCL ,Reclamation" "Not empty,Empty"
|
|
bitfld.long 0x00 12. " HCH ,HC Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " SRI ,SOF Received" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " AAI ,Interrupt on Async Advance" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRI ,Frame List Rollover" "No rollover,Rollover"
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
elif ((per.l(0x600+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x144+0x600)++0x03
|
|
line.long 0x00 "UH3_USBSTS,USB Status Register"
|
|
eventfld.long 0x00 25. " TI1 ,General Purpose Timer Interrupt 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " TI0 ,General Purpose Timer Interrupt 0" "No interrupt,Interrupt"
|
|
sif (cpuis("K70*"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPI ,USB host Periodic Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " UAI ,USB host Asynchronous Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
sif (cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
rbitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 16. " NAKI ,NAK Interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPII ,ULPI Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SLI ,DC Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 7. " SRI ,SOF Received" "Not received,Received"
|
|
eventfld.long 0x00 6. " URI ,USB Reset Received" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SEI ,System Error" "No error,Error"
|
|
bitfld.long 0x00 2. " PCI ,Port Change Detect" "Not changed,Changed"
|
|
bitfld.long 0x00 1. " UEI ,USB Error Interrupt" "No error,Error"
|
|
bitfld.long 0x00 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
else
|
|
hgroup.long (0x144+0x600)++0x03
|
|
hide.long 0x00 "UH3_USBSTS,USB Status Register"
|
|
endif
|
|
endif
|
|
group.long (0x148+0x600)++0x07
|
|
line.long 0x00 "UH3_USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x00 25. " TIE1 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 0" "Disabled,Enabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 24. " TIE0 ,GPT Interrupt Enable 1" "Disabled,Enabled"
|
|
endif
|
|
sif (cpuis("K70*")||cpuis("IMX6*"))||(cpuis("RAYLEIGH-CA7"))
|
|
textline " "
|
|
bitfld.long 0x00 19. " UPIE ,USB host Periodic Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " UAIE ,USB host Asynchronous Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " NAKIE ,NAK Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPIE ,ULPI Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLE ,Sleep Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SRE ,SOF Received Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " URE ,USB Reset Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SEE ,System Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UH3_FRINDEX,USB Frame Index Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame Index"
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*")&&!cpuis("RAYLEIGH-CA7"))
|
|
hgroup.long (0x150+0x600)++0x03
|
|
hide.long 0x00 "UH3_CTRLDSSEGMENT,CTRLDSSEGMENT"
|
|
endif
|
|
if ((per.l((0x600+ad:0x73f80000+0x1a8))&0x3)==0x3)
|
|
group.long (0x154+0x600)++0x03
|
|
line.long 0x00 "UH3_PERIODICLISTBASE,Host Controller Frame List Base Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " BASEADR ,Base Address (Low)"
|
|
elif ((per.l(0x600+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x154+0x600)++0x03
|
|
line.long 0x00 "UH3_DEVICEADDR,Device Controller USB Device Address Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x02 " USBADR ,Device Address"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 24. " USBADRA ,Device Address Advance" "0,1"
|
|
endif
|
|
else
|
|
hgroup.long (0x154+0x600)++0x03
|
|
hide.long 0x00 "UH3_DEVICEADDR,Device Controller USB Device Address Register"
|
|
endif
|
|
if ((per.l(0x600+ad:0x73f80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x158+0x600)++0x03
|
|
line.long 0x00 "UH3_ASYNCLISTADDR,Host Controller Next Asynch Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " ASYBASE[31:5] ,Link Pointer Low"
|
|
elif ((per.l(0x600+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x158+0x600)++0x03
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6SOLO")||(cpu()=="IMX6DUALLITE")
|
|
line.long 0x00 "UH3_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
else
|
|
line.long 0x00 "UH3_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
endif
|
|
hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE[31:11] ,Device Controller Endpoint List Address"
|
|
else
|
|
hgroup.long (0x158+0x600)++0x03
|
|
hide.long 0x00 "UH3_ENDPTLISTADDR,Device Controller Endpoint List Address Register"
|
|
endif
|
|
sif (cpuis("K70*"))
|
|
group.long 0x15c++0x3
|
|
line.long 0x00 "USBHS_TTCTRL,Host TT Asynchronous Buffer Control"
|
|
hexmask.long.byte 0x00 24.--30. 1. " TTHA ,TT Hub Address"
|
|
endif
|
|
group.long (0x160+0x600)++0x7
|
|
line.long 0x00 "UH3_BURSTSIZE,Programmable Burst Size"
|
|
hexmask.long.word 0x00 8.--16. 1. " TXPBURST ,Programmable TX Burst Length"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length"
|
|
line.long 0x04 "UH3_TXFILLTUNING,TX FIFO Fill Tuning Register"
|
|
bitfld.long 0x04 16.--21. " TXFIFOTHRES ,FIFO Burst Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 8.--12. " TXSCHEALTH ,Scheduler Health Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXSCHOH ,Scheduler Overhead"
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(!cpuis("K70*"))&&(cpu()!="IMX6SOLOLITE")
|
|
group.long (0x16C+0x600)++0x03
|
|
line.long 0x00 "IC_USB,IC_USB Enable"
|
|
bitfld.long 0x00 31. " IC8 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--30. " IC_VDD8 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 27. " IC7 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--26. " IC_VDD7 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " IC6 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " IC_VDD6 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 19. " IC5 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " IC_VDD5 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " IC4 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " IC_VDD4 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
bitfld.long 0x00 11. " IC3 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " IC_VDD3 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " IC2 ,Inter-Chip transceiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " IC_VDD2 ,PIt selects which voltage is being supplied to the peripheral through each port" "No voltage,1.0 V,1.2 V,1.5 V,1.8 V,3.0 V,?..."
|
|
endif
|
|
sif (!cpuis("IMX6*"))
|
|
group.long (0x170+0x600)++0x03
|
|
line.long 0x00 "UH3_ULPIVIEW,ULPI Vieport Register"
|
|
bitfld.long 0x00 31. " ULPIWU ,ULPI Wakeup" "No wakeup,Wakeup"
|
|
bitfld.long 0x00 30. " ULPIRUN ,ULPI Read/Write Run" "No effect,Read/write"
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Write"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Not normal,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,ULPI Data Write"
|
|
endif
|
|
sif (cpuis("IMX6*")||cpuis("RAYLEIGH-CA7"))
|
|
endif
|
|
sif (cpuis("K70*")&&(cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE"))
|
|
rgroup.long (0x180+0x600)++0x03
|
|
line.long 0x00 "UH3_CFGFLAG,Config Flag Register (Reserved)"
|
|
else
|
|
rgroup.long (0x180+0x600)++0x03
|
|
line.long 0x00 "UH3_CONFIGFLAG,Configure Flag Register"
|
|
bitfld.long 0x00 0. " CF ,Configure Flag" "Low,High"
|
|
endif
|
|
if ((per.l(0x600+ad:0x73f80000+0x1a8)&0x3)==0x3)
|
|
group.long (0x184+0x600)++0x03
|
|
line.long 0x00 "UH3_PORTSC1,Port 1 Status and Control Register"
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial,HSIC,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("K70*"))
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Undefined"
|
|
textline " "
|
|
sif (cpuis("IMX6*"))&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,Undefined"
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current Active" "No over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device"
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*")&&!cpuis("RAYLEIGH-CA7"))
|
|
group.long (0x184+0x600+0x04)++0x1B
|
|
line.long 0x00 "UH3_PORTSC2,Port 2 Status and Control Register"
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x04 "UH3_PORTSC3,Port 3 Status and Control Register"
|
|
bitfld.long 0x04 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x04 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x04 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x04 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x04 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x04 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x04 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x04 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x04 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x04 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x04 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x04 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x04 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x04 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x04 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x04 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x04 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x04 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x08 "UH3_PORTSC4,Port 4 Status and Control Register"
|
|
bitfld.long 0x08 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x08 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x08 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x08 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x08 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x08 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x08 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x08 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x08 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x08 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x08 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x08 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x08 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x08 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x08 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x08 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x08 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x08 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x08 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x0C "UH3_PORTSC5,Port 5 Status and Control Register"
|
|
bitfld.long 0x0C 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x0C 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x0C 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x0C 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x0C 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x0C 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x0C 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x0C 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x0C 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x0C 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x0C 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x0C 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x0C 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x0C 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x0C 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x10 "UH3_PORTSC6,Port 6 Status and Control Register"
|
|
bitfld.long 0x10 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x10 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x10 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x10 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x10 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x10 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x10 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x10 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x10 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
textline " "
|
|
bitfld.long 0x10 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
bitfld.long 0x10 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x10 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x10 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
textline " "
|
|
bitfld.long 0x10 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x10 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x10 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x10 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
eventfld.long 0x10 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x10 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x10 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x14 "UH3_PORTSC7,Port 7 Status and Control Register"
|
|
bitfld.long 0x14 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x14 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x14 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x14 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x14 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x14 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x14 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x14 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,SE0,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x14 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
textline " "
|
|
bitfld.long 0x14 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
bitfld.long 0x14 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x14 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x14 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
textline " "
|
|
bitfld.long 0x14 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x14 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x14 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x14 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x14 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
eventfld.long 0x14 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x14 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x14 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x14 0. " CCS ,Current Connect Status" "No device,Device"
|
|
line.long 0x18 "UH3_PORTSC8,Port 8 Status and Control Register"
|
|
bitfld.long 0x18 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
bitfld.long 0x18 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x18 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
bitfld.long 0x18 26.--27. " PSPD ,Port Speed" "Full,Low,High,"
|
|
textline " "
|
|
bitfld.long 0x18 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
bitfld.long 0x18 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x18 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x18 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
bitfld.long 0x18 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,"
|
|
bitfld.long 0x18 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x18 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x18 10.--11. " LS ,Line Status" "SE0,J-state,K-state,"
|
|
bitfld.long 0x18 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
bitfld.long 0x18 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x18 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x18 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
eventfld.long 0x18 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
bitfld.long 0x18 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x18 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x18 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
eventfld.long 0x18 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x18 0. " CCS ,Current Connect Status" "No device,Device"
|
|
endif
|
|
elif ((per.l(0x600+ad:0x73f80000+0x1a8)&0x3)==0x2)
|
|
group.long (0x184+0x600)++0x03
|
|
line.long 0x00 "UH3_PORTSC1,Port 1 Status and Control Register"
|
|
sif (cpuis("RAYLEIGH-CA7"))||(cpu()=="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial,HSIC,?..."
|
|
textline " "
|
|
elif (cpuis("IMX6*"))
|
|
bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI/UTMI+,,ULPI,Serial"
|
|
textline " "
|
|
elif (!cpuis("K70*"))
|
|
bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "Not selected,Selected"
|
|
bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,16-bit"
|
|
textline " "
|
|
elif (cpuis("IMX6*"))&&(cpu()!="IMX6SOLOLITE")
|
|
bitfld.long 0x00 25. " PTS[2] ,Parallel Transceiver Select - RW" "No effect,UTMI for HSIC PHY"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full,Low,High,Undefined"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced"
|
|
bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WKDC ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC[3:0] ,Port Test Control" "Disabled,J_STATE,K_STATE,NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Disabled,Amber,Green,Undefined"
|
|
bitfld.long 0x00 13. " PO ,Port Owner (Reserved)" "Cleared,Set"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Not available,Available"
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,Undefined"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " HSP ,High-Speed Port" "Not high-speed,High-speed"
|
|
rbitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not forced,Forced"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OCC ,Over-current Change" "Not changed,Changed"
|
|
rbitfld.long 0x00 4. " OCA ,Over-current Active" "Not over-current,Over-current"
|
|
textline " "
|
|
eventfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " CCS ,Current Connect Status" "Not attached,Attached"
|
|
else
|
|
sif (!cpuis("K70*")&&!cpuis("IMX6*"))
|
|
hgroup.long (0x184+0x600)++0x1f
|
|
hide.long 0x00 "UH3_PORTSC1,Port 1 Status and Control Register"
|
|
hide.long 0x04 "UH3_PORTSC2,Port 2 Status and Control Register"
|
|
hide.long 0x08 "UH3_PORTSC3,Port 3 Status and Control Register"
|
|
hide.long 0x0c "UH3_PORTSC4,Port 4 Status and Control Register"
|
|
hide.long 0x10 "UH3_PORTSC5,Port 5 Status and Control Register"
|
|
hide.long 0x14 "UH3_PORTSC6,Port 6 Status and Control Register"
|
|
hide.long 0x18 "UH3_PORTSC7,Port 7 Status and Control Register"
|
|
hide.long 0x1c "UH3_PORTSC8,Port 8 Status and Control Register"
|
|
endif
|
|
endif
|
|
textline " "
|
|
textline " "
|
|
group.long (0x1a8+0x600)++0x03
|
|
line.long 0x00 "UH3_USBMODE,USB Device Mode Register"
|
|
bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active"
|
|
sif (cpu()=="IMX6DUAL")||(cpu()=="IMX6QUAD")||(cpu()=="IMX6DUALLITE")||(cpu()=="IMX6SOLO")||(cpu()=="RAYLEIGH-CA7")||(cpu()=="IMX6SOLOLITE")
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "Enabled,Disabled"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big"
|
|
bitfld.long 0x00 0.--1. " CM[1:0] ,Controller Mode" "Idle,,Device,Host"
|
|
textline " "
|
|
textline " "
|
|
sif (cpu()!="IMX6DUAL")&&(cpu()!="IMX6QUAD")&&(cpu()!="IMX6SOLO")&&(cpu()!="IMX6DUALLITE")&&(cpu()!="IMX6SOLOLITE")
|
|
group.long (0x770+0x600)++0x03
|
|
line.long 0x00 "USB_UH3_ULPIVIEW,ULPI Viewport"
|
|
eventfld.long 0x00 31. " ULPIWU ,ULPI wake-up" "No,Yes"
|
|
eventfld.long 0x00 30. " ULPIRUN ,ULPI Run " "No,Yes"
|
|
bitfld.long 0x00 29. " ULPIRW ,ULPI Read/Write Control" "Read,Wrtie"
|
|
bitfld.long 0x00 27. " ULPISS ,ULPI Sync State" "Different state,Sync state"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " ULPIPORT ,ULPI Port Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ULPIADDR ,ULPI Data Address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ULPIDATRD ,ULPI Data Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ULPIDATWR ,ULPI Data Write "
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "VPU (Video Processing Unit)"
|
|
base ad:0x83ff4000
|
|
width 0xE
|
|
wgroup.long 0x0++0xF
|
|
line.long 0x0 "CODERUN,VPU Code Run Register"
|
|
bitfld.long 0x0 0. " CODERUN ,BIT processor run start bit" "Stopped,Started"
|
|
line.long 0x4 "CODEDOWN,BIT Boot Code Download Data register"
|
|
hexmask.long.word 0x4 16.--28. 1. " CODEADDR[12:0] ,Download address of VPU BIT boot code which is VPU internal address of BIT processor"
|
|
textline " "
|
|
hexmask.long.word 0x4 0.--15. 1. " CODEDATA[15:0] ,Download data of VPU BIT boot code"
|
|
line.long 0x8 "HOSTINTREQ,Host Interrupt Request to BIT"
|
|
bitfld.long 0x8 0. " INTREQ ,The host interrupt request bit" "Not requested,Requested"
|
|
line.long 0xC "BITINTCLEAR,BIT Interrupt Clear"
|
|
bitfld.long 0xC 0. " INTCLEAR ,BIT interrrupt clear bit" "No operation,Cleared"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "BITINTSTS,BIT Interrupt Status"
|
|
bitfld.long 0x0 0. " INTSTS ,BIT interrupt status bit" "No interrupt,Interrupt"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "BITCODERESET,BIT Code Reset"
|
|
bitfld.long 0x0 0. " CODERESET ,BIT code reset bit" "No reset,Reset"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "BITCURPC,BIT Current PC"
|
|
hexmask.long.word 0x0 0.--13. 1. " CURPC[13:0] ,BIT current PC value"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "BITCODECBUSY,VPU BIT Busy Register"
|
|
bitfld.long 0x0 0. " CODECBUSY ,Codec busy flag for Bit processor" "Not busy,Busy"
|
|
width 0xB
|
|
tree.end
|
|
tree "WDOG (Watchdog Timer)"
|
|
base ad:0x73f98000
|
|
width 6.
|
|
group.word 0x00++0x3
|
|
line.word 0x00 "WCR,Watchdog Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " WT ,Watchdog Timeout Field"
|
|
bitfld.word 0x00 7. " WDW ,Watchdog Disable for Wait" "Continue,Suspended"
|
|
bitfld.word 0x00 5. " WDA ,/ipp_wdog Assertion" "Asserted,No effect"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SRS ,Software Reset Signal" "Asserted,No effect"
|
|
bitfld.word 0x00 3. " WDT ,/ipp_wdog Timeout assertion" "No effect,Asserted"
|
|
textline " "
|
|
bitfld.word 0x00 2. " WDE ,Watchdog Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WDBG ,Operation of the WDOG module during DEBUG mode" "Continue,Suspended"
|
|
bitfld.word 0x00 0. " WDZST ,Watchdog Low Power" "Continue,Suspended"
|
|
line.word 0x02 "WSR,Watchdog Service Register"
|
|
rgroup.word 0x04++0x1
|
|
line.word 0x00 "WRSR,Watchdog Reset Status Register"
|
|
bitfld.word 0x00 1. " TOUT ,Indicates whether the reset is the result of a WDOG time-out" "Not time-out,Time-out"
|
|
bitfld.word 0x00 0. " SFTW ,Software Reset" "Not software,Software"
|
|
group.word 0x06++0x3
|
|
line.word 0x00 "WICR,Watchdog Interrupt Control Register"
|
|
bitfld.word 0x00 15. " WIE ,Watchdog Timer Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.word 0x00 14. " WTIS ,Watchdog Timer Interrupt Status" "No interrupt,Interrupt"
|
|
hexmask.word.byte 0x00 0.--7. 1. " WICT ,Watchdog Interrupt Count Timeout"
|
|
line.word 0x02 "WMCR,Watchdog Miscellaneous Control Register"
|
|
bitfld.word 0x02 0. " PDE ,Power Down Enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
textline ""
|