3859 lines
241 KiB
Plaintext
3859 lines
241 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: M05/16LAN/2LAN/2ZAN/4LAN/4ZAN/8LAN/8ZAN/16ZAN On-Chip Peripherals
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; @Props: Released
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; @Author: TAT
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; @Changelog: 2011-08-12 TAT
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: rm.pdf (2010-09-08)
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; @Core: Cortex-M0
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perm05xx.per 12762 2021-01-18 10:40:58Z pegold $
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config 16. 8.
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width 0xB
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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tree.end
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width 6.
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tree "Interrupt Priority Registers"
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group.long 0x400++0x1F
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line.long 0x00 "INT0,Interrupt Priority Register"
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bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
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bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
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bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
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bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
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line.long 0x04 "INT1,Interrupt Priority Register"
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bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
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bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
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bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
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bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
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line.long 0x08 "INT2,Interrupt Priority Register"
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bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
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bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
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bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
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bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
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line.long 0x0C "INT3,Interrupt Priority Register"
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bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
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bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
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bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
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bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
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line.long 0x10 "INT4,Interrupt Priority Register"
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bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
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bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
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bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
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bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
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line.long 0x14 "INT5,Interrupt Priority Register"
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bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
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bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
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bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
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bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
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line.long 0x18 "INT6,Interrupt Priority Register"
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|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree.open "System Manager"
|
|
tree "Control Registers"
|
|
base ad:0x50000000
|
|
width 11.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "PDID,Part device identification number register"
|
|
group.long 0x04++0xB
|
|
line.long 0x00 "RSTSRC,System reset source register"
|
|
eventfld.long 0x00 7. " RSTS_CPU ,CPU software reset" "No reset,Reset"
|
|
eventfld.long 0x00 5. " RSTS_MCU ,System software reset" "No reset,Reset"
|
|
eventfld.long 0x00 4. " RSTS_BOD ,Brown-Out-Detector reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RSTS_LVR ,Low-Voltage-Reset controller reset" "No reset,Reset"
|
|
eventfld.long 0x00 2. " RSTS_WDT ,Watchdog timer reset" "No reset,Reset"
|
|
eventfld.long 0x00 1. " RSTS_RESET ,Pin /RESET reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSTS_POR ,Power-On Reset reset" "No reset,Reset"
|
|
line.long 0x04 "IPRSTC1,Peripheral Reset Control Resister 1"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x04 3. " EBI_RST ,EBI Controller Reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " CPU_RST ,CPU kernel one shot reset" "No reset,Reset"
|
|
bitfld.long 0x04 0. " CHIP_RST ,CHIP one shot reset" "No reset,Reset"
|
|
line.long 0x08 "IPRSTC2,Peripheral Reset Control Resister 2"
|
|
bitfld.long 0x08 28. " ADC_RST ,ADC Controller Reset" "No reset,Reset"
|
|
bitfld.long 0x08 21. " PWM47_RST ,PWM47 controller Reset" "No reset,Reset"
|
|
bitfld.long 0x08 20. " PWM03_RST ,PWM03 controller Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 17. " UART1_RST ,UART1 controller Reset" "No reset,Reset"
|
|
bitfld.long 0x08 16. " UART0_RST ,UART0 controller Reset" "No reset,Reset"
|
|
textline " "
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x08 13. " SPI1_RST ,SPI1 controller Reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 12. " SPI0_RST ,SPI0 controller Reset" "No reset,Reset"
|
|
bitfld.long 0x08 8. " I2C0_RST ,I2C0 controller Reset" "No reset,Reset"
|
|
bitfld.long 0x08 5. " TMR3_RST ,Timer3 controller Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TMR2_RST ,Timer2 controller Reset" "No reset,Reset"
|
|
bitfld.long 0x08 3. " TMR1_RST ,Timer1 controller Reset" "No reset,Reset"
|
|
bitfld.long 0x08 2. " TMR0_RST ,Timer0 controller Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 1. " GPIO_RST ,GPIO controller Reset" "No reset,Reset"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "BODCR,Brown-out detector control register"
|
|
bitfld.long 0x00 7. " LVR_EN ,Low Voltage Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " BOD_OUT ,Brown-Out Detector output status" ">BOD_VL,<BOD_VL"
|
|
bitfld.long 0x00 5. " BOD_LPM ,Brown-Out Detector Low power Mode" "Normal,Low power"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BOD_INTF ,Brown-Out Detector Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " BOD_RSTEN ,Brown-Out Reset Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " BOD_VL ,Brown-Out Detector Threshold Voltage Selection" "2.2V,2.7V,3.8V,4.5V"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BOD_EN ,Brown-Out Detector Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "PORCR,Brown-out detector control register"
|
|
hexmask.long.word 0x00 0.--15. 1. " POR_DIS_CODE ,POR disable code"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
width 11.
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P0_MFP ,P0 multiple function and input type control register"
|
|
bitfld.long 0x00 23. " P0_TYPE7 ,P0.7 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P0_TYPE6 ,P0.6 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P0_TYPE5 ,P0.5 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P0_TYPE4 ,P0.4 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " P0_TYPE3 ,P0.3 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " P0_TYPE2 ,P0.2 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P0_TYPE1 ,P0.1 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P0_TYPE0 ,P0.0 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. 15. " P0_MFP7 ,P0.7 Pin Multiple function Selection" "P0.7,AD7,SPICLK1,?..."
|
|
bitfld.long 0x00 6. 14. " P0_MFP6 ,P0.6 Pin Multiple function Selection" "P0.6,AD6,MISO_1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. 13. " P0_MFP5 ,P0.5 Pin Multiple function Selection" "P0.5,AD5,MOSI_1,?..."
|
|
bitfld.long 0x00 4. 12. " P0_MFP4 ,P0.4 Pin Multiple function Selection" "P0.4,ADC4,SPISS1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. 11. " P0_MFP3 ,P0.3 Pin Multiple function Selection" "P0.3,AD3,RTS0,?..."
|
|
bitfld.long 0x00 2. 10. " P0_MFP2 ,P0.2 Pin Multiple function Selection" "P0.2,ADC2,CTS0,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. 9. " P0_MFP1 ,P0.1 Pin Multiple function Selection" "P0.1,AD1,RTS1,?..."
|
|
bitfld.long 0x00 0. 8. " P0_MFP0 ,P0.0 Pin Multiple function Selection" "P0.0,AD0,CTS1,?..."
|
|
line.long 0x04 "P1_MFP ,P1 multiple function and input type control register"
|
|
bitfld.long 0x04 23. " P1_TYPE7 ,P1.7 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " P1_TYPE6 ,P1.6 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P1_TYPE5 ,P1.5 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " P1_TYPE4 ,P1.4 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P1_TYPE3 ,P1.3 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " P1_TYPE2 ,P1.2 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P1_TYPE1 ,P1.1 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " P1_TYPE0 ,P1.0 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. 15. " P1_MFP7 ,P1.7 Pin Multiple function Selection" "P1.7,AIN7,SPICLK0,?..."
|
|
bitfld.long 0x04 6. 14. " P1_MFP6 ,P1.6 Pin Multiple function Selection" "P1.6,AIN6,MISO_0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 5. 13. " P1_MFP5 ,P1.5 Pin Multiple function Selection" "P1.5,AIN5,MOSI_0,?..."
|
|
bitfld.long 0x04 4. 12. " P1_MFP4 ,P1.4 Pin Multiple function Selection" "P1.4,AIN4,SPISS0,?..."
|
|
textline " "
|
|
bitfld.long 0x04 3. 11. " P1_MFP3 ,P1.3 Pin Multiple function Selection" "P1.3,AIN3,TXD1,?..."
|
|
bitfld.long 0x04 2. 10. " P1_MFP2 ,P1.2 Pin Multiple function Selection" "P1.2,AIN2,RXD1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 1. 9. " P1_MFP1 ,P1.1 Pin Multiple function Selection" "P1.1,AIN1,T3,?..."
|
|
bitfld.long 0x04 0. 8. " P1_MFP0 ,P1.0 Pin Multiple function Selection" "P1.0,AIN0,T2,?..."
|
|
line.long 0x08 "P2_MFP ,P2 multiple function and input type control register"
|
|
bitfld.long 0x08 23. " P2_TYPE7 ,P2.7 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " P2_TYPE6 ,P2.6 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " P2_TYPE5 ,P2.5 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " P2_TYPE4 ,P2.4 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " P2_TYPE3 ,P2.3 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " P2_TYPE2 ,P2.2 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " P2_TYPE1 ,P2.1 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " P2_TYPE0 ,P2.0 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. 15. " P2_MFP7 ,P2.7 Pin Multiple function Selection" "P2.7,AD15,PWM7,?..."
|
|
bitfld.long 0x08 6. 14. " P2_MFP6 ,P2.6 Pin Multiple function Selection" "P2.6,AD14,PWM6,?..."
|
|
textline " "
|
|
bitfld.long 0x08 5. 13. " P2_MFP5 ,P2.5 Pin Multiple function Selection" "P2.5,AD13,PWM5,?..."
|
|
bitfld.long 0x08 4. 12. " P2_MFP4 ,P2.4 Pin Multiple function Selection" "P2.4,AD12,PWM4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 3. 11. " P2_MFP3 ,P2.3 Pin Multiple function Selection" "P2.3,AD11,PWM3,?..."
|
|
bitfld.long 0x08 2. 10. " P2_MFP2 ,P2.2 Pin Multiple function Selection" "P2.2,AD10,PWM2,?..."
|
|
textline " "
|
|
bitfld.long 0x08 1. 9. " P2_MFP1 ,P2.1 Pin Multiple function Selection" "P2.1,AD9,PWM1,?..."
|
|
bitfld.long 0x08 0. 8. " P2_MFP0 ,P2.0 Pin Multiple function Selection" "P2.0,AD8,PWM0,?..."
|
|
line.long 0x0C "P3_MFP ,P3 multiple function and input type control register"
|
|
bitfld.long 0x0C 23. " P3_TYPE7 ,P3.7 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " P3_TYPE6 ,P3.6 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " P3_TYPE5 ,P3.5 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " P3_TYPE4 ,P3.4 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " P3_TYPE3 ,P3.3 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " P3_TYPE2 ,P3.2 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " P3_TYPE1 ,P3.1 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " P3_TYPE0 ,P3.0 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " P3_MFP7 ,P3.7 Pin Multiple function Selection" "P3.7,RD"
|
|
bitfld.long 0x0C 6. 14. " P3_MFP6 ,P3.6 Pin Multiple function Selection" "P3.6,WR,CKO,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 5. 13. " P3_MFP5 ,P3.5 Pin Multiple function Selection" "P3.5,T1,SCL,?..."
|
|
bitfld.long 0x0C 4. 12. " P3_MFP4 ,P3.4 Pin Multiple function Selection" "P3.4,T0,SDA,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 3. 11. " P3_MFP3 ,P3.3 Pin Multiple function Selection" "P3.3,/INT1,MCLK,?..."
|
|
bitfld.long 0x0C 2. " P3_MFP2 ,P3.2 Pin Multiple function Selection" "P3.2,/INT0"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " P3_MFP1 ,P3.1 Pin Multiple function Selection" "P3.1,TXD"
|
|
bitfld.long 0x0C 0. " P3_MFP0 ,P3.0 Pin Multiple function Selection" "P3.0,RXD"
|
|
line.long 0x10 "P4_MFP ,P4 multiple function and input type control register"
|
|
bitfld.long 0x10 23. " P4_TYPE7 ,P4.7 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " P4_TYPE6 ,P4.6 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " P4_TYPE5 ,P4.5 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " P4_TYPE4 ,P4.4 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " P4_TYPE3 ,P4.3 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " P4_TYPE2 ,P4.2 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " P4_TYPE1 ,P4.1 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " P4_TYPE0 ,P4.0 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " P4_MFP7 ,P4.7 Pin Multiple function Selection" "P4.7,ICE_DAT"
|
|
bitfld.long 0x10 6. " P4_MFP6 ,P4.6 Pin Multiple function Selection" "P4.6,ICE_CLK"
|
|
textline " "
|
|
bitfld.long 0x10 5. " P4_MFP5 ,P4.5 Pin Multiple function Selection" "P4.5,ALE"
|
|
bitfld.long 0x10 4. " P4_MFP4 ,P4.4 Pin Multiple function Selection" "P4.4,/CS"
|
|
textline " "
|
|
bitfld.long 0x10 3. " P4_MFP3 ,P4.3 Pin Multiple function Selection" "P4.3,PWM3"
|
|
bitfld.long 0x10 2. " P4_MFP2 ,P4.2 Pin Multiple function Selection" "P4.2,PWM2"
|
|
textline " "
|
|
bitfld.long 0x10 1. " P4_MFP1 ,P4.1 Pin Multiple function Selection" "P4.1,PWM1"
|
|
bitfld.long 0x10 0. " P4_MFP0 ,P4.0 Pin Multiple function Selection" "P4.0,PWM0"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "REGWRPROT ,Register write protect register"
|
|
hexmask.long.byte 0x00 1.--7. 1. " REGWRPROT ,Register Write-Protection Code"
|
|
bitfld.long 0x00 0. " REGPROTDIS ,Register Write-Protection Disable" "No,Yes"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "RCADJ ,RC Adjustment control register "
|
|
bitfld.long 0x00 0.--5. " RCADJ ,RC Adjustment control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xB
|
|
else
|
|
width 11.
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P0_MFP ,P0 multiple function and input type control register"
|
|
bitfld.long 0x00 23. " P0_TYPE7 ,P0.7 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " P0_TYPE6 ,P0.6 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P0_TYPE5 ,P0.5 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " P0_TYPE4 ,P0.4 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P0_TYPE1 ,P0.1 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " P0_TYPE0 ,P0.0 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. 15. " P0_ALT7 ,P0.7 Pin Alternate function Selection" "P0.7,Reserved,SPICLK1,?..."
|
|
bitfld.long 0x00 6. 14. " P0_ALT6 ,P0.6 Pin Alternate function Selection" "P0.6,Reserved,MISO_1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. 13. " P0_ALT5 ,P0.5 Pin Alternate function Selection" "P0.5,Reserved,MOSI_1,?..."
|
|
bitfld.long 0x00 4. 12. " P0_ALT4 ,P0.4 Pin Alternate function Selection" "P0.4,Reserved,SPISS1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. 9. " P0_ALT1 ,P0.1 Pin Alternate function Selection" "P0.1,Reserved,RTS1,?..."
|
|
bitfld.long 0x00 0. 8. " P0_ALT0 ,P0.0 Pin Alternate function Selection" "P0.0,Reserved,CTS1,?..."
|
|
line.long 0x04 "P1_MFP ,P1 multiple function and input type control register"
|
|
bitfld.long 0x04 21. " P1_TYPE5 ,P1.5 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " P1_TYPE4 ,P1.4 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P1_TYPE3 ,P1.3 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " P1_TYPE2 ,P1.2 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " P1_TYPE0 ,P1.0 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P1_ALT5 ,P1.5 Pin Alternate function Selection" "P1.5,AIN5"
|
|
bitfld.long 0x04 4. " P1_ALT4 ,P1.4 Pin Alternate function Selection" "P1.4,AIN4"
|
|
textline " "
|
|
bitfld.long 0x04 3. 11. " P1_ALT3 ,P1.3 Pin Alternate function Selection" "P1.3,AIN3,TXD1,?..."
|
|
bitfld.long 0x04 2. 10. " P1_ALT2 ,P1.2 Pin Alternate function Selection" "P1.2,AIN2,RXD1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0. 8. " P1_ALT0 ,P1.0 Pin Alternate function Selection" "P1.0,AIN0,T2,?..."
|
|
line.long 0x08 "P2_MFP ,P2 multiple function and input type control register"
|
|
bitfld.long 0x08 22. " P2_TYPE6 ,P2.6 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " P2_TYPE5 ,P2.5 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " P2_TYPE4 ,P2.4 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " P2_TYPE3 ,P2.3 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " P2_TYPE2 ,P2.2 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. 14. " P2_ALT6 ,P2.6 Pin Alternate function Selection" "P2.6,Reserved,PWM6,?..."
|
|
bitfld.long 0x08 5. 13. " P2_ALT5 ,P2.5 Pin Alternate function Selection" "P2.5,Reserved,PWM5,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4. 12. " P2_ALT4 ,P2.4 Pin Alternate function Selection" "P2.4,Reserved,PWM4,?..."
|
|
bitfld.long 0x08 3. 11. " P2_ALT3 ,P2.3 Pin Alternate function Selection" "P2.3,Reserved,PWM3,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2. 10. " P2_ALT2 ,P2.2 Pin Alternate function Selection" "P2.2,Reserved,PWM2,?..."
|
|
line.long 0x0C "P3_MFP ,P3 multiple function and input type control register"
|
|
bitfld.long 0x0C 22. " P3_TYPE6 ,P3.6 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " P3_TYPE5 ,P3.5 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " P3_TYPE4 ,P3.4 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " P3_TYPE2 ,P3.2 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " P3_TYPE1 ,P3.1 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " P3_TYPE0 ,P3.0 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 6. 14. " P3_ALT6 ,P3.6 Pin Alternate function Selection" "P3.6,Reserved,CKO,?..."
|
|
bitfld.long 0x0C 5. 13. " P3_ALT5 ,P3.5 Pin Alternate function Selection" "P3.5,T1,SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 4. 12. " P3_ALT4 ,P3.4 Pin Alternate function Selection" "P3.4,T0,SDA,?..."
|
|
bitfld.long 0x0C 2. " P3_ALT2 ,P3.2 Pin Alternate function Selection" "P3.2,/INT0"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " P3_ALT1 ,P3.1 Pin Alternate function Selection" "P3.1,TXD"
|
|
bitfld.long 0x0C 0. " P3_ALT0 ,P3.0 Pin Alternate function Selection" "P3.0,RXD"
|
|
line.long 0x10 "P4_MFP ,P4 multiple function and input type control register"
|
|
bitfld.long 0x10 23. " P4_TYPE7 ,P4.7 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " P4_TYPE6 ,P4.6 I/O input Schmitt Trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " P4_ALT7 ,P4.7 Pin Alternate function Selection" "P4.7,ICE_DAT"
|
|
bitfld.long 0x10 6. " P4_ALT6 ,P4.6 Pin Alternate function Selection" "P4.6,ICE_CLK"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "REGWRPROT ,Register write protect register"
|
|
hexmask.long.byte 0x00 1.--7. 1. " REGWRPROT ,Register Write-Protection Code"
|
|
bitfld.long 0x00 0. " REGPROTDIS ,Register Write-Protection Disable" "No,Yes"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "RCADJ ,RC Adjustment control register "
|
|
bitfld.long 0x00 0.--5. " RCADJ ,RC Adjustment control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xB
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "System Timer (SysTick)"
|
|
base ad:0xE000E000
|
|
width 10.
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
in
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "SYST_RVR,SysTick Reload value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,Reload value"
|
|
line.long 0x04 "SYST_CVR,SysTick Current value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,Current counter value"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "Nested Vectored Interrupt Controller (NVIC)"
|
|
tree "NVIC Control Registers"
|
|
base ad:0xE000E000
|
|
width 16.
|
|
group.long 0x100++0x03 "Interrupt Set/Clear Enable Register"
|
|
line.long 0x00 "NVIC_SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,ADC_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,PWRWU_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,I2C_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,SPI1_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,SPI0_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,UART1_INTInterrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,UART0_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,TMR3_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,TMR2_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,TMR1_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,TMR0_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,PWMB_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,PWMA_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,GP234_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,GP01_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,EINT1 Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,EINT0 Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,WDT_INT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,BOD_OUT Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
group.long 0x200++0x03 "Interrupt Set/Clear Pending Register"
|
|
line.long 0x00 "NVIC_SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,ADC_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,PWRWU_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,I2C_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,SPI1_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,SPI0_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,UART1_INTInterrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,UART0_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,TMR3_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,TMR2_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,TMR1_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,TMR0_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,PWMB_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,PWMA_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,GP234_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,GP01_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,EINT1 Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,EINT0 Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,WDT_INT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,BOD_OUT Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
width 10.
|
|
group.long 0x400++0x13
|
|
line.long 0x00 "NVIC_IPR0,Priority Control Register 0"
|
|
bitfld.long 0x00 30.--31. " PRI_3 ,Priority of EINT1 interrupt" "0(highest),1,2,3(lowest)"
|
|
bitfld.long 0x00 22.--23. " PRI_2 ,Priority of EINT0 interrupt" "0(highest),1,2,3(lowest)"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " PRI_1 ,Priority of WDT_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
bitfld.long 0x00 6.--7. " PRI_0 ,Priority of BOD_OUT interrupt" "0(highest),1,2,3(lowest)"
|
|
line.long 0x04 "NVIC_IPR1,Priority Control Register 1"
|
|
bitfld.long 0x04 30.--31. " PRI_7 ,Priority of PWMB_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
bitfld.long 0x04 22.--23. " PRI_6 ,Priority of PWMA_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " PRI_5 ,Priority of GP234_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
bitfld.long 0x04 6.--7. " PRI_4 ,Priority of GP01_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
line.long 0x08 "NVIC_IPR2,Priority Control Register 2"
|
|
bitfld.long 0x08 30.--31. " PRI_11 ,Priority of TMR3_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
bitfld.long 0x08 22.--23. " PRI_10 ,Priority of TMR2_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " PRI_9 ,Priority of TMR1_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
bitfld.long 0x08 6.--7. " PRI_8 ,Priority of TMR0_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
line.long 0x0C "NVIC_IPR3,Priority Control Register 3"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x0C 30.--31. " PRI_15 ,Priority of SPI1_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 22.--23. " PRI_14 ,Priority of SPI0_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " PRI_13 ,Priority of UART1_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
bitfld.long 0x0C 6.--7. " PRI_12 ,Priority of UART0_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
line.long 0x10 "NVIC_IPR4,Priority Control Register 4"
|
|
bitfld.long 0x10 22.--23. " PRI_18 ,Priority of I2C_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
group.long 0x41C++0x3
|
|
line.long 0x00 "NVIC_IPR7,Priority Control Register 7"
|
|
bitfld.long 0x00 14.--15. " PRI_29 ,Priority of ADC_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
bitfld.long 0x00 6.--7. " PRI_28 ,Priority of PWRWU_INT interrupt" "0(highest),1,2,3(lowest)"
|
|
width 0xB
|
|
tree.end
|
|
tree "Interrupt Source Control Registers"
|
|
base ad:0x50000300
|
|
width 10.
|
|
rgroup.long 0x00++0xB
|
|
line.long 0x00 " IRQ0_SRC,BOD interrupt source identity"
|
|
bitfld.long 0x00 0. " INT_SRC[0] ,BOD interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 " IRQ1_SRC,WDT interrupt source identity"
|
|
bitfld.long 0x04 0. " INT_SRC[0] ,WDT interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 " IRQ2_SRC,EINT0 interrupt source identity"
|
|
bitfld.long 0x08 0. " INT_SRC[0] ,EINT0 interrupt" "No interrupt,Interrupt"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x00 " IRQ3_SRC,EINT1 interrupt source identity"
|
|
bitfld.long 0x00 0. " INT_SRC[0] ,EINT1 interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0x10++0x2B
|
|
line.long 0x00 " IRQ4_SRC,GPA/B interrupt source identity"
|
|
bitfld.long 0x00 1. " INT_SRC[1] ,P1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INT_SRC[0] ,P0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 " IRQ5_SRC,GPC/D/E interrupt source identity"
|
|
bitfld.long 0x04 2. " INT_SRC[2] ,P4 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INT_SRC[1] ,P3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " INT_SRC[0] ,P2 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 " IRQ6_SRC,PWMA interrupt source identity"
|
|
bitfld.long 0x08 3. " INT_SRC[3] ,PWM3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 2. " INT_SRC[2] ,PWM2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " INT_SRC[1] ,PWM1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 0. " INT_SRC[0] ,PWM0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C " IRQ7_SRC,PWMB interrupt source identity"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x0C 3. " INT_SRC[3] ,PWM7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " INT_SRC[2] ,PWM6 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " INT_SRC[1] ,PWM5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " INT_SRC[0] ,PWM4 interrupt" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x0C 0. " INT_SRC[0] ,PWM4 interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
line.long 0x10 " IRQ8_SRC,TMR0 interrupt source identity"
|
|
bitfld.long 0x10 0. " INT_SRC[0] ,TMR0 interrupt source" "No interrupt,Interrupt"
|
|
line.long 0x14 " IRQ9_SRC,TMR1 interrupt source identity"
|
|
bitfld.long 0x14 0. " INT_SRC[0] ,TMR1 interrupt source" "No interrupt,Interrupt"
|
|
line.long 0x18 " IRQ10_SRC,TMR2 interrupt source identity"
|
|
bitfld.long 0x18 0. " INT_SRC[0] ,TMR2 interrupt source" "No interrupt,Interrupt"
|
|
line.long 0x1C " IRQ11_SRC,TMR3 interrupt source identity"
|
|
bitfld.long 0x1C 0. " INT_SRC[0] ,TMR3 interrupt source" "No interrupt,Interrupt"
|
|
line.long 0x20 " IRQ12_SRC,URT0 interrupt source identity"
|
|
bitfld.long 0x20 0. " INT_SRC[0] ,URT0 interrupt source" "No interrupt,Interrupt"
|
|
line.long 0x24 " IRQ13_SRC,URT1 interrupt source identity"
|
|
bitfld.long 0x24 0. " INT_SRC[0] ,URT1 interrupt source" "No interrupt,Interrupt"
|
|
line.long 0x28 " IRQ14_SRC,SPI0 interrupt source identity"
|
|
bitfld.long 0x28 0. " INT_SRC[0] ,SPI0 interrupt source" "No interrupt,Interrupt"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 " IRQ15_SRC,SPI1 interrupt source identity"
|
|
bitfld.long 0x00 0. " INT_SRC[0] ,SPI1 interrupt source" "No interrupt,Interrupt"
|
|
endif
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x00 " IRQ18_SRC,I2C interrupt source identity"
|
|
bitfld.long 0x00 0. " INT_SRC[0] ,I2C0 interrupt source" "No interrupt,Interrupt"
|
|
rgroup.long 0x70++0x7
|
|
line.long 0x00 " IRQ28_SRC,PWRWU interrupt source identity "
|
|
bitfld.long 0x00 0. " INT_SRC[0] ,PWRWU interrupt source" "No interrupt,Interrupt"
|
|
line.long 0x04 " IRQ29_SRC,ADC interrupt source identity "
|
|
bitfld.long 0x00 0. " INT_SRC[0] ,ADC interrupt source" "No interrupt,Interrupt"
|
|
group.long 0x80++0x7
|
|
line.long 0x00 " NMI_SEL,NMI source interrupt select control register"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x00 0.--4. " NMI_SEL ,NMI interrupt source select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Reserved,Reserved,18,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,28,29,?..."
|
|
else
|
|
bitfld.long 0x00 0.--4. " NMI_SEL ,NMI interrupt source select" "0,1,2,Reserved,4,5,6,7,8,9,10,11,12,13,14,Reserved,Reserved,Reserved,18,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,28,29,?..."
|
|
endif
|
|
line.long 0x04 " MCU_IRQ,MCU IRQ Number identity register"
|
|
bitfld.long 0x04 29. " MCU_IRQ29 ,ADC_INT Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " MCU_IRQ28 ,PWRWU_INT Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 18. " MCU_IRQ18 ,I2C0_INT Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x04 15. " MCU_IRQ15 ,SPI1_INT Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 14. " MCU_IRQ14 ,SPI0_INT Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " MCU_IRQ13 ,UART1_INTInterrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 12. " MCU_IRQ12 ,UART0_INT Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " MCU_IRQ11 ,TMR3_INT Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MCU_IRQ10 ,TMR2_INT Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " MCU_IRQ9 ,TMR1_INT Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " MCU_IRQ8 ,TMR0_INT Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " MCU_IRQ7 ,PWMB_INT Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MCU_IRQ6 ,PWMA_INT Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " MCU_IRQ5 ,P2/3/4 Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " MCU_IRQ4 ,P0/1 Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x04 3. " MCU_IRQ3 ,EINT1 Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 2. " MCU_IRQ2 ,EINT0 Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " MCU_IRQ1 ,WDT_INT Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MCU_IRQ0 ,BOD_OUT Interrupt" "No interrupt,Interrupt"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "System Control Registers"
|
|
base ad:0xE000E000
|
|
width 10.
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
|
|
bitfld.long 0x00 16.--19. " PART ,Parts" "0,1,2,3,4,5,6,7,8,9,10,11,ARMv6-M,13,14,15"
|
|
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xd04++0x3
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,NMI set-pending bit" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDSVSET ,PendSV set-pending bit" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PENDSVCLR ,PendSV clear-pending bit" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PENDSTSET ,SysTick exception set-pending bit" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PENDSTCLR ,SysTick exception clear-pending bit" "No effect,Clear"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception serviced on exit" "Not serviced,Serviced"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending"
|
|
sif (cpuis("NUC100*")||cpuis("NUC120*"))
|
|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Highest priority pending enabled exception number"
|
|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVE ,Active exception number"
|
|
else
|
|
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Highest priority pending enabled exception number"
|
|
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active exception number"
|
|
endif
|
|
group.long 0xd0c++0x07
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Register Key"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System Reset Request" "No effect,Reset"
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clear All Active Vectors Bit" "No effect,Clear"
|
|
line.long 0x04 "SCR,System Control Register"
|
|
bitfld.long 0x04 4. " SEVONPEND ,Wake up by Enabled/disabled events/interrupts" "Enabled only,Enabled/disabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SLEEPDEEP ,Sleep Deep Bit" "Sleep,Deep sleep"
|
|
bitfld.long 0x04 1. " SLEEPONEXIT , Sleep on Exit when Returning from Handler Mode" "Not sleep,Sleep"
|
|
group.long 0xd1c++0x7
|
|
line.long 0x00 "SHPR2,System Handlers Priority Register 2"
|
|
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11 (SVCall)" "0(highest),1,2,3(lowest)"
|
|
line.long 0x04 "SHPR3,System Handlers Priority Register 3"
|
|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15 (SysTick)" "0(highest),1,2,3(lowest)"
|
|
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14 (PendSV)" "0(highest),1,2,3(lowest)"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "Clock controller"
|
|
base ad:0x50000200
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "PWRCON,System Power Down Control Register"
|
|
bitfld.long 0x00 8. " PD_WAIT_CPU ,Power down wait enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " PWR_DOWN_EN ,System Power Down Enable Bit" "Disabled,Enabled"
|
|
eventfld.long 0x00 6. " PD_WU_STS ,Power Down Mode Wake-up Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PD_WU_INT_EN ,Power Down Mode Wake-up Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PD_WU_DLY ,Enable the Wake-up Delay Counter" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " OSC10K_EN ,Internal 10 kHz Oscillator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OSC22M_EN ,Internal 22.1184 MHz Oscillator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XTL12M_EN ,External 12 MHz Crystal Oscillator Enable" "Disabled,Enabled"
|
|
line.long 0x04 " AHBCLK,AHB Devices Clock Enable Control Register"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x04 3. " EBI_EN ,EBI Controller Clock Enable Control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 2. " ISP_EN ,Flash ISP Controller Clock Enable Control" "Disabled,Enabled"
|
|
line.long 0x08 " APBCLK,APB Devices Clock Enable Control Register"
|
|
bitfld.long 0x08 28. " ADC_EN ,Analog-Digital-Converter (ADC) Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x08 23. " PWM67_EN ,PWM_67 Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 22. " PWM45_EN ,PWM_45 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " PWM23_EN ,PWM_23 Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " PWM01_EN ,PWM_01 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " UART1_EN ,UART1 Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " UART0_EN ,UART0 Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x08 13. " SPI1_EN ,SPI1 Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 12. " SPI0_EN ,SPI0 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " I2C_EN ,I2C Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " FDIV_EN ,Frequency Divider Output Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TMR3_EN ,Timer3 Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TMR2_EN ,Timer2 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TMR1_EN ,Timer1 Clock Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TMR0_EN ,Timer0 Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " WDT_EN ,Watchdog Timer Clock Enable" "Disabled,Enabled"
|
|
line.long 0x0C " CLKSTATUS,Clock status monitor Register"
|
|
eventfld.long 0x0C 7. " CLK_SW_FAIL ,Clock switch fail flag" "Success,Failure"
|
|
bitfld.long 0x0C 4. " OSC22M_STB ,OSC22M clock source stable flag" "Not stable|disabled,Stable"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " OSC10K_STB ,OSC10K clock source stable flag" "Not stable|disabled,Stable"
|
|
bitfld.long 0x0C 2. " PLL_STB ,PLL clock source stable flag" "Not stable|disabled,Stable"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XTL12M_STB ,XTL12M clock source stable flag" "Not stable|disabled,Stable"
|
|
line.long 0x10 " CLKSEL0,Clock Source Select Control Register 0"
|
|
bitfld.long 0x10 3.--5. " STCLK_S ,Cortex_M0 SysTick clock source select" "12 MHz crystal clock,Reserved,12 MHz crystal clock/2,HCLK/2,Internal 22.1184 MHz oscillator clock/2,Internal 22.1184 MHz oscillator clock/2,Internal 22.1184 MHz oscillator clock/2,Internal 22.1184 MHz oscillator clock/2"
|
|
bitfld.long 0x10 0.--2. " HCLK_S ,HCLK clock source select" "12 MHz crystal clock,Reserved,PLL clock,Internal 10 kHz oscillator clock,Reserved,Reserved,Reserved,Internal 22.1184 MHz oscillator clock"
|
|
line.long 0x14 " CLKSEL1,Clock Source Select Control Register 1"
|
|
bitfld.long 0x14 30.--31. " PWM23_S ,PWM2 and PWM3 clock source" "External 12 MHz crystal clock,Reserved,HCLK,Internal 22.1184 MHz oscillator clock"
|
|
bitfld.long 0x14 28.--29. " PWM01_S ,PWM0 and PWM1 clock source" "External 12 MHz crystal clock,Reserved,HCLK,Internal 22.1184 MHz oscillator clock"
|
|
textline " "
|
|
bitfld.long 0x14 24.--25. " UART_S ,UART clock source" "External 12 MHz crystal clock,PLL clock,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock"
|
|
bitfld.long 0x14 20.--22. " TMR3_S ,TIMER3 clock source select" "External 12 MHz crystal clock,Reserved,HCLK,External trigger,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " TMR2_S ,TIMER2 clock source" "External 12 MHz crystal clock,Reserved,HCLK,External trigger,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock"
|
|
bitfld.long 0x14 12.--14. " TMR1_S ,TIMER1 clock source" "External 12 MHz crystal clock,Reserved,HCLK,External trigger,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock"
|
|
textline " "
|
|
bitfld.long 0x14 8.--10. " TMR0_S ,TIMER0 clock source" "External 12 MHz crystal clock,Reserved,HCLK,External trigger,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock"
|
|
bitfld.long 0x14 2.--3. " ADC_S ,ADC clock source" "External 12 MHz crystal clock,PLL clock,Internal 22.1184 MHz oscillator clock,Internal 22.1184 MHz oscillator clock"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " WDT_S ,Watchdog Timer clock source" "External 12 MHz crystal clock,Reserved,HCLK/2048 clock,Internal 10 kHz oscillator clock"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 " CLKSEL2,Clock Source Select Control Register 2"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x00 6.--7. " PWM67_S ,PWM6 and PWM7 Clock Source" "External 12 MHz crystal clock,Reserved,HCLK,Internal 22.1184 MHz oscillator clock"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--5. " PWM45_S ,PWM4 and PWM5 Clock Source" "External 12 MHz crystal clock,Reserved,HCLK,Internal 22.1184 MHz oscillator clock"
|
|
bitfld.long 0x00 2.--3. " FRQDIV_S ,Clock Divider Clock Source" "External 12 MHz crystal clock,Reserved,HCLK,Internal 22.1184 MHz oscillator clock"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 " CLKDIV,Clock Divider Number Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ADC_N ,ADC clock divide number from ADC clock source"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " UART_N ,UART clock divide number from UART clock source" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " HCLK_N ,HCLK clock divide number from HCLK clock source" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
group.long 0x20++0x7
|
|
line.long 0x00 " PLLCON,PLL Control Register"
|
|
bitfld.long 0x00 19. " PLL_SRC ,PLL Source Clock" "12 MHz crystal,22.1184 MHz oscillator"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OE ,PLL FOUT enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 17. " BP ,PLL Bypass Control" "Normal mode,XTALin"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PD ,PLL power down mode" "Normal,Power-down"
|
|
bitfld.long 0x00 14.--15. " OUT_DV ,PLL Output Divider Control Pins" "/1,/2,/3,/4"
|
|
textline " "
|
|
bitfld.long 0x00 9.--13. " IN_DV ,PLL Input Divider Control Pins" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
hexmask.long.word 0x00 0.--8. 1. " FB_DV ,PLL Feedback Divider Control Pins"
|
|
line.long 0x04 " FRQDIV,Frequency Divider Control Register"
|
|
bitfld.long 0x04 4. " DIVIDER_EN ,Frequency Divider Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--3. " FSEL ,Divider Output Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "GPIO (General Purpose I/O)"
|
|
tree "Common"
|
|
base ad:0x50004000
|
|
width 10.
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "DBNCECON,De-bounce Cycle Control"
|
|
bitfld.long 0x00 5. " ICLK_ON ,Interrupt clock On mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DBCLKSRC ,De-bounce counter clock source select" "HCLK,Internal 10 kHz low speed oscillator"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DBCLKSEL ,De-bounce sampling cycle select" "1 clock,2 clocks,4 clocks,8 clocks,16 clocks,32 clocks,64 clocks,128 clocks,256 clocks,2*256 clocks,4*256 clocks,8*256 clocks,16*256 clocks,32*256 clocks,64*256 clocks,128*256 clocks"
|
|
width 0xb
|
|
tree.end
|
|
tree "Port 0"
|
|
base ad:0x50004000
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
width 13.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 " P0_PMD,Port 0 Pin I/O Mode Control"
|
|
bitfld.long 0x00 14.--15. " PMD7 ,P0 I/O Pin[7] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 12.--13. " PMD6 ,P0 I/O Pin[6] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PMD5 ,P0 I/O Pin[5] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 8.--9. " PMD4 ,P0 I/O Pin[4] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PMD3 ,P0 I/O Pin[3] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 4.--5. " PMD2 ,P0 I/O Pin[2] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PMD1 ,P0 I/O Pin[1] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 0.--1. " PMD0 ,P0 I/O Pin[0] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
line.long 0x04 " P0_OFFD,Port 0 Pin OFF Digital Enable"
|
|
bitfld.long 0x04 23. " OFFD7 ,P0 I/O Pin[7] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 22. " OFFD6 ,P0 I/O Pin[6] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OFFD5 ,P0 I/O Pin[5] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 20. " OFFD4 ,P0 I/O Pin[4] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OFFD3 ,P0 I/O Pin[3] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 18. " OFFD2 ,P0 I/O Pin[2] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OFFD1 ,P0 I/O Pin[1] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 16. " OFFD0 ,P0 I/O Pin[0] OFF digital input path Enable" "Enabled,Disabled"
|
|
line.long 0x08 " P0_DOUT,Port 0 Data Output Value"
|
|
bitfld.long 0x08 7. " DOUT7 ,P0 I/O Pin[7] Output Value" "Low,High"
|
|
bitfld.long 0x08 6. " DOUT6 ,P0 I/O Pin[6] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DOUT5 ,P0 I/O Pin[5] Output Value" "Low,High"
|
|
bitfld.long 0x08 4. " DOUT4 ,P0 I/O Pin[4] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DOUT3 ,P0 I/O Pin[3] Output Value" "Low,High"
|
|
bitfld.long 0x08 2. " DOUT2 ,P0 I/O Pin[2] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DOUT1 ,P0 I/O Pin[1] Output Value" "Low,High"
|
|
bitfld.long 0x08 0. " DOUT0 ,P0 I/O Pin[0] Output Value" "Low,High"
|
|
line.long 0x0C " P0_DMASK,Port 0 Data Output Write Mask"
|
|
bitfld.long 0x0C 7. " DMASK7 ,P0 I/O Pin[7] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " DMASK6 ,P0 I/O Pin[6] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DMASK5 ,P0 I/O Pin[5] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " DMASK4 ,P0 I/O Pin[4] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DMASK3 ,P0 I/O Pin[3] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " DMASK2 ,P0 I/O Pin[2] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DMASK1 ,P0 I/O Pin[1] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " DMASK0 ,P0 I/O Pin[0] Data Output Write Mask" "Not masked,Masked"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 " P0_PIN,Port 0 Pin Value"
|
|
bitfld.long 0x00 7. " PIN7 ,P0 I/O Pin[7] Value" "Low,High"
|
|
bitfld.long 0x00 6. " PIN6 ,P0 I/O Pin[6] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIN5 ,P0 I/O Pin[5] Value" "Low,High"
|
|
bitfld.long 0x00 4. " PIN4 ,P0 I/O Pin[4] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIN3 ,P0 I/O Pin[3] Value" "Low,High"
|
|
bitfld.long 0x00 2. " PIN2 ,P0 I/O Pin[2] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIN1 ,P0 I/O Pin[1] Value" "Low,High"
|
|
bitfld.long 0x00 0. " PIN0 ,P0 I/O Pin[0] Value" "Low,High"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 " P0_DBEN,Port 0 De-bounce Enable"
|
|
bitfld.long 0x00 7. " DBEN7 ,P0 I/O Pin[7] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " DBEN6 ,P0 I/O Pin[6] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBEN5 ,P0 I/O Pin[5] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " DBEN4 ,P0 I/O Pin[4] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DBEN3 ,P0 I/O Pin[3] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DBEN2 ,P0 I/O Pin[2] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBEN1 ,P0 I/O Pin[1] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " DBEN0 ,P0 I/O Pin[0] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
line.long 0x04 " P0_IMD,Port 0 Interrupt Mode Control"
|
|
bitfld.long 0x04 7. " IMD7 ,P0 I/O Pin[7] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 6. " IMD6 ,P0 I/O Pin[6] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IMD5 ,P0 I/O Pin[5] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 4. " IMD4 ,P0 I/O Pin[4] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IMD3 ,P0 I/O Pin[3] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 2. " IMD2 ,P0 I/O Pin[2] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IMD1 ,P0 I/O Pin[1] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 0. " IMD0 ,P0 I/O Pin[0] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
line.long 0x08 " P0_IEN,Port 0 Interrupt Enable"
|
|
bitfld.long 0x08 23. " IR_EN7 ,P0 I/O Pin[7] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " IR_EN6 ,P0 I/O Pin[6] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " IR_EN5 ,P0 I/O Pin[5] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IR_EN4 ,P0 I/O Pin[4] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IR_EN3 ,P0 I/O Pin[3] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IR_EN2 ,P0 I/O Pin[2] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " IR_EN1 ,P0 I/O Pin[1] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " IR_EN0 ,P0 I/O Pin[0] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IF_EN7 ,P0 I/O Pin[7] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IF_EN6 ,P0 I/O Pin[6] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IF_EN5 ,P0 I/O Pin[5] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " IF_EN4 ,P0 I/O Pin[4] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IF_EN3 ,P0 I/O Pin[3] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IF_EN2 ,P0 I/O Pin[2] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IF_EN1 ,P0 I/O Pin[1] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IF_EN0 ,P0 I/O Pin[0] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
line.long 0x0C " P0_ISRC,Port 0 Interrupt Source Flag"
|
|
bitfld.long 0x0C 7. " ISRC7 ,P0 I/O Pin[7] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 6. " ISRC6 ,P0 I/O Pin[6] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ISRC5 ,P0 I/O Pin[5] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " ISRC4 ,P0 I/O Pin[4] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ISRC3 ,P0 I/O Pin[3] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " ISRC2 ,P0 I/O Pin[2] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " ISRC1 ,P0 I/O Pin[1] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " ISRC0 ,P0 I/O Pin[0] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
base ad:0x50004200
|
|
width 13.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 " P00_DOUT,P0.0 Bit Output Control"
|
|
bitfld.long 0x00 0. " P00_DOUT ,P0 I/O Pin 0 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P01_DOUT,P0.1 Bit Output Control"
|
|
bitfld.long 0x04 0. " P01_DOUT ,P0 I/O Pin 1 Bit Output Control" "Low,High"
|
|
group.long 0x08++0x7
|
|
line.long 0x00 " P02_DOUT,P0.2 Bit Output Control"
|
|
bitfld.long 0x00 0. " P02_DOUT ,P0 I/O Pin 2 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P03_DOUT,P0.3 Bit Output Control"
|
|
bitfld.long 0x04 0. " P03_DOUT ,P0 I/O Pin 3 Bit Output Control" "Low,High"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 " P04_DOUT,P0.4 Bit Output Control"
|
|
bitfld.long 0x00 0. " P04_DOUT ,P0 I/O Pin 4 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P05_DOUT,P0.5 Bit Output Control"
|
|
bitfld.long 0x04 0. " P05_DOUT ,P0 I/O Pin 5 Bit Output Control" "Low,High"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 " P06_DOUT,P0.6 Bit Output Control"
|
|
bitfld.long 0x00 0. " P06_DOUT ,P0 I/O Pin 6 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P07_DOUT,P0.7 Bit Output Control"
|
|
bitfld.long 0x04 0. " P07_DOUT ,P0 I/O Pin 7 Bit Output Control" "Low,High"
|
|
width 0xB
|
|
elif (cpuis("M05?ZAN")||cpuis("M0516ZAN"))
|
|
width 13.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 " P0_PMD,Port 0 Pin I/O Mode Control"
|
|
bitfld.long 0x00 14.--15. " PMD7 ,P0 I/O Pin[7] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 12.--13. " PMD6 ,P0 I/O Pin[6] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PMD5 ,P0 I/O Pin[5] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 8.--9. " PMD4 ,P0 I/O Pin[4] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PMD1 ,P0 I/O Pin[1] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 0.--1. " PMD0 ,P0 I/O Pin[0] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
line.long 0x04 " P0_OFFD,Port 0 Pin OFF Digital Enable"
|
|
bitfld.long 0x04 23. " OFFD7 ,P0 I/O Pin[7] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 22. " OFFD6 ,P0 I/O Pin[6] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OFFD5 ,P0 I/O Pin[5] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 20. " OFFD4 ,P0 I/O Pin[4] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OFFD1 ,P0 I/O Pin[1] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 16. " OFFD0 ,P0 I/O Pin[0] OFF digital input path Enable" "Enabled,Disabled"
|
|
line.long 0x08 " P0_DOUT,Port 0 Data Output Value"
|
|
bitfld.long 0x08 7. " DOUT7 ,P0 I/O Pin[7] Output Value" "Low,High"
|
|
bitfld.long 0x08 6. " DOUT6 ,P0 I/O Pin[6] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DOUT5 ,P0 I/O Pin[5] Output Value" "Low,High"
|
|
bitfld.long 0x08 4. " DOUT4 ,P0 I/O Pin[4] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DOUT1 ,P0 I/O Pin[1] Output Value" "Low,High"
|
|
bitfld.long 0x08 0. " DOUT0 ,P0 I/O Pin[0] Output Value" "Low,High"
|
|
line.long 0x0C " P0_DMASK,Port 0 Data Output Write Mask"
|
|
bitfld.long 0x0C 7. " DMASK7 ,P0 I/O Pin[7] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " DMASK6 ,P0 I/O Pin[6] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DMASK5 ,P0 I/O Pin[5] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " DMASK4 ,P0 I/O Pin[4] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DMASK1 ,P0 I/O Pin[1] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " DMASK0 ,P0 I/O Pin[0] Data Output Write Mask" "Not masked,Masked"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 " P0_PIN,Port 0 Pin Value"
|
|
bitfld.long 0x00 7. " PIN7 ,P0 I/O Pin[7] Value" "Low,High"
|
|
bitfld.long 0x00 6. " PIN6 ,P0 I/O Pin[6] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIN5 ,P0 I/O Pin[5] Value" "Low,High"
|
|
bitfld.long 0x00 4. " PIN4 ,P0 I/O Pin[4] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIN1 ,P0 I/O Pin[1] Value" "Low,High"
|
|
bitfld.long 0x00 0. " PIN0 ,P0 I/O Pin[0] Value" "Low,High"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 " P0_DBEN,Port 0 De-bounce Enable"
|
|
bitfld.long 0x00 7. " DBEN7 ,P0 I/O Pin[7] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " DBEN6 ,P0 I/O Pin[6] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBEN5 ,P0 I/O Pin[5] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " DBEN4 ,P0 I/O Pin[4] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBEN1 ,P0 I/O Pin[1] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " DBEN0 ,P0 I/O Pin[0] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
line.long 0x04 " P0_IMD,Port 0 Interrupt Mode Control"
|
|
bitfld.long 0x04 7. " IMD7 ,P0 I/O Pin[7] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 6. " IMD6 ,P0 I/O Pin[6] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IMD5 ,P0 I/O Pin[5] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 4. " IMD4 ,P0 I/O Pin[4] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IMD1 ,P0 I/O Pin[1] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 0. " IMD0 ,P0 I/O Pin[0] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
line.long 0x08 " P0_IEN,Port 0 Interrupt Enable"
|
|
bitfld.long 0x08 23. " IR_EN7 ,P0 I/O Pin[7] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " IR_EN6 ,P0 I/O Pin[6] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " IR_EN5 ,P0 I/O Pin[5] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IR_EN4 ,P0 I/O Pin[4] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " IR_EN1 ,P0 I/O Pin[1] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " IR_EN0 ,P0 I/O Pin[0] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IF_EN7 ,P0 I/O Pin[7] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IF_EN6 ,P0 I/O Pin[6] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IF_EN5 ,P0 I/O Pin[5] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " IF_EN4 ,P0 I/O Pin[4] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IF_EN1 ,P0 I/O Pin[1] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IF_EN0 ,P0 I/O Pin[0] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
line.long 0x0C " P0_ISRC,Port 0 Interrupt Source Flag"
|
|
bitfld.long 0x0C 7. " ISRC7 ,P0 I/O Pin[7] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 6. " ISRC6 ,P0 I/O Pin[6] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ISRC5 ,P0 I/O Pin[5] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " ISRC4 ,P0 I/O Pin[4] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " ISRC1 ,P0 I/O Pin[1] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " ISRC0 ,P0 I/O Pin[0] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
base ad:0x50004200
|
|
width 13.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 " P00_DOUT,P0.0 Bit Output Control"
|
|
bitfld.long 0x00 0. " P00_DOUT ,P0 I/O Pin 0 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P01_DOUT,P0.1 Bit Output Control"
|
|
bitfld.long 0x04 0. " P01_DOUT ,P0 I/O Pin 1 Bit Output Control" "Low,High"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 " P04_DOUT,P0.4 Bit Output Control"
|
|
bitfld.long 0x00 0. " P04_DOUT ,P0 I/O Pin 4 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P05_DOUT,P0.5 Bit Output Control"
|
|
bitfld.long 0x04 0. " P05_DOUT ,P0 I/O Pin 5 Bit Output Control" "Low,High"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 " P06_DOUT,P0.6 Bit Output Control"
|
|
bitfld.long 0x00 0. " P06_DOUT ,P0 I/O Pin 6 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P07_DOUT,P0.7 Bit Output Control"
|
|
bitfld.long 0x04 0. " P07_DOUT ,P0 I/O Pin 7 Bit Output Control" "Low,High"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "Port 1"
|
|
base ad:0x50004040
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
width 13.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 " P1_PMD,Port 1 Pin I/O Mode Control"
|
|
bitfld.long 0x00 14.--15. " PMD7 ,P1 I/O Pin[7] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 12.--13. " PMD6 ,P1 I/O Pin[6] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PMD5 ,P1 I/O Pin[5] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 8.--9. " PMD4 ,P1 I/O Pin[4] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PMD3 ,P1 I/O Pin[3] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 4.--5. " PMD2 ,P1 I/O Pin[2] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PMD1 ,P1 I/O Pin[1] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 0.--1. " PMD0 ,P1 I/O Pin[0] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
line.long 0x04 " P1_OFFD,Port 1 Pin OFF Digital Enable"
|
|
bitfld.long 0x04 23. " OFFD7 ,P1 I/O Pin[7] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 22. " OFFD6 ,P1 I/O Pin[6] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OFFD5 ,P1 I/O Pin[5] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 20. " OFFD4 ,P1 I/O Pin[4] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OFFD3 ,P1 I/O Pin[3] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 18. " OFFD2 ,P1 I/O Pin[2] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OFFD1 ,P1 I/O Pin[1] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 16. " OFFD0 ,P1 I/O Pin[0] OFF digital input path Enable" "Enabled,Disabled"
|
|
line.long 0x08 " P1_DOUT,Port 1 Data Output Value"
|
|
bitfld.long 0x08 7. " DOUT7 ,P1 I/O Pin[7] Output Value" "Low,High"
|
|
bitfld.long 0x08 6. " DOUT6 ,P1 I/O Pin[6] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DOUT5 ,P1 I/O Pin[5] Output Value" "Low,High"
|
|
bitfld.long 0x08 4. " DOUT4 ,P1 I/O Pin[4] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DOUT3 ,P1 I/O Pin[3] Output Value" "Low,High"
|
|
bitfld.long 0x08 2. " DOUT2 ,P1 I/O Pin[2] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DOUT1 ,P1 I/O Pin[1] Output Value" "Low,High"
|
|
bitfld.long 0x08 0. " DOUT0 ,P1 I/O Pin[0] Output Value" "Low,High"
|
|
line.long 0x0C " P1_DMASK,Port 1 Data Output Write Mask"
|
|
bitfld.long 0x0C 7. " DMASK7 ,P1 I/O Pin[7] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " DMASK6 ,P1 I/O Pin[6] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DMASK5 ,P1 I/O Pin[5] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " DMASK4 ,P1 I/O Pin[4] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DMASK3 ,P1 I/O Pin[3] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " DMASK2 ,P1 I/O Pin[2] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DMASK1 ,P1 I/O Pin[1] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " DMASK0 ,P1 I/O Pin[0] Data Output Write Mask" "Not masked,Masked"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 " P1_PIN,Port 1 Pin Value"
|
|
bitfld.long 0x00 7. " PIN7 ,P1 I/O Pin[7] Value" "Low,High"
|
|
bitfld.long 0x00 6. " PIN6 ,P1 I/O Pin[6] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIN5 ,P1 I/O Pin[5] Value" "Low,High"
|
|
bitfld.long 0x00 4. " PIN4 ,P1 I/O Pin[4] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIN3 ,P1 I/O Pin[3] Value" "Low,High"
|
|
bitfld.long 0x00 2. " PIN2 ,P1 I/O Pin[2] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIN1 ,P1 I/O Pin[1] Value" "Low,High"
|
|
bitfld.long 0x00 0. " PIN0 ,P1 I/O Pin[0] Value" "Low,High"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 " P1_DBEN,Port 1 De-bounce Enable"
|
|
bitfld.long 0x00 7. " DBEN7 ,P1 I/O Pin[7] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " DBEN6 ,P1 I/O Pin[6] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBEN5 ,P1 I/O Pin[5] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " DBEN4 ,P1 I/O Pin[4] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DBEN3 ,P1 I/O Pin[3] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DBEN2 ,P1 I/O Pin[2] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBEN1 ,P1 I/O Pin[1] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " DBEN0 ,P1 I/O Pin[0] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
line.long 0x04 " P1_IMD,Port 1 Interrupt Mode Control"
|
|
bitfld.long 0x04 7. " IMD7 ,P1 I/O Pin[7] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 6. " IMD6 ,P1 I/O Pin[6] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IMD5 ,P1 I/O Pin[5] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 4. " IMD4 ,P1 I/O Pin[4] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IMD3 ,P1 I/O Pin[3] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 2. " IMD2 ,P1 I/O Pin[2] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IMD1 ,P1 I/O Pin[1] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 0. " IMD0 ,P1 I/O Pin[0] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
line.long 0x08 " P1_IEN,Port 1 Interrupt Enable"
|
|
bitfld.long 0x08 23. " IR_EN7 ,P1 I/O Pin[7] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " IR_EN6 ,P1 I/O Pin[6] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " IR_EN5 ,P1 I/O Pin[5] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IR_EN4 ,P1 I/O Pin[4] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IR_EN3 ,P1 I/O Pin[3] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IR_EN2 ,P1 I/O Pin[2] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " IR_EN1 ,P1 I/O Pin[1] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " IR_EN0 ,P1 I/O Pin[0] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IF_EN7 ,P1 I/O Pin[7] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IF_EN6 ,P1 I/O Pin[6] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IF_EN5 ,P1 I/O Pin[5] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " IF_EN4 ,P1 I/O Pin[4] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IF_EN3 ,P1 I/O Pin[3] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IF_EN2 ,P1 I/O Pin[2] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IF_EN1 ,P1 I/O Pin[1] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IF_EN0 ,P1 I/O Pin[0] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
line.long 0x0C " P1_ISRC,Port 1 Interrupt Source Flag"
|
|
bitfld.long 0x0C 7. " ISRC7 ,P1 I/O Pin[7] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 6. " ISRC6 ,P1 I/O Pin[6] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ISRC5 ,P1 I/O Pin[5] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " ISRC4 ,P1 I/O Pin[4] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ISRC3 ,P1 I/O Pin[3] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " ISRC2 ,P1 I/O Pin[2] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " ISRC1 ,P1 I/O Pin[1] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " ISRC0 ,P1 I/O Pin[0] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
base ad:0x50004220
|
|
width 13.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 " P10_DOUT,P1.0 Bit Output Control"
|
|
bitfld.long 0x00 0. " P10_DOUT ,P1 I/O Pin 0 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P11_DOUT,P1.1 Bit Output Control"
|
|
bitfld.long 0x04 0. " P11_DOUT ,P1 I/O Pin 1 Bit Output Control" "Low,High"
|
|
group.long 0x08++0x7
|
|
line.long 0x00 " P12_DOUT,P1.2 Bit Output Control"
|
|
bitfld.long 0x00 0. " P12_DOUT ,P1 I/O Pin 2 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P13_DOUT,P1.3 Bit Output Control"
|
|
bitfld.long 0x04 0. " P13_DOUT ,P1 I/O Pin 3 Bit Output Control" "Low,High"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 " P14_DOUT,P1.4 Bit Output Control"
|
|
bitfld.long 0x00 0. " P14_DOUT ,P1 I/O Pin 4 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P15_DOUT,P1.5 Bit Output Control"
|
|
bitfld.long 0x04 0. " P15_DOUT ,P1 I/O Pin 5 Bit Output Control" "Low,High"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 " P16_DOUT,P1.6 Bit Output Control"
|
|
bitfld.long 0x00 0. " P16_DOUT ,P1 I/O Pin 6 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P17_DOUT,P1.7 Bit Output Control"
|
|
bitfld.long 0x04 0. " P17_DOUT ,P1 I/O Pin 7 Bit Output Control" "Low,High"
|
|
width 0xB
|
|
elif (cpuis("M05?ZAN")||cpuis("M0516ZAN"))
|
|
width 13.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 " P1_PMD,Port 1 Pin I/O Mode Control"
|
|
bitfld.long 0x00 10.--11. " PMD5 ,P1 I/O Pin[5] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 8.--9. " PMD4 ,P1 I/O Pin[4] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PMD3 ,P1 I/O Pin[3] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 4.--5. " PMD2 ,P1 I/O Pin[2] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PMD0 ,P1 I/O Pin[0] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
line.long 0x04 " P1_OFFD,Port 1 Pin OFF Digital Enable"
|
|
bitfld.long 0x04 21. " OFFD5 ,P1 I/O Pin[5] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 20. " OFFD4 ,P1 I/O Pin[4] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OFFD3 ,P1 I/O Pin[3] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 18. " OFFD2 ,P1 I/O Pin[2] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " OFFD0 ,P1 I/O Pin[0] OFF digital input path Enable" "Enabled,Disabled"
|
|
line.long 0x08 " P1_DOUT,Port 1 Data Output Value"
|
|
bitfld.long 0x08 5. " DOUT5 ,P1 I/O Pin[5] Output Value" "Low,High"
|
|
bitfld.long 0x08 4. " DOUT4 ,P1 I/O Pin[4] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DOUT3 ,P1 I/O Pin[3] Output Value" "Low,High"
|
|
bitfld.long 0x08 2. " DOUT2 ,P1 I/O Pin[2] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DOUT0 ,P1 I/O Pin[0] Output Value" "Low,High"
|
|
line.long 0x0C " P1_DMASK,Port 1 Data Output Write Mask"
|
|
bitfld.long 0x0C 5. " DMASK5 ,P1 I/O Pin[5] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " DMASK4 ,P1 I/O Pin[4] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DMASK3 ,P1 I/O Pin[3] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " DMASK2 ,P1 I/O Pin[2] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " DMASK0 ,P1 I/O Pin[0] Data Output Write Mask" "Not masked,Masked"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 " P1_PIN,Port 1 Pin Value"
|
|
bitfld.long 0x00 5. " PIN5 ,P1 I/O Pin[5] Value" "Low,High"
|
|
bitfld.long 0x00 4. " PIN4 ,P1 I/O Pin[4] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIN3 ,P1 I/O Pin[3] Value" "Low,High"
|
|
bitfld.long 0x00 2. " PIN2 ,P1 I/O Pin[2] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PIN0 ,P1 I/O Pin[0] Value" "Low,High"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 " P1_DBEN,Port 1 De-bounce Enable"
|
|
bitfld.long 0x00 5. " DBEN5 ,P1 I/O Pin[5] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " DBEN4 ,P1 I/O Pin[4] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DBEN3 ,P1 I/O Pin[3] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DBEN2 ,P1 I/O Pin[2] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DBEN0 ,P1 I/O Pin[0] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
line.long 0x04 " P1_IMD,Port 1 Interrupt Mode Control"
|
|
bitfld.long 0x04 5. " IMD5 ,P1 I/O Pin[5] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 4. " IMD4 ,P1 I/O Pin[4] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IMD3 ,P1 I/O Pin[3] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 2. " IMD2 ,P1 I/O Pin[2] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 0. " IMD0 ,P1 I/O Pin[0] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
line.long 0x08 " P1_IEN,Port 1 Interrupt Enable"
|
|
bitfld.long 0x08 21. " IR_EN5 ,P1 I/O Pin[5] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IR_EN4 ,P1 I/O Pin[4] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IR_EN3 ,P1 I/O Pin[3] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IR_EN2 ,P1 I/O Pin[2] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " IR_EN0 ,P1 I/O Pin[0] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IF_EN5 ,P1 I/O Pin[5] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " IF_EN4 ,P1 I/O Pin[4] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IF_EN3 ,P1 I/O Pin[3] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IF_EN2 ,P1 I/O Pin[2] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " IF_EN0 ,P1 I/O Pin[0] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
line.long 0x0C " P1_ISRC,Port 1 Interrupt Source Flag"
|
|
bitfld.long 0x0C 5. " ISRC5 ,P1 I/O Pin[5] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " ISRC4 ,P1 I/O Pin[4] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ISRC3 ,P1 I/O Pin[3] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " ISRC2 ,P1 I/O Pin[2] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " ISRC0 ,P1 I/O Pin[0] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
base ad:0x50004220
|
|
width 13.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 " P10_DOUT,P1.0 Bit Output Control"
|
|
bitfld.long 0x00 0. " P10_DOUT ,P1 I/O Pin 0 Bit Output Control" "Low,High"
|
|
group.long 0x08++0x7
|
|
line.long 0x00 " P12_DOUT,P1.2 Bit Output Control"
|
|
bitfld.long 0x00 0. " P12_DOUT ,P1 I/O Pin 2 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P13_DOUT,P1.3 Bit Output Control"
|
|
bitfld.long 0x04 0. " P13_DOUT ,P1 I/O Pin 3 Bit Output Control" "Low,High"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 " P14_DOUT,P1.4 Bit Output Control"
|
|
bitfld.long 0x00 0. " P14_DOUT ,P1 I/O Pin 4 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P15_DOUT,P1.5 Bit Output Control"
|
|
bitfld.long 0x04 0. " P15_DOUT ,P1 I/O Pin 5 Bit Output Control" "Low,High"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "Port 2"
|
|
base ad:0x50004080
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
width 13.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 " P2_PMD,Port 2 Pin I/O Mode Control"
|
|
bitfld.long 0x00 14.--15. " PMD7 ,P2 I/O Pin[7] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 12.--13. " PMD6 ,P2 I/O Pin[6] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PMD5 ,P2 I/O Pin[5] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 8.--9. " PMD4 ,P2 I/O Pin[4] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PMD3 ,P2 I/O Pin[3] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 4.--5. " PMD2 ,P2 I/O Pin[2] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PMD1 ,P2 I/O Pin[1] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 0.--1. " PMD0 ,P2 I/O Pin[0] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
line.long 0x04 " P2_OFFD,Port 2 Pin OFF Digital Enable"
|
|
bitfld.long 0x04 23. " OFFD7 ,P2 I/O Pin[7] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 22. " OFFD6 ,P2 I/O Pin[6] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OFFD5 ,P2 I/O Pin[5] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 20. " OFFD4 ,P2 I/O Pin[4] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OFFD3 ,P2 I/O Pin[3] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 18. " OFFD2 ,P2 I/O Pin[2] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OFFD1 ,P2 I/O Pin[1] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 16. " OFFD0 ,P2 I/O Pin[0] OFF digital input path Enable" "Enabled,Disabled"
|
|
line.long 0x08 " P2_DOUT,Port 2 Data Output Value"
|
|
bitfld.long 0x08 7. " DOUT7 ,P2 I/O Pin[7] Output Value" "Low,High"
|
|
bitfld.long 0x08 6. " DOUT6 ,P2 I/O Pin[6] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DOUT5 ,P2 I/O Pin[5] Output Value" "Low,High"
|
|
bitfld.long 0x08 4. " DOUT4 ,P2 I/O Pin[4] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DOUT3 ,P2 I/O Pin[3] Output Value" "Low,High"
|
|
bitfld.long 0x08 2. " DOUT2 ,P2 I/O Pin[2] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DOUT1 ,P2 I/O Pin[1] Output Value" "Low,High"
|
|
bitfld.long 0x08 0. " DOUT0 ,P2 I/O Pin[0] Output Value" "Low,High"
|
|
line.long 0x0C " P2_DMASK,Port 2 Data Output Write Mask"
|
|
bitfld.long 0x0C 7. " DMASK7 ,P2 I/O Pin[7] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " DMASK6 ,P2 I/O Pin[6] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DMASK5 ,P2 I/O Pin[5] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " DMASK4 ,P2 I/O Pin[4] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DMASK3 ,P2 I/O Pin[3] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " DMASK2 ,P2 I/O Pin[2] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DMASK1 ,P2 I/O Pin[1] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " DMASK0 ,P2 I/O Pin[0] Data Output Write Mask" "Not masked,Masked"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 " P2_PIN,Port 2 Pin Value"
|
|
bitfld.long 0x00 7. " PIN7 ,P2 I/O Pin[7] Value" "Low,High"
|
|
bitfld.long 0x00 6. " PIN6 ,P2 I/O Pin[6] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIN5 ,P2 I/O Pin[5] Value" "Low,High"
|
|
bitfld.long 0x00 4. " PIN4 ,P2 I/O Pin[4] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIN3 ,P2 I/O Pin[3] Value" "Low,High"
|
|
bitfld.long 0x00 2. " PIN2 ,P2 I/O Pin[2] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIN1 ,P2 I/O Pin[1] Value" "Low,High"
|
|
bitfld.long 0x00 0. " PIN0 ,P2 I/O Pin[0] Value" "Low,High"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 " P2_DBEN,Port 2 De-bounce Enable"
|
|
bitfld.long 0x00 7. " DBEN7 ,P2 I/O Pin[7] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " DBEN6 ,P2 I/O Pin[6] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBEN5 ,P2 I/O Pin[5] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " DBEN4 ,P2 I/O Pin[4] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DBEN3 ,P2 I/O Pin[3] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DBEN2 ,P2 I/O Pin[2] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBEN1 ,P2 I/O Pin[1] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " DBEN0 ,P2 I/O Pin[0] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
line.long 0x04 " P2_IMD,Port 2 Interrupt Mode Control"
|
|
bitfld.long 0x04 7. " IMD7 ,P2 I/O Pin[7] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 6. " IMD6 ,P2 I/O Pin[6] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IMD5 ,P2 I/O Pin[5] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 4. " IMD4 ,P2 I/O Pin[4] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IMD3 ,P2 I/O Pin[3] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 2. " IMD2 ,P2 I/O Pin[2] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IMD1 ,P2 I/O Pin[1] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 0. " IMD0 ,P2 I/O Pin[0] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
line.long 0x08 " P2_IEN,Port 2 Interrupt Enable"
|
|
bitfld.long 0x08 23. " IR_EN7 ,P2 I/O Pin[7] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " IR_EN6 ,P2 I/O Pin[6] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " IR_EN5 ,P2 I/O Pin[5] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IR_EN4 ,P2 I/O Pin[4] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IR_EN3 ,P2 I/O Pin[3] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IR_EN2 ,P2 I/O Pin[2] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " IR_EN1 ,P2 I/O Pin[1] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " IR_EN0 ,P2 I/O Pin[0] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IF_EN7 ,P2 I/O Pin[7] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IF_EN6 ,P2 I/O Pin[6] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IF_EN5 ,P2 I/O Pin[5] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " IF_EN4 ,P2 I/O Pin[4] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IF_EN3 ,P2 I/O Pin[3] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IF_EN2 ,P2 I/O Pin[2] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IF_EN1 ,P2 I/O Pin[1] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IF_EN0 ,P2 I/O Pin[0] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
line.long 0x0C " P2_ISRC,Port 2 Interrupt Source Flag"
|
|
bitfld.long 0x0C 7. " ISRC7 ,P2 I/O Pin[7] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 6. " ISRC6 ,P2 I/O Pin[6] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ISRC5 ,P2 I/O Pin[5] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " ISRC4 ,P2 I/O Pin[4] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ISRC3 ,P2 I/O Pin[3] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " ISRC2 ,P2 I/O Pin[2] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " ISRC1 ,P2 I/O Pin[1] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " ISRC0 ,P2 I/O Pin[0] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
base ad:0x50004240
|
|
width 13.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 " P20_DOUT,P2.0 Bit Output Control"
|
|
bitfld.long 0x00 0. " P20_DOUT ,P2 I/O Pin 0 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P21_DOUT,P2.1 Bit Output Control"
|
|
bitfld.long 0x04 0. " P21_DOUT ,P2 I/O Pin 1 Bit Output Control" "Low,High"
|
|
group.long 0x08++0x7
|
|
line.long 0x00 " P22_DOUT,P2.2 Bit Output Control"
|
|
bitfld.long 0x00 0. " P22_DOUT ,P2 I/O Pin 2 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P23_DOUT,P2.3 Bit Output Control"
|
|
bitfld.long 0x04 0. " P23_DOUT ,P2 I/O Pin 3 Bit Output Control" "Low,High"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 " P24_DOUT,P2.4 Bit Output Control"
|
|
bitfld.long 0x00 0. " P24_DOUT ,P2 I/O Pin 4 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P25_DOUT,P2.5 Bit Output Control"
|
|
bitfld.long 0x04 0. " P25_DOUT ,P2 I/O Pin 5 Bit Output Control" "Low,High"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 " P26_DOUT,P2.6 Bit Output Control"
|
|
bitfld.long 0x00 0. " P26_DOUT ,P2 I/O Pin 6 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P27_DOUT,P2.7 Bit Output Control"
|
|
bitfld.long 0x04 0. " P27_DOUT ,P2 I/O Pin 7 Bit Output Control" "Low,High"
|
|
width 0xB
|
|
elif (cpuis("M05?ZAN")||cpuis("M0516ZAN"))
|
|
width 13.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 " P2_PMD,Port 2 Pin I/O Mode Control"
|
|
bitfld.long 0x00 12.--13. " PMD6 ,P2 I/O Pin[6] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PMD5 ,P2 I/O Pin[5] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 8.--9. " PMD4 ,P2 I/O Pin[4] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PMD3 ,P2 I/O Pin[3] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 4.--5. " PMD2 ,P2 I/O Pin[2] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
line.long 0x04 " P2_OFFD,Port 2 Pin OFF Digital Enable"
|
|
bitfld.long 0x04 22. " OFFD6 ,P2 I/O Pin[6] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OFFD5 ,P2 I/O Pin[5] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 20. " OFFD4 ,P2 I/O Pin[4] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OFFD3 ,P2 I/O Pin[3] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 18. " OFFD2 ,P2 I/O Pin[2] OFF digital input path Enable" "Enabled,Disabled"
|
|
line.long 0x08 " P2_DOUT,Port 2 Data Output Value"
|
|
bitfld.long 0x08 6. " DOUT6 ,P2 I/O Pin[6] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DOUT5 ,P2 I/O Pin[5] Output Value" "Low,High"
|
|
bitfld.long 0x08 4. " DOUT4 ,P2 I/O Pin[4] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DOUT3 ,P2 I/O Pin[3] Output Value" "Low,High"
|
|
bitfld.long 0x08 2. " DOUT2 ,P2 I/O Pin[2] Output Value" "Low,High"
|
|
line.long 0x0C " P2_DMASK,Port 2 Data Output Write Mask"
|
|
bitfld.long 0x0C 6. " DMASK6 ,P2 I/O Pin[6] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DMASK5 ,P2 I/O Pin[5] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " DMASK4 ,P2 I/O Pin[4] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DMASK3 ,P2 I/O Pin[3] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " DMASK2 ,P2 I/O Pin[2] Data Output Write Mask" "Not masked,Masked"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 " P2_PIN,Port 2 Pin Value"
|
|
bitfld.long 0x00 6. " PIN6 ,P2 I/O Pin[6] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIN5 ,P2 I/O Pin[5] Value" "Low,High"
|
|
bitfld.long 0x00 4. " PIN4 ,P2 I/O Pin[4] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIN3 ,P2 I/O Pin[3] Value" "Low,High"
|
|
bitfld.long 0x00 2. " PIN2 ,P2 I/O Pin[2] Value" "Low,High"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 " P2_DBEN,Port 2 De-bounce Enable"
|
|
bitfld.long 0x00 6. " DBEN6 ,P2 I/O Pin[6] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBEN5 ,P2 I/O Pin[5] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " DBEN4 ,P2 I/O Pin[4] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DBEN3 ,P2 I/O Pin[3] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DBEN2 ,P2 I/O Pin[2] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
line.long 0x04 " P2_IMD,Port 2 Interrupt Mode Control"
|
|
bitfld.long 0x04 6. " IMD6 ,P2 I/O Pin[6] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IMD5 ,P2 I/O Pin[5] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 4. " IMD4 ,P2 I/O Pin[4] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IMD3 ,P2 I/O Pin[3] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 2. " IMD2 ,P2 I/O Pin[2] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
line.long 0x08 " P2_IEN,Port 2 Interrupt Enable"
|
|
bitfld.long 0x08 22. " IR_EN6 ,P2 I/O Pin[6] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " IR_EN5 ,P2 I/O Pin[5] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IR_EN4 ,P2 I/O Pin[4] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IR_EN3 ,P2 I/O Pin[3] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IR_EN2 ,P2 I/O Pin[2] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " IF_EN6 ,P2 I/O Pin[6] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IF_EN5 ,P2 I/O Pin[5] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " IF_EN4 ,P2 I/O Pin[4] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IF_EN3 ,P2 I/O Pin[3] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IF_EN2 ,P2 I/O Pin[2] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
line.long 0x0C " P2_ISRC,Port 2 Interrupt Source Flag"
|
|
bitfld.long 0x0C 6. " ISRC6 ,P2 I/O Pin[6] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ISRC5 ,P2 I/O Pin[5] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " ISRC4 ,P2 I/O Pin[4] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ISRC3 ,P2 I/O Pin[3] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " ISRC2 ,P2 I/O Pin[2] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
base ad:0x50004240
|
|
width 13.
|
|
group.long 0x08++0x7
|
|
line.long 0x00 " P22_DOUT,P2.2 Bit Output Control"
|
|
bitfld.long 0x00 0. " P22_DOUT ,P2 I/O Pin 2 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P23_DOUT,P2.3 Bit Output Control"
|
|
bitfld.long 0x04 0. " P23_DOUT ,P2 I/O Pin 3 Bit Output Control" "Low,High"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 " P24_DOUT,P2.4 Bit Output Control"
|
|
bitfld.long 0x00 0. " P24_DOUT ,P2 I/O Pin 4 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P25_DOUT,P2.5 Bit Output Control"
|
|
bitfld.long 0x04 0. " P25_DOUT ,P2 I/O Pin 5 Bit Output Control" "Low,High"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 " P26_DOUT,P2.6 Bit Output Control"
|
|
bitfld.long 0x00 0. " P26_DOUT ,P2 I/O Pin 6 Bit Output Control" "Low,High"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "Port 3"
|
|
base ad:0x500040C0
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
width 13.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 " P3_PMD,Port 3 Pin I/O Mode Control"
|
|
bitfld.long 0x00 14.--15. " PMD7 ,P3 I/O Pin[7] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 12.--13. " PMD6 ,P3 I/O Pin[6] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PMD5 ,P3 I/O Pin[5] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 8.--9. " PMD4 ,P3 I/O Pin[4] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PMD3 ,P3 I/O Pin[3] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 4.--5. " PMD2 ,P3 I/O Pin[2] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PMD1 ,P3 I/O Pin[1] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 0.--1. " PMD0 ,P3 I/O Pin[0] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
line.long 0x04 " P3_OFFD,Port 3 Pin OFF Digital Enable"
|
|
bitfld.long 0x04 23. " OFFD7 ,P3 I/O Pin[7] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 22. " OFFD6 ,P3 I/O Pin[6] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OFFD5 ,P3 I/O Pin[5] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 20. " OFFD4 ,P3 I/O Pin[4] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OFFD3 ,P3 I/O Pin[3] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 18. " OFFD2 ,P3 I/O Pin[2] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OFFD1 ,P3 I/O Pin[1] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 16. " OFFD0 ,P3 I/O Pin[0] OFF digital input path Enable" "Enabled,Disabled"
|
|
line.long 0x08 " P3_DOUT,Port 3 Data Output Value"
|
|
bitfld.long 0x08 7. " DOUT7 ,P3 I/O Pin[7] Output Value" "Low,High"
|
|
bitfld.long 0x08 6. " DOUT6 ,P3 I/O Pin[6] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DOUT5 ,P3 I/O Pin[5] Output Value" "Low,High"
|
|
bitfld.long 0x08 4. " DOUT4 ,P3 I/O Pin[4] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DOUT3 ,P3 I/O Pin[3] Output Value" "Low,High"
|
|
bitfld.long 0x08 2. " DOUT2 ,P3 I/O Pin[2] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DOUT1 ,P3 I/O Pin[1] Output Value" "Low,High"
|
|
bitfld.long 0x08 0. " DOUT0 ,P3 I/O Pin[0] Output Value" "Low,High"
|
|
line.long 0x0C " P3_DMASK,Port 3 Data Output Write Mask"
|
|
bitfld.long 0x0C 7. " DMASK7 ,P3 I/O Pin[7] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " DMASK6 ,P3 I/O Pin[6] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DMASK5 ,P3 I/O Pin[5] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " DMASK4 ,P3 I/O Pin[4] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DMASK3 ,P3 I/O Pin[3] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " DMASK2 ,P3 I/O Pin[2] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DMASK1 ,P3 I/O Pin[1] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " DMASK0 ,P3 I/O Pin[0] Data Output Write Mask" "Not masked,Masked"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 " P3_PIN,Port 3 Pin Value"
|
|
bitfld.long 0x00 7. " PIN7 ,P3 I/O Pin[7] Value" "Low,High"
|
|
bitfld.long 0x00 6. " PIN6 ,P3 I/O Pin[6] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIN5 ,P3 I/O Pin[5] Value" "Low,High"
|
|
bitfld.long 0x00 4. " PIN4 ,P3 I/O Pin[4] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIN3 ,P3 I/O Pin[3] Value" "Low,High"
|
|
bitfld.long 0x00 2. " PIN2 ,P3 I/O Pin[2] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIN1 ,P3 I/O Pin[1] Value" "Low,High"
|
|
bitfld.long 0x00 0. " PIN0 ,P3 I/O Pin[0] Value" "Low,High"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 " P3_DBEN,Port 3 De-bounce Enable"
|
|
bitfld.long 0x00 7. " DBEN7 ,P3 I/O Pin[7] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " DBEN6 ,P3 I/O Pin[6] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBEN5 ,P3 I/O Pin[5] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " DBEN4 ,P3 I/O Pin[4] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DBEN3 ,P3 I/O Pin[3] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DBEN2 ,P3 I/O Pin[2] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBEN1 ,P3 I/O Pin[1] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " DBEN0 ,P3 I/O Pin[0] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
line.long 0x04 " P3_IMD,Port 3 Interrupt Mode Control"
|
|
bitfld.long 0x04 7. " IMD7 ,P3 I/O Pin[7] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 6. " IMD6 ,P3 I/O Pin[6] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IMD5 ,P3 I/O Pin[5] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 4. " IMD4 ,P3 I/O Pin[4] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IMD3 ,P3 I/O Pin[3] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 2. " IMD2 ,P3 I/O Pin[2] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IMD1 ,P3 I/O Pin[1] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 0. " IMD0 ,P3 I/O Pin[0] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
line.long 0x08 " P3_IEN,Port 3 Interrupt Enable"
|
|
bitfld.long 0x08 23. " IR_EN7 ,P3 I/O Pin[7] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " IR_EN6 ,P3 I/O Pin[6] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " IR_EN5 ,P3 I/O Pin[5] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IR_EN4 ,P3 I/O Pin[4] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IR_EN3 ,P3 I/O Pin[3] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IR_EN2 ,P3 I/O Pin[2] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " IR_EN1 ,P3 I/O Pin[1] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " IR_EN0 ,P3 I/O Pin[0] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IF_EN7 ,P3 I/O Pin[7] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IF_EN6 ,P3 I/O Pin[6] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IF_EN5 ,P3 I/O Pin[5] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " IF_EN4 ,P3 I/O Pin[4] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IF_EN3 ,P3 I/O Pin[3] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IF_EN2 ,P3 I/O Pin[2] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IF_EN1 ,P3 I/O Pin[1] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IF_EN0 ,P3 I/O Pin[0] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
line.long 0x0C " P3_ISRC,Port 3 Interrupt Source Flag"
|
|
bitfld.long 0x0C 7. " ISRC7 ,P3 I/O Pin[7] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 6. " ISRC6 ,P3 I/O Pin[6] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ISRC5 ,P3 I/O Pin[5] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " ISRC4 ,P3 I/O Pin[4] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ISRC3 ,P3 I/O Pin[3] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " ISRC2 ,P3 I/O Pin[2] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " ISRC1 ,P3 I/O Pin[1] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " ISRC0 ,P3 I/O Pin[0] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
base ad:0x50004260
|
|
width 13.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 " P30_DOUT,P3.0 Bit Output Control"
|
|
bitfld.long 0x00 0. " P30_DOUT ,P3 I/O Pin 0 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P31_DOUT,P3.1 Bit Output Control"
|
|
bitfld.long 0x04 0. " P31_DOUT ,P3 I/O Pin 1 Bit Output Control" "Low,High"
|
|
group.long 0x08++0x7
|
|
line.long 0x00 " P32_DOUT,P3.2 Bit Output Control"
|
|
bitfld.long 0x00 0. " P32_DOUT ,P3 I/O Pin 2 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P33_DOUT,P3.3 Bit Output Control"
|
|
bitfld.long 0x04 0. " P33_DOUT ,P3 I/O Pin 3 Bit Output Control" "Low,High"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 " P34_DOUT,P3.4 Bit Output Control"
|
|
bitfld.long 0x00 0. " P34_DOUT ,P3 I/O Pin 4 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P35_DOUT,P3.5 Bit Output Control"
|
|
bitfld.long 0x04 0. " P35_DOUT ,P3 I/O Pin 5 Bit Output Control" "Low,High"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 " P36_DOUT,P3.6 Bit Output Control"
|
|
bitfld.long 0x00 0. " P36_DOUT ,P3 I/O Pin 6 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P37_DOUT,P3.7 Bit Output Control"
|
|
bitfld.long 0x04 0. " P37_DOUT ,P3 I/O Pin 7 Bit Output Control" "Low,High"
|
|
width 0xB
|
|
elif (cpuis("M05?ZAN")||cpuis("M0516ZAN"))
|
|
width 13.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 " P3_PMD,Port 3 Pin I/O Mode Control"
|
|
bitfld.long 0x00 12.--13. " PMD6 ,P3 I/O Pin[6] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PMD5 ,P3 I/O Pin[5] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 8.--9. " PMD4 ,P3 I/O Pin[4] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PMD2 ,P3 I/O Pin[2] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PMD1 ,P3 I/O Pin[1] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 0.--1. " PMD0 ,P3 I/O Pin[0] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
line.long 0x04 " P3_OFFD,Port 3 Pin OFF Digital Enable"
|
|
bitfld.long 0x04 22. " OFFD6 ,P3 I/O Pin[6] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OFFD5 ,P3 I/O Pin[5] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 20. " OFFD4 ,P3 I/O Pin[4] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " OFFD2 ,P3 I/O Pin[2] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OFFD1 ,P3 I/O Pin[1] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 16. " OFFD0 ,P3 I/O Pin[0] OFF digital input path Enable" "Enabled,Disabled"
|
|
line.long 0x08 " P3_DOUT,Port 3 Data Output Value"
|
|
bitfld.long 0x08 6. " DOUT6 ,P3 I/O Pin[6] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DOUT5 ,P3 I/O Pin[5] Output Value" "Low,High"
|
|
bitfld.long 0x08 4. " DOUT4 ,P3 I/O Pin[4] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DOUT2 ,P3 I/O Pin[2] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DOUT1 ,P3 I/O Pin[1] Output Value" "Low,High"
|
|
bitfld.long 0x08 0. " DOUT0 ,P3 I/O Pin[0] Output Value" "Low,High"
|
|
line.long 0x0C " P3_DMASK,Port 3 Data Output Write Mask"
|
|
bitfld.long 0x0C 6. " DMASK6 ,P3 I/O Pin[6] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DMASK5 ,P3 I/O Pin[5] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " DMASK4 ,P3 I/O Pin[4] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " DMASK2 ,P3 I/O Pin[2] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DMASK1 ,P3 I/O Pin[1] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " DMASK0 ,P3 I/O Pin[0] Data Output Write Mask" "Not masked,Masked"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 " P3_PIN,Port 3 Pin Value"
|
|
bitfld.long 0x00 6. " PIN6 ,P3 I/O Pin[6] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIN5 ,P3 I/O Pin[5] Value" "Low,High"
|
|
bitfld.long 0x00 4. " PIN4 ,P3 I/O Pin[4] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PIN2 ,P3 I/O Pin[2] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIN1 ,P3 I/O Pin[1] Value" "Low,High"
|
|
bitfld.long 0x00 0. " PIN0 ,P3 I/O Pin[0] Value" "Low,High"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 " P3_DBEN,Port 3 De-bounce Enable"
|
|
bitfld.long 0x00 6. " DBEN6 ,P3 I/O Pin[6] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBEN5 ,P3 I/O Pin[5] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " DBEN4 ,P3 I/O Pin[4] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DBEN2 ,P3 I/O Pin[2] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBEN1 ,P3 I/O Pin[1] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " DBEN0 ,P3 I/O Pin[0] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
line.long 0x04 " P3_IMD,Port 3 Interrupt Mode Control"
|
|
bitfld.long 0x04 6. " IMD6 ,P3 I/O Pin[6] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IMD5 ,P3 I/O Pin[5] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 4. " IMD4 ,P3 I/O Pin[4] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 2. " IMD2 ,P3 I/O Pin[2] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IMD1 ,P3 I/O Pin[1] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 0. " IMD0 ,P3 I/O Pin[0] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
line.long 0x08 " P3_IEN,Port 3 Interrupt Enable"
|
|
bitfld.long 0x08 22. " IR_EN6 ,P3 I/O Pin[6] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " IR_EN5 ,P3 I/O Pin[5] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IR_EN4 ,P3 I/O Pin[4] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " IR_EN2 ,P3 I/O Pin[2] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " IR_EN1 ,P3 I/O Pin[1] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " IR_EN0 ,P3 I/O Pin[0] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " IF_EN6 ,P3 I/O Pin[6] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IF_EN5 ,P3 I/O Pin[5] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " IF_EN4 ,P3 I/O Pin[4] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " IF_EN2 ,P3 I/O Pin[2] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IF_EN1 ,P3 I/O Pin[1] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IF_EN0 ,P3 I/O Pin[0] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
line.long 0x0C " P3_ISRC,Port 3 Interrupt Source Flag"
|
|
bitfld.long 0x0C 6. " ISRC6 ,P3 I/O Pin[6] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ISRC5 ,P3 I/O Pin[5] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " ISRC4 ,P3 I/O Pin[4] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " ISRC2 ,P3 I/O Pin[2] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " ISRC1 ,P3 I/O Pin[1] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " ISRC0 ,P3 I/O Pin[0] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
base ad:0x50004260
|
|
width 13.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 " P30_DOUT,P3.0 Bit Output Control"
|
|
bitfld.long 0x00 0. " P30_DOUT ,P3 I/O Pin 0 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P31_DOUT,P3.1 Bit Output Control"
|
|
bitfld.long 0x04 0. " P31_DOUT ,P3 I/O Pin 1 Bit Output Control" "Low,High"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 " P32_DOUT,P3.2 Bit Output Control"
|
|
bitfld.long 0x00 0. " P32_DOUT ,P3 I/O Pin 2 Bit Output Control" "Low,High"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 " P34_DOUT,P3.4 Bit Output Control"
|
|
bitfld.long 0x00 0. " P34_DOUT ,P3 I/O Pin 4 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P35_DOUT,P3.5 Bit Output Control"
|
|
bitfld.long 0x04 0. " P35_DOUT ,P3 I/O Pin 5 Bit Output Control" "Low,High"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 " P36_DOUT,P3.6 Bit Output Control"
|
|
bitfld.long 0x00 0. " P36_DOUT ,P3 I/O Pin 6 Bit Output Control" "Low,High"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "Port 4"
|
|
base ad:0x50004100
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
width 13.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 " P4_PMD,Port 4 Pin I/O Mode Control"
|
|
bitfld.long 0x00 14.--15. " PMD7 ,P4 I/O Pin[7] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 12.--13. " PMD6 ,P4 I/O Pin[6] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " PMD5 ,P4 I/O Pin[5] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 8.--9. " PMD4 ,P4 I/O Pin[4] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " PMD3 ,P4 I/O Pin[3] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 4.--5. " PMD2 ,P4 I/O Pin[2] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PMD1 ,P4 I/O Pin[1] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 0.--1. " PMD0 ,P4 I/O Pin[0] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
line.long 0x04 " P4_OFFD,Port 4 Pin OFF Digital Enable"
|
|
bitfld.long 0x04 23. " OFFD7 ,P4 I/O Pin[7] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 22. " OFFD6 ,P4 I/O Pin[6] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " OFFD5 ,P4 I/O Pin[5] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 20. " OFFD4 ,P4 I/O Pin[4] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " OFFD3 ,P4 I/O Pin[3] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 18. " OFFD2 ,P4 I/O Pin[2] OFF digital input path Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OFFD1 ,P4 I/O Pin[1] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 16. " OFFD0 ,P4 I/O Pin[0] OFF digital input path Enable" "Enabled,Disabled"
|
|
line.long 0x08 " P4_DOUT,Port 4 Data Output Value"
|
|
bitfld.long 0x08 7. " DOUT7 ,P4 I/O Pin[7] Output Value" "Low,High"
|
|
bitfld.long 0x08 6. " DOUT6 ,P4 I/O Pin[6] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DOUT5 ,P4 I/O Pin[5] Output Value" "Low,High"
|
|
bitfld.long 0x08 4. " DOUT4 ,P4 I/O Pin[4] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DOUT3 ,P4 I/O Pin[3] Output Value" "Low,High"
|
|
bitfld.long 0x08 2. " DOUT2 ,P4 I/O Pin[2] Output Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DOUT1 ,P4 I/O Pin[1] Output Value" "Low,High"
|
|
bitfld.long 0x08 0. " DOUT0 ,P4 I/O Pin[0] Output Value" "Low,High"
|
|
line.long 0x0C " P4_DMASK,Port 4 Data Output Write Mask"
|
|
bitfld.long 0x0C 7. " DMASK7 ,P4 I/O Pin[7] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " DMASK6 ,P4 I/O Pin[6] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DMASK5 ,P4 I/O Pin[5] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 4. " DMASK4 ,P4 I/O Pin[4] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " DMASK3 ,P4 I/O Pin[3] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " DMASK2 ,P4 I/O Pin[2] Data Output Write Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DMASK1 ,P4 I/O Pin[1] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " DMASK0 ,P4 I/O Pin[0] Data Output Write Mask" "Not masked,Masked"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 " P4_PIN,Port 4 Pin Value"
|
|
bitfld.long 0x00 7. " PIN7 ,P4 I/O Pin[7] Value" "Low,High"
|
|
bitfld.long 0x00 6. " PIN6 ,P4 I/O Pin[6] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIN5 ,P4 I/O Pin[5] Value" "Low,High"
|
|
bitfld.long 0x00 4. " PIN4 ,P4 I/O Pin[4] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PIN3 ,P4 I/O Pin[3] Value" "Low,High"
|
|
bitfld.long 0x00 2. " PIN2 ,P4 I/O Pin[2] Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PIN1 ,P4 I/O Pin[1] Value" "Low,High"
|
|
bitfld.long 0x00 0. " PIN0 ,P4 I/O Pin[0] Value" "Low,High"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 " P4_DBEN,Port 4 De-bounce Enable"
|
|
bitfld.long 0x00 7. " DBEN7 ,P4 I/O Pin[7] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " DBEN6 ,P4 I/O Pin[6] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBEN5 ,P4 I/O Pin[5] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " DBEN4 ,P4 I/O Pin[4] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DBEN3 ,P4 I/O Pin[3] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " DBEN2 ,P4 I/O Pin[2] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBEN1 ,P4 I/O Pin[1] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " DBEN0 ,P4 I/O Pin[0] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
line.long 0x04 " P4_IMD,Port 4 Interrupt Mode Control"
|
|
bitfld.long 0x04 7. " IMD7 ,P4 I/O Pin[7] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 6. " IMD6 ,P4 I/O Pin[6] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IMD5 ,P4 I/O Pin[5] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 4. " IMD4 ,P4 I/O Pin[4] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IMD3 ,P4 I/O Pin[3] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 2. " IMD2 ,P4 I/O Pin[2] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IMD1 ,P4 I/O Pin[1] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 0. " IMD0 ,P4 I/O Pin[0] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
line.long 0x08 " P4_IEN,Port 4 Interrupt Enable"
|
|
bitfld.long 0x08 23. " IR_EN7 ,P4 I/O Pin[7] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " IR_EN6 ,P4 I/O Pin[6] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " IR_EN5 ,P4 I/O Pin[5] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " IR_EN4 ,P4 I/O Pin[4] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " IR_EN3 ,P4 I/O Pin[3] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " IR_EN2 ,P4 I/O Pin[2] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " IR_EN1 ,P4 I/O Pin[1] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " IR_EN0 ,P4 I/O Pin[0] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IF_EN7 ,P4 I/O Pin[7] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IF_EN6 ,P4 I/O Pin[6] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " IF_EN5 ,P4 I/O Pin[5] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " IF_EN4 ,P4 I/O Pin[4] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " IF_EN3 ,P4 I/O Pin[3] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " IF_EN2 ,P4 I/O Pin[2] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " IF_EN1 ,P4 I/O Pin[1] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " IF_EN0 ,P4 I/O Pin[0] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
line.long 0x0C " P4_ISRC,Port 4 Interrupt Source Flag"
|
|
bitfld.long 0x0C 7. " ISRC7 ,P4 I/O Pin[7] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 6. " ISRC6 ,P4 I/O Pin[6] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " ISRC5 ,P4 I/O Pin[5] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 4. " ISRC4 ,P4 I/O Pin[4] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " ISRC3 ,P4 I/O Pin[3] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " ISRC2 ,P4 I/O Pin[2] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " ISRC1 ,P4 I/O Pin[1] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " ISRC0 ,P4 I/O Pin[0] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
base ad:0x50004280
|
|
width 13.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 " P40_DOUT,P4.0 Bit Output Control"
|
|
bitfld.long 0x00 0. " P40_DOUT ,P4 I/O Pin 0 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P41_DOUT,P4.1 Bit Output Control"
|
|
bitfld.long 0x04 0. " P41_DOUT ,P4 I/O Pin 1 Bit Output Control" "Low,High"
|
|
group.long 0x08++0x7
|
|
line.long 0x00 " P42_DOUT,P4.2 Bit Output Control"
|
|
bitfld.long 0x00 0. " P42_DOUT ,P4 I/O Pin 2 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P43_DOUT,P4.3 Bit Output Control"
|
|
bitfld.long 0x04 0. " P43_DOUT ,P4 I/O Pin 3 Bit Output Control" "Low,High"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 " P44_DOUT,P4.4 Bit Output Control"
|
|
bitfld.long 0x00 0. " P44_DOUT ,P4 I/O Pin 4 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P45_DOUT,P4.5 Bit Output Control"
|
|
bitfld.long 0x04 0. " P45_DOUT ,P4 I/O Pin 5 Bit Output Control" "Low,High"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 " P46_DOUT,P4.6 Bit Output Control"
|
|
bitfld.long 0x00 0. " P46_DOUT ,P4 I/O Pin 6 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P47_DOUT,P4.7 Bit Output Control"
|
|
bitfld.long 0x04 0. " P47_DOUT ,P4 I/O Pin 7 Bit Output Control" "Low,High"
|
|
width 0xB
|
|
elif (cpuis("M05?ZAN")||cpuis("M0516ZAN"))
|
|
width 13.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 " P4_PMD,Port 4 Pin I/O Mode Control"
|
|
bitfld.long 0x00 14.--15. " PMD7 ,P4 I/O Pin[7] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
bitfld.long 0x00 12.--13. " PMD6 ,P4 I/O Pin[6] Mode Control" "Input,Output,Open-drain,Input/output"
|
|
line.long 0x04 " P4_OFFD,Port 4 Pin OFF Digital Enable"
|
|
bitfld.long 0x04 23. " OFFD7 ,P4 I/O Pin[7] OFF digital input path Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 22. " OFFD6 ,P4 I/O Pin[6] OFF digital input path Enable" "Enabled,Disabled"
|
|
line.long 0x08 " P4_DOUT,Port 4 Data Output Value"
|
|
bitfld.long 0x08 7. " DOUT7 ,P4 I/O Pin[7] Output Value" "Low,High"
|
|
bitfld.long 0x08 6. " DOUT6 ,P4 I/O Pin[6] Output Value" "Low,High"
|
|
line.long 0x0C " P4_DMASK,Port 4 Data Output Write Mask"
|
|
bitfld.long 0x0C 7. " DMASK7 ,P4 I/O Pin[7] Data Output Write Mask" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " DMASK6 ,P4 I/O Pin[6] Data Output Write Mask" "Not masked,Masked"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 " P4_PIN,Port 4 Pin Value"
|
|
bitfld.long 0x00 7. " PIN7 ,P4 I/O Pin[7] Value" "Low,High"
|
|
bitfld.long 0x00 6. " PIN6 ,P4 I/O Pin[6] Value" "Low,High"
|
|
group.long 0x14++0xF
|
|
line.long 0x00 " P4_DBEN,Port 4 De-bounce Enable"
|
|
bitfld.long 0x00 7. " DBEN7 ,P4 I/O Pin[7] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " DBEN6 ,P4 I/O Pin[6] Input Signal De-bounce Enable" "Enabled,Disabled"
|
|
line.long 0x04 " P4_IMD,Port 4 Interrupt Mode Control"
|
|
bitfld.long 0x04 7. " IMD7 ,P4 I/O Pin[7] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
bitfld.long 0x04 6. " IMD6 ,P4 I/O Pin[6] Edge/Level Detection Interrupt Control" "Edge,Level"
|
|
line.long 0x08 " P4_IEN,Port 4 Interrupt Enable"
|
|
bitfld.long 0x08 23. " IR_EN7 ,P4 I/O Pin[7] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " IR_EN6 ,P4 I/O Pin[6] Interrupt Enable by Input Rising Edge/Input Level High" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " IF_EN7 ,P4 I/O Pin[7] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " IF_EN6 ,P4 I/O Pin[6] Interrupt Enable by Input Falling Edge or Input Level Low" "Disabled,Enabled"
|
|
line.long 0x0C " P4_ISRC,Port 4 Interrupt Source Flag"
|
|
bitfld.long 0x0C 7. " ISRC7 ,P4 I/O Pin[7] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 6. " ISRC6 ,P4 I/O Pin[6] Interrupt Trigger Source Indicator" "No interrupt,Interrupt"
|
|
base ad:0x50004280
|
|
width 13.
|
|
group.long 0x18++0x7
|
|
line.long 0x00 " P46_DOUT,P4.6 Bit Output Control"
|
|
bitfld.long 0x00 0. " P46_DOUT ,P4 I/O Pin 6 Bit Output Control" "Low,High"
|
|
line.long 0x04 " P47_DOUT,P4.7 Bit Output Control"
|
|
bitfld.long 0x04 0. " P47_DOUT ,P4 I/O Pin 7 Bit Output Control" "Low,High"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (I2C Serial Interface Controller)"
|
|
base ad:0x40020000
|
|
width 11.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "I2CON,I2C Control Register"
|
|
bitfld.long 0x00 7. " EI ,I2C interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ENS1 ,I2C Controller Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STA ,I2C START Control Bit" "Not started,Started"
|
|
bitfld.long 0x00 4. " STO ,I2C STOP Control Bit" "Not stopped,Stopped"
|
|
textline " "
|
|
eventfld.long 0x00 3. " SI ,I2C Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " AA ,Assert Acknowledge Control Bit" "Not acknowledged,Acknowledged"
|
|
line.long 0x04 "I2CADDR0,I2C Slave Address Register 0"
|
|
hexmask.long.byte 0x04 1.--7. 0x2 " I2CADDR0 ,I2C Address Register 0"
|
|
bitfld.long 0x04 0. " GC ,General Call Function" "Disabled,Enabled"
|
|
line.long 0x08 "I2CDAT,I2C DATA Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " I2CDAT ,I2C data register"
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x00 "I2CSTATUS,I2C Status Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " I2CSTATUS ,I2C status register"
|
|
group.long 0x10++0x23
|
|
line.long 0x00 "I2CLK,I2C Clock Divided Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " I2CLK ,I2C clock divided register"
|
|
line.long 0x04 "I2CTOC,I2C Time Out Control Register"
|
|
bitfld.long 0x04 2. " ENTI ,Time-out counter" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DIV4 ,Time-Out counter input clock is divided by 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TIF ,Time-Out Flag" "Not occurred,Occurred"
|
|
line.long 0x08 "I2CADDR1,I2C Slave Address Register 1"
|
|
hexmask.long.byte 0x08 1.--7. 0x2 " I2CADDR1 ,I2C Address Register 1"
|
|
bitfld.long 0x08 0. " GC ,General Call Function" "Disabled,Enabled"
|
|
line.long 0x0C "I2CADDR2,I2C Slave Address Register 2"
|
|
hexmask.long.byte 0x0C 1.--7. 0x2 " I2CADDR2 ,I2C Address Register 2"
|
|
bitfld.long 0x0C 0. " GC ,General Call Function" "Disabled,Enabled"
|
|
line.long 0x10 "I2CADDR3,I2C Slave Address Register 3"
|
|
hexmask.long.byte 0x10 1.--7. 0x2 " I2CADDR3 ,I2C Address Register 3"
|
|
bitfld.long 0x10 0. " GC ,General Call Function" "Disabled,Enabled"
|
|
line.long 0x14 "I2CADM0,I2C Slave Address Mask Register 0"
|
|
bitfld.long 0x14 7. " I2CADM0 ,Adress mask bit 7" "0,1"
|
|
bitfld.long 0x14 6. ",Adress mask bit 6" "0,1"
|
|
bitfld.long 0x14 5. ",Adress mask bit 5" "0,1"
|
|
bitfld.long 0x14 4. ",Adress mask bit 4" "0,1"
|
|
bitfld.long 0x14 3. ",Adress mask bit 3" "0,1"
|
|
bitfld.long 0x14 2. ",Adress mask bit 2" "0,1"
|
|
bitfld.long 0x14 1. ",Adress mask bit 1" "0,1"
|
|
line.long 0x18 "I2CADM1,I2C Slave Address Mask Register 1"
|
|
bitfld.long 0x18 7. " I2CADM1 ,Adress mask bit 7" "0,1"
|
|
bitfld.long 0x18 6. ",Adress mask bit 6" "0,1"
|
|
bitfld.long 0x18 5. ",Adress mask bit 5" "0,1"
|
|
bitfld.long 0x18 4. ",Adress mask bit 4" "0,1"
|
|
bitfld.long 0x18 3. ",Adress mask bit 3" "0,1"
|
|
bitfld.long 0x18 2. ",Adress mask bit 2" "0,1"
|
|
bitfld.long 0x18 1. ",Adress mask bit 1" "0,1"
|
|
line.long 0x1C "I2CADM2,I2C Slave Address Mask Register 2"
|
|
bitfld.long 0x1C 7. " I2CADM2 ,Adress mask bit 7" "0,1"
|
|
bitfld.long 0x1C 6. ",Adress mask bit 6" "0,1"
|
|
bitfld.long 0x1C 5. ",Adress mask bit 5" "0,1"
|
|
bitfld.long 0x1C 4. ",Adress mask bit 4" "0,1"
|
|
bitfld.long 0x1C 3. ",Adress mask bit 3" "0,1"
|
|
bitfld.long 0x1C 2. ",Adress mask bit 2" "0,1"
|
|
bitfld.long 0x1C 1. ",Adress mask bit 1" "0,1"
|
|
line.long 0x20 "I2CADM3,I2C Slave Address Mask Register 3"
|
|
bitfld.long 0x20 7. " I2CADM3 ,Adress mask bit 7" "0,1"
|
|
bitfld.long 0x20 6. ",Adress mask bit 6" "0,1"
|
|
bitfld.long 0x20 5. ",Adress mask bit 5" "0,1"
|
|
bitfld.long 0x20 4. ",Adress mask bit 4" "0,1"
|
|
bitfld.long 0x20 3. ",Adress mask bit 3" "0,1"
|
|
bitfld.long 0x20 2. ",Adress mask bit 2" "0,1"
|
|
bitfld.long 0x20 1. ",Adress mask bit 1" "0,1"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "PWM (PWM Generator and Capture Timer)"
|
|
tree "PWM A"
|
|
base ad:0x40040000
|
|
width 10.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "PPR,PWM Group A Prescaler Register "
|
|
hexmask.long.byte 0x00 24.--31. 1. " DZI23 ,Dead Zone Interval for pair of CH2 and CH3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DZI01 ,Dead Zone Interval for pair of CH0 and CH1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CP23 ,Clock Prescaler 2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CP01 ,Clock Prescaler 0"
|
|
line.long 0x04 "CSR,PWM Group A Clock Select Register "
|
|
bitfld.long 0x04 12.--14. " CSR3 ,PWM Timer 3 Clock Source (input clock divisor)" "2,4,8,16,1,?..."
|
|
bitfld.long 0x04 8.--10. " CSR2 ,PWM Timer 2 Clock Source (input clock divisor)" "2,4,8,16,1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " CSR1 ,PWM Timer 1 Clock Source (input clock divisor)" "2,4,8,16,1,?..."
|
|
bitfld.long 0x04 0.--2. " CSR0 ,PWM Timer 0 Clock Source (input clock divisor)" "2,4,8,16,1,?..."
|
|
line.long 0x08 "PCR,PWM Group A Control Register"
|
|
bitfld.long 0x08 27. " CH3MOD ,PWM-Timer 3 Auto-reload/One-Shot Mode" "One-Shot,Auto-reload"
|
|
bitfld.long 0x08 26. " CH3INV ,PWM-Timer 3 Output Inverter Enable " "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " CH3EN ,PWM-Timer 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CH2MOD ,PWM-Timer 2 Auto-reload/One-Shot Mode" "One-Shot,Auto-reload"
|
|
bitfld.long 0x08 18. " CH2INV ,PWM-Timer 2 Output Inverter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " CH2EN ,PWM-Timer 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " CH1MOD ,PWM-Timer 1 Auto-reload/One-Shot Mode" "One-Shot,Auto-reload"
|
|
bitfld.long 0x08 10. " CH1INV ,PWM-Timer 1 Output Inverter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " CH1EN ,PWM-Timer 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DZEN23 ,Dead-Zone 2 Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " DZEN01 ,Dead-Zone 0 Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " CH0MOD ,PWM-Timer 0 Auto-reload/One-Shot Mode" "One-Shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x08 2. " CH0INV ,PWM-Timer 0 Output Inverter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CH0EN ,PWM-Timer 0 Enable" "Disabled,Enabled"
|
|
group.long 0xC++0x7
|
|
line.long 0x00 "CNR0,PWM Group A Counter Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNR0 ,PWM Timer Loaded Value 0"
|
|
line.long 0x04 "CMR0,PWM Group A Comparator Register 0"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMR0 ,PWM Comparator Register 0"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "PDR0,PWM Group A Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDR0 ,PWM Data Register 0"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "CNR1,PWM Group A Counter Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNR1 ,PWM Timer Loaded Value 1"
|
|
line.long 0x04 "CMR1,PWM Group A Comparator Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMR1 ,PWM Comparator Register 1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "PDR1,PWM Group A Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDR1 ,PWM Data Register 1"
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "CNR2,PWM Group A Counter Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNR2 ,PWM Timer Loaded Value 2"
|
|
line.long 0x04 "CMR2,PWM Group A Comparator Register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMR2 ,PWM Comparator Register 2"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "PDR2,PWM Group A Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDR2 ,PWM Data Register 2"
|
|
group.long 0x30++0x7
|
|
line.long 0x00 "CNR3,PWM Group A Counter Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNR3 ,PWM Timer Loaded Value 3"
|
|
line.long 0x04 "CMR3,PWM Group A Comparator Register 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMR3 ,PWM Comparator Register 3"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "PDR3,PWM Group A Data Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDR3 ,PWM Data Register 3"
|
|
sif (cpuis("NUC1?????CN")||cpuis("NUC1?????BN"))
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "PBCR,PWM Group A backward compatible Register"
|
|
bitfld.long 0x00 0. " BCA ,PWM Backward Compatible Register" "Write 0 to clear,Write 1 to clear"
|
|
endif
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "PIER,PWM Group A Interrupt Enable Register"
|
|
bitfld.long 0x00 3. " PWMIE3 ,PWM channel 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWMIE2 ,PWM channel 2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PWMIE1 ,PWM channel 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PWMIE0 ,PWM channel 0 Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PIIR,PWM Group A Interrupt Indication Register"
|
|
eventfld.long 0x04 3. " PWMIF3 ,PWM channel 3 Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " PWMIF2 ,PWM channel 2 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 1. " PWMIF1 ,PWM channel 1 Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " PWMIF0 ,PWM channel 0 Interrupt Status" "No interrupt,Interrupt"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "CCR0,PWM Group A Capture Control Register 0"
|
|
sif (cpuis("M05*"))
|
|
eventfld.long 0x00 23. " CFLRI1 ,CFLR1 Latched Indicator Bit" "Low,High"
|
|
eventfld.long 0x00 22. " CRLRI1 ,CRLR1 Latched Indicator Bit" "Low,High"
|
|
else
|
|
bitfld.long 0x00 23. " CFLRI1 ,CFLR1 Latched Indicator Bit" "Low,High"
|
|
bitfld.long 0x00 22. " CRLRI1 ,CRLR1 Latched Indicator Bit" "Low,High"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x00 20. " CAPIF1 ,Channel 1 Capture Interrupt Indication Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " CAPCH1EN ,Channel 1 Capture Function Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CFL_IE1 ,Channel 1 Falling Latch Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CRL_IE1 ,Channel 1 Rising Latch Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INV1 ,Channel 1 Inverter Enable" "Disabled,Enabled"
|
|
sif (cpuis("M05*"))
|
|
eventfld.long 0x00 7. " CFLRI0 ,CFLR0 Latched Indicator Bit" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 6. " CRLRI0 ,CRLR0 Latched Indicator Bit" "Low,High"
|
|
else
|
|
bitfld.long 0x00 7. " CFLRI0 ,CFLR0 Latched Indicator Bit" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CRLRI0 ,CRLR0 Latched Indicator Bit" "Low,High"
|
|
endif
|
|
eventfld.long 0x00 4. " CAPIF0 ,Channel 0 Capture Interrupt Indication Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCH0EN ,Channel 0 Capture Function Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CFL_IE0 ,Channel 0 Falling Latch Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CRL_IE0 ,Channel 0 Rising Latch Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV0 ,Channel 0 Inverter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CCR2,PWM Group A Capture Control Register 2"
|
|
sif (cpuis("M05*"))
|
|
eventfld.long 0x04 23. " CFLRI3 ,CFLR3 Latched Indicator Bit" "Low,High"
|
|
eventfld.long 0x04 22. " CRLRI3 ,CRLR3 Latched Indicator Bit" "Low,High"
|
|
else
|
|
bitfld.long 0x04 23. " CFLRI3 ,CFLR3 Latched Indicator Bit" "Low,High"
|
|
bitfld.long 0x04 22. " CRLRI3 ,CRLR3 Latched Indicator Bit" "Low,High"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x04 20. " CAPIF3 ,Channel 3 Capture Interrupt Indication Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 19. " CAPCH3EN ,Channel 3 Capture Function Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " CFL_IE3 ,Channel 3 Falling Latch Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CRL_IE3 ,Channel 3 Rising Latch Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " INV3 ,Channel 3 Inverter Enable" "Disabled,Enabled"
|
|
sif (cpuis("M05*"))
|
|
eventfld.long 0x04 7. " CFLRI2 ,CFLR2 Latched Indicator Bit" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x04 6. " CRLRI2 ,CRLR2 Latched Indicator Bit" "Low,High"
|
|
else
|
|
bitfld.long 0x04 7. " CFLRI2 ,CFLR2 Latched Indicator Bit" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 6. " CRLRI2 ,CRLR2 Latched Indicator Bit" "Low,High"
|
|
endif
|
|
eventfld.long 0x04 4. " CAPIF2 ,Channel 2 Capture Interrupt Indication Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CAPCH2EN ,Channel 2 Capture Function Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " CFL_IE2 ,Channel 2 Falling Latch Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CRL_IE2 ,Channel 2 Rising Latch Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INV2 ,Channel 2 Inverter Enable" "Disabled,Enabled"
|
|
rgroup.long 0x58++0x1F
|
|
line.long 0x00 "CRLR0,PWM Group A Capture Rising Latch Register (Channel 0)"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRLR0 ,Capture Rising Latch Register"
|
|
line.long 0x04 "CFLR0,PWM Group A Capture Falling Latch Register (Channel 0)"
|
|
hexmask.long.word 0x04 0.--15. 1. " CFLR0 ,Capture Falling Latch Register"
|
|
line.long 0x08 "CRLR1,PWM Group A Capture Rising Latch Register (Channel 1)"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRLR1 ,Capture Rising Latch Register"
|
|
line.long 0x0C "CFLR1,PWM Group A Capture Falling Latch Register (Channel 1)"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CFLR1 ,Capture Falling Latch Register"
|
|
line.long 0x10 "CRLR2,PWM Group A Capture Rising Latch Register (Channel 2)"
|
|
hexmask.long.word 0x10 0.--15. 1. " CRLR2 ,Capture Rising Latch Register"
|
|
line.long 0x14 "CFLR2,PWM Group A Capture Falling Latch Register (Channel 2)"
|
|
hexmask.long.word 0x14 0.--15. 1. " CFLR2 ,Capture Falling Latch Register"
|
|
line.long 0x18 "CRLR3,PWM Group A Capture Rising Latch Register (Channel 3)"
|
|
hexmask.long.word 0x18 0.--15. 1. " CRLR3 ,Capture Rising Latch Register"
|
|
line.long 0x1C "CFLR3,PWM Group A Capture Falling Latch Register (Channel 3)"
|
|
hexmask.long.word 0x1C 0.--15. 1. " CFLR3 ,Capture Falling Latch Register"
|
|
group.long 0x78++0x7
|
|
line.long 0x00 "CAPENR,PWM Group A Capture Input 0-3 Enable Register"
|
|
bitfld.long 0x00 3. " CAPENR3 ,Channel 3 capture input enable register" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAPENR2 ,Channel 2 capture input enable register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPENR1 ,Channel 1 capture input enable register" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAPENR0 ,Channel 0 capture input enable register" "Disabled,Enabled"
|
|
line.long 0x04 "POE,PWM Group A Output Enable for channel 0-3"
|
|
bitfld.long 0x04 3. " PWM3 ,Channel 3 ouput enable register" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PWM2 ,Channel 2 ouput enable register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PWM1 ,Channel 1 ouput enable register" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PWM0 ,Channel 0 ouput enable register" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "PWM B"
|
|
base ad:0x40140000
|
|
width 10.
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "PPR,PWM Group B Prescaler Register "
|
|
hexmask.long.byte 0x00 24.--31. 1. " DZI67 ,Dead Zone Interval for pair of CH6 and CH7"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DZI45 ,Dead Zone Interval for pair of CH4 and CH5"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CP67 ,Clock Prescaler 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CP45 ,Clock Prescaler 0"
|
|
endif
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "CSR,PWM Group B Clock Select Register "
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x00 12.--14. " CSR7 ,PWM Timer 7 Clock Source (input clock divisor)" "2,4,8,16,1,?..."
|
|
bitfld.long 0x00 8.--10. " CSR6 ,PWM Timer 6 Clock Source (input clock divisor)" "2,4,8,16,1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CSR5 ,PWM Timer 5 Clock Source (input clock divisor)" "2,4,8,16,1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--2. " CSR4 ,PWM Timer 4 Clock Source (input clock divisor)" "2,4,8,16,1,?..."
|
|
line.long 0x04 "PCR,PWM Group B Control Register"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x04 27. " CH7MOD ,PWM-Timer 7 Auto-reload/One-Shot Mode" "One-Shot,Auto-reload"
|
|
bitfld.long 0x04 26. " CH7INV ,PWM-Timer 7 Output Inverter Enable " "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " CH7EN ,PWM-Timer 7 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CH6MOD ,PWM-Timer 6 Auto-reload/One-Shot Mode" "One-Shot,Auto-reload"
|
|
bitfld.long 0x04 18. " CH6INV ,PWM-Timer 6 Output Inverter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CH6EN ,PWM-Timer 6 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CH5MOD ,PWM-Timer 5 Auto-reload/One-Shot Mode" "One-Shot,Auto-reload"
|
|
bitfld.long 0x04 10. " CH5INV ,PWM-Timer 5 Output Inverter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " CH5EN ,PWM-Timer 5 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DZEN67 ,Dead-Zone 6 Generator Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " DZEN45 ,Dead-Zone 4 Generator Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 3. " CH4MOD ,PWM-Timer 4 Auto-reload/One-Shot Mode" "One-Shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x04 2. " CH4INV ,PWM-Timer 4 Output Inverter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CH4EN ,PWM-Timer 4 Enable" "Disabled,Enabled"
|
|
group.long 0xC++0x7
|
|
line.long 0x00 "CNR0,PWM Group B Counter Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNR0 ,PWM Timer Loaded Value 0"
|
|
line.long 0x04 "CMR0,PWM Group B Comparator Register 0"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMR0 ,PWM Comparator Register 0"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "PDR0,PWM Group B Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDR0 ,PWM Data Register 0"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "CNR1,PWM Group B Counter Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNR1 ,PWM Timer Loaded Value 1"
|
|
line.long 0x04 "CMR1,PWM Group B Comparator Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMR1 ,PWM Comparator Register 1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "PDR1,PWM Group B Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDR1 ,PWM Data Register 1"
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "CNR2,PWM Group B Counter Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNR2 ,PWM Timer Loaded Value 2"
|
|
line.long 0x04 "CMR2,PWM Group B Comparator Register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMR2 ,PWM Comparator Register 2"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x00 "PDR2,PWM Group B Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDR2 ,PWM Data Register 2"
|
|
group.long 0x30++0x7
|
|
line.long 0x00 "CNR3,PWM Group B Counter Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNR3 ,PWM Timer Loaded Value 3"
|
|
line.long 0x04 "CMR3,PWM Group B Comparator Register 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " CMR3 ,PWM Comparator Register 3"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "PDR3,PWM Group B Data Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDR3 ,PWM Data Register 3"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "PIER,PWM Group B Interrupt Enable Register"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x00 3. " PWMIE7 ,PWM channel 7 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PWMIE6 ,PWM channel 6 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PWMIE5 ,PWM channel 5 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " PWMIE4 ,PWM channel 4 Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "PIIR,PWM Group B Interrupt Indication Register"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
eventfld.long 0x04 3. " PWMIF7 ,PWM channel 7 Interrupt Status" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " PWMIF6 ,PWM channel 6 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 1. " PWMIF5 ,PWM channel 5 Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x04 0. " PWMIF4 ,PWM channel 4 Interrupt Status" "No interrupt,Interrupt"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "CCR0,PWM Group B Capture Control Register 0"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
eventfld.long 0x00 23. " CFLRI5 ,CFLR5 Latched Indicator Bit" "Low,High"
|
|
eventfld.long 0x00 22. " CRLRI5 ,CRLR5 Latched Indicator Bit" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 20. " CAPIF5 ,Channel 5 Capture Interrupt Indication Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " CAPCH5EN ,Channel 5 Capture Function Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CFL_IE5 ,Channel 5 Falling Latch Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CRL_IE5 ,Channel 5 Rising Latch Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INV5 ,Channel 5 Inverter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 7. " CFLRI4 ,CFLR4 Latched Indicator Bit" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 6. " CRLRI4 ,CRLR4 Latched Indicator Bit" "Low,High"
|
|
eventfld.long 0x00 4. " CAPIF4 ,Channel 4 Capture Interrupt Indication Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCH4EN ,Channel 4 Capture Function Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CFL_IE4 ,Channel 4 Falling Latch Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CRL_IE4 ,Channel 4 Rising Latch Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV4 ,Channel 4 Inverter Enable" "Disabled,Enabled"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "CCR2,PWM Group B Capture Control Register 2"
|
|
eventfld.long 0x00 23. " CFLRI7 ,CFLR7 Latched Indicator Bit" "Low,High"
|
|
eventfld.long 0x00 22. " CRLRI7 ,CRLR7 Latched Indicator Bit" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 20. " CAPIF7 ,Channel 7 Capture Interrupt Indication Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " CAPCH7EN ,Channel 7 Capture Function Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CFL_IE7 ,Channel 7 Falling Latch Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CRL_IE7 ,Channel 7 Rising Latch Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " INV7 ,Channel 7 Inverter Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 7. " CFLRI6 ,CFLR6 Latched Indicator Bit" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x00 6. " CRLRI6 ,CRLR6 Latched Indicator Bit" "Low,High"
|
|
eventfld.long 0x00 4. " CAPIF6 ,Channel 6 Capture Interrupt Indication Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CAPCH6EN ,Channel 6 Capture Function Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CFL_IE6 ,Channel 6 Falling Latch Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CRL_IE6 ,Channel 6 Rising Latch Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INV6 ,Channel 6 Inverter Enable" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x58++0x7
|
|
line.long 0x00 "CRLR4,PWM Group B Capture Rising Latch Register (Channel 4)"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRLR4 ,Capture Rising Latch Register"
|
|
line.long 0x04 "CFLR4,PWM Group B Capture Falling Latch Register (Channel 4)"
|
|
hexmask.long.word 0x04 0.--15. 1. " CFLR4 ,Capture Falling Latch Register"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
rgroup.long 0x60++0x7
|
|
line.long 0x00 "CRLR5,PWM Group B Capture Rising Latch Register (Channel 5)"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRLR5 ,Capture Rising Latch Register"
|
|
line.long 0x04 "CFLR5,PWM Group B Capture Falling Latch Register (Channel 5)"
|
|
hexmask.long.word 0x04 0.--15. 1. " CFLR5 ,Capture Falling Latch Register"
|
|
endif
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
rgroup.long 0x68++0xF
|
|
line.long 0x00 "CRLR6,PWM Group B Capture Rising Latch Register (Channel 6)"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRLR6 ,Capture Rising Latch Register"
|
|
line.long 0x04 "CFLR6,PWM Group B Capture Falling Latch Register (Channel 6)"
|
|
hexmask.long.word 0x04 0.--15. 1. " CFLR6 ,Capture Falling Latch Register"
|
|
line.long 0x08 "CRLR7,PWM Group B Capture Rising Latch Register (Channel 7)"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRLR7 ,Capture Rising Latch Register"
|
|
line.long 0x0C "CFLR7,PWM Group B Capture Falling Latch Register (Channel 7)"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CFLR7 ,Capture Falling Latch Register"
|
|
endif
|
|
group.long 0x78++0x7
|
|
line.long 0x00 "CAPENR,PWM Group B Capture Input 4-7 Enable Register"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x00 3. " CAPENR7 ,Channel 7 capture input enable register" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CAPENR6 ,Channel 6 capture input enable register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CAPENR5 ,Channel 5 capture input enable register" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " CAPENR4 ,Channel 4 capture input enable register" "Disabled,Enabled"
|
|
line.long 0x04 "POE,PWM Group B Output Enable for channel 4-7"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
bitfld.long 0x04 3. " PWM7 ,Channel 7 ouput enable register" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PWM6 ,Channel 6 ouput enable register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PWM5 ,Channel 5 ouput enable register" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " PWM4 ,Channel 4 ouput enable register" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI 0"
|
|
base ad:0x40030000
|
|
width 13.
|
|
if (((d.l(ad:0x40030000))&0x40000)==0x0)
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "SPI_CNTRL,Control and Status Register"
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
bitfld.long 0x00 27. " TX_FULL ,Transmitted FIFO_FULL STATUS" "Not full,Full"
|
|
bitfld.long 0x00 26. " TX_EMPTY ,Transmitted FIFO_EMPTY STATUS" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RX_FULL ,Received FIFO_FULL STATUS" "Not full,Full"
|
|
bitfld.long 0x00 24. " RX_EMPTY ,Received FIFO_EMPTY STATUS" "Not empty,Empty"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " VARCLK_EN ,Variable Clock" "VARCLK/DIVIDER/DIVIDER2,DIVIDER"
|
|
textline " "
|
|
sif (!cpuis("M05*"))
|
|
bitfld.long 0x00 22. " TWOB ,Two Bits Transfer Mode Active" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
bitfld.long 0x00 21. " FIFO ,FIFO Mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19.--20. " REORDER ,Reorder/byte suspend function" "Disabled/disabled,Enabled/enabled,Enabled/disabled,Disabled/enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SLAVE ,Slave Mode Indication" "Master,Slave"
|
|
bitfld.long 0x00 17. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " IF ,Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12.--15. " SP_CYCLE ,Suspend Interval" "2*SPICLK,3*SPICLK,4*SPICLK,5*SPICLK,6*SPICLK,7*SPICLK,8*SPICLK,9*SPICLK,10*SPICLK,11*SPICLK,12*SPICLK,13*SPICLK,14*SPICLK,15*SPICLK,16*SPICLK,17*SPICLK"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLKP ,Idle clock Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " LSB ,LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_NUM ,Transmit/Receive Word Number" "1,2,?..."
|
|
bitfld.long 0x00 3.--7. " TX_BIT_LEN ,Transmit Bit Length" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_NEG ,Transmit At Negative Edge" "Rising-edge,Falling-edge"
|
|
bitfld.long 0x00 1. " RX_NEG ,Receive At Negative Edge" "Rising-edge,Falling-edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GO_BUSY ,Data transfer control" "Stopped,Started"
|
|
line.long 0x04 "SPI_DIVIDER,Clock Divider Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DIVIDER2 ,Clock Divider 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DIVIDER ,Clock Divider Register"
|
|
line.long 0x08 "SPI_SSR,Slave Select Register"
|
|
bitfld.long 0x08 5. " LTRIG_FLAG ,Level Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x08 3. " AUTOSS ,Automatic Slave Select" "SSR,Automatic"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SS_LVL ,Slave Select Active Level" "Low-level/falling-edge,High-level/rising-edge"
|
|
sif (cpuis("M05*"))
|
|
bitfld.long 0x08 0. " SSR ,Slave Select Register" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x08 0.--1. " SSR ,Slave Select Register" "0,1,2,3"
|
|
endif
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SPI_CNTRL,Control and Status Register"
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
bitfld.long 0x00 27. " TX_FULL ,Transmitted FIFO_FULL STATUS" "Not full,Full"
|
|
bitfld.long 0x00 26. " TX_EMPTY ,Transmitted FIFO_EMPTY STATUS" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RX_FULL ,Received FIFO_FULL STATUS" "Not full,Full"
|
|
bitfld.long 0x00 24. " RX_EMPTY ,Received FIFO_EMPTY STATUS" "Not empty,Empty"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("M05*"))
|
|
bitfld.long 0x00 22. " TWOB ,Two Bits Transfer Mode Active" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
bitfld.long 0x00 21. " FIFO ,FIFO Mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19.--20. " REORDER ,Reorder/byte suspend function" "Disabled/disabled,Enabled/enabled,Enabled/disabled,Disabled/enabled"
|
|
bitfld.long 0x00 18. " SLAVE ,Slave Mode Indication" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 16. " IF ,Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLKP ,Idle clock Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " LSB ,LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_NUM ,Transmit/Receive Word Number" "1,2,?..."
|
|
bitfld.long 0x00 3.--7. " TX_BIT_LEN ,Transmit Bit Length" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_NEG ,Transmit At Negative Edge" "Rising-edge,Falling-edge"
|
|
bitfld.long 0x00 1. " RX_NEG ,Receive At Negative Edge" "Rising-edge,Falling-edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GO_BUSY ,Slave ready bit" "Not ready,Ready"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SPI_SSR,Slave Select Register"
|
|
bitfld.long 0x00 5. " LTRIG_FLAG ,Level Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " SS_LTRIG ,Slave Select Level Trigger" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SS_LVL ,Slave Select Active Level" "Low-level/falling-edge,High-level/rising-edge"
|
|
endif
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "SPI_RX0,Data Receive Register 0"
|
|
line.long 0x04 "SPI_RX1,Data Receive Register 1"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x00 "SPI_TX0,Data Transmit Register 0"
|
|
line.long 0x04 "SPI_TX1,Data Transmit Register 1"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "SPI_VARCLK,Variable Clock Pattern Register"
|
|
sif (cpuis("NUC1?0*"))
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "SPI_DMA,SPI DMA Control Register"
|
|
bitfld.long 0x00 1. " RX_DMA_GO ,Receive DMA Start" "Not started,Started"
|
|
bitfld.long 0x00 0. " TX_DMA_GO ,Transmit DMA Start" "Not started,Started"
|
|
endif
|
|
sif (cpuis("NUC1?0???CN"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x00 "SPI_CNTRL2,Control and Status Register 2"
|
|
eventfld.long 0x00 11. " SLV_START_INTSTS ,Slave Start Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " SSTA_INTEN ,Slave Start Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLV_ABORT ,Abort in Slave Mode with No Slave Select (Force interrupt)" "Not aborted,Aborted"
|
|
bitfld.long 0x00 8. " NOSLVSEL ,No Slave Select in Slave Mode" "4-wire bi-direction,3-wire bi-direction"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DIV_ONE ,SPI clock divider control" "SPI_DIVIDER,Enabled"
|
|
line.long 0x04 "SPI_FIFO_CTL,FIFO Control Register"
|
|
eventfld.long 0x04 1. " TX_CLR ,Clear Tx FIFO" "No effect,Clear"
|
|
eventfld.long 0x04 0. " RX_CLR ,Clear Rx FIFO" "No effect,Clear"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI 1"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
base ad:0x40034000
|
|
width 13.
|
|
if (((d.l(ad:0x40034000))&0x40000)==0x0)
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "SPI_CNTRL,Control and Status Register"
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
bitfld.long 0x00 27. " TX_FULL ,Transmitted FIFO_FULL STATUS" "Not full,Full"
|
|
bitfld.long 0x00 26. " TX_EMPTY ,Transmitted FIFO_EMPTY STATUS" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RX_FULL ,Received FIFO_FULL STATUS" "Not full,Full"
|
|
bitfld.long 0x00 24. " RX_EMPTY ,Received FIFO_EMPTY STATUS" "Not empty,Empty"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " VARCLK_EN ,Variable Clock" "VARCLK/DIVIDER/DIVIDER2,DIVIDER"
|
|
textline " "
|
|
sif (!cpuis("M05*"))
|
|
bitfld.long 0x00 22. " TWOB ,Two Bits Transfer Mode Active" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
bitfld.long 0x00 21. " FIFO ,FIFO Mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19.--20. " REORDER ,Reorder/byte suspend function" "Disabled/disabled,Enabled/enabled,Enabled/disabled,Disabled/enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SLAVE ,Slave Mode Indication" "Master,Slave"
|
|
bitfld.long 0x00 17. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 16. " IF ,Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12.--15. " SP_CYCLE ,Suspend Interval" "2*SPICLK,3*SPICLK,4*SPICLK,5*SPICLK,6*SPICLK,7*SPICLK,8*SPICLK,9*SPICLK,10*SPICLK,11*SPICLK,12*SPICLK,13*SPICLK,14*SPICLK,15*SPICLK,16*SPICLK,17*SPICLK"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLKP ,Idle clock Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " LSB ,LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_NUM ,Transmit/Receive Word Number" "1,2,?..."
|
|
bitfld.long 0x00 3.--7. " TX_BIT_LEN ,Transmit Bit Length" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_NEG ,Transmit At Negative Edge" "Rising-edge,Falling-edge"
|
|
bitfld.long 0x00 1. " RX_NEG ,Receive At Negative Edge" "Rising-edge,Falling-edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GO_BUSY ,Data transfer control" "Stopped,Started"
|
|
line.long 0x04 "SPI_DIVIDER,Clock Divider Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " DIVIDER2 ,Clock Divider 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DIVIDER ,Clock Divider Register"
|
|
line.long 0x08 "SPI_SSR,Slave Select Register"
|
|
bitfld.long 0x08 5. " LTRIG_FLAG ,Level Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x08 3. " AUTOSS ,Automatic Slave Select" "SSR,Automatic"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SS_LVL ,Slave Select Active Level" "Low-level/falling-edge,High-level/rising-edge"
|
|
sif (cpuis("M05*"))
|
|
bitfld.long 0x08 0. " SSR ,Slave Select Register" "Inactive,Active"
|
|
else
|
|
bitfld.long 0x08 0.--1. " SSR ,Slave Select Register" "0,1,2,3"
|
|
endif
|
|
else
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SPI_CNTRL,Control and Status Register"
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
bitfld.long 0x00 27. " TX_FULL ,Transmitted FIFO_FULL STATUS" "Not full,Full"
|
|
bitfld.long 0x00 26. " TX_EMPTY ,Transmitted FIFO_EMPTY STATUS" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 25. " RX_FULL ,Received FIFO_FULL STATUS" "Not full,Full"
|
|
bitfld.long 0x00 24. " RX_EMPTY ,Received FIFO_EMPTY STATUS" "Not empty,Empty"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("M05*"))
|
|
bitfld.long 0x00 22. " TWOB ,Two Bits Transfer Mode Active" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
bitfld.long 0x00 21. " FIFO ,FIFO Mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19.--20. " REORDER ,Reorder/byte suspend function" "Disabled/disabled,Enabled/enabled,Enabled/disabled,Disabled/enabled"
|
|
bitfld.long 0x00 18. " SLAVE ,Slave Mode Indication" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 16. " IF ,Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLKP ,Idle clock Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " LSB ,LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TX_NUM ,Transmit/Receive Word Number" "1,2,?..."
|
|
bitfld.long 0x00 3.--7. " TX_BIT_LEN ,Transmit Bit Length" "32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX_NEG ,Transmit At Negative Edge" "Rising-edge,Falling-edge"
|
|
bitfld.long 0x00 1. " RX_NEG ,Receive At Negative Edge" "Rising-edge,Falling-edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GO_BUSY ,Slave ready bit" "Not ready,Ready"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "SPI_SSR,Slave Select Register"
|
|
bitfld.long 0x00 5. " LTRIG_FLAG ,Level Trigger Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " SS_LTRIG ,Slave Select Level Trigger" "Edge,Level"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SS_LVL ,Slave Select Active Level" "Low-level/falling-edge,High-level/rising-edge"
|
|
endif
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "SPI_RX0,Data Receive Register 0"
|
|
line.long 0x04 "SPI_RX1,Data Receive Register 1"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x00 "SPI_TX0,Data Transmit Register 0"
|
|
line.long 0x04 "SPI_TX1,Data Transmit Register 1"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "SPI_VARCLK,Variable Clock Pattern Register"
|
|
sif (cpuis("NUC1?0*"))
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "SPI_DMA,SPI DMA Control Register"
|
|
bitfld.long 0x00 1. " RX_DMA_GO ,Receive DMA Start" "Not started,Started"
|
|
bitfld.long 0x00 0. " TX_DMA_GO ,Transmit DMA Start" "Not started,Started"
|
|
endif
|
|
sif (cpuis("NUC1?0???CN"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x00 "SPI_CNTRL2,Control and Status Register 2"
|
|
eventfld.long 0x00 11. " SLV_START_INTSTS ,Slave Start Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " SSTA_INTEN ,Slave Start Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SLV_ABORT ,Abort in Slave Mode with No Slave Select (Force interrupt)" "Not aborted,Aborted"
|
|
bitfld.long 0x00 8. " NOSLVSEL ,No Slave Select in Slave Mode" "4-wire bi-direction,3-wire bi-direction"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DIV_ONE ,SPI clock divider control" "SPI_DIVIDER,Enabled"
|
|
line.long 0x04 "SPI_FIFO_CTL,FIFO Control Register"
|
|
eventfld.long 0x04 1. " TX_CLR ,Clear Tx FIFO" "No effect,Clear"
|
|
eventfld.long 0x04 0. " RX_CLR ,Clear Rx FIFO" "No effect,Clear"
|
|
endif
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree.open "TMR (Timer Controller)"
|
|
tree "TIMER 0"
|
|
base ad:0x40010000
|
|
width 9.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "TCSR0,Timer 0 Control and Status Register"
|
|
sif (cpuis("NUC1?0???CN"))
|
|
bitfld.long 0x00 31. " DBGACK_TMR ,ICE debug mode acknowledge Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 30. " CEN ,Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("NUC1?0???CN")||cpuis("NUC1?0???BN"))
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,Toggle,Continuous counting"
|
|
elif (cpuis("M05*"))
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,Toggle,?..."
|
|
else
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 26. " CRST ,Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x00 25. " CACT ,Timer Active Status" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpuis("NUC1?0???CN")||cpuis("NUC1?0???BN"))
|
|
bitfld.long 0x00 24. " CTB ,Counter Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " TDR_EN ,Data Load Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRESCALE ,Pre-scale Counter"
|
|
line.long 0x04 "TCMPR0,Timer 0 Compare Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " TCMP ,Timer Compared Value"
|
|
line.long 0x08 "TISR0,Timer 0 Interrupt Status Register"
|
|
eventfld.long 0x08 0. " TIF ,Timer Interrupt Flag" "No interrupt,Interrupt"
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "TDR0,Timer 0 Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TDR ,Timer Data Register"
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "TCAP0,Timer 0 Capture Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TCAP , Timer Capture Data Register"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "TEXCON0,Timer 0 External Control Register"
|
|
bitfld.long 0x00 7. " TCDB ,Timer Counter pin De-bounce enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TEXDB ,Timer External Capture pin De-bounce enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TEXIEN ,Timer External interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RSTCAP0 ,Timer External Reset Counter/capture mode select" "Capture,Counter reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEXEN ,Timer External Pin Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " TEX_EDGE ,Timer External Pin Edge Detect" "Falling edge,Rising edge,Both edges,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " TX_PHASE ,Timer External Count Phase" "Falling edge,Rising edge"
|
|
line.long 0x04 "TEXISR0,Timer 0 External Interrupt Status Register"
|
|
bitfld.long 0x04 0. " TEXIF ,Timer External Interrupt Flag" "No interrupt,Interrupt"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TIMER 1"
|
|
base ad:0x40010020
|
|
width 9.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "TCSR1,Timer 1 Control and Status Register"
|
|
sif (cpuis("NUC1?0???CN"))
|
|
bitfld.long 0x00 31. " DBGACK_TMR ,ICE debug mode acknowledge Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 30. " CEN ,Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("NUC1?0???CN")||cpuis("NUC1?0???BN"))
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,Toggle,Continuous counting"
|
|
elif (cpuis("M05*"))
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,Toggle,?..."
|
|
else
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 26. " CRST ,Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x00 25. " CACT ,Timer Active Status" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpuis("NUC1?0???CN")||cpuis("NUC1?0???BN"))
|
|
bitfld.long 0x00 24. " CTB ,Counter Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " TDR_EN ,Data Load Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRESCALE ,Pre-scale Counter"
|
|
line.long 0x04 "TCMPR1,Timer 1 Compare Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " TCMP ,Timer Compared Value"
|
|
line.long 0x08 "TISR1,Timer 1 Interrupt Status Register"
|
|
eventfld.long 0x08 0. " TIF ,Timer Interrupt Flag" "No interrupt,Interrupt"
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "TDR1,Timer 1 Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TDR ,Timer Data Register"
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TIMER 2"
|
|
base ad:0x40110000
|
|
width 9.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "TCSR2,Timer 2 Control and Status Register"
|
|
sif (cpuis("NUC1?0???CN"))
|
|
bitfld.long 0x00 31. " DBGACK_TMR ,ICE debug mode acknowledge Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 30. " CEN ,Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("NUC1?0???CN")||cpuis("NUC1?0???BN"))
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,Toggle,Continuous counting"
|
|
elif (cpuis("M05*"))
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,Toggle,?..."
|
|
else
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 26. " CRST ,Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x00 25. " CACT ,Timer Active Status" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpuis("NUC1?0???CN")||cpuis("NUC1?0???BN"))
|
|
bitfld.long 0x00 24. " CTB ,Counter Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " TDR_EN ,Data Load Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRESCALE ,Pre-scale Counter"
|
|
line.long 0x04 "TCMPR2,Timer 2 Compare Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " TCMP ,Timer Compared Value"
|
|
line.long 0x08 "TISR2,Timer 2 Interrupt Status Register"
|
|
eventfld.long 0x08 0. " TIF ,Timer Interrupt Flag" "No interrupt,Interrupt"
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "TDR2,Timer 2 Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TDR ,Timer Data Register"
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "TIMER 3"
|
|
base ad:0x40110020
|
|
width 9.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "TCSR3,Timer 3 Control and Status Register"
|
|
sif (cpuis("NUC1?0???CN"))
|
|
bitfld.long 0x00 31. " DBGACK_TMR ,ICE debug mode acknowledge Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 30. " CEN ,Timer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IE ,Interrupt Enable" "Disabled,Enabled"
|
|
sif (cpuis("NUC1?0???CN")||cpuis("NUC1?0???BN"))
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,Toggle,Continuous counting"
|
|
elif (cpuis("M05*"))
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,Toggle,?..."
|
|
else
|
|
bitfld.long 0x00 27.--28. " MODE ,Timer Operating Mode" "One-shot,Periodic,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 26. " CRST ,Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x00 25. " CACT ,Timer Active Status" "Not activated,Activated"
|
|
textline " "
|
|
sif (cpuis("NUC1?0???CN")||cpuis("NUC1?0???BN"))
|
|
bitfld.long 0x00 24. " CTB ,Counter Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " TDR_EN ,Data Load Enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRESCALE ,Pre-scale Counter"
|
|
line.long 0x04 "TCMPR3,Timer 3 Compare Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " TCMP ,Timer Compared Value"
|
|
line.long 0x08 "TISR3,Timer 3 Interrupt Status Register"
|
|
eventfld.long 0x08 0. " TIF ,Timer Interrupt Flag" "No interrupt,Interrupt"
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "TDR3,Timer 3 Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TDR ,Timer Data Register"
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40004000
|
|
width 10.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "WTCR,Watchdog Timer Control Register"
|
|
sif (cpuis("NUC1?0???CN"))
|
|
bitfld.long 0x00 31. " DBGACK_WDT ,ICE debug mode acknowledge Disable" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8.--10. " WTIS ,Watchdog Timer Interval" "(2^4)*Twdt,(2^6)*Twdt,(2^8)*Twdt,(2^10)*Twdt,(2^12)*Twdt,(2^14)*Twdt,(2^16)*Twdt,(2^18)*Twdt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WTE ,Watchdog Timer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " WTIE ,Watchdog Timer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 5. " WTWKF ,Watchdog Timer Wake-up Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " WTWKE ,Watchdog Timer Wake-up Function Enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 3. " WTIF ,Watchdog Timer Interrupt Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " WTRF ,Watchdog Timer Reset Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WTRE ,Watchdog Timer Reset Enable" "Disabled,Enabled"
|
|
sif (cpuis("M05*"))
|
|
eventfld.long 0x00 0. " WTR ,Clear Watchdog Timer" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x00 0. " WTR ,Clear Watchdog Timer" "No effect,Reset"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.open "UART (UART Interface Controller)"
|
|
tree "UART 0"
|
|
base ad:0x40050000
|
|
width 10.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "UA_RBR,UART0 Receive Buffer Register"
|
|
in
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "UA_THR,UART0 Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " THR ,Transmit Holding Register"
|
|
group.long 0x04++0x2F
|
|
line.long 0x00 "UA_IER,UART0 Interrupt Enable Register"
|
|
bitfld.long 0x00 13. " AUTO_CTS_EN ,CTS Auto Flow Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AUTO_RTS_EN ,RTS Auto Flow Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TIME_OUT_EN ,Time Out Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " WAKE_EN ,UART Wake-up Function Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RTO_IEN ,RX Time Out Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MODEM_IEN ,Modem Status Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RLS_IEN ,Receive Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " THRE_IEN ,Transmit Holding Register Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDA_IEN ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UA_FCR,UART0 FIFO Control Register"
|
|
bitfld.long 0x04 16.--19. " RTS_TRI_LEV ,RTS Trigger Level for Auto-flow Control Use" "1-byte,4-bytes,8-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes"
|
|
bitfld.long 0x04 8. " RX_DIS ,Receiver Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " RFITL ,RX FIFO Interrupt (INT_RDA) Trigger Level" "1-byte,4-bytes,8-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes"
|
|
bitfld.long 0x04 2. " TFR ,TX Field Software Reset " "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFR ,RX Field Software Reset" "No effect,Reset"
|
|
line.long 0x08 "UA_LCR,UART0 Line Control Register"
|
|
bitfld.long 0x08 6. " BCB ,Break Control Bit" "Low,High"
|
|
bitfld.long 0x08 5. " SPE ,Stick Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " EPE ,Even Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " PBE ,Parity Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " NSB ,Number of STOP bit" "One,One and a half"
|
|
bitfld.long 0x08 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
line.long 0x0C "UA_MCR,UART0 Modem Control Register"
|
|
bitfld.long 0x0C 13. " RTS_ST ,RTS Pin State" "Low,High"
|
|
bitfld.long 0x0C 9. " LEV_RTS ,RTS Trigger Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " RTS ,Request-To-Send Signal" "Low,High"
|
|
line.long 0x10 "UA_MSR,UART0 Modem Status Register"
|
|
bitfld.long 0x10 8. " LEV_CTS ,CTS Trigger Level" "Low,High"
|
|
bitfld.long 0x10 4. " CTS_ST ,CTS Pin Status" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 0. " DCTSF ,Detect CTS State Change Flag" "Not detected,Detected"
|
|
line.long 0x14 "UA_FSR,UART0 FIFO Status Register"
|
|
bitfld.long 0x14 28. " TE_FLAG ,Transmitter Empty Flag" "Not empty,Empty"
|
|
bitfld.long 0x14 23. " TX_OVER ,Transmitter FIFO Over" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.long 0x14 22. " TX_EMPTY ,Transmitter FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x14 16.--21. " TX_POINTER ,TX FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x14 15. " RX_OVER ,Receiver FIFO Over" "Not overflowed,Overflowed"
|
|
bitfld.long 0x14 14. " RX_EMPTY ,Receiver FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 8.--13. " RX_POINTER ,RX FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
eventfld.long 0x14 6. " BIF ,Break Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 5. " FEF ,Framing Error Flag" "No error,Error"
|
|
eventfld.long 0x14 4. " PEF ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x14 3. " RS485_ADD_DETF ,RS-485 Address Byte Detection Flag" "Not detected,Detected"
|
|
line.long 0x18 "UA_ISR,UART0 Interrupt Status Register"
|
|
bitfld.long 0x18 12. " TOUT_INT ,Time Out Interrupt Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 11. " MODEM_INT ,MODEM Status Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 10. " RLS_INT ,Receive Line Status Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 9. " THRE_INT ,Transmit Holding Register Empty Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 8. " RDA_INT ,Receive Data Available Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 4. " TOUT_IF ,Time Out Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x18 3. " MODEM_IF ,MODEM Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 2. " RLS_IF ,Receive Line Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 1. " THRE_IF ,Transmit Holding Register Empty Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 0. " RDA_IF ,Receive Data Available Interrupt Flag" "No interrupt,Interrupt"
|
|
line.long 0x1C "UA_TOR,UART0 Time Out Register"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " DLY ,TX Delay time value"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--6. 1. " TOIC ,Time Out Interrupt Comparator"
|
|
line.long 0x20 "UA_BAUD,UART0 Baud Rate Divisor Register"
|
|
bitfld.long 0x20 29. " DIV_X_EN ,Divider X Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 28. " DIV_X_ONE ,Divider X equal 1" "M = X,M = 1"
|
|
textline " "
|
|
bitfld.long 0x20 24.--27. " DIVIDER_X ,Divider X" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x20 0.--15. 1. " BRD ,Baud Rate Divider"
|
|
line.long 0x24 "UA_IRCR,UART0 IrDA Control Register"
|
|
bitfld.long 0x24 6. " INV_RX ,INV_RX" "No inverted,Inverted"
|
|
bitfld.long 0x24 5. " INV_TX ,INV_TX" "No inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x24 1. " TX_SELECT ,IrDA mode" "Receiver,Transmitter"
|
|
line.long 0x28 "UA_ALT_CSR,UART0 Alternate Control/Status Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " ADDR_MATCH ,Address match value register"
|
|
textline " "
|
|
bitfld.long 0x28 15. " RS485_ADD_EN ,RS-485 Address Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 10. " RS485_AUD ,RS-485 Auto Direction Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 9. " RS485_AAD ,RS-485 Auto Address Detection Operation Mode" "Disabled,Enabled"
|
|
bitfld.long 0x28 8. " RS485_NMM ,RS-485 Normal Multi-drop Operation Mode" "Disabled,Enabled"
|
|
line.long 0x2C "UA_FUN_SEL,UART0 Function Select Register"
|
|
bitfld.long 0x2C 0.--1. " FUN_SEL ,Function Select Enable" "UART,Reserved,IrDA,RS-485"
|
|
width 0xB
|
|
tree.end
|
|
tree "UART 1"
|
|
base ad:0x40150000
|
|
width 10.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "UA_RBR,UART1 Receive Buffer Register"
|
|
in
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "UA_THR,UART1 Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " THR ,Transmit Holding Register"
|
|
group.long 0x04++0x2F
|
|
line.long 0x00 "UA_IER,UART1 Interrupt Enable Register"
|
|
bitfld.long 0x00 13. " AUTO_CTS_EN ,CTS Auto Flow Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " AUTO_RTS_EN ,RTS Auto Flow Control Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TIME_OUT_EN ,Time Out Counter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " WAKE_EN ,UART Wake-up Function Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RTO_IEN ,RX Time Out Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MODEM_IEN ,Modem Status Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RLS_IEN ,Receive Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " THRE_IEN ,Transmit Holding Register Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RDA_IEN ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "UA_FCR,UART1 FIFO Control Register"
|
|
bitfld.long 0x04 16.--19. " RTS_TRI_LEV ,RTS Trigger Level for Auto-flow Control Use" "1-byte,4-bytes,8-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes"
|
|
bitfld.long 0x04 8. " RX_DIS ,Receiver Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " RFITL ,RX FIFO Interrupt (INT_RDA) Trigger Level" "1-byte,4-bytes,8-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes,14-bytes"
|
|
bitfld.long 0x04 2. " TFR ,TX Field Software Reset " "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFR ,RX Field Software Reset" "No effect,Reset"
|
|
line.long 0x08 "UA_LCR,UART1 Line Control Register"
|
|
bitfld.long 0x08 6. " BCB ,Break Control Bit" "Low,High"
|
|
bitfld.long 0x08 5. " SPE ,Stick Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " EPE ,Even Parity Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " PBE ,Parity Bit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " NSB ,Number of STOP bit" "One,One and a half"
|
|
bitfld.long 0x08 0.--1. " WLS ,Word Length Select" "5-bit,6-bit,7-bit,8-bit"
|
|
line.long 0x0C "UA_MCR,UART1 Modem Control Register"
|
|
bitfld.long 0x0C 13. " RTS_ST ,RTS Pin State" "Low,High"
|
|
bitfld.long 0x0C 9. " LEV_RTS ,RTS Trigger Level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " RTS ,Request-To-Send Signal" "Low,High"
|
|
line.long 0x10 "UA_MSR,UART1 Modem Status Register"
|
|
bitfld.long 0x10 8. " LEV_CTS ,CTS Trigger Level" "Low,High"
|
|
bitfld.long 0x10 4. " CTS_ST ,CTS Pin Status" "Low,High"
|
|
textline " "
|
|
eventfld.long 0x10 0. " DCTSF ,Detect CTS State Change Flag" "Not detected,Detected"
|
|
line.long 0x14 "UA_FSR,UART1 FIFO Status Register"
|
|
bitfld.long 0x14 28. " TE_FLAG ,Transmitter Empty Flag" "Not empty,Empty"
|
|
bitfld.long 0x14 23. " TX_OVER ,Transmitter FIFO Over" "Not overflowed,Overflowed"
|
|
textline " "
|
|
bitfld.long 0x14 22. " TX_EMPTY ,Transmitter FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x14 16.--21. " TX_POINTER ,TX FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x14 15. " RX_OVER ,Receiver FIFO Over" "Not overflowed,Overflowed"
|
|
bitfld.long 0x14 14. " RX_EMPTY ,Receiver FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x14 8.--13. " RX_POINTER ,RX FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
eventfld.long 0x14 6. " BIF ,Break Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 5. " FEF ,Framing Error Flag" "No error,Error"
|
|
eventfld.long 0x14 4. " PEF ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x14 3. " RS485_ADD_DETF ,RS-485 Address Byte Detection Flag" "Not detected,Detected"
|
|
line.long 0x18 "UA_ISR,UART1 Interrupt Status Register"
|
|
bitfld.long 0x18 12. " TOUT_INT ,Time Out Interrupt Indicator" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 11. " MODEM_INT ,MODEM Status Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 10. " RLS_INT ,Receive Line Status Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 9. " THRE_INT ,Transmit Holding Register Empty Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 8. " RDA_INT ,Receive Data Available Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 4. " TOUT_IF ,Time Out Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x18 3. " MODEM_IF ,MODEM Interrupt Flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x18 2. " RLS_IF ,Receive Line Interrupt Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 1. " THRE_IF ,Transmit Holding Register Empty Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 0. " RDA_IF ,Receive Data Available Interrupt Flag" "No interrupt,Interrupt"
|
|
line.long 0x1C "UA_TOR,UART1 Time Out Register"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " DLY ,TX Delay time value"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--6. 1. " TOIC ,Time Out Interrupt Comparator"
|
|
line.long 0x20 "UA_BAUD,UART1 Baud Rate Divisor Register"
|
|
bitfld.long 0x20 29. " DIV_X_EN ,Divider X Enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 28. " DIV_X_ONE ,Divider X equal 1" "M = X,M = 1"
|
|
textline " "
|
|
bitfld.long 0x20 24.--27. " DIVIDER_X ,Divider X" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x20 0.--15. 1. " BRD ,Baud Rate Divider"
|
|
line.long 0x24 "UA_IRCR,UART1 IrDA Control Register"
|
|
bitfld.long 0x24 6. " INV_RX ,INV_RX" "No inverted,Inverted"
|
|
bitfld.long 0x24 5. " INV_TX ,INV_TX" "No inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x24 1. " TX_SELECT ,IrDA mode" "Receiver,Transmitter"
|
|
line.long 0x28 "UA_ALT_CSR,UART1 Alternate Control/Status Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " ADDR_MATCH ,Address match value register"
|
|
textline " "
|
|
bitfld.long 0x28 15. " RS485_ADD_EN ,RS-485 Address Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x28 10. " RS485_AUD ,RS-485 Auto Direction Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 9. " RS485_AAD ,RS-485 Auto Address Detection Operation Mode" "Disabled,Enabled"
|
|
bitfld.long 0x28 8. " RS485_NMM ,RS-485 Normal Multi-drop Operation Mode" "Disabled,Enabled"
|
|
line.long 0x2C "UA_FUN_SEL,UART1 Function Select Register"
|
|
bitfld.long 0x2C 0.--1. " FUN_SEL ,Function Select Enable" "UART,Reserved,IrDA,RS-485"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x400E0000
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
width 9.
|
|
hgroup.long 0x00++0x1F
|
|
hide.long 0x0 " ADDR0,A/D Data Register 0"
|
|
in
|
|
hide.long 0x4 " ADDR1,A/D Data Register 1"
|
|
in
|
|
hide.long 0x8 " ADDR2,A/D Data Register 2"
|
|
in
|
|
hide.long 0xC " ADDR3,A/D Data Register 3"
|
|
in
|
|
hide.long 0x10 " ADDR4,A/D Data Register 4"
|
|
in
|
|
hide.long 0x14 " ADDR5,A/D Data Register 5"
|
|
in
|
|
hide.long 0x18 " ADDR6,A/D Data Register 6"
|
|
in
|
|
hide.long 0x1C " ADDR7,A/D Data Register 7"
|
|
in
|
|
group.long 0x20++0x17
|
|
line.long 0x00 " ADCR,A/D Control Register"
|
|
sif (cpuis("NUC1?0???BN")||cpuis("NUC1?0???CN"))
|
|
bitfld.long 0x00 31. " DMOF ,A/D differential input Mode Output Format" "Unsigned,Complement"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " ADST ,A/D Conversion Start" "Stopped,Started"
|
|
bitfld.long 0x00 10. " DIFFEN ,Differential Input Mode Enable" "Single-end,Differential"
|
|
textline " "
|
|
sif (!cpuis("M05*"))
|
|
bitfld.long 0x00 9. " PTEN ,PDMA Transfer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " TRGEN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " TRGCOND ,External Trigger Condition" "Low level,High level,Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TRGS ,Hardware Trigger Source" "STADC pin,?..."
|
|
textline " "
|
|
sif (cpuis("M05*"))
|
|
bitfld.long 0x00 2.--3. " ADMD ,A/D Converter Operation Mode" "Single conversion,Burst conversion,Single-cycle scan,Continuous scan"
|
|
else
|
|
bitfld.long 0x00 2.--3. " ADMD ,A/D Converter Operation Mode" "Single conversion,Reserved,Single-cycle scan,Continuous scan"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADIE ,A/D Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADEN ,A/D Converter Enable" "Disabled,Enabled"
|
|
line.long 0x04 " ADCHER,A/D Channel Enable Register"
|
|
sif (cpuis("M05*"))
|
|
bitfld.long 0x04 8.--9. " PRESEL ,Analog Input Channel 7 select" "External analog input,Internal bandgap voltage,?..."
|
|
else
|
|
bitfld.long 0x04 8.--9. " PRESEL ,Analog Input Channel 7 select" "External analog input,Internal bandgap voltage,Internal temperature sensor,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 7. " CHEN7 ,Analog Input Channel 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " CHEN6 ,Analog Input Channel 6 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CHEN5 ,Analog Input Channel 5 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CHEN4 ,Analog Input Channel 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CHEN3 ,Analog Input Channel 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " CHEN2 ,Analog Input Channel 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CHEN1 ,Analog Input Channel 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CHEN0 ,Analog Input Channel 0 Enable" "Disabled,Enabled"
|
|
line.long 0x08 " ADCMPR0,A/D Compare Register 0"
|
|
hexmask.long.word 0x08 16.--27. 1. " CMPD ,Comparison Data"
|
|
bitfld.long 0x08 8.--11. " CMPMATCNT ,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 3.--5. " CMPCH ,Compare Channel Selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
textline " "
|
|
bitfld.long 0x08 2. " CMPCOND ,Compare Condition" "RSLT < CMPD,RSLT >= CMPD"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CMPIE ,Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CMPEN ,Compare Enable" "Disabled,Enabled"
|
|
line.long 0x0C " ADCMPR1,A/D Compare Register 1"
|
|
hexmask.long.word 0x0C 16.--27. 1. " CMPD ,Comparison Data"
|
|
bitfld.long 0x0C 8.--11. " CMPMATCNT ,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0C 3.--5. " CMPCH ,Compare Channel Selection" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMPCOND ,Compare Condition" "RSLT < CMPD,RSLT >= CMPD"
|
|
bitfld.long 0x0C 1. " CMPIE ,Compare Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CMPEN ,Compare Enable" "Disabled,Enabled"
|
|
line.long 0x10 " ADSR,A/D Status Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " OVERRUN ,Over Run flag"
|
|
hexmask.long.byte 0x10 8.--15. 1. " VALID ,Data Valid flag"
|
|
textline " "
|
|
bitfld.long 0x10 4.--6. " CHANNEL ,Current Conversion Channel" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
textline " "
|
|
bitfld.long 0x10 3. " BUSY ,BUSY/IDLE" "Idle,Busy"
|
|
eventfld.long 0x10 2. " CMPF1 ,Compare Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x10 1. " CMPF0 ,Compare Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x10 0. " ADF ,A/D Conversion End Flag" "Not occurred,Occurred"
|
|
line.long 0x14 " ADCALR,A/D Calibration Register"
|
|
bitfld.long 0x14 1. " CALDONE ,Calibration is Done" "Not calibrated,Calibrated"
|
|
bitfld.long 0x14 0. " CALEN ,Self Calibration Enable" "Disabled,Enabled"
|
|
sif (!cpuis("M05*"))
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 " ADPDMA,ADC PDMA current transfer data"
|
|
hexmask.long.word 0x00 0.--11. 1. " AD_PDMA ,ADC PDMA current transfer data register"
|
|
endif
|
|
width 0xb
|
|
elif (cpuis("M05?ZAN")||cpuis("M0516ZAN"))
|
|
width 9.
|
|
hgroup.long 0x00++0x1F
|
|
hide.long 0x0 " ADDR0,A/D Data Register 0"
|
|
in
|
|
hide.long 0x4 " ADDR1,A/D Data Register 1"
|
|
in
|
|
hide.long 0x8 " ADDR2,A/D Data Register 2"
|
|
in
|
|
hide.long 0xC " ADDR3,A/D Data Register 3"
|
|
in
|
|
hide.long 0x10 " ADDR4,A/D Data Register 4"
|
|
in
|
|
group.long 0x20++0x17
|
|
line.long 0x00 " ADCR,A/D Control Register"
|
|
sif (cpuis("NUC1?0???BN")||cpuis("NUC1?0???CN"))
|
|
bitfld.long 0x00 31. " DMOF ,A/D differential input Mode Output Format" "Unsigned,Complement"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11. " ADST ,A/D Conversion Start" "Stopped,Started"
|
|
bitfld.long 0x00 10. " DIFFEN ,Differential Input Mode Enable" "Single-end,Differential"
|
|
textline " "
|
|
sif (!cpuis("M05*"))
|
|
bitfld.long 0x00 9. " PTEN ,PDMA Transfer Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " TRGEN ,External Trigger Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--7. " TRGCOND ,External Trigger Condition" "Low level,High level,Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " TRGS ,Hardware Trigger Source" "STADC pin,?..."
|
|
textline " "
|
|
sif (cpuis("M05*"))
|
|
bitfld.long 0x00 2.--3. " ADMD ,A/D Converter Operation Mode" "Single conversion,Burst conversion,Single-cycle scan,Continuous scan"
|
|
else
|
|
bitfld.long 0x00 2.--3. " ADMD ,A/D Converter Operation Mode" "Single conversion,Reserved,Single-cycle scan,Continuous scan"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADIE ,A/D Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADEN ,A/D Converter Enable" "Disabled,Enabled"
|
|
line.long 0x04 " ADCHER,A/D Channel Enable Register"
|
|
bitfld.long 0x04 4. " CHEN4 ,Analog Input Channel 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CHEN3 ,Analog Input Channel 3 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " CHEN2 ,Analog Input Channel 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CHEN1 ,Analog Input Channel 1 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " CHEN0 ,Analog Input Channel 0 Enable" "Disabled,Enabled"
|
|
line.long 0x08 " ADCMPR0,A/D Compare Register 0"
|
|
hexmask.long.word 0x08 16.--27. 1. " CMPD ,Comparison Data"
|
|
bitfld.long 0x08 8.--11. " CMPMATCNT ,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 3.--5. " CMPCH ,Compare Channel Selection" "CH0,CH1,CH2,CH3,CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 2. " CMPCOND ,Compare Condition" "RSLT < CMPD,RSLT >= CMPD"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CMPIE ,Compare Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " CMPEN ,Compare Enable" "Disabled,Enabled"
|
|
line.long 0x0C " ADCMPR1,A/D Compare Register 1"
|
|
hexmask.long.word 0x0C 16.--27. 1. " CMPD ,Comparison Data"
|
|
bitfld.long 0x0C 8.--11. " CMPMATCNT ,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0C 3.--5. " CMPCH ,Compare Channel Selection" "CH0,CH1,CH2,CH3,CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CMPCOND ,Compare Condition" "RSLT < CMPD,RSLT >= CMPD"
|
|
bitfld.long 0x0C 1. " CMPIE ,Compare Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CMPEN ,Compare Enable" "Disabled,Enabled"
|
|
line.long 0x10 " ADSR,A/D Status Register"
|
|
hexmask.long.byte 0x10 16.--23. 1. " OVERRUN ,Over Run flag"
|
|
hexmask.long.byte 0x10 8.--15. 1. " VALID ,Data Valid flag"
|
|
textline " "
|
|
bitfld.long 0x10 4.--6. " CHANNEL ,Current Conversion Channel" "CH0,CH1,CH2,CH3,CH4,?..."
|
|
textline " "
|
|
bitfld.long 0x10 3. " BUSY ,BUSY/IDLE" "Idle,Busy"
|
|
eventfld.long 0x10 2. " CMPF1 ,Compare Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x10 1. " CMPF0 ,Compare Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x10 0. " ADF ,A/D Conversion End Flag" "Not occurred,Occurred"
|
|
line.long 0x14 " ADCALR,A/D Calibration Register"
|
|
bitfld.long 0x14 1. " CALDONE ,Calibration is Done" "Not calibrated,Calibrated"
|
|
bitfld.long 0x14 0. " CALEN ,Self Calibration Enable" "Disabled,Enabled"
|
|
sif (!cpuis("M05*"))
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 " ADPDMA,ADC PDMA current transfer data"
|
|
hexmask.long.word 0x00 0.--11. 1. " AD_PDMA ,ADC PDMA current transfer data register"
|
|
endif
|
|
width 0xb
|
|
endif
|
|
tree.end
|
|
tree "EBI (External Bus Interface)"
|
|
sif (cpuis("M05?LAN")||cpuis("M0516LAN"))
|
|
base ad:0x50010000
|
|
width 8.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "EBICON,External Bus Interface General Control Register"
|
|
bitfld.long 0x00 16.--18. " EXTTALE ,Expand Time of ALE" "MCLK,2*MCLK,3*MCLK,4*MCLK,5*MCLK,6*MCLK,7*MCLK,8*MCLK"
|
|
bitfld.long 0x00 8.--10. " MCLKDIV ,External Output Clock Divider" "HCLK,HCLK/2,HCLK/4,HCLK/8,HCLK/16,HCLK/32,HCLK,HCLK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EXTBW16 ,EBI data width 16-bit" "8-bit,16-bit"
|
|
bitfld.long 0x00 0. " EXTEN ,EBI Enable" "Disabled,Enabled"
|
|
line.long 0x04 "EXTIME,External Bus Interface Timing Control Register"
|
|
bitfld.long 0x04 24.--27. " EXTIR2R ,Idle State Cycle Between Read-Read" "Disabled,MCLK,2*MCLK,3*MCLK,4*MCLK,5*MCLK,6*MCLK,7*MCLK,8*MCLK,9*MCLK,10*MCLK,11*MCLK,12*MCLK,13*MCLK,14*MCLK,15*MCLK"
|
|
bitfld.long 0x04 12.--15. " EXTIW2X ,Idle State Cycle After Write" "Disabled,MCLK,2*MCLK,3*MCLK,4*MCLK,5*MCLK,6*MCLK,7*MCLK,8*MCLK,9*MCLK,10*MCLK,11*MCLK,12*MCLK,13*MCLK,14*MCLK,15*MCLK"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " EXTTAHD ,EBI Data Access Hold Time" "MCLK,2*MCLK,3*MCLK,4*MCLK,5*MCLK,6*MCLK,7*MCLK,8*MCLK"
|
|
bitfld.long 0x04 3.--7. " EXTTACC ,EBI Data Access Time" "MCLK,2*MCLK,3*MCLK,4*MCLK,5*MCLK,6*MCLK,7*MCLK,8*MCLK,9*MCLK,10*MCLK,11*MCLK,12*MCLK,13*MCLK,14*MCLK,15*MCLK,16*MCLK,17*MCLK,18*MCLK,19*MCLK,20*MCLK,21*MCLK,22*MCLK,23*MCLK,24*MCLK,25*MCLK,26*MCLK,27*MCLK,28*MCLK,29*MCLK,30*MCLK,31*MCLK,32*MCLK"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree.open "FMC (Flash Memory Controller)"
|
|
tree "User Configuration"
|
|
base ad:0x00300000
|
|
width 9.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CONFIG0,User Configuration Register 0"
|
|
bitfld.long 0x00 28. " CKF ,XT1 Clock Filter Enable" "Disabled,Enabled"
|
|
sif (cpuis("M05*"))
|
|
bitfld.long 0x00 24.--26. " CFOSC ,CPU Clock Source Selection After Reset" "External 12 MHz crystal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Internal RC 22.1184 MHz oscillator"
|
|
else
|
|
bitfld.long 0x00 24.--26. " CFOSC ,CPU Clock Source Selection After Reset" "External 4~24 MHz crystal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Internal RC 22.1184 MHz oscillator"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 23. " CBODEN ,Brown-Out Detector Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21.--22. " CBOV1-0 ,Brown-Out Voltage Selection" "2.2 V,2.7 V,3.8 V,4.5 V"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CBORST ,Brown-Out Reset Enable" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " CBS ,Chip Boot Selection" "LDROM,APROM"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCK ,Security Lock" "Locked,Not locked"
|
|
sif (cpuis("NUC1???E*"))
|
|
bitfld.long 0x00 0. " DFEN ,Data Flash Enable" "Enabled,Disabled"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "CONFIG1,User Configuration Register 1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " DFBADR ,Data Flash Base Address"
|
|
endif
|
|
tree.end
|
|
tree "Flash Control Registers"
|
|
base ad:0x5000C000
|
|
width 8.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "ISPCON,ISP Control Register"
|
|
bitfld.long 0x00 12.--14. " ET ,Flash Erase Time" "20ms,25ms,30ms,35ms,3ms,5ms,10ms,15ms"
|
|
bitfld.long 0x00 8.--10. " PT ,Flash Program Time" "40us,45us,50us,55us,20us,25us,30us,35us"
|
|
textline " "
|
|
sif (cpuis("M05*"))
|
|
bitfld.long 0x00 7. " SWRST ,Software Reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 6. " ISPFF ,ISP Fail Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " LDUEN ,LDROM Update Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CFGUEN ,Config Update Enable" "Disabled,Enabled"
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
bitfld.long 0x00 3. " APUEN ,APROM Update Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1. " BS ,Boot Select" "APROM,LDROM"
|
|
bitfld.long 0x00 0. " ISPEN ,ISP Enable" "Disabled,Enabled"
|
|
line.long 0x04 "ISPADR,ISP Address Register"
|
|
line.long 0x08 "ISPDAT,ISP Data Register"
|
|
line.long 0x0C "ISPCMD,ISP Command Register"
|
|
sif (cpuis("M05*"))
|
|
bitfld.long 0x0C 0.--5. " FOEN ,ISP Command" "Read,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Program,Page Erase,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Standby,?..."
|
|
else
|
|
bitfld.long 0x0C 0.--5. " FOEN ,ISP Command" "Read,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Program,Page Erase,?..."
|
|
endif
|
|
line.long 0x10 "ISPTRG,ISP Trigger Register"
|
|
bitfld.long 0x10 0. " ISPGO ,ISP start trigger" "Stopped,Started"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "DFBADR,Data Flash Start Address"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "FATCON,Flash Access Window Control Register"
|
|
sif (cpuis("NUC130*")||cpuis("NUC140*"))
|
|
bitfld.long 0x00 4. " LFOM ,Low Frequency Optimization Mode" "Disabled,Enabled"
|
|
elif (cpuis("M05*"))
|
|
bitfld.long 0x00 4. " L_SPEED ,Flash Low Speed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " FATS ,Flash Access Time Window Select" "40ns,50ns,60ns,70ns,80ns,90ns,100ns,?..."
|
|
bitfld.long 0x00 0. " FPSEN ,Flash Power Save Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
textline ""
|