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8532a4c95c1064bdcb9e901339d1cc049595ecd9
Gen4_R-Car_Trace32/2_Trunk/perm031.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: M031 On-Chip Peripherals
; @Props: Released
; @Author: PIW
; @Changelog: 2022-02-18 PIW
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
; @Doc: SVD generated based on: M031AE_v1.svd
; @Core: Cortex-M0
; @Chip: M031BTYD2AN, M031BTYE3AN, M031EB0AE, M031EC1AE, M031FB0AE, M031FC1AE,
; M031GGC2AE, M031GGD2AE, M031GTC2AE, M031GTD2AE, M031LC2AE, M031LD2AE,
; M031LE3AE, M031LG6AE, M031LG8AE, M031KG6AE, M031KG8AE, M031KIAAE,
; M031SC2AE, M031SD2AE, M031SE3AE, M031SG6AE, M031SG8AE, M031SIAAE,
; M031TB0AE, M031TC1AE, M031TD2AE, M031TE3AE, M032EC1AE, M032FC1AE,
; M032KG6AE, M032KG8AE, M032KIAAE, M032LC2AE, M032LD2AE, M032LE3AE,
; M032LG6AE, M032LG8AE, M032SE3AE, M032SG6AE, M032SG8AE, M032SIAAE,
; M032TC1AE, M032TD2AE
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perm031.per 14356 2022-02-22 13:54:06Z kwisniewski $
config 16. 8.
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "ACMP (ACMP Register Map)"
base ad:0x40045000
group.long 0x00++0x03
line.long 0x00 "ACMP_CTL0,Analog Comparator 0 Control Register"
bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected"
bitfld.long 0x00 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
newline
bitfld.long 0x00 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,2: ACMP0 output is sampled 2 consecutive PCLKs,3: ACMP0 output is sampled 4 consecutive PCLKs,4: ACMP0 output is sampled 8 consecutive PCLKs,5: ACMP0 output is sampled 16 consecutive PCLKs,6: ACMP0 output is sampled 32 consecutive PCLKs,7: ACMP0 output is sampled 64 consecutive PCLKs"
newline
bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 0 output to ACMP0_O pin is..,1: Comparator 0 output to ACMP0_O pin is from.."
bitfld.long 0x00 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved"
newline
bitfld.long 0x00 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP0_P0,1: Input from ACMP0_P1,2: Input from ACMP0_P2,3: Input from ACMP0_P3"
bitfld.long 0x00 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP0_N pin,1: Internal comparator reference voltage (CRV),2: Band-gap voltage,3: Reserved"
newline
bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled"
bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled"
newline
bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled"
group.long 0x04++0x03
line.long 0x00 "ACMP_CTL1,Analog Comparator 1 Control Register"
bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected"
bitfld.long 0x00 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
newline
bitfld.long 0x00 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,2: ACMP1 output is sampled 2 consecutive PCLKs,3: ACMP1 output is sampled 4 consecutive PCLKs,4: ACMP1 output is sampled 8 consecutive PCLKs,5: ACMP1 output is sampled 16 consecutive PCLKs,6: ACMP1 output is sampled 32 consecutive PCLKs,7: ACMP1 output is sampled 64 consecutive PCLKs"
newline
bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is..,1: Comparator 1 output to ACMP1_O pin is from.."
bitfld.long 0x00 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved"
newline
bitfld.long 0x00 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP1_P0,1: Input from ACMP1_P1,2: Input from ACMP1_P2,3: Input from ACMP1_P3"
bitfld.long 0x00 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP1_N pin,1: Internal comparator reference voltage (CRV),2: Band-gap voltage,3: Reserved"
newline
bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled"
bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled"
newline
bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 1 Disabled,1: Comparator 1 Enabled"
group.long 0x08++0x03
line.long 0x00 "ACMP_STATUS,Analog Comparator Status Register"
bitfld.long 0x00 16. "ACMPWO,Comparator Window Output\nThis bit shows the output status of window compare mode" "0: The positive input voltage is outside the..,1: The positive input voltage is in the window"
bitfld.long 0x00 13. "ACMPS1,Comparator 1 Status\nSynchronized to the PCLK to allow reading by software" "0,1"
newline
bitfld.long 0x00 12. "ACMPS0,Comparator 0 Status \nSynchronized to the PCLK to allow reading by software" "0,1"
bitfld.long 0x00 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
newline
bitfld.long 0x00 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
bitfld.long 0x00 5. "ACMPO1,Comparator 1 Output\nSynchronized to the PCLK to allow reading by software" "0,1"
newline
bitfld.long 0x00 4. "ACMPO0,Comparator 0 Output\nSynchronized to the PCLK to allow reading by software" "0,1"
bitfld.long 0x00 1. "ACMPIF1,Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output" "0,1"
newline
bitfld.long 0x00 0. "ACMPIF0,Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output" "0,1"
group.long 0x0C++0x03
line.long 0x00 "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
bitfld.long 0x00 6. "CRVSSEL,CRV Source Voltage Selection" "0: AVDD is selected as CRV source voltage,1: VREF is selected as as CRV source voltage"
bitfld.long 0x00 0.--3. "CRVCTL,Comparator Reference Voltage Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "ACMP_CALCTL,Analog Comparator Calibration Control Register"
bitfld.long 0x00 17. "CALRVS1,OPA1 Calibration Reference Voltage Selection \nNote: CALRVS0 and CALRVS1 must be the same setting in calibration" "0: VREF is,1: VREF from high vcm to low vcm"
bitfld.long 0x00 16. "CALRVS0,OPA0 Calibration Reference Voltage Selection \nNote: CALRVS0 and CALRVS1 must be the same setting in calibration" "0: VREF is,1: VREF from high vcm to low vcm"
newline
bitfld.long 0x00 1. "CALTRG1,OP Amplifier 1 Calibration Trigger Bit\n" "0: Calibration is stopped,1: Calibration is triggered"
bitfld.long 0x00 0. "CALTRG0,OP Amplifier 0 Calibration Trigger Bit\n" "0: Calibration is stopped,1: Calibration is triggered"
rgroup.long 0x14++0x03
line.long 0x00 "ACMP_CALSR,Analog Comparator Calibration Status Register"
bitfld.long 0x00 6. "CALPS1,Comparator1 Calibration Result Status for PMOS" "0: Pass,1: Fail"
bitfld.long 0x00 5. "CALNS1,Comparator1 Calibration Result Status for NMOS" "0: Pass,1: Fail"
newline
bitfld.long 0x00 4. "DONE1,Comparator1 Calibration Done Status" "0: Calibrating,1: Calibration Done"
bitfld.long 0x00 2. "CALPS0,Comparator0 Calibration Result Status for PMOS" "0: Pass,1: Fail"
newline
bitfld.long 0x00 1. "CALNS0,Comparator0 Calibration Result Status for NMOS" "0: Pass,1: Fail"
bitfld.long 0x00 0. "DONE0,Comparator0 Calibration Done Status" "0: Calibrating,1: Calibration Done"
tree.end
tree "ADC (ADC Register Map)"
base ad:0x40043000
rgroup.long 0x00++0x03
line.long 0x00 "ADC_ADDR0,ADC Data Register 0"
bitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
bitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
repeat 16. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" "29" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x70 )
group.long ($2+0x04)++0x03
line.long 0x00 "ADC_ADDR$1,ADC Data Register $1"
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
repeat.end
group.long 0x80++0x03
line.long 0x00 "ADC_ADCR,ADC Control Register"
bitfld.long 0x00 31. "DMOF,Differential Input Mode Output Format\nIf user enables differential input mode the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format)" "0: A/D Conversion result will be filled in RSLT..,1: A/D Conversion result will be filled in RSLT.."
bitfld.long 0x00 12. "RESET,ADC RESET (Write Protect)\nIf user writes this bit the ADC analog macro will reset" "0,1"
newline
bitfld.long 0x00 11. "ADST,A/D Conversion Start or Calibration Start\nADST bit can be set to 1 from four sources: software external pin STADC PWM trigger and Timer trigger" "0: Conversion stops and A/D converter enters..,1: Conversion starts or Calibration Start"
bitfld.long 0x00 10. "DIFFEN,Differential Input Mode Control\nNote: In Differential Input mode only the even number of the two corresponding channels needs to be enabled in ADCHER register" "0: Single-end analog input mode,1: Differential analog input mode"
newline
bitfld.long 0x00 9. "PTEN,PDMA Transfer Enable Bit\nWhen A/D conversion is completed the converted data is loaded into ADDR0~15 ADDR29" "0: PDMA data transfer Disabled,1: PDMA data transfer in ADDR0~15 ADDR29 Enabled"
bitfld.long 0x00 8. "TRGEN,External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external STADC pin PWM trigger BPWM trigger and Timer trigger" "0: External trigger Disabled,1: External trigger Enabled"
newline
bitfld.long 0x00 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge" "0: Low level,1: High level,2: Falling edge,3: Rising edge"
bitfld.long 0x00 4.--5. "TRGS,Hardware Trigger Source\nNote: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits" "0: A/D conversion is started by external STADC pin,1: Timer0 ~ Timer3 overflow pulse trigger,2: A/D conversion is started by BPWM trigger,3: A/D conversion is started by PWM trigger"
newline
bitfld.long 0x00 2.--3. "ADMD,A/D Converter Operation Mode Control\n" "0: Single conversion,1: Burst conversion,2: Single-cycle Scan,3: Continuous Scan"
bitfld.long 0x00 1. "ADIE,A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit is set to 1" "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
newline
bitfld.long 0x00 0. "ADEN,A/D Converter Enable Bit\nNote: Before starting A/D conversion function this bit should be set to 1" "0: A/D converter Disabled,1: A/D converter Enabled"
group.long 0x84++0x03
line.long 0x00 "ADC_ADCHER,ADC Channel Enable Register"
hexmask.long 0x00 0.--31. 1. "CHEN,Analog Input Channel Enable Control\nSet ADCHER[15:0] bits to enable the corresponding analog input channel 15 ~ 0"
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0x88)++0x03
line.long 0x00 "ADC_ADCMPR$1,ADC Compare Register $1"
hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)"
bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register" "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
newline
bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3.--7. "CMPCH,Compare Channel Selection" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be..,8: Channel 8 conversion result is selected to be..,9: Channel 9 conversion result is selected to be..,10: Channel 10 conversion result is selected to..,11: Channel 11 conversion result is selected to..,12: Channel 12 conversion result is selected to..,13: Channel 13 conversion result is selected to..,14: Channel 14 conversion result is selected to..,15: Channel 15 conversion result is selected to..,?,?,?,?,?,?,?,?,?,?,?,?,28: Floating detect channel conversion result is..,29: Band-gap voltage conversion result is..,?..."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1) the CMPFx bit will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
bitfld.long 0x00 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x00 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register" "0: Compare function Disabled,1: Compare function Enabled"
repeat.end
group.long 0x90++0x03
line.long 0x00 "ADC_ADSR0,ADC Status Register0"
rbitfld.long 0x00 27.--31. "CHANNEL,Current Conversion Channel (Read Only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x00 16. "OVERRUNF,Overrun Flag (Read Only)\nIf any one of OVERRUN (ADDRx[16]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun this flag will be set to 1" "0,1"
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rbitfld.long 0x00 8. "VALIDF,Data Valid Flag (Read Only)\nIf any one of VALID (ADDRx[17]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid this flag will be set to 1" "0,1"
rbitfld.long 0x00 7. "BUSY,BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADCR register" "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
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bitfld.long 0x00 2. "CMPF1,Compare Flag 1\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register this bit is set to 1 it is cleared by writing 1 to it" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR1 setting"
bitfld.long 0x00 1. "CMPF0,Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR0 setting"
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bitfld.long 0x00 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion" "0,1"
rgroup.long 0x94++0x03
line.long 0x00 "ADC_ADSR1,ADC Status Register1"
hexmask.long 0x00 0.--31. 1. "VALID,Data Valid Flag (Read Only)\nVALID[29 15:0] are the mirror of the VALID bits in ADDR29[17] ADDR15[17]~ ADDR0[17]"
rgroup.long 0x98++0x03
line.long 0x00 "ADC_ADSR2,ADC Status Register2"
hexmask.long 0x00 0.--31. 1. "OVERRUN,Overrun Flag (Read Only)\nOVERRUN[29 15:0] are the mirror of the OVERRUN bit in ADDR29[16] ADDR15[16] ~ ADDR0[16]"
group.long 0xA0++0x03
line.long 0x00 "ADC_ESMPCTL,ADC Extend Sample Time Control Register"
hexmask.long.byte 0x00 0.--7. 1. "EXTSMPT,ADC Sampling Time Extend \nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
group.long 0xA4++0x03
line.long 0x00 "ADC_CFDCTL,ADC Channel Floating Detect Control Register"
bitfld.long 0x00 8. "FDETCHEN,Floating Detect Channel Enable Bit\nNote: if FDETCHEN is enabled internal channel is always turn on" "0: Floating Detect Channel Disabled,1: Floating Detect Channel Enabled"
bitfld.long 0x00 1. "DISCHEN,Discharge Enable\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable" "0: Channel discharge Disabled,1: Channel discharge Enabled"
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bitfld.long 0x00 0. "PRECHEN,Precharge Enable\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable" "0: Channel precharge Disabled,1: Channel precharge Enabled"
rgroup.long 0x100++0x03
line.long 0x00 "ADC_ADPDMA,ADC PDMA Current Transfer Data Register"
hexmask.long.tbyte 0x00 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data could be the content of ADDR0 ~ ADDR15 and ADDR29 registers"
group.long 0x180++0x03
line.long 0x00 "ADC_ADCALR,ADC Calibration Mode Register"
bitfld.long 0x00 1. "CALIE,Calibration Interrupt Enable Bit\nIf calibration function is enabled and the calibration finish CALIF bit will be asserted in the meanwhile if CALIE bit is set to 1 a calibration interrupt request is generated" "0: Calibration function Interrupt Disabled,1: Calibration function Interrupt Enabled"
bitfld.long 0x00 0. "CALEN,Calibration Function Enable Bit\nNote: If chip is powered off calibration function should be executed again" "0: Calibration function Disabled,?..."
group.long 0x184++0x03
line.long 0x00 "ADC_ADCALSTSR,ADC Calibration Status Register"
bitfld.long 0x00 0. "CALIF,Calibration Finish Interrupt Flag\nIf calibration is finished this flag will be set to 1" "0,1"
tree.end
tree "BPWM (BPWM Register Map)"
repeat 2. (list 0. 1.) (list ad:0x4005A000 ad:0x4005B000)
tree "BPWM$1"
base $2
group.long 0x00++0x03
line.long 0x00 "BPWM_CTL0,BPWM Control Register 0"
bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects BPWM..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
bitfld.long 0x00 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
bitfld.long 0x00 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
bitfld.long 0x00 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
group.long 0x04++0x03
line.long 0x00 "BPWM_CTL1,BPWM Control Register 1"
bitfld.long 0x00 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
group.long 0x10++0x03
line.long 0x00 "BPWM_CLKSRC,BPWM Clock Source Register"
bitfld.long 0x00 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
group.long 0x14++0x03
line.long 0x00 "BPWM_CLKPSC,BPWM Clock Prescale Register"
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler"
group.long 0x20++0x03
line.long 0x00 "BPWM_CNTEN,BPWM Counter Enable Register"
bitfld.long 0x00 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
group.long 0x24++0x03
line.long 0x00 "BPWM_CNTCLR,BPWM Clear Counter Register"
bitfld.long 0x00 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
group.long 0x30++0x03
line.long 0x00 "BPWM_PERIOD,BPWM Period Register"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD"
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
group.long ($2+0x50)++0x03
line.long 0x00 "BPWM_CMPDAT$1,BPWM Comparator Register $1"
hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
repeat.end
rgroup.long 0x90++0x03
line.long 0x00 "BPWM_CNT,BPWM Counter Register"
bitfld.long 0x00 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
hexmask.long.word 0x00 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter"
group.long 0xB0++0x03
line.long 0x00 "BPWM_WGCTL0,BPWM Generation Register 0"
bitfld.long 0x00 26.--27. "PRDPCTL5,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
bitfld.long 0x00 24.--25. "PRDPCTL4,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
bitfld.long 0x00 20.--21. "PRDPCTL2,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
bitfld.long 0x00 16.--17. "PRDPCTL0,BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
bitfld.long 0x00 8.--9. "ZPCTL4,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
bitfld.long 0x00 4.--5. "ZPCTL2,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
bitfld.long 0x00 0.--1. "ZPCTL0,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to zero" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
group.long 0xB4++0x03
line.long 0x00 "BPWM_WGCTL1,BPWM Generation Register 1"
bitfld.long 0x00 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
bitfld.long 0x00 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
bitfld.long 0x00 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
bitfld.long 0x00 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter down count to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
bitfld.long 0x00 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
bitfld.long 0x00 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
bitfld.long 0x00 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter up count to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
group.long 0xB8++0x03
line.long 0x00 "BPWM_MSKEN,BPWM Mask Enable Register"
bitfld.long 0x00 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
bitfld.long 0x00 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
bitfld.long 0x00 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
bitfld.long 0x00 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
group.long 0xBC++0x03
line.long 0x00 "BPWM_MSK,BPWM Mask Data Register"
bitfld.long 0x00 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
bitfld.long 0x00 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
bitfld.long 0x00 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
bitfld.long 0x00 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
group.long 0xD4++0x03
line.long 0x00 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
bitfld.long 0x00 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
bitfld.long 0x00 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
bitfld.long 0x00 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
bitfld.long 0x00 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output" "0: BPWM output polar inverse Disabled,1: BPWM output polar inverse Enabled"
group.long 0xD8++0x03
line.long 0x00 "BPWM_POEN,BPWM Output Enable Register"
bitfld.long 0x00 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
bitfld.long 0x00 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x00 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
bitfld.long 0x00 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x00 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
bitfld.long 0x00 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
group.long 0xE0++0x03
line.long 0x00 "BPWM_INTEN,BPWM Interrupt Enable Register"
bitfld.long 0x00 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x00 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x00 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x00 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x00 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x00 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x00 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x00 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
group.long 0xE8++0x03
line.long 0x00 "BPWM_INTSTS,BPWM Interrupt Flag Register"
bitfld.long 0x00 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
bitfld.long 0x00 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
bitfld.long 0x00 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
bitfld.long 0x00 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
bitfld.long 0x00 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
bitfld.long 0x00 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
bitfld.long 0x00 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to 0" "0,1"
bitfld.long 0x00 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0 software can write 1 to clear this bit to 0" "0,1"
group.long 0xF8++0x03
line.long 0x00 "BPWM_ADCTS0,BPWM Trigger ADC Source Select Register 0"
bitfld.long 0x00 31. "TRGEN3,BPWM_CH3 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 24.--27. "TRGSEL3,BPWM_CH3 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count CMPDAT point,4: BPWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH3 up-count CMPDAT point,9: BPWM_CH3 down-count CMPDAT point,?..."
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bitfld.long 0x00 23. "TRGEN2,BPWM_CH2 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 16.--19. "TRGSEL2,BPWM_CH2 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count CMPDAT point,4: BPWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH3 up-count CMPDAT point,9: BPWM_CH3 down-count CMPDAT point,?..."
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bitfld.long 0x00 15. "TRGEN1,BPWM_CH1 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 8.--11. "TRGSEL1,BPWM_CH1 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count CMPDAT point,4: BPWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH1 up-count CMPDAT point,9: BPWM_CH1 down-count CMPDAT point,?..."
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bitfld.long 0x00 7. "TRGEN0,BPWM_CH0 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 0.--3. "TRGSEL0,BPWM_CH0 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count CMPDAT point,4: BPWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH1 up-count CMPDAT point,9: BPWM_CH1 down-count CMPDAT point,?..."
group.long 0xFC++0x03
line.long 0x00 "BPWM_ADCTS1,BPWM Trigger ADC Source Select Register 1"
bitfld.long 0x00 15. "TRGEN5,BPWM_CH5 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 8.--11. "TRGSEL5,BPWM_CH5 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count CMPDAT point,4: BPWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH5 up-count CMPDAT point,9: BPWM_CH5 down-count CMPDAT point,?..."
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bitfld.long 0x00 7. "TRGEN4,BPWM_CH4 Trigger ADC Enable Bit" "0,1"
bitfld.long 0x00 0.--3. "TRGSEL4,BPWM_CH4 Trigger ADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count CMPDAT point,4: BPWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH5 up-count CMPDAT point,9: BPWM_CH5 down-count CMPDAT point,?..."
group.long 0x110++0x03
line.long 0x00 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
bitfld.long 0x00 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
bitfld.long 0x00 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)" "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
wgroup.long 0x114++0x03
line.long 0x00 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
bitfld.long 0x00 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit(Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
group.long 0x120++0x03
line.long 0x00 "BPWM_STATUS,BPWM Status Register"
bitfld.long 0x00 21. "ADCTRG5,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.."
bitfld.long 0x00 20. "ADCTRG4,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "ADCTRG3,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.."
bitfld.long 0x00 18. "ADCTRG2,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "ADCTRG1,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.."
bitfld.long 0x00 16. "ADCTRG0,ADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n" "0: No ADC start of conversion trigger event has..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x00 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Status" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
group.long 0x200++0x03
line.long 0x00 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
group.long 0x204++0x03
line.long 0x00 "BPWM_CAPCTL,BPWM Capture Control Register"
bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
rgroup.long 0x208++0x03
line.long 0x00 "BPWM_CAPSTS,BPWM Capture Status Register"
bitfld.long 0x00 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
bitfld.long 0x00 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
bitfld.long 0x00 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
bitfld.long 0x00 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
bitfld.long 0x00 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
bitfld.long 0x00 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
bitfld.long 0x00 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
rgroup.long 0x20C++0x03
line.long 0x00 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
rgroup.long 0x210++0x03
line.long 0x00 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x214++0x03
line.long 0x00 "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
group.long 0x218++0x03
line.long 0x00 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x21C++0x03
line.long 0x00 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
group.long 0x220++0x03
line.long 0x00 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x224++0x03
line.long 0x00 "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
group.long 0x228++0x03
line.long 0x00 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x22C++0x03
line.long 0x00 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
group.long 0x230++0x03
line.long 0x00 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x234++0x03
line.long 0x00 "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
group.long 0x238++0x03
line.long 0x00 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
group.long 0x250++0x03
line.long 0x00 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
bitfld.long 0x00 8.--13. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled,?..."
bitfld.long 0x00 0.--5. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled,?..."
group.long 0x254++0x03
line.long 0x00 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
bitfld.long 0x00 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x00 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x00 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x00 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x00 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x00 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x00 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
rgroup.long 0x304++0x03
line.long 0x00 "BPWM_PBUF,BPWM PERIOD Buffer"
hexmask.long.word 0x00 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register"
rgroup.long 0x31C++0x03
line.long 0x00 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
group.long 0x320++0x03
line.long 0x00 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
group.long 0x324++0x03
line.long 0x00 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
group.long 0x328++0x03
line.long 0x00 "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
group.long 0x32C++0x03
line.long 0x00 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
group.long 0x330++0x03
line.long 0x00 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
tree.end
repeat.end
tree.end
tree "CLK (CLK Register Map)"
base ad:0x40000200
group.long 0x00++0x03
line.long 0x00 "CLK_PWRCTL,System Power-down Control Register"
bitfld.long 0x00 25.--26. "LXTGAIN,LXT Gain Control Bit (Write Protect)\nNote: This bit is write protected" "0: LXT Crystal ESR = 35K CL=12.5pF,?,2: LXT Crystal ESR = 70K CL=12.5pF,?..."
bitfld.long 0x00 24. "LXTSELXT,LXT Mode Selection\n" "0: LXT work as crystal mode,1: LXT work as external clock mode"
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bitfld.long 0x00 20.--22. "HXTGAIN,HXT Gain Control Bit (Write Protect)\nThis is a protected register" "0: HXT frequency is lower than from 4 MHz,1: HXT frequency is from 4 MHz to 8 MHz,2: HXT frequency is from 8 MHz to 12 MHz,3: HXT frequency is from 12 MHz to 16 MHz,4: HXT frequency is from 16 MHz to 24 MHz,?,?,7: HXT frequency is from 24 MHz to 32 MHz"
bitfld.long 0x00 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode this bit.." "0: Chip operating normally or chip in idle mode..,1: Chip enters Power-down mode instant or wait.."
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bitfld.long 0x00 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' it indicates that resume from Power-down mode' \nThe flag is set if any wake-up source is occurred" "0,1"
bitfld.long 0x00 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\n" "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled"
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bitfld.long 0x00 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
bitfld.long 0x00 3. "LIRCEN,LIRC Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Internal low speed RC oscillator (LIRC)..,1: Internal low speed RC oscillator (LIRC) Enabled"
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bitfld.long 0x00 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Internal high speed RC oscillator (HIRC)..,1: Internal high speed RC oscillator (HIRC).."
bitfld.long 0x00 1. "LXTEN,LXT Enable Bit (Write Protect)\nNote1 : \n" "0: External low speed crystal (LXT) Disabled,1: External low speed crystal (LXT) Enabled"
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bitfld.long 0x00 0. "HXTEN,HXT Enable Bit (Write Protect)\nNote1 : reset by power on reset\n" "0: Eexternal high speed crystal (HXT) Disabled,1: External high speed crystal (HXT) Enabled"
group.long 0x04++0x03
line.long 0x00 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
bitfld.long 0x00 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled"
bitfld.long 0x00 4. "HDIV_EN,Divider Controller Clock Enable Control" "0: Divider controller peripheral clock Disabled,1: Divider controller peripheral clock Enabled"
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bitfld.long 0x00 3. "EBICKEN,EBI Controller Clock Enable Bit" "0: EBI peripheral clock Disabled,1: EBI peripheral clock Enabled"
bitfld.long 0x00 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
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bitfld.long 0x00 1. "PDMACKEN,PDMA Controller Clock Enable Bit" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled"
group.long 0x08++0x03
line.long 0x00 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
bitfld.long 0x00 28. "ADCCKEN,Analog-digital-converter (ADC) Clock Enable Bit" "0: ADC clock Disabled,1: ADC clock Enabled"
bitfld.long 0x00 27. "USBDCKEN,USB Device Clock Enable Bit" "0: USB Device clock Disabled,1: USB Device clock Enabled"
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bitfld.long 0x00 23. "UART7CKEN,UART7 Clock Enable Bit" "0: UART7 clock Disabled,1: UART7 clock Enabled"
bitfld.long 0x00 22. "UART6CKEN,UART6 Clock Enable Bit" "0: UART6 clock Disabled,1: UART6 clock Enabled"
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bitfld.long 0x00 21. "UART5CKEN,UART5 Clock Enable Bit" "0: UART5 clock Disabled,1: UART5 clock Enabled"
bitfld.long 0x00 20. "UART4CKEN,UART4 Clock Enable Bit" "0: UART4 clock Disabled,1: UART4 clock Enabled"
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bitfld.long 0x00 19. "UART3CKEN,UART3 Clock Enable Bit" "0: UART3 clock Disabled,1: UART3 clock Enabled"
bitfld.long 0x00 18. "UART2CKEN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled"
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bitfld.long 0x00 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
bitfld.long 0x00 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
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bitfld.long 0x00 13. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
bitfld.long 0x00 12. "QSPI0CKEN,QSPI0 Clock Enable Bit" "0: QSPI0 clock Disabled,1: QSPI0 clock Enabled"
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bitfld.long 0x00 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
bitfld.long 0x00 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
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bitfld.long 0x00 7. "ACMP01CKEN,Analog Comparator 0/1 Clock Enable Bit" "0: Analog comparator 0/1 clock Disabled,1: Analog comparator 0/1 clock Enabled"
bitfld.long 0x00 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO clock Disabled,1: CLKO clock Enabled"
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bitfld.long 0x00 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
bitfld.long 0x00 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
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bitfld.long 0x00 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
bitfld.long 0x00 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
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bitfld.long 0x00 1. "RTCCKEN,RTC Clock Enable Bit" "0: RTC clock Disabled,1: RTC clock Enabled"
bitfld.long 0x00 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Watchdog timer clock Disabled,1: Watchdog timer clock Enabled"
group.long 0x0C++0x03
line.long 0x00 "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
bitfld.long 0x00 19. "BPWM1CKEN,BPWM1 Clock Enable Bit" "0: BPWM1 clock Disabled,1: BPWM1 clock Enabled"
bitfld.long 0x00 18. "BPWM0CKEN,BPWM0 Clock Enable Bit" "0: BPWM0 clock Disabled,1: BPWM0 clock Enabled"
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bitfld.long 0x00 17. "PWM1CKEN,PWM1 Clock Enable Bit" "0: PWM1 clock Disabled,1: PWM1 clock Enabled"
bitfld.long 0x00 16. "PWM0CKEN,PWM0 Clock Enable Bit" "0: PWM0 clock Disabled,1: PWM0 clock Enabled"
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bitfld.long 0x00 9. "USCI1CKEN,USCI1 Clock Enable Bit" "0: USCI1 clock Disabled,1: USCI1 clock Enabled"
bitfld.long 0x00 8. "USCI0CKEN,USCI0 Clock Enable Bit" "0: USCI0 clock Disabled,1: USCI0 clock Enabled"
group.long 0x10++0x03
line.long 0x00 "CLK_CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x00 8. "USBDSEL,USB Device Clock Source Selection (Write Protect)\nThese bits are protected bit" "0: Clock source from HIRC,1: Clock source from PLL divided"
bitfld.long 0x00 3.--5. "STCLKSEL,Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote: This bit is write protected" "0: Clock source from HXT,1: Clock source from LXT,2: Clock source from HXT/2,3: Clock source from HCLK/2,?,?,?,7: Clock source from HIRC/2"
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bitfld.long 0x00 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\nNote: This bit is write protected" "0: Clock source from HXT,1: Clock source from LXT,2: Clock source from PLL,3: Clock source from LIRC,?,?,?,7: Clock source from HIRC"
group.long 0x14++0x03
line.long 0x00 "CLK_CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x00 28.--30. "UART1SEL,UART1 Clock Source Selection\nNote: If PLL is not supported clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported clock source of selection '000' or '010' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC..,4: Clock source from PCLK1,5: Clock source from internal low speed RC..,?..."
bitfld.long 0x00 24.--26. "UART0SEL,UART0 Clock Source Selection\nNote: If PLL is not supported clock source of selection '001' will be changed to PCLK0.\nNote: If LXT or HXT is not supported clock source of selection '000' or '010' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC..,4: Clock source from PCLK0,5: Clock source from internal low speed RC..,?..."
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bitfld.long 0x00 20.--22. "TMR3SEL,TIMER3 Clock Source Selection\nNote: If LXT or HXT is not supported clock source of selection '000' or '001' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK1,3: Clock source from external clock TM3 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.."
bitfld.long 0x00 16.--18. "TMR2SEL,TIMER2 Clock Source Selection\nNote: If LXT or HXT is not supported clock source of selection '000' or '001' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK1,3: Clock source from external clock TM2 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.."
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bitfld.long 0x00 12.--14. "TMR1SEL,TIMER1 Clock Source Selection\nNote: If LXT or HXT is not supported clock source of selection '000' or '001' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK0,3: Clock source from external clock TM1 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.."
bitfld.long 0x00 8.--10. "TMR0SEL,TIMER0 Clock Source Selection\nNote: If LXT or HXT is not supported clock source of selection '000' or '001' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK0,3: Clock source from external clock TM0 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.."
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bitfld.long 0x00 4.--6. "CLKOSEL,Clock Divider Clock Source Selection\nNote: If PLL is not supported clock source of selection '110' will be changed to HIRC.\nNote: If LXT or HXT is not supported clock source of selection '000' or '001' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from HCLK,3: Clock source from internal high speed RC..,4: Clock source from internal low speed RC..,5: Clock source from internal high speed RC..,6: Clock source from PLL,?..."
bitfld.long 0x00 2.--3. "WWDTSEL,Window Watchdog Timer Clock Source Selection (Write Protect)" "?,?,2: Clock source from HCLK/2048,3: Clock source from internal low speed RC.."
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bitfld.long 0x00 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\nNote: This bit is write protected" "0: Reserved,1: Clock source from external low speed crystal..,2: Clock source from HCLK/2048,3: Clock source from internal low speed RC.."
group.long 0x18++0x03
line.long 0x00 "CLK_CLKSEL2,Clock Source Select Control Register 2"
bitfld.long 0x00 20.--21. "ADCSEL,ADC Clock Source Selection\nNote: If PLL is not supported clock source of selection '01' will be changed to PCLK1.\nNote: If HXT is not supported clock source of selection '00' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from PCLK1,3: Clock source from internal high speed RC.."
bitfld.long 0x00 9. "BPWM1SEL,BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL" "0: Clock source from PLL,1: Clock source from PCLK1"
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bitfld.long 0x00 8. "BPWM0SEL,BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL" "0: Clock source from PLL,1: Clock source from PCLK0"
bitfld.long 0x00 4.--5. "SPI0SEL,SPI0 Clock Source Selection\nNote: If PLL is not supported clock source of selection '01' will be changed to PCLK1.\nNote: If HXT is not supported clock source of selection '00' will be stopped.\nPlease refer to section 3.2 NuMicro M031/M032.." "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from PCLK1,3: Clock source from internal high speed RC.."
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bitfld.long 0x00 2.--3. "QSPI0SEL,QSPI0 Clock Source Selection\nNote: If PLL is not supported clock source of selection '01' will be changed to PCLK0.\nNote: If HXT is not supported clock source of selection '00' will be stopped.\nPlease refer to section 3.2 NuMicro M031/M032.." "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from PCLK0,3: Clock source from internal high speed RC.."
bitfld.long 0x00 1. "PWM1SEL,PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL" "0: Clock source from PLL,1: Clock source from PCLK1"
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bitfld.long 0x00 0. "PWM0SEL,PWM0 Clock Source Selection\nThe peripheral clock source of PWM0 is defined by PWM0SEL" "0: Clock source from PLL,1: Clock source from PCLK0"
group.long 0x1C++0x03
line.long 0x00 "CLK_CLKSEL3,Clock Source Select Control Register 3"
bitfld.long 0x00 28.--30. "UART3SEL,UART3 Clock Source Selection\nNote: If PLL is not supported clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported clock source of selection '000' or '010' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC..,4: Clock source from PCLK1,5: Clock source from internal low speed RC..,?..."
bitfld.long 0x00 24.--26. "UART2SEL,UART2 Clock Source Selection\nNote: If PLL is not supported clock source of selection '001' will be changed to PCLK0.\nNote: If LXT or HXT is not supported clock source of selection '000' or '010' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC..,4: Clock source from PCLK0,5: Clock source from internal low speed RC..,?..."
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bitfld.long 0x00 20.--22. "UART5SEL,UART5 Clock Source Selection\nNote: If PLL is not supported clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported clock source of selection '000' or '010' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC..,4: Clock source from PCLK1,5: Clock source from internal low speed RC..,?..."
bitfld.long 0x00 16.--18. "UART4SEL,UART4 Clock Source Selection\nNote: If PLL is not supported clock source of selection '001' will be changed to PCLK0.\nNote: If LXT or HXT is not supported clock source of selection '000' or '010' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC..,4: Clock source from PCLK0,5: Clock source from internal low speed RC..,?..."
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bitfld.long 0x00 12.--14. "UART7SEL,UART7 Clock Source Selection\nNote: If PLL is not supported clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported clock source of selection '000' or '010' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC..,4: Clock source from PCLK1,5: Clock source from internal low speed RC..,?..."
bitfld.long 0x00 8.--10. "UART6SEL,UART6 Clock Source Selection\nNote: If PLL is not supported clock source of selection '001' will be changed to PCLK0.\nNote: If LXT or HXT is not supported clock source of selection '000' or '010' will be stopped" "0: Clock source from external high speed crystal..,1: Clock source from PLL,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC..,4: Clock source from PCLK0,5: Clock source from internal low speed RC..,?..."
group.long 0x20++0x03
line.long 0x00 "CLK_CLKDIV0,Clock Divider Number Register 0"
hexmask.long.byte 0x00 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source"
bitfld.long 0x00 12.--15. "UART1DIV,UART1 Clock Divide Number From UART1 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "UART0DIV,UART0 Clock Divide Number From UART0 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "USBDIV,USB Clock Divide Number From PLL Clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "CLK_CLKDIV4,Clock Divider Number Register 4"
bitfld.long 0x00 20.--23. "UART7DIV,UART7 Clock Divide Number From UART7 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "UART6DIV,UART6 Clock Divide Number From UART6 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "UART5DIV,UART5 Clock Divide Number From UART5 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "UART4DIV,UART4 Clock Divide Number From UART4 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "UART3DIV,UART3 Clock Divide Number From UART3 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "UART2DIV,UART2 Clock Divide Number From UART2 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x34++0x03
line.long 0x00 "CLK_PCLKDIV,APB Clock Divider Register"
bitfld.long 0x00 4.--6. "APB1DIV,APB1 Clock DIvider\nAPB1 clock can be divided from HCLK\nOthers: Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "APB0DIV,APB0 Clock DIvider\nAPB0 clock can be divided from HCLK\nOthers: Reserved" "0,1,2,3,4,5,6,7"
group.long 0x40++0x03
line.long 0x00 "CLK_PLLCTL,PLL Control Register"
bitfld.long 0x00 23. "STBSEL,PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected" "0: PLL stable time is 6144 PLL source clock..,1: PLL stable time is 16128 PLL source clock.."
bitfld.long 0x00 19. "PLLSRC,PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected" "0: PLL source clock from external high-speed..,1: PLL source clock from 48 MHz internal.."
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bitfld.long 0x00 18. "OE,PLL OE (FOUT Enable) Pin Control (Write Protect)\nNote: This bit is write protected" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
bitfld.long 0x00 17. "BP,PLL Bypass Control (Write Protect)\nNote: This bit is write protected" "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN"
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bitfld.long 0x00 16. "PD,Power-down Mode (Write Protect)\nIf set the PDEN bit to 1 in CLK_PWRCTL register the PLL will enter Power-down mode too.\nNote: This bit is write protected" "0: PLL is in normal mode,1: PLL is in Power-down mode (default)"
bitfld.long 0x00 14.--15. "OUTDIV,PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected" "0,1,2,3"
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bitfld.long 0x00 9.--13. "INDIV,PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--8. 1. "FBDIV,PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected"
rgroup.long 0x50++0x03
line.long 0x00 "CLK_STATUS,Clock Status Monitor Register"
bitfld.long 0x00 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source" "0: Clock switching success,1: Clock switching failure"
bitfld.long 0x00 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: Internal high speed RC oscillator (HIRC)..,1: Internal high speed RC oscillator (HIRC).."
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bitfld.long 0x00 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: Internal low speed RC oscillator (LIRC) clock..,1: Internal low speed RC oscillator (LIRC) clock.."
bitfld.long 0x00 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)\nNote: If PLL is not supported this bit field will be invalid" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled"
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bitfld.long 0x00 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)\nNote: If LXT is not supported this bit field will be invalid" "0: External low speed crystal oscillator (LXT)..,1: External low speed crystal oscillator (LXT).."
bitfld.long 0x00 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)\nNote: If HXT is not supported this bit field will be invalid" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).."
group.long 0x60++0x03
line.long 0x00 "CLK_CLKOCTL,Clock Output Control Register"
bitfld.long 0x00 6. "CLK1HZEN,Clock Output 1Hz Enable Bit" "0: 1 Hz clock output for 32.768 kHz frequency..,1: 1 Hz clock output for 32.768 kHz frequency.."
bitfld.long 0x00 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
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bitfld.long 0x00 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled"
bitfld.long 0x00 0.--3. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70++0x03
line.long 0x00 "CLK_CLKDCTL,Clock Fail Detector Control Register"
bitfld.long 0x00 17. "HXTFQIEN,HXT Clock Frequency Range Detector Interrupt Enable Bit" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).."
bitfld.long 0x00 16. "HXTFQDEN,HXT Clock Frequency Range Detector Enable Bit" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).."
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bitfld.long 0x00 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: External low speed crystal oscillator (LXT)..,1: External low speed crystal oscillator (LXT).."
bitfld.long 0x00 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: External low speed crystal oscillator (LXT)..,1: External low speed crystal oscillator (LXT).."
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bitfld.long 0x00 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).."
bitfld.long 0x00 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).."
group.long 0x74++0x03
line.long 0x00 "CLK_CLKDSTS,Clock Fail Detector Status Register"
bitfld.long 0x00 8. "HXTFQIF,HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).."
bitfld.long 0x00 1. "LXTFIF,LXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0" "0: External low speed crystal oscillator (LXT)..,1: External low speed crystal oscillator (LXT).."
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bitfld.long 0x00 0. "HXTFIF,HXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).."
group.long 0x78++0x03
line.long 0x00 "CLK_CDUPB,Clock Frequency Range Detector Upper Boundary Register"
hexmask.long.word 0x00 0.--9. 1. "UPERBD,HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency is higher than this maximum frequency value the HXT Clock Frequency Range Detector Interrupt Flag.."
group.long 0x7C++0x03
line.long 0x00 "CLK_CDLOWB,Clock Frequency Range Detector Lower Boundary Register"
hexmask.long.word 0x00 0.--9. 1. "LOWERBD,HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency lower than this minimum frequency value the HXT Clock Frequency Range Detector Interrupt Flag will.."
group.long 0x80++0x03
line.long 0x00 "CLK_LDOCTL,LDO Control Register"
group.long 0xB4++0x03
line.long 0x00 "CLK_HXTFSEL,HXT Filter Select Control Register"
bitfld.long 0x00 0. "HXTFSEL,HXT Filter Select \nNote: This bit should not be changed during HXT running" "0: HXT frequency is greater than12 MHz,1: HXT frequency is less than or equal to 12 MHz"
tree.end
tree "CRC (CRC Register Map)"
base ad:0x40031000
group.long 0x00++0x03
line.long 0x00 "CRC_CTL,CRC Control Register"
bitfld.long 0x00 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode" "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,2: CRC-16 Polynomial mode,3: CRC-32 Polynomial mode"
bitfld.long 0x00 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.\nData length is..,?..."
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bitfld.long 0x00 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register" "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
bitfld.long 0x00 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register" "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled"
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bitfld.long 0x00 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
bitfld.long 0x00 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reversed for CRC write data in..,1: Bit order reversed for CRC write data in.."
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bitfld.long 0x00 1. "CHKSINIT,Checksum Initialization\nNote: This bit will be cleared automatically" "0: No effect,1: Initial checksum value by auto reload.."
bitfld.long 0x00 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled"
group.long 0x04++0x03
line.long 0x00 "CRC_DAT,CRC Write Data Register"
hexmask.long 0x00 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if.."
group.long 0x08++0x03
line.long 0x00 "CRC_SEED,CRC Seed Register"
hexmask.long 0x00 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1])"
rgroup.long 0x0C++0x03
line.long 0x00 "CRC_CHECKSUM,CRC Checksum Register"
hexmask.long 0x00 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result"
tree.end
tree "EBI (EBI Register Map)"
base ad:0x40010000
group.long 0x00++0x03
line.long 0x00 "EBI_CTL0,External Bus Interface Bank0 Control Register"
bitfld.long 0x00 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit is only available in EBI_CTL0 register" "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
bitfld.long 0x00 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field is only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/64,7: HCLK/128"
bitfld.long 0x00 4. "CACCESS,Continuous Data Access Mode\nWhen Continuous access mode is enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request" "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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bitfld.long 0x00 3. "ADSEPEN,EBI Address/Data Bus Separating Mode Enable Bit" "0: Address/Data Bus Separating Mode Disabled,1: Address/Data Bus Separating Mode Enabled"
bitfld.long 0x00 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)" "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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bitfld.long 0x00 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
bitfld.long 0x00 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
group.long 0x04++0x03
line.long 0x00 "EBI_TCTL0,External Bus Interface Bank0 Timing Control Register"
bitfld.long 0x00 24.--27. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nNote: When read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "WAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 22. "RAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
bitfld.long 0x00 12.--15. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nNote: When write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--7. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x10++0x03
line.long 0x00 "EBI_CTL1,External Bus Interface Bank1 Control Register"
bitfld.long 0x00 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit is only available in EBI_CTL0 register" "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
bitfld.long 0x00 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field is only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/64,7: HCLK/128"
bitfld.long 0x00 4. "CACCESS,Continuous Data Access Mode\nWhen Continuous access mode is enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request" "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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bitfld.long 0x00 3. "ADSEPEN,EBI Address/Data Bus Separating Mode Enable Bit" "0: Address/Data Bus Separating Mode Disabled,1: Address/Data Bus Separating Mode Enabled"
bitfld.long 0x00 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)" "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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bitfld.long 0x00 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
bitfld.long 0x00 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
group.long 0x14++0x03
line.long 0x00 "EBI_TCTL1,External Bus Interface Bank1 Timing Control Register"
bitfld.long 0x00 24.--27. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nNote: When read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "WAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 22. "RAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
bitfld.long 0x00 12.--15. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nNote: When write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--7. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "FMC (FMC Register Map)"
base ad:0x4000C000
group.long 0x00++0x03
line.long 0x00 "FMC_ISPCTL,ISP Control Register"
bitfld.long 0x00 24. "INTEN,ISP Interrupt Enabled Bit (Write Protect)\nNote: This bit is write protected" "0: ISP INT Disabled,1: ISP INT Enabled"
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN.." "0,1"
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bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write-protected" "0: LDROM cannot be updated,1: LDROM can be updated"
bitfld.long 0x00 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: CONFIG cannot be updated,1: CONFIG can be updated"
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bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in.."
bitfld.long 0x00 2. "SPUEN,SPROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: SPROM cannot be updated,1: SPROM can be updated"
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bitfld.long 0x00 1. "BS,Boot Selection (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively" "0: Booting from APROM,1: Booting from LDROM"
bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect)\nNote: This bit is write-protected" "?,1: ISP function Enabled"
group.long 0x04++0x03
line.long 0x00 "FMC_ISPADDR,ISP Address Register"
hexmask.long 0x00 0.--31. 1. "ISPADDR,ISP Address\nThe M031/M032 series is equipped with embedded Flash"
group.long 0x08++0x03
line.long 0x00 "FMC_ISPDAT,ISP Data Register"
hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation"
group.long 0x0C++0x03
line.long 0x00 "FMC_ISPCMD,ISP Command Register"
hexmask.long.byte 0x00 0.--6. 1. "CMD,ISP CMD\nISP command table is shown below:\nThe other commands are invalid"
group.long 0x10++0x03
line.long 0x00 "FMC_ISPTRG,ISP Trigger Control Register"
bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished" "0: ISP operation is finished,1: ISP is progressed"
rgroup.long 0x14++0x03
line.long 0x00 "FMC_DFBA,Data Flash Base Address"
hexmask.long 0x00 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates Data Flash start address"
group.long 0x18++0x03
line.long 0x00 "FMC_FTCTL,Flash Access Time Control Register"
bitfld.long 0x00 9. "CACHEINV,Flash Cache Invalidation (Write Protect)\n" "0: Flash Cache Invalidation finished (default),1: Flash Cache Invalidation"
bitfld.long 0x00 7. "BBOFF,Flash Branch Buffer Disable Control (Write Protect)\n" "0: Flash Branch Buffer function Enabled (default),1: Flash Branch Buffer function Disabled"
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bitfld.long 0x00 4.--6. "FOM,Frequency Optimization Mode (Write Protect)\nThe M031/M032 series support adjustable Flash access timing to optimize the Flash access cycles in different system working frequency.\nFor 16/32/64/128 Kbytes Flash:\nNote: This bit is write-protected" "0: Frequency is less than or equal to 48 MHz,1: Frequency is less than or equal to 24..,2: Frequency is less than or equal to 36 MHz,3: Frequency is less than or equal to 60 MHz,?..."
group.long 0x40++0x03
line.long 0x00 "FMC_ISPSTS,ISP Status Register"
bitfld.long 0x00 31. "SCODE,Security Code Active Flag\nThis bit is set to 1 by hardware when detecting SPROM secured code is active at Flash initialization or software writes 1 to this bit to make secured code active this bit is only cleared by SPROM page erase operation" "0: SPROM secured code is inactive,1: SPROM secured code is active"
bitfld.long 0x00 30. "FBS,Flash Bank Select Indicator\nThis bit indicates which APROM address model is selected to boot.\nNote: Only supported in 256/512 Kbytes Flash" "0: Address model OP0 is selected to boot,1: Address model OP1 is selected to boot"
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hexmask.long.tbyte 0x00 9.--29. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0] 9'h000} ~ {VECMAP[20:0] 9'h1FF} except SPROM.\nVECMAP [18:12] should be 0"
bitfld.long 0x00 8. "INTFLAG,ISP Command Finish Interrupt Flag\nNote: Only supported in 256/512 Kbytes Flash" "0: ISP Not Finished,1: ISP done or ISPFF set"
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bitfld.long 0x00 7. "ALLONE,Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1 and cleared if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit can also be cleared by writing 1" "0: Flash bits are not all 1 after'Run Flash..,1: All of Flash bits are 1 after'Run Flash.."
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1"
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rbitfld.long 0x00 5. "PGFF,Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification" "0: Flash Program is successful,1: Flash Program is failed"
rbitfld.long 0x00 1.--2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened" "0: LDROM with IAP mode,1: LDROM without IAP mode,2: APROM with IAP mode,3: APROM without IAP mode"
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rbitfld.long 0x00 0. "ISPBUSY,ISP BUSY (Read Only)" "0: ISP operation is finished,1: ISP operation is busy"
group.long 0x80++0x03
line.long 0x00 "FMC_MPDAT0,ISP Data0 Register"
hexmask.long 0x00 0.--31. 1. "ISPDAT0,ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming and it is also the mirror of FMC_ISPDAT both registers keep the same data"
group.long 0x84++0x03
line.long 0x00 "FMC_MPDAT1,ISP Data1 Register"
hexmask.long 0x00 0.--31. 1. "ISPDAT1,ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming"
group.long 0x88++0x03
line.long 0x00 "FMC_MPDAT2,ISP Data2 Register"
hexmask.long 0x00 0.--31. 1. "ISPDAT2,ISP Data 2\nThis register is the third 32-bit data for multi-word programming"
group.long 0x8C++0x03
line.long 0x00 "FMC_MPDAT3,ISP Data3 Register"
hexmask.long 0x00 0.--31. 1. "ISPDAT3,ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming"
rgroup.long 0xC0++0x03
line.long 0x00 "FMC_MPSTS,ISP Multi-program Status Register"
bitfld.long 0x00 7. "D3,ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto cleared to 0 when the FMC_MPDAT3 data is programmed to Flash complete" "0: FMC_MPDAT3 register is empty or program to..,1: FMC_MPDAT3 register has been written and not.."
bitfld.long 0x00 6. "D2,ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto cleared to 0 when the FMC_MPDAT2 data is programmed to Flash complete" "0: FMC_MPDAT2 register is empty or program to..,1: FMC_MPDAT2 register has been written and not.."
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bitfld.long 0x00 5. "D1,ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto cleared to 0 when the FMC_MPDAT1 data is programmed to Flash complete" "0: FMC_MPDAT1 register is empty or program to..,1: FMC_MPDAT1 register has been written and not.."
bitfld.long 0x00 4. "D0,ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto cleared to 0 when the FMC_MPDAT0 data is programmed to Flash complete" "0: FMC_MPDAT0 register is empty or program to..,1: FMC_MPDAT0 register has been written and not.."
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bitfld.long 0x00 2. "ISPFF,ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1"
bitfld.long 0x00 1. "PPGO,ISP Multi-program Status (Read Only)" "0: ISP multi-word program operation is not active,1: ISP multi-word program operation is in progress"
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bitfld.long 0x00 0. "MPBUSY,ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of.." "0: ISP Multi-Word program operation is finished,1: ISP Multi-Word program operation is progressed"
rgroup.long 0xC4++0x03
line.long 0x00 "FMC_MPADDR,ISP Multi-program Address Register"
hexmask.long 0x00 0.--31. 1. "MPADDR,ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete"
tree.end
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
base ad:0x40004000
group.long 0x00++0x03
line.long 0x00 "PA_MODE,PA I/O Mode Control"
bitfld.long 0x00 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
group.long 0x04++0x03
line.long 0x00 "PA_DINOFF,PA Digital Input Path Disable Control"
bitfld.long 0x00 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
group.long 0x08++0x03
line.long 0x00 "PA_DOUT,PA Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0x0C++0x03
line.long 0x00 "PA_DATMSK,PA Data Output Write Mask"
bitfld.long 0x00 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
rgroup.long 0x10++0x03
line.long 0x00 "PA_PIN,PA Pin Value"
bitfld.long 0x00 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x14++0x03
line.long 0x00 "PA_DBEN,PA De-bounce Enable Control Register"
bitfld.long 0x00 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
group.long 0x18++0x03
line.long 0x00 "PA_INTTYPE,PA Interrupt Trigger Type Control"
bitfld.long 0x00 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x1C++0x03
line.long 0x00 "PA_INTEN,PA Interrupt Enable Control Register"
bitfld.long 0x00 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
group.long 0x20++0x03
line.long 0x00 "PA_INTSRC,PA Interrupt Source Flag"
bitfld.long 0x00 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
group.long 0x40++0x03
line.long 0x00 "PB_MODE,PB I/O Mode Control"
bitfld.long 0x00 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
group.long 0x44++0x03
line.long 0x00 "PB_DINOFF,PB Digital Input Path Disable Control"
bitfld.long 0x00 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
group.long 0x48++0x03
line.long 0x00 "PB_DOUT,PB Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0x4C++0x03
line.long 0x00 "PB_DATMSK,PB Data Output Write Mask"
bitfld.long 0x00 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
group.long 0x50++0x03
line.long 0x00 "PB_PIN,PB Pin Value"
rbitfld.long 0x00 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x54++0x03
line.long 0x00 "PB_DBEN,PB De-bounce Enable Control Register"
bitfld.long 0x00 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
group.long 0x58++0x03
line.long 0x00 "PB_INTTYPE,PB Interrupt Trigger Type Control"
bitfld.long 0x00 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x5C++0x03
line.long 0x00 "PB_INTEN,PB Interrupt Enable Control Register"
bitfld.long 0x00 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
group.long 0x60++0x03
line.long 0x00 "PB_INTSRC,PB Interrupt Source Flag"
bitfld.long 0x00 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
group.long 0x80++0x03
line.long 0x00 "PC_MODE,PC I/O Mode Control"
bitfld.long 0x00 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
group.long 0x84++0x03
line.long 0x00 "PC_DINOFF,PC Digital Input Path Disable Control"
bitfld.long 0x00 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
group.long 0x88++0x03
line.long 0x00 "PC_DOUT,PC Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0x8C++0x03
line.long 0x00 "PC_DATMSK,PC Data Output Write Mask"
bitfld.long 0x00 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
group.long 0x90++0x03
line.long 0x00 "PC_PIN,PC Pin Value"
rbitfld.long 0x00 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x94++0x03
line.long 0x00 "PC_DBEN,PC De-bounce Enable Control Register"
bitfld.long 0x00 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
group.long 0x98++0x03
line.long 0x00 "PC_INTTYPE,PC Interrupt Trigger Type Control"
bitfld.long 0x00 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x9C++0x03
line.long 0x00 "PC_INTEN,PC Interrupt Enable Control Register"
bitfld.long 0x00 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
group.long 0xA0++0x03
line.long 0x00 "PC_INTSRC,PC Interrupt Source Flag"
bitfld.long 0x00 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
group.long 0xC0++0x03
line.long 0x00 "PD_MODE,PD I/O Mode Control"
bitfld.long 0x00 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
group.long 0xC4++0x03
line.long 0x00 "PD_DINOFF,PD Digital Input Path Disable Control"
bitfld.long 0x00 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
group.long 0xC8++0x03
line.long 0x00 "PD_DOUT,PD Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0xCC++0x03
line.long 0x00 "PD_DATMSK,PD Data Output Write Mask"
bitfld.long 0x00 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
group.long 0xD0++0x03
line.long 0x00 "PD_PIN,PD Pin Value"
rbitfld.long 0x00 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0xD4++0x03
line.long 0x00 "PD_DBEN,PD De-bounce Enable Control Register"
bitfld.long 0x00 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
group.long 0xD8++0x03
line.long 0x00 "PD_INTTYPE,PD Interrupt Trigger Type Control"
bitfld.long 0x00 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0xDC++0x03
line.long 0x00 "PD_INTEN,PD Interrupt Enable Control Register"
bitfld.long 0x00 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
group.long 0xE0++0x03
line.long 0x00 "PD_INTSRC,PD Interrupt Source Flag"
bitfld.long 0x00 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
group.long 0x100++0x03
line.long 0x00 "PE_MODE,PE I/O Mode Control"
bitfld.long 0x00 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
group.long 0x104++0x03
line.long 0x00 "PE_DINOFF,PE Digital Input Path Disable Control"
bitfld.long 0x00 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
group.long 0x108++0x03
line.long 0x00 "PE_DOUT,PE Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0x10C++0x03
line.long 0x00 "PE_DATMSK,PE Data Output Write Mask"
bitfld.long 0x00 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
group.long 0x110++0x03
line.long 0x00 "PE_PIN,PE Pin Value"
rbitfld.long 0x00 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x114++0x03
line.long 0x00 "PE_DBEN,PE De-bounce Enable Control Register"
bitfld.long 0x00 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
group.long 0x118++0x03
line.long 0x00 "PE_INTTYPE,PE Interrupt Trigger Type Control"
bitfld.long 0x00 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x11C++0x03
line.long 0x00 "PE_INTEN,PE Interrupt Enable Control Register"
bitfld.long 0x00 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
group.long 0x120++0x03
line.long 0x00 "PE_INTSRC,PE Interrupt Source Flag"
bitfld.long 0x00 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
group.long 0x140++0x03
line.long 0x00 "PF_MODE,PF I/O Mode Control"
bitfld.long 0x00 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
group.long 0x144++0x03
line.long 0x00 "PF_DINOFF,PF Digital Input Path Disable Control"
bitfld.long 0x00 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
group.long 0x148++0x03
line.long 0x00 "PF_DOUT,PF Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0x14C++0x03
line.long 0x00 "PF_DATMSK,PF Data Output Write Mask"
bitfld.long 0x00 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
group.long 0x150++0x03
line.long 0x00 "PF_PIN,PF Pin Value"
rbitfld.long 0x00 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x154++0x03
line.long 0x00 "PF_DBEN,PF De-bounce Enable Control Register"
bitfld.long 0x00 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
group.long 0x158++0x03
line.long 0x00 "PF_INTTYPE,PF Interrupt Trigger Type Control"
bitfld.long 0x00 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x15C++0x03
line.long 0x00 "PF_INTEN,PF Interrupt Enable Control Register"
bitfld.long 0x00 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
group.long 0x160++0x03
line.long 0x00 "PF_INTSRC,PF Interrupt Source Flag"
bitfld.long 0x00 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
group.long 0x180++0x03
line.long 0x00 "PG_MODE,PG I/O Mode Control"
bitfld.long 0x00 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
group.long 0x184++0x03
line.long 0x00 "PG_DINOFF,PG Digital Input Path Disable Control"
bitfld.long 0x00 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
group.long 0x188++0x03
line.long 0x00 "PG_DOUT,PG Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0x18C++0x03
line.long 0x00 "PG_DATMSK,PG Data Output Write Mask"
bitfld.long 0x00 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
group.long 0x190++0x03
line.long 0x00 "PG_PIN,PG Pin Value"
rbitfld.long 0x00 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x194++0x03
line.long 0x00 "PG_DBEN,PG De-bounce Enable Control Register"
bitfld.long 0x00 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
group.long 0x198++0x03
line.long 0x00 "PG_INTTYPE,PG Interrupt Trigger Type Control"
bitfld.long 0x00 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x19C++0x03
line.long 0x00 "PG_INTEN,PG Interrupt Enable Control Register"
bitfld.long 0x00 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
group.long 0x1A0++0x03
line.long 0x00 "PG_INTSRC,PG Interrupt Source Flag"
bitfld.long 0x00 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
group.long 0x1C0++0x03
line.long 0x00 "PH_MODE,PH I/O Mode Control"
bitfld.long 0x00 30.--31. "MODE15,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 28.--29. "MODE14,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 24.--25. "MODE12,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 20.--21. "MODE10,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 16.--17. "MODE8,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "MODE6,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "MODE4,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "MODE2,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "MODE0,Port A-H I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
group.long 0x1C4++0x03
line.long 0x00 "PH_DINOFF,PH Digital Input Path Disable Control"
bitfld.long 0x00 31. "DINOFF15,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 30. "DINOFF14,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 28. "DINOFF12,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 26. "DINOFF10,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 24. "DINOFF8,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 22. "DINOFF6,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 20. "DINOFF4,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 18. "DINOFF2,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
bitfld.long 0x00 16. "DINOFF0,Port A-H Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
group.long 0x1C8++0x03
line.long 0x00 "PH_DOUT,PH Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-H Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0x1CC++0x03
line.long 0x00 "PH_DATMSK,PH Data Output Write Mask"
bitfld.long 0x00 15. "DATMSK15,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 14. "DATMSK14,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 12. "DATMSK12,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 10. "DATMSK10,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 8. "DATMSK8,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 6. "DATMSK6,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 4. "DATMSK4,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 2. "DATMSK2,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
bitfld.long 0x00 0. "DATMSK0,Port A-H Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
group.long 0x1D0++0x03
line.long 0x00 "PH_PIN,PH Pin Value"
rbitfld.long 0x00 15. "PIN15,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port A-H Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x1D4++0x03
line.long 0x00 "PH_DBEN,PH De-bounce Enable Control Register"
bitfld.long 0x00 15. "DBEN15,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 14. "DBEN14,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 12. "DBEN12,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 10. "DBEN10,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 8. "DBEN8,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 6. "DBEN6,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 4. "DBEN4,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 2. "DBEN2,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
bitfld.long 0x00 0. "DBEN0,Port A-H Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
group.long 0x1D8++0x03
line.long 0x00 "PH_INTTYPE,PH Interrupt Trigger Type Control"
bitfld.long 0x00 15. "TYPE15,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 14. "TYPE14,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 12. "TYPE12,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 10. "TYPE10,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 8. "TYPE8,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "TYPE6,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "TYPE4,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "TYPE2,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "TYPE0,Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x1DC++0x03
line.long 0x00 "PH_INTEN,PH Interrupt Enable Control Register"
bitfld.long 0x00 31. "RHIEN15,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 30. "RHIEN14,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 28. "RHIEN12,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 26. "RHIEN10,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 24. "RHIEN8,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 22. "RHIEN6,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 20. "RHIEN4,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 18. "RHIEN2,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
bitfld.long 0x00 16. "RHIEN0,Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 14. "FLIEN14,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 12. "FLIEN12,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 10. "FLIEN10,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 8. "FLIEN8,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 6. "FLIEN6,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 4. "FLIEN4,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 2. "FLIEN2,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
bitfld.long 0x00 0. "FLIEN0,Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
group.long 0x1E0++0x03
line.long 0x00 "PH_INTSRC,PH Interrupt Source Flag"
bitfld.long 0x00 15. "INTSRC15,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 14. "INTSRC14,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 12. "INTSRC12,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 10. "INTSRC10,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 8. "INTSRC8,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 6. "INTSRC6,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 4. "INTSRC4,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 2. "INTSRC2,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
bitfld.long 0x00 0. "INTSRC0,Port A-H Pin[n] Interrupt Source Flag\nWrite Operation :\nNote: \nThe PC.15/PF.12~13/PG.0~1 5~8/PH.0~3 12~15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
group.long 0x440++0x03
line.long 0x00 "GPIO_DBCTL,Interrupt De-bounce Control Register"
bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 38.4.."
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
group.long 0x800++0x03
line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x804++0x03
line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x808++0x03
line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x80C++0x03
line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x810++0x03
line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x814++0x03
line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x818++0x03
line.long 0x00 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x81C++0x03
line.long 0x00 "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x820++0x03
line.long 0x00 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x824++0x03
line.long 0x00 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x828++0x03
line.long 0x00 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x82C++0x03
line.long 0x00 "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x830++0x03
line.long 0x00 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x834++0x03
line.long 0x00 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x838++0x03
line.long 0x00 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x83C++0x03
line.long 0x00 "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x840++0x03
line.long 0x00 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x844++0x03
line.long 0x00 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x848++0x03
line.long 0x00 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x84C++0x03
line.long 0x00 "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x850++0x03
line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x854++0x03
line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x858++0x03
line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x85C++0x03
line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x860++0x03
line.long 0x00 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x864++0x03
line.long 0x00 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x868++0x03
line.long 0x00 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x86C++0x03
line.long 0x00 "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x870++0x03
line.long 0x00 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x874++0x03
line.long 0x00 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x878++0x03
line.long 0x00 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x87C++0x03
line.long 0x00 "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
group.long 0x880++0x03
line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x884++0x03
line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x888++0x03
line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x88C++0x03
line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x890++0x03
line.long 0x00 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x894++0x03
line.long 0x00 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x898++0x03
line.long 0x00 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x89C++0x03
line.long 0x00 "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x8A0++0x03
line.long 0x00 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x8A4++0x03
line.long 0x00 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x8A8++0x03
line.long 0x00 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x8AC++0x03
line.long 0x00 "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x8B0++0x03
line.long 0x00 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x8B4++0x03
line.long 0x00 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x8B8++0x03
line.long 0x00 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
group.long 0x8C0++0x03
line.long 0x00 "PD0_PDIO,GPIO PD.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x8C4++0x03
line.long 0x00 "PD1_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8C8++0x03
line.long 0x00 "PD2_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8CC++0x03
line.long 0x00 "PD3_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8D0++0x03
line.long 0x00 "PD4_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8D4++0x03
line.long 0x00 "PD5_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8D8++0x03
line.long 0x00 "PD6_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8DC++0x03
line.long 0x00 "PD7_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8E0++0x03
line.long 0x00 "PD8_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8E4++0x03
line.long 0x00 "PD9_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8E8++0x03
line.long 0x00 "PD10_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8EC++0x03
line.long 0x00 "PD11_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8F0++0x03
line.long 0x00 "PD12_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8F4++0x03
line.long 0x00 "PD13_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8F8++0x03
line.long 0x00 "PD14_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x8FC++0x03
line.long 0x00 "PD15_PDIO,GPIO PD.n Pin Data Input/Output Register"
group.long 0x900++0x03
line.long 0x00 "PE0_PDIO,GPIO PE.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x904++0x03
line.long 0x00 "PE1_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x908++0x03
line.long 0x00 "PE2_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x90C++0x03
line.long 0x00 "PE3_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x910++0x03
line.long 0x00 "PE4_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x914++0x03
line.long 0x00 "PE5_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x918++0x03
line.long 0x00 "PE6_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x91C++0x03
line.long 0x00 "PE7_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x920++0x03
line.long 0x00 "PE8_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x924++0x03
line.long 0x00 "PE9_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x928++0x03
line.long 0x00 "PE10_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x92C++0x03
line.long 0x00 "PE11_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x930++0x03
line.long 0x00 "PE12_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x934++0x03
line.long 0x00 "PE13_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x938++0x03
line.long 0x00 "PE14_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x93C++0x03
line.long 0x00 "PE15_PDIO,GPIO PE.n Pin Data Input/Output Register"
group.long 0x940++0x03
line.long 0x00 "PFn_PDIO,GPIO PF.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x980++0x03
line.long 0x00 "PGn_PDIO,GPIO PG.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x9D0++0x03
line.long 0x00 "PH4_PDIO,GPIO PH.n Pin Data Input/Output Register"
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x9D4++0x03
line.long 0x00 "PH5_PDIO,GPIO PH.n Pin Data Input/Output Register"
group.long 0x9D8++0x03
line.long 0x00 "PH6_PDIO,GPIO PH.n Pin Data Input/Output Register"
group.long 0x9DC++0x03
line.long 0x00 "PH7_PDIO,GPIO PH.n Pin Data Input/Output Register"
group.long 0x9E0++0x03
line.long 0x00 "PH8_PDIO,GPIO PH.n Pin Data Input/Output Register"
group.long 0x9E4++0x03
line.long 0x00 "PH9_PDIO,GPIO PH.n Pin Data Input/Output Register"
group.long 0x9E8++0x03
line.long 0x00 "PH10_PDIO,GPIO PH.n Pin Data Input/Output Register"
group.long 0x9EC++0x03
line.long 0x00 "PH11_PDIO,GPIO PH.n Pin Data Input/Output Register"
tree.end
tree "HDIV (HDIV Register Map)"
base ad:0x40014000
group.long 0x00++0x03
line.long 0x00 "DIVIDEND,Dividend Source Register"
hexmask.long 0x00 0.--31. 1. "DIVIDEND,Dividend Source\nThis register is given the dividend of divider before calculation starts"
group.long 0x04++0x03
line.long 0x00 "DIVISOR,Divisor Source Resister"
hexmask.long.word 0x00 0.--15. 1. "DIVISOR,Divisor Source\nThis register is provided with the divisor of divider before calculation starts.\nNote: When this register is written hardware divider will start calculation"
group.long 0x08++0x03
line.long 0x00 "DIVQUO,Quotient Result Resister"
hexmask.long 0x00 0.--31. 1. "QUOTIENT,Quotient Result\nThis register holds the quotient result of divider after calculation is complete"
group.long 0x0C++0x03
line.long 0x00 "DIVREM,Remainder Result Register"
hexmask.long.word 0x00 16.--31. 1. "REMAINDER31_16,Sign Extension of REMAINDER[15:0]\nThe remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]) with sign extension (REMAINDER[31:16]) to 32-bit integer"
hexmask.long.word 0x00 0.--15. 1. "REMAINDER15_0,Remainder Result\nThis register holds the remainder result of divider after calculation is complete"
rgroup.long 0x10++0x03
line.long 0x00 "DIVSTS,Divider Status Register"
bitfld.long 0x00 1. "DIV0,Divisor Zero Warning (Read Only)\nNote: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written" "0: The divisor is not 0,1: The divisor is 0"
tree.end
tree "I2C (Inter-Integrated Circuit)"
repeat 2. (list 0. 1.) (list ad:0x40080000 ad:0x40081000)
tree "I2C$1"
base $2
group.long 0x00++0x03
line.long 0x00 "I2C_CTL0,I2C Control Register 0"
bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
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bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected" "0,1"
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bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware" "0,1"
bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
group.long 0x04++0x03
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
group.long 0x08++0x03
line.long 0x00 "I2C_DAT,I2C Data Register"
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port"
rgroup.long 0x0C++0x03
line.long 0x00 "I2C_STATUS0,I2C Status Register 0"
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status"
group.long 0x10++0x03
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
hexmask.long.word 0x00 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4"
group.long 0x14++0x03
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled"
bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1"
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
group.long ($2+0x18)++0x03
line.long 0x00 "I2C_ADDR$1,I2C Slave Address Register $1"
hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x24)++0x03
line.long 0x00 "I2C_ADDRMSK$1,I2C Slave Address Mask Register $1"
hexmask.long.byte 0x00 1.--7. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
repeat.end
group.long 0x3C++0x03
line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received" "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
group.long 0x40++0x03
line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
rbitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame (Read Only)\nNote: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit" "0: Write command be record on the address match..,1: Read command be record on the address match.."
bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1"
group.long 0x44++0x03
line.long 0x00 "I2C_CTL1,I2C Control Register 1"
bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.."
bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
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bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
group.long 0x48++0x03
line.long 0x00 "I2C_STATUS1,I2C Status Register 1"
rbitfld.long 0x00 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
group.long 0x4C++0x03
line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register"
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode"
hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs"
group.long 0x50++0x03
line.long 0x00 "I2C_BUSCTL,I2C Bus Management Control Register"
bitfld.long 0x00 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
bitfld.long 0x00 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x00 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock..,1: There is SI interrupt in the 9th clock cycle.."
bitfld.long 0x00 10. "PECCLR,PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected" "0: PEC calculation is cleared by 'Repeat Start'..,1: PEC calculation is cleared by 'Repeat Start'.."
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bitfld.long 0x00 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle" "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period.."
bitfld.long 0x00 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x00 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition" "0: The system management function Disabled,1: The system management function Enabled"
bitfld.long 0x00 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x00 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
bitfld.long 0x00 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x00 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
bitfld.long 0x00 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable,1: Device default address Enabled"
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bitfld.long 0x00 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode the bit should be enabled after wake-up if needed PEC calculation" "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
bitfld.long 0x00 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit" "0: Slave byte control Disabled,1: Slave byte control Enabled"
group.long 0x54++0x03
line.long 0x00 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
bitfld.long 0x00 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled"
bitfld.long 0x00 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x00 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCLK low time-out interrupt Disabled.\nBus..,1: SCLK low time-out interrupt Enabled.\nBus.."
bitfld.long 0x00 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection..,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x00 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
group.long 0x58++0x03
line.long 0x00 "I2C_BUSSTS,I2C Bus Management Status Register"
bitfld.long 0x00 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: PEC transmission/ receive is not finished..,1: PEC transmission/ receive is finished when.."
bitfld.long 0x00 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit" "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x00 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit" "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
rbitfld.long 0x00 4. "SCTLDIN,Bus Suspend or Control Signal Input Status (Read Only)" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x00 3. "ALERT,SMBus Alert Status \nNote: 1" "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is.."
bitfld.long 0x00 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit" "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x00 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: Byte count transmission/ receive is not..,1: Byte count transmission/ receive is finished.."
rbitfld.long 0x00 0. "BUSY,Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus" "0: Bus is IDLE (both SCLK and SDA High),1: Bus is busy"
group.long 0x5C++0x03
line.long 0x00 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
hexmask.long.word 0x00 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set"
rgroup.long 0x60++0x03
line.long 0x00 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
hexmask.long.byte 0x00 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
group.long 0x64++0x03
line.long 0x00 "I2C_BUSTOUT,I2C Bus Management Timer Register"
hexmask.long.byte 0x00 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]).."
group.long 0x68++0x03
line.long 0x00 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
hexmask.long.byte 0x00 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set"
tree.end
repeat.end
tree.end
tree "NMI (NMI Register Map)"
base ad:0x40000300
group.long 0x00++0x03
line.long 0x00 "NMIEN,NMI Source Interrupt Enable Register"
bitfld.long 0x00 15. "UART1_INT,UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled"
bitfld.long 0x00 14. "UART0_INT,UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled"
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bitfld.long 0x00 13. "EINT5,External Interrupt From PB.7 PD.12 or PF.14 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.7 PD.12 or PF.14..,1: External interrupt from PB.7 PD.12 or PF.14.."
bitfld.long 0x00 12. "EINT4,External Interrupt From PA.8 PB.6 or PF.15 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.8 PB.6 or PF.15..,1: External interrupt from PA.8 PB.6 or PF.15.."
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bitfld.long 0x00 11. "EINT3,External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.2 or PC.7 pin NMI..,1: External interrupt from PB.2 or PC.7 pin NMI.."
bitfld.long 0x00 10. "EINT2,External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.3 or PC.6 pin NMI..,1: External interrupt from PB.3 or PC.6 pin NMI.."
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bitfld.long 0x00 9. "EINT1,External Interrupt From PA.7 PB.4 or PD.15 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.7 PB.4 or PD.15..,1: External interrupt from PA.7 PB.4 or PD.15.."
bitfld.long 0x00 8. "EINT0,External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.6 or PB.5 pin NMI..,1: External interrupt from PA.6 or PB.5 pin NMI.."
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bitfld.long 0x00 6. "RTC_INT,RTC NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: RTC NMI source Disabled,1: RTC NMI source Enabled"
bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: Clock fail detected and IRC Auto Trim..,1: Clock fail detected and IRC Auto Trim.."
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bitfld.long 0x00 3. "SRAM_PERR,SRAM ParityCheck Error NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: SRAM parity check error NMI source Disabled,1: SRAM parity check error NMI source Enabled"
bitfld.long 0x00 2. "PWRWU_INT,Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
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bitfld.long 0x00 1. "IRC_INT,IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled"
bitfld.long 0x00 0. "BODOUT,BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "NMISTS,NMI Source Interrupt Status Register"
bitfld.long 0x00 15. "UART1_INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
bitfld.long 0x00 14. "UART0_INT,UART0 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
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bitfld.long 0x00 13. "EINT5,External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.7 or PF.14..,1: External Interrupt from PB.7 or PF.14.."
bitfld.long 0x00 12. "EINT4,External Interrupt From PA.8 PB.6 or PF.15 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.8 PB.6 or PF.15..,1: External Interrupt from PA.8 PB.6 or PF.15.."
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bitfld.long 0x00 11. "EINT3,External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.2 or PC.7..,1: External Interrupt from PB.2 or PC.7.."
bitfld.long 0x00 10. "EINT2,External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.3 or PC.6..,1: External Interrupt from PB.3 or PC.6.."
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bitfld.long 0x00 9. "EINT1,External Interrupt From PA.7 PB.4 or PD.15 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.7 PB.4 or PD.15..,1: External Interrupt from PA.7 PB.4 or PD.15.."
bitfld.long 0x00 8. "EINT0,External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.6 or PB.5..,1: External Interrupt from PA.6 or PB.5.."
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bitfld.long 0x00 6. "RTC_INT,RTC Interrupt Flag (Read Only)" "0: RTC interrupt is deasserted,1: RTC interrupt is asserted"
bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only)" "0: Clock fail detected or IRC Auto Trim..,1: Clock fail detected or IRC Auto Trim.."
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bitfld.long 0x00 3. "SRAM_PERR,SRAM ParityCheck Error Interrupt Flag (Read Only)" "0: SRAM parity check error interrupt is deasserted,1: SRAM parity check error interrupt is asserted"
bitfld.long 0x00 2. "PWRWU_INT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
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bitfld.long 0x00 1. "IRC_INT,IRC TRIM Interrupt Flag (Read Only)" "0: HIRC TRIM interrupt is deasserted,1: HIRC TRIM interrupt is asserted"
bitfld.long 0x00 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
tree.end
tree "NVIC (NVIC Register Map)"
base ad:0xE000E100
group.long 0x00++0x03
line.long 0x00 "NVIC_ISER0,IRQ0 ~ IRQ31 Set-enable Control Register"
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0 registers enable interrupts and show which interrupts are enabled\nWrite Operation"
group.long 0x80++0x03
line.long 0x00 "NVIC_ICER0,IRQ0 ~ IRQ31 Clear-enable Control Register"
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
group.long 0x100++0x03
line.long 0x00 "NVIC_ISPR0,IRQ0 ~ IRQ31 Set-pending Control Register"
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation"
group.long 0x180++0x03
line.long 0x00 "NVIC_ICPR0,IRQ0 ~ IRQ31 Clear-pending Control Register"
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation"
group.long 0x200++0x03
line.long 0x00 "NVIC_IABR0,IRQ0 ~ IRQ31 Active Bit Register"
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0 registers indicate which interrupts are active"
tree.end
tree "PDMA (PDMA Register Map)"
base ad:0x40008000
group.long 0x00++0x03
line.long 0x00 "PDMA_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
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bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
group.long 0x10++0x03
line.long 0x00 "PDMA_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
newline
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
group.long 0x20++0x03
line.long 0x00 "PDMA_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
newline
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
group.long 0x30++0x03
line.long 0x00 "PDMA_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
newline
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
group.long 0x40++0x03
line.long 0x00 "PDMA_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
newline
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
group.long 0x50++0x03
line.long 0x00 "PDMA_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
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bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
newline
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
group.long 0x60++0x03
line.long 0x00 "PDMA_DSCT6_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
newline
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
newline
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
newline
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
group.long 0x70++0x03
line.long 0x00 "PDMA_DSCT7_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
newline
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
newline
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
group.long 0x80++0x03
line.long 0x00 "PDMA_DSCT8_CTL,Descriptor Table Control Register of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
newline
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function is not supported in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
newline
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
newline
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
group.long 0x04++0x03
line.long 0x00 "PDMA_DSCT0_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
group.long 0x14++0x03
line.long 0x00 "PDMA_DSCT1_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
group.long 0x24++0x03
line.long 0x00 "PDMA_DSCT2_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
group.long 0x34++0x03
line.long 0x00 "PDMA_DSCT3_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
group.long 0x44++0x03
line.long 0x00 "PDMA_DSCT4_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
group.long 0x54++0x03
line.long 0x00 "PDMA_DSCT5_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
group.long 0x64++0x03
line.long 0x00 "PDMA_DSCT6_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
group.long 0x74++0x03
line.long 0x00 "PDMA_DSCT7_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
group.long 0x84++0x03
line.long 0x00 "PDMA_DSCT8_SA,Source Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
group.long 0x08++0x03
line.long 0x00 "PDMA_DSCT0_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
group.long 0x18++0x03
line.long 0x00 "PDMA_DSCT1_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
group.long 0x28++0x03
line.long 0x00 "PDMA_DSCT2_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
group.long 0x38++0x03
line.long 0x00 "PDMA_DSCT3_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
group.long 0x48++0x03
line.long 0x00 "PDMA_DSCT4_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
group.long 0x58++0x03
line.long 0x00 "PDMA_DSCT5_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
group.long 0x68++0x03
line.long 0x00 "PDMA_DSCT6_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
group.long 0x78++0x03
line.long 0x00 "PDMA_DSCT7_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
group.long 0x88++0x03
line.long 0x00 "PDMA_DSCT8_DA,Destination Address Register of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
group.long 0x0C++0x03
line.long 0x00 "PDMA_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
group.long 0x1C++0x03
line.long 0x00 "PDMA_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
group.long 0x2C++0x03
line.long 0x00 "PDMA_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
group.long 0x3C++0x03
line.long 0x00 "PDMA_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
group.long 0x4C++0x03
line.long 0x00 "PDMA_DSCT4_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
group.long 0x5C++0x03
line.long 0x00 "PDMA_DSCT5_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
group.long 0x6C++0x03
line.long 0x00 "PDMA_DSCT6_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
group.long 0x7C++0x03
line.long 0x00 "PDMA_DSCT7_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
group.long 0x8C++0x03
line.long 0x00 "PDMA_DSCT8_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
rgroup.long 0x100++0x03
line.long 0x00 "PDMA_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
repeat 8. (strings "1" "2" "3" "4" "5" "6" "7" "8" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x104)++0x03
line.long 0x00 "PDMA_CURSCAT$1,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
repeat.end
group.long 0x400++0x03
line.long 0x00 "PDMA_CHCTL,PDMA Channel Control Register"
bitfld.long 0x00 8. "CHEN8,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x00 7. "CHEN7,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x00 6. "CHEN6,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x00 5. "CHEN5,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x00 4. "CHEN4,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x00 3. "CHEN3,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x00 2. "CHEN2,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
bitfld.long 0x00 1. "CHEN1,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x00 0. "CHEN0,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
wgroup.long 0x404++0x03
line.long 0x00 "PDMA_PAUSE,PDMA Transfer Pause Control Register"
bitfld.long 0x00 8. "PAUSE8,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x00 7. "PAUSE7,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 6. "PAUSE6,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x00 5. "PAUSE5,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 4. "PAUSE4,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x00 3. "PAUSE3,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 2. "PAUSE2,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
bitfld.long 0x00 1. "PAUSE1,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 0. "PAUSE0,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
wgroup.long 0x408++0x03
line.long 0x00 "PDMA_SWREQ,PDMA Software Request Register"
bitfld.long 0x00 8. "SWREQ8,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
bitfld.long 0x00 7. "SWREQ7,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 6. "SWREQ6,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
bitfld.long 0x00 5. "SWREQ5,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 4. "SWREQ4,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
bitfld.long 0x00 3. "SWREQ3,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 2. "SWREQ2,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
bitfld.long 0x00 1. "SWREQ1,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 0. "SWREQ0,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
rgroup.long 0x40C++0x03
line.long 0x00 "PDMA_TRGSTS,PDMA Channel Request Status Register"
bitfld.long 0x00 8. "REQSTS8,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x00 7. "REQSTS7,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 6. "REQSTS6,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x00 5. "REQSTS5,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 4. "REQSTS4,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x00 3. "REQSTS3,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 2. "REQSTS2,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
bitfld.long 0x00 1. "REQSTS1,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 0. "REQSTS0,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
group.long 0x410++0x03
line.long 0x00 "PDMA_PRISET,PDMA Fixed Priority Setting Register"
bitfld.long 0x00 8. "FPRISET8,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x00 7. "FPRISET7,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 6. "FPRISET6,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x00 5. "FPRISET5,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 4. "FPRISET4,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x00 3. "FPRISET3,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 2. "FPRISET2,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
bitfld.long 0x00 1. "FPRISET1,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 0. "FPRISET0,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
wgroup.long 0x414++0x03
line.long 0x00 "PDMA_PRICLR,PDMA Fixed Priority Clear Register"
bitfld.long 0x00 8. "FPRICLR8,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x00 7. "FPRICLR7,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 6. "FPRICLR6,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x00 5. "FPRICLR5,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 4. "FPRICLR4,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x00 3. "FPRICLR3,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 2. "FPRICLR2,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
bitfld.long 0x00 1. "FPRICLR1,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 0. "FPRICLR0,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
group.long 0x418++0x03
line.long 0x00 "PDMA_INTEN,PDMA Interrupt Enable Register"
bitfld.long 0x00 8. "INTEN8,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x00 7. "INTEN7,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 6. "INTEN6,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x00 5. "INTEN5,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 4. "INTEN4,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x00 3. "INTEN3,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 2. "INTEN2,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
bitfld.long 0x00 1. "INTEN1,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 0. "INTEN0,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
group.long 0x41C++0x03
line.long 0x00 "PDMA_INTSTS,PDMA Interrupt Status Register"
bitfld.long 0x00 9. "REQTOF1,Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1 user can write 1 to clear these bits.\nNote: Please disable time-out function before clear this bit" "0: No request time-out,1: Peripheral request time-out"
bitfld.long 0x00 8. "REQTOF0,Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0 user can write 1 to clear these bits.\nNote: Please disable time-out function before clear this bit" "0: No request time-out,1: Peripheral request time-out"
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rbitfld.long 0x00 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
rbitfld.long 0x00 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer" "0: Not finished yet,1: PDMA channel has finished transmission"
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rbitfld.long 0x00 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error" "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
group.long 0x420++0x03
line.long 0x00 "PDMA_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
bitfld.long 0x00 8. "ABTIF8,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
bitfld.long 0x00 7. "ABTIF7,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 6. "ABTIF6,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
bitfld.long 0x00 5. "ABTIF5,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
bitfld.long 0x00 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
bitfld.long 0x00 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
group.long 0x424++0x03
line.long 0x00 "PDMA_TDSTS,PDMA Channel Transfer Done Flag Register"
bitfld.long 0x00 8. "TDIF8,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0x00 7. "TDIF7,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 6. "TDIF6,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0x00 5. "TDIF5,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 4. "TDIF4,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0x00 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
bitfld.long 0x00 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
group.long 0x428++0x03
line.long 0x00 "PDMA_ALIGN,PDMA Transfer Alignment Status Register"
bitfld.long 0x00 8. "ALIGN8,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x00 7. "ALIGN7,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 6. "ALIGN6,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x00 5. "ALIGN5,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 4. "ALIGN4,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x00 3. "ALIGN3,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 2. "ALIGN2,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
bitfld.long 0x00 1. "ALIGN1,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 0. "ALIGN0,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
rgroup.long 0x42C++0x03
line.long 0x00 "PDMA_TACTSTS,PDMA Transfer Active Flag Register"
bitfld.long 0x00 8. "TXACTF8,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x00 7. "TXACTF7,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x00 6. "TXACTF6,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x00 5. "TXACTF5,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x00 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x00 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x00 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
bitfld.long 0x00 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
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bitfld.long 0x00 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active"
group.long 0x430++0x03
line.long 0x00 "PDMA_TOUTPSC,PDMA Time-out Prescaler Register"
bitfld.long 0x00 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,2: PDMA channel 1 time-out clock source is..,3: PDMA channel 1 time-out clock source is..,4: PDMA channel 1 time-out clock source is..,5: PDMA channel 1 time-out clock source is..,6: PDMA channel 1 time-out clock source is..,7: PDMA channel 1 time-out clock source is.."
bitfld.long 0x00 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,2: PDMA channel 0 time-out clock source is..,3: PDMA channel 0 time-out clock source is..,4: PDMA channel 0 time-out clock source is..,5: PDMA channel 0 time-out clock source is..,6: PDMA channel 0 time-out clock source is..,7: PDMA channel 0 time-out clock source is.."
group.long 0x434++0x03
line.long 0x00 "PDMA_TOUTEN,PDMA Time-out Enable Register"
bitfld.long 0x00 1. "TOUTEN1,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
bitfld.long 0x00 0. "TOUTEN0,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
group.long 0x438++0x03
line.long 0x00 "PDMA_TOUTIEN,PDMA Time-out Interrupt Enable Register"
bitfld.long 0x00 1. "TOUTIEN1,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
bitfld.long 0x00 0. "TOUTIEN0,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
group.long 0x43C++0x03
line.long 0x00 "PDMA_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
hexmask.long.word 0x00 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-Gather mode this is the base address for calculating the next link - list address"
group.long 0x440++0x03
line.long 0x00 "PDMA_TOC0_1,PDMA Time-out Counter Ch1 and Ch0 Register"
hexmask.long.word 0x00 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1"
hexmask.long.word 0x00 0.--15. 1. "TOC0,Time-out Counter for Channel 0"
group.long 0x460++0x03
line.long 0x00 "PDMA_CHRST,PDMA Channel Reset Register"
hexmask.long.word 0x00 0.--8. 1. "CHnRST,Channel n Reset"
group.long 0x480++0x03
line.long 0x00 "PDMA_REQSEL0_3,PDMA Request Source Select Register 0"
bitfld.long 0x00 24.--29. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0" "0: Disable PDMA peripheral request,1: Reserved,?,?,4: Channel connects to UART0_TX,5: Channel connects to UART0_RX,6: Channel connects to UART1_TX,7: Channel connects to UART1_RX,8: Channel connects to UART2_TX,9: Channel connects to UART2_RX,10: Channel connects to USCI0_TX,11: Channel connects to USCI0_RX,12: Channel connects to USCI1_TX,13: Channel connects to USCI1_RX,14: Reserved,15: Reserved,16: Channel connects to QSPI0_TX,17: Channel connects to QSPI0_RX,18: Channel connects to SPI0_TX,19: Channel connects to SPI0_RX,20: Channel connects to ADC_RX,21: Channel connects to PWM0_P1_RX,22: Channel connects to PWM0_P2_RX,23: Channel connects to PWM0_P3_RX,24: Channel connects to PWM1_P1_RX,25: Channel connects to PWM1_P2_RX,26: Channel connects to PWM1_P3_RX,27: Reserved,28: Channel connects to I2C0_TX,29: Channel connects to I2C0_RX,30: Channel connects to I2C1_TX,31: Channel connects to I2C1_RX,32: Channel connects to TMR0,33: Channel connects to TMR1,34: Channel connects to TMR2,35: Channel connects to TMR3,36: Channel connects to UART3_TX,37: Channel connects to UART3_RX,38: Channel connects to UART4_TX,39: Channel connects to UART4_RX,40: Channel connects to UART5_TX,41: Channel connects to UART5_RX,42: Channel connects to UART6_TX,43: Channel connects to UART6_RX,44: Channel connects to UART7_TX,45: Channel connects to UART7_RX,?..."
group.long 0x484++0x03
line.long 0x00 "PDMA_REQSEL4_7,PDMA Request Source Select Register 1"
bitfld.long 0x00 24.--29. "REQSRC7,Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 16.--21. "REQSRC6,Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "REQSRC5,Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--5. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x488++0x03
line.long 0x00 "PDMA_REQSEL8,PDMA Request Source Select Register 2"
bitfld.long 0x00 0.--5. "REQSRC8,Channel 8 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
tree "PWM (Pulse-Width Modulator)"
repeat 2. (list 0. 1.) (list ad:0x40058000 ad:0x40059000)
tree "PWM$1"
base $2
group.long 0x00++0x03
line.long 0x00 "PWM_CTL0,PWM Control Register 0"
bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled PWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disable,1: ICE debug mode counter halt Enable"
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bitfld.long 0x00 16. "IMMLDENn,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
bitfld.long 0x00 0. "CTRLDn,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
group.long 0x04++0x03
line.long 0x00 "PWM_CTL1,PWM Control Register 1"
bitfld.long 0x00 24.--26. "OUTMODEn,PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: PWM independent mode,1: PWM complementary mode,?..."
bitfld.long 0x00 8.--9. "CNTTYPE4,PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 4.--5. "CNTTYPE2,PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
bitfld.long 0x00 0.--1. "CNTTYPE0,PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
group.long 0x10++0x03
line.long 0x00 "PWM_CLKSRC,PWM Clock Source Register"
bitfld.long 0x00 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
bitfld.long 0x00 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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bitfld.long 0x00 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
group.long 0x14++0x03
line.long 0x00 "PWM_CLKPSC0_1,PWM Clock Prescale Register 0/1"
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler"
group.long 0x18++0x03
line.long 0x00 "PWM_CLKPSC2_3,PWM Clock Prescale Register 2/3"
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler"
group.long 0x1C++0x03
line.long 0x00 "PWM_CLKPSC4_5,PWM Clock Prescale Register 4/5"
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler"
group.long 0x20++0x03
line.long 0x00 "PWM_CNTEN,PWM Counter Enable Register"
bitfld.long 0x00 4. "CNTEN4,PWM Counter Enable Bit 4" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
bitfld.long 0x00 2. "CNTEN2,PWM Counter Enable Bit 2" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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bitfld.long 0x00 0. "CNTEN0,PWM Counter Enable Bit 0" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
group.long 0x24++0x03
line.long 0x00 "PWM_CNTCLR,PWM Clear Counter Register"
bitfld.long 0x00 4. "CNTCLR4,Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0000H"
bitfld.long 0x00 2. "CNTCLR2,Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0000H"
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bitfld.long 0x00 0. "CNTCLR0,Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0000H"
repeat 3. (strings "0" "2" "4" )(list 0x0 0x8 0x10 )
group.long ($2+0x30)++0x03
line.long 0x00 "PWM_PERIOD$1,PWM Period Register $1"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD"
repeat.end
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
group.long ($2+0x50)++0x03
line.long 0x00 "PWM_CMPDAT$1,PWM Comparator Register $1"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as first.."
repeat.end
group.long 0x70++0x03
line.long 0x00 "PWM_DTCTL0_1,PWM Dead-time Control Register 0/1"
bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
group.long 0x74++0x03
line.long 0x00 "PWM_DTCTL2_3,PWM Dead-time Control Register 2/3"
bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
group.long 0x78++0x03
line.long 0x00 "PWM_DTCTL4_5,PWM Dead-time Control Register 4/5"
bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
rgroup.long 0x90++0x03
line.long 0x00 "PWM_CNT0,PWM Counter Register 0"
bitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter"
repeat 2. (strings "2" "4" )(list 0x0 0x8 )
group.long ($2+0x98)++0x03
line.long 0x00 "PWM_CNT$1,PWM Counter Register $1"
rbitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter"
repeat.end
group.long 0xB0++0x03
line.long 0x00 "PWM_WGCTL0,PWM Generation Register 0"
bitfld.long 0x00 26.--27. "PRDPCTL5,PWM Period (Center) Point Control\n" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
bitfld.long 0x00 24.--25. "PRDPCTL4,PWM Period (Center) Point Control\n" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,PWM Period (Center) Point Control\n" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
bitfld.long 0x00 20.--21. "PRDPCTL2,PWM Period (Center) Point Control\n" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,PWM Period (Center) Point Control\n" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
bitfld.long 0x00 16.--17. "PRDPCTL0,PWM Period (Center) Point Control\n" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
bitfld.long 0x00 8.--9. "ZPCTL4,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
bitfld.long 0x00 4.--5. "ZPCTL2,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
bitfld.long 0x00 0.--1. "ZPCTL0,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
group.long 0xB4++0x03
line.long 0x00 "PWM_WGCTL1,PWM Generation Register 1"
bitfld.long 0x00 26.--27. "CMPDCTL5,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
bitfld.long 0x00 24.--25. "CMPDCTL4,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
bitfld.long 0x00 20.--21. "CMPDCTL2,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
bitfld.long 0x00 16.--17. "CMPDCTL0,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
bitfld.long 0x00 8.--9. "CMPUCTL4,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
bitfld.long 0x00 4.--5. "CMPUCTL2,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
bitfld.long 0x00 0.--1. "CMPUCTL0,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
group.long 0xB8++0x03
line.long 0x00 "PWM_MSKEN,PWM Mask Enable Register"
bitfld.long 0x00 5. "MSKEN5,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
bitfld.long 0x00 4. "MSKEN4,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
bitfld.long 0x00 2. "MSKEN2,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
bitfld.long 0x00 0. "MSKEN0,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
group.long 0xBC++0x03
line.long 0x00 "PWM_MSK,PWM Mask Data Register"
bitfld.long 0x00 5. "MSKDAT5,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
bitfld.long 0x00 4. "MSKDAT4,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0x00 3. "MSKDAT3,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
bitfld.long 0x00 2. "MSKDAT2,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
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bitfld.long 0x00 1. "MSKDAT1,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
bitfld.long 0x00 0. "MSKDAT0,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n"
group.long 0xC0++0x03
line.long 0x00 "PWM_BNF,PWM Brake Noise Filter Register"
bitfld.long 0x00 24. "BK1SRC,Brake 1 Pin Source Select\nFor PWM0 setting" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
bitfld.long 0x00 16. "BK0SRC,Brake 0 Pin Source Select\nFor PWM0 setting" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x00 15. "BRK1PINV,Brake 1 Pin Inverse" "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is.."
bitfld.long 0x00 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
bitfld.long 0x00 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled"
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bitfld.long 0x00 7. "BRK0PINV,Brake 0 Pin Inverse" "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is.."
bitfld.long 0x00 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
bitfld.long 0x00 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled"
group.long 0xC4++0x03
line.long 0x00 "PWM_FAILBRK,PWM System Fail Brake Control Register"
bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection..,1: Brake Function triggered by CSS detection.."
group.long 0xC8++0x03
line.long 0x00 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0/1"
bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected" "0: PWM odd channel level-detect brake function..,1: PWM odd channel output tri-state when..,2: PWM odd channel output low level when..,3: PWM odd channel output high level when.."
bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected" "0: PWM even channel level-detect brake function..,1: PWM even channel output tri-state when..,2: PWM even channel output low level when..,3: PWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
group.long 0xCC++0x03
line.long 0x00 "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2/3"
bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected" "0: PWM odd channel level-detect brake function..,1: PWM odd channel output tri-state when..,2: PWM odd channel output low level when..,3: PWM odd channel output high level when.."
bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected" "0: PWM even channel level-detect brake function..,1: PWM even channel output tri-state when..,2: PWM even channel output low level when..,3: PWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
group.long 0xD0++0x03
line.long 0x00 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4/5"
bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected" "0: PWM odd channel level-detect brake function..,1: PWM odd channel output tri-state when..,2: PWM odd channel output low level when..,3: PWM odd channel output high level when.."
bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected" "0: PWM even channel level-detect brake function..,1: PWM even channel output tri-state when..,2: PWM even channel output low level when..,3: PWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
group.long 0xD4++0x03
line.long 0x00 "PWM_POLCTL,PWM Pin Polar Inverse Register"
bitfld.long 0x00 5. "PINV5,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
bitfld.long 0x00 4. "PINV4,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
bitfld.long 0x00 2. "PINV2,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
bitfld.long 0x00 0. "PINV0,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled"
group.long 0xD8++0x03
line.long 0x00 "PWM_POEN,PWM Output Enable Register"
bitfld.long 0x00 5. "POEN5,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
bitfld.long 0x00 4. "POEN4,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x00 3. "POEN3,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
bitfld.long 0x00 2. "POEN2,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
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bitfld.long 0x00 1. "POEN1,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
bitfld.long 0x00 0. "POEN0,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode"
wgroup.long 0xDC++0x03
line.long 0x00 "PWM_SWBRK,PWM Software Brake Control Register"
bitfld.long 0x00 10. "BRKLTRG4,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register" "0,1"
bitfld.long 0x00 9. "BRKLTRG2,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 8. "BRKLTRG0,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register" "0,1"
bitfld.long 0x00 2. "BRKETRG4,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 1. "BRKETRG2,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register" "0,1"
bitfld.long 0x00 0. "BRKETRG0,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register" "0,1"
group.long 0xE0++0x03
line.long 0x00 "PWM_INTEN0,PWM Interrupt Enable Register 0"
bitfld.long 0x00 29. "CMPDIEN5,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x00 28. "CMPDIEN4,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x00 26. "CMPDIEN2,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
bitfld.long 0x00 24. "CMPDIEN0,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x00 20. "CMPUIEN4,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x00 18. "CMPUIEN2,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
bitfld.long 0x00 16. "CMPUIEN0,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 12. "PIEN4,PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x00 10. "PIEN2,PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
bitfld.long 0x00 4. "ZIEN4,PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 2. "ZIEN2,PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
bitfld.long 0x00 0. "ZIEN0,PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
group.long 0xE4++0x03
line.long 0x00 "PWM_INTEN1,PWM Interrupt Enable Register 1"
bitfld.long 0x00 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
bitfld.long 0x00 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
bitfld.long 0x00 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected" "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3.."
bitfld.long 0x00 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1.."
group.long 0xE8++0x03
line.long 0x00 "PWM_INTSTS0,PWM Interrupt Flag Register 0"
bitfld.long 0x00 29. "CMPDIF5,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1"
bitfld.long 0x00 28. "CMPDIF4,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 27. "CMPDIF3,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1"
bitfld.long 0x00 26. "CMPDIF2,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 25. "CMPDIF1,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1"
bitfld.long 0x00 24. "CMPDIF0,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 16.--21. "CMPUIFn,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 12. "PIF4,PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x00 10. "PIF2,PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1" "0,1"
bitfld.long 0x00 8. "PIF0,PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x00 4. "ZIF4,PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1" "0,1"
bitfld.long 0x00 2. "ZIF2,PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1" "0,1"
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bitfld.long 0x00 0. "ZIF0,PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1" "0,1"
group.long 0xEC++0x03
line.long 0x00 "PWM_INTSTS1,PWM Interrupt Flag Register 1"
rbitfld.long 0x00 29. "BRKLSTS5,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
rbitfld.long 0x00 28. "BRKLSTS4,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
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rbitfld.long 0x00 27. "BRKLSTS3,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
rbitfld.long 0x00 26. "BRKLSTS2,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
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rbitfld.long 0x00 25. "BRKLSTS1,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
rbitfld.long 0x00 24. "BRKLSTS0,PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
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rbitfld.long 0x00 21. "BRKESTS5,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
rbitfld.long 0x00 20. "BRKESTS4,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 19. "BRKESTS3,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
rbitfld.long 0x00 18. "BRKESTS2,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 17. "BRKESTS1,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
rbitfld.long 0x00 16. "BRKESTS0,PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
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bitfld.long 0x00 13. "BRKLIF5,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
bitfld.long 0x00 12. "BRKLIF4,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0x00 11. "BRKLIF3,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
bitfld.long 0x00 10. "BRKLIF2,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0x00 9. "BRKLIF1,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
bitfld.long 0x00 8. "BRKLIF0,PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0x00 5. "BRKEIF5,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
bitfld.long 0x00 4. "BRKEIF4,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0x00 3. "BRKEIF3,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
bitfld.long 0x00 2. "BRKEIF2,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0x00 1. "BRKEIF1,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
bitfld.long 0x00 0. "BRKEIF0,PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
group.long 0xF8++0x03
line.long 0x00 "PWM_ADCTS0,PWM Trigger ADC Source Select Register 0"
bitfld.long 0x00 31. "TRGEN3,PWM_CH3 Trigger ADC Enable Bit" "0: PWM_CH3 Trigger ADC function Disabled,1: PWM_CH3 Trigger ADC function Enabled"
bitfld.long 0x00 24.--27. "TRGSEL3,PWM_CH3 Trigger ADC Source Select" "0: PWM_CH2 zero point,1: PWM_CH2 period point,2: PWM_CH2 zero or period point,3: PWM_CH2 up-count CMPDAT point,4: PWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH3 up-count CMPDAT point,9: PWM_CH3 down-count CMPDAT point,?..."
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bitfld.long 0x00 23. "TRGEN2,PWM_CH2 Trigger ADC Enable Bit" "0: PWM_CH2 Trigger ADC function Disabled,1: PWM_CH2 Trigger ADC function Enabled"
bitfld.long 0x00 16.--19. "TRGSEL2,PWM_CH2 Trigger ADC Source Select" "0: PWM_CH2 zero point,1: PWM_CH2 period point,2: PWM_CH2 zero or period point,3: PWM_CH2 up-count CMPDAT point,4: PWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH3 up-count CMPDAT point,9: PWM_CH3 down-count CMPDAT point,?..."
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bitfld.long 0x00 15. "TRGEN1,PWM_CH1 Trigger ADC Enable Bit" "0: PWM_CH1 Trigger ADC function Disabled,1: PWM_CH1 Trigger ADC function Enabled"
bitfld.long 0x00 8.--11. "TRGSEL1,PWM_CH1 Trigger ADC Source Select" "0: PWM_CH0 zero point,1: PWM_CH0 period point,2: PWM_CH0 zero or period point,3: PWM_CH0 up-count CMPDAT point,4: PWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH1 up-count CMPDAT point,9: PWM_CH1 down-count CMPDAT point,?..."
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bitfld.long 0x00 7. "TRGEN0,PWM_CH0 Trigger ADC Enable Bit" "0: PWM_CH0 Trigger ADC function Disabled,1: PWM_CH0 Trigger ADC function Enabled"
bitfld.long 0x00 0.--3. "TRGSEL0,PWM_CH0 Trigger ADC Source Select" "0: PWM_CH0 zero point,1: PWM_CH0 period point,2: PWM_CH0 zero or period point,3: PWM_CH0 up-count CMPDAT point,4: PWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH1 up-count CMPDAT point,9: PWM_CH1 down-count CMPDAT point,?..."
group.long 0xFC++0x03
line.long 0x00 "PWM_ADCTS1,PWM Trigger ADC Source Select Register 1"
bitfld.long 0x00 15. "TRGEN5,PWM_CH5 Trigger ADC Enable Bit" "0: PWM_CH5 Trigger ADC function Disabled,1: PWM_CH5 Trigger ADC function Enabled"
bitfld.long 0x00 8.--11. "TRGSEL5,PWM_CH5 Trigger ADC Source Select" "0: PWM_CH4 zero point,1: PWM_CH4 period point,2: PWM_CH4 zero or period point,3: PWM_CH4 up-count CMPDAT point,4: PWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH5 up-count CMPDAT point,9: PWM_CH5 down-count CMPDAT point,?..."
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bitfld.long 0x00 7. "TRGEN4,PWM_CH4 Trigger ADC Enable Bit" "0: PWM_CH4 Trigger ADC function Disabled,1: PWM_CH4 Trigger ADC function Enabled"
bitfld.long 0x00 0.--3. "TRGSEL4,PWM_CH4 Trigger ADC Source Select" "0: PWM_CH4 zero point,1: PWM_CH4 period point,2: PWM_CH4 zero or period point,3: PWM_CH4 up-count CMPDAT point,4: PWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH5 up-count CMPDAT point,9: PWM_CH5 down-count CMPDAT point,?..."
group.long 0x110++0x03
line.long 0x00 "PWM_SSCTL,PWM Synchronous Start Control Register"
bitfld.long 0x00 8.--9. "SSRC,PWM Synchronous Start Source Select Bits" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1,2: Reserved,3: Reserved"
bitfld.long 0x00 4. "SSEN4,PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x00 2. "SSEN2,PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
bitfld.long 0x00 0. "SSEN0,PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
wgroup.long 0x114++0x03
line.long 0x00 "PWM_SSTRG,PWM Synchronous Start Trigger Register"
bitfld.long 0x00 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
group.long 0x120++0x03
line.long 0x00 "PWM_STATUS,PWM Status Register"
bitfld.long 0x00 21. "ADCTRG5,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
bitfld.long 0x00 20. "ADCTRG4,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "ADCTRG3,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
bitfld.long 0x00 18. "ADCTRG2,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "ADCTRG1,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
bitfld.long 0x00 16. "ADCTRG0,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.."
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bitfld.long 0x00 4. "CNTMAX4,Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
bitfld.long 0x00 2. "CNTMAX2,Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
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bitfld.long 0x00 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.."
group.long 0x200++0x03
line.long 0x00 "PWM_CAPINEN,PWM Capture Input Enable Register"
bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
group.long 0x204++0x03
line.long 0x00 "PWM_CAPCTL,PWM Capture Control Register"
bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
rgroup.long 0x208++0x03
line.long 0x00 "PWM_CAPSTS,PWM Capture Status Register"
bitfld.long 0x00 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
bitfld.long 0x00 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
bitfld.long 0x00 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
bitfld.long 0x00 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
bitfld.long 0x00 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
bitfld.long 0x00 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
bitfld.long 0x00 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
rgroup.long 0x20C++0x03
line.long 0x00 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
rgroup.long 0x210++0x03
line.long 0x00 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x214++0x03
line.long 0x00 "PWM_RCAPDAT1,PWM Rising Capture Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
group.long 0x218++0x03
line.long 0x00 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x21C++0x03
line.long 0x00 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
group.long 0x220++0x03
line.long 0x00 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x224++0x03
line.long 0x00 "PWM_RCAPDAT3,PWM Rising Capture Data Register 3"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
group.long 0x228++0x03
line.long 0x00 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x22C++0x03
line.long 0x00 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
group.long 0x230++0x03
line.long 0x00 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x234++0x03
line.long 0x00 "PWM_RCAPDAT5,PWM Rising Capture Data Register 5"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
group.long 0x238++0x03
line.long 0x00 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
group.long 0x23C++0x03
line.long 0x00 "PWM_PDMACTL,PWM PDMA Control Register"
bitfld.long 0x00 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel4,1: Channel5"
bitfld.long 0x00 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid" "0: PWM_FCAPDAT4/5 is the first captured data to..,1: PWM_RCAPDAT4/5 is the first captured data to.."
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bitfld.long 0x00 17.--18. "CAPMOD4_5,Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Reserved,1: PWM_RCAPDAT4/5,2: PWM_FCAPDAT4/5,3: Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5"
bitfld.long 0x00 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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bitfld.long 0x00 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel2,1: Channel3"
bitfld.long 0x00 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid" "0: PWM_FCAPDAT2/3 is the first captured data to..,1: PWM_RCAPDAT2/3 is the first captured data to.."
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bitfld.long 0x00 9.--10. "CAPMOD2_3,Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Reserved,1: PWM_RCAPDAT2/3,2: PWM_FCAPDAT2/3,3: Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3"
bitfld.long 0x00 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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bitfld.long 0x00 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel0,1: Channel1"
bitfld.long 0x00 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid" "0: PWM_FCAPDAT0/1 is the first captured data to..,1: PWM_RCAPDAT0/1 is the first captured data to.."
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bitfld.long 0x00 1.--2. "CAPMOD0_1,Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Reserved,1: PWM_RCAPDAT0/1,2: PWM_FCAPDAT0/1,3: Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1"
bitfld.long 0x00 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
rgroup.long 0x240++0x03
line.long 0x00 "PWM_PDMACAP0_1,PWM Capture Channel 01 PDMA Register"
hexmask.long.word 0x00 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid"
group.long 0x244++0x03
line.long 0x00 "PWM_PDMACAP2_3,PWM Capture Channel 23 PDMA Register"
hexmask.long.word 0x00 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid"
group.long 0x248++0x03
line.long 0x00 "PWM_PDMACAP4_5,PWM Capture Channel 45 PDMA Register"
hexmask.long.word 0x00 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid"
group.long 0x250++0x03
line.long 0x00 "PWM_CAPIEN,PWM Capture Interrupt Enable Register"
bitfld.long 0x00 13. "CAPFIEN5,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
bitfld.long 0x00 12. "CAPFIEN4,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 11. "CAPFIEN3,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
bitfld.long 0x00 10. "CAPFIEN2,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 9. "CAPFIEN1,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
bitfld.long 0x00 8. "CAPFIEN0,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 5. "CAPRIEN5,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
bitfld.long 0x00 4. "CAPRIEN4,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 3. "CAPRIEN3,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
bitfld.long 0x00 2. "CAPRIEN2,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 1. "CAPRIEN1,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
bitfld.long 0x00 0. "CAPRIEN0,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
group.long 0x254++0x03
line.long 0x00 "PWM_CAPIF,PWM Capture Interrupt Flag Register"
bitfld.long 0x00 13. "CFLIF5,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x00 12. "CFLIF4,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 11. "CFLIF3,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x00 10. "CFLIF2,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 9. "CFLIF1,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x00 8. "CFLIF0,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 5. "CRLIF5,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x00 4. "CRLIF4,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 3. "CRLIF3,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x00 2. "CRLIF2,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 1. "CRLIF1,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x00 0. "CRLIF0,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
rgroup.long 0x304++0x03
line.long 0x00 "PWM_PBUF0,PWM PERIOD0 Buffer"
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
group.long 0x30C++0x03
line.long 0x00 "PWM_PBUF2,PWM PERIOD2 Buffer"
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
group.long 0x314++0x03
line.long 0x00 "PWM_PBUF4,PWM PERIOD4 Buffer"
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
rgroup.long 0x31C++0x03
line.long 0x00 "PWM_CMPBUF0,PWM CMPDAT0 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x320++0x03
line.long 0x00 "PWM_CMPBUF1,PWM CMPDAT1 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x324++0x03
line.long 0x00 "PWM_CMPBUF2,PWM CMPDAT2 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x328++0x03
line.long 0x00 "PWM_CMPBUF3,PWM CMPDAT3 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x32C++0x03
line.long 0x00 "PWM_CMPBUF4,PWM CMPDAT4 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
group.long 0x330++0x03
line.long 0x00 "PWM_CMPBUF5,PWM CMPDAT5 Buffer"
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
tree.end
repeat.end
tree.end
tree "QSPI (Queued Synchronous Peripheral Interface)"
base ad:0x40060000
group.long 0x00++0x03
line.long 0x00 "QSPIx_CTL,QSPI Control Register"
bitfld.long 0x00 22. "QUADIOEN,Quad I/O Mode Enable Bit" "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
bitfld.long 0x00 21. "DUALIOEN,Dual I/O Mode Enable Bit" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: QSPI data is input direction,1: QSPI data is output direction"
bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: QSPI unit transfer interrupt Disabled,1: QSPI unit transfer interrupt Enabled"
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bitfld.long 0x00 16. "TWOBIT,2-bit Transfer Mode Enable Bit\nNote: When 2-bit Transfer mode is enabled the first serial transmitted bit data is from the first FIFO buffer data and the 2nd serial transmitted bit data is from the second FIFO buffer data" "0: 2-bit Transfer mode Disabled,1: 2-bit Transfer mode Enabled"
bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,QSPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for QSPI transfer" "0: QSPI operates in full-duplex transfer,1: QSPI operates in half-duplex transfer"
bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the QSPIx TX register is.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: QSPI bus clock is idle low,1: QSPI bus clock is idle high"
bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
bitfld.long 0x00 0. "SPIEN,QSPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
group.long 0x04++0x03
line.long 0x00 "QSPIx_CLKDIV,QSPI Clock Divider Register"
hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the QSPI bus clock of QSPI Master"
group.long 0x08++0x03
line.long 0x00 "QSPIx_SSCTL,QSPI Slave Select Control Register"
hexmask.long.word 0x00 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period\nIn Slave mode these bits indicate the time-out period when there is bus clock input during slave select active"
bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
bitfld.long 0x00 6. "SLVTORST,Slave Mode Time-out Reset Control" "0: When Slave mode time-out event occurs the TX..,1: When Slave mode time-out event occurs the TX.."
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bitfld.long 0x00 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable Bit" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
bitfld.long 0x00 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode the QSPI controller can work with 3-wire interface including QSPIx_CLK QSPIx_MISO and QSPIx_MOSI pins" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (QSPIx_SS)" "0: The slave selection signal QSPIx_SS is active..,1: The slave selection signal QSPIx_SS is active.."
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the QSPIx_SS line to inactive..,1: set the QSPIx_SS line to active.."
group.long 0x0C++0x03
line.long 0x00 "QSPIx_PDMACTL,QSPI PDMA Control Register"
bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the QSPI.."
bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In QSPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
group.long 0x10++0x03
line.long 0x00 "QSPIx_FIFOCTL,QSPI FIFO Control Register"
bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (QSPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\n" "0: The QSPI data out is keep 0 if there is TX..,1: The QSPI data out is keep 1 if there is TX.."
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
bitfld.long 0x00 4. "RXTOIEN,Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in QSPI Slave mode this bit can be used to make QSPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
group.long 0x14++0x03
line.long 0x00 "QSPIx_STATUS,QSPI Status Register"
rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x00 15. "SPIENSTS,QSPI Enable Status (Read Only)\nNote: The QSPI peripheral clock is asynchronous with the system clock" "0: QSPI controller Disabled,1: QSPI controller Enabled"
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag \nWhen the slave select is active and the value of SLVTOCNT is not 0 if the bus clock is detected the slave time-out counter in QSPI controller logic will be started" "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: QSPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: QSPI controller is in idle state,1: QSPI controller is in busy state"
wgroup.long 0x20++0x03
line.long 0x00 "QSPIx_TX,QSPI Data Transmit Register"
hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers"
rgroup.long 0x30++0x03
line.long 0x00 "QSPIx_RX,QSPI Data Receive Register"
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 8-level FIFO buffers in this controller"
tree.end
tree "RTC (Real-time Counter)"
base ad:0x40041000
group.long 0x00++0x03
line.long 0x00 "RTC_INIT,RTC Initiation Register"
hexmask.long 0x00 1.--31. 1. "INIT,RTC Initiation (Write Only)\nWhen RTC block is powered on RTC is at reset state"
rbitfld.long 0x00 0. "INIT_ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state"
group.long 0x08++0x03
line.long 0x00 "RTC_FREQADJ,RTC Frequency Compensation Register"
bitfld.long 0x00 8.--12. "INTEGER,Integer Part" "0: Integer part of detected value is 32752,1: Integer part of detected value is 32753,2: Integer part of detected value is 32754,3: Integer part of detected value is 32755,4: Integer part of detected value is 32756,5: Integer part of detected value is 32757,6: Integer part of detected value is 32758,7: Integer part of detected value is 32759,8: Integer part of detected value is 32760,9: Integer part of detected value is 32761,10: Integer part of detected value is 32762,11: Integer part of detected value is 32763,12: Integer part of detected value is 32764,13: Integer part of detected value is 32765,14: Integer part of detected value is 32766,15: Integer part of detected value is 32767,16: Integer part of detected value is 32768,17: Integer part of detected value is 32769,18: Integer part of detected value is 32770,19: Integer part of detected value is 32771,20: Integer part of detected value is 32772,21: Integer part of detected value is 32773,22: Integer part of detected value is 32774,23: Integer part of detected value is 32775,24: Integer part of detected value is 32776,25: Integer part of detected value is 32777,26: Integer part of detected value is 32778,27: Integer part of detected value is 32779,28: Integer part of detected value is 32780,29: Integer part of detected value is 32781,30: Integer part of detected value is 32782,31: Integer part of detected value is 32783"
bitfld.long 0x00 0.--5. "FRACTION,Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "RTC_TIME,RTC Time Loading Register"
bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "RTC_CAL,RTC Calendar Loading Register"
bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "RTC_CLKFMT,RTC Time Scale Selection Register"
bitfld.long 0x00 0. "_24HEN,24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
group.long 0x18++0x03
line.long 0x00 "RTC_WEEKDAY,RTC Day of the Week Register"
bitfld.long 0x00 0.--2. "WEEKDAY,Day of the Week Register" "0: Sunday,1: Monday,2: Tuesday,3: Wednesday,4: Thursday,5: Friday,6: Saturday,7: Reserved"
group.long 0x1C++0x03
line.long 0x00 "RTC_TALM,RTC Time Alarm Register"
bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "RTC_CALM,RTC Calendar Alarm Register"
bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x24++0x03
line.long 0x00 "RTC_LEAPYEAR,RTC Leap Year Indicator Register"
bitfld.long 0x00 0. "LEAPYEAR,Leap Year Indication (Read Only)" "0: This year is not a leap year,1: This year is leap year"
group.long 0x28++0x03
line.long 0x00 "RTC_INTEN,RTC Interrupt Enable Register"
bitfld.long 0x00 1. "TICKIEN,Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated" "0: RTC Time Tick interrupt Disabled,1: RTC Time Tick interrupt Enabled"
bitfld.long 0x00 0. "ALMIEN,Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated" "0: RTC Alarm interrupt Disabled,1: RTC Alarm interrupt Enabled"
group.long 0x2C++0x03
line.long 0x00 "RTC_INTSTS,RTC Interrupt Status Register"
bitfld.long 0x00 1. "TICKIF,RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit" "0: Tick condition did not occur,1: Tick condition occurred"
bitfld.long 0x00 0. "ALMIF,RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit" "0: Alarm condition is not matched,1: Alarm condition is matched"
group.long 0x30++0x03
line.long 0x00 "RTC_TICK,RTC Time Tick Register"
bitfld.long 0x00 0.--2. "TICK,Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request" "0: Time tick is 1 second,1: Time tick is 1/2 second,2: Time tick is 1/4 second,3: Time tick is 1/8 second,4: Time tick is 1/16 second,5: Time tick is 1/32 second,6: Time tick is 1/64 second,7: Time tick is 1/128 second"
group.long 0x34++0x03
line.long 0x00 "RTC_TAMSK,RTC Time Alarm Mask Register"
bitfld.long 0x00 5. "MTENHR,Mask 10-Hour Time Digit of Alarm Setting (0~2)" "0,1"
bitfld.long 0x00 4. "MHR,Mask 1-Hour Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 3. "MTENMIN,Mask 10-Min Time Digit of Alarm Setting (0~5)" "0,1"
bitfld.long 0x00 2. "MMIN,Mask 1-Min Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 1. "MTENSEC,Mask 10-Sec Time Digit of Alarm Setting (0~5)" "0,1"
bitfld.long 0x00 0. "MSEC,Mask 1-Sec Time Digit of Alarm Setting (0~9)" "0,1"
group.long 0x38++0x03
line.long 0x00 "RTC_CAMSK,RTC Calendar Alarm Mask Register"
bitfld.long 0x00 5. "MTENYEAR,Mask 10-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
bitfld.long 0x00 4. "MYEAR,Mask 1-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 3. "MTENMON,Mask 10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
bitfld.long 0x00 2. "MMON,Mask 1-Month Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 1. "MTENDAY,Mask 10-Day Calendar Digit of Alarm Setting (0~3)" "0,1"
bitfld.long 0x00 0. "MDAY,Mask 1-Day Calendar Digit of Alarm Setting (0~9)" "0,1"
group.long 0x100++0x03
line.long 0x00 "RTC_LXTCTL,RTC 32K.768 KHz LXT Control Register"
bitfld.long 0x00 7. "OSC32_S,Clock 32K Source Selection" "0: Clock source from LXT32K,1: Clock source from LIRC38K"
tree.end
tree "SPI (SPI Register Map)"
base ad:0x40061000
group.long 0x00++0x03
line.long 0x00 "SPIx_CTL,SPI Control Register"
bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
group.long 0x04++0x03
line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
abitfld.long 0x00 0.--8. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master" "0x001=1: Not supported in I2S mode.\n,0x002=2: The time interval must be larger than.."
group.long 0x08++0x03
line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
group.long 0x0C++0x03
line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
group.long 0x10++0x03
line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\n" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
group.long 0x14++0x03
line.long 0x00 "SPIx_STATUS,SPI Status Register"
rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
wgroup.long 0x20++0x03
line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
rgroup.long 0x30++0x03
line.long 0x00 "SPIx_RX,SPI Data Receive Register"
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
group.long 0x60++0x03
line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
bitfld.long 0x00 31. "SLVERRIEN,Bit Clock Loss Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit clock loss event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\n" "0: I2S mode Disabled,1: I2S mode Enabled"
group.long 0x64++0x03
line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
group.long 0x68++0x03
line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
bitfld.long 0x00 22. "SLVERRIF,Bit Clock Loss Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it" "0: No bit clock loss event occurred,1: Bit clock loss event occurred"
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bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI/I2S control logic Disabled,1: SPI/I2S control logic Enabled"
bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
tree.end
tree "SYS (SYS Register Map)"
base ad:0x40000000
rgroup.long 0x00++0x03
line.long 0x00 "SYS_PDID,Part Device Identification Number Register"
hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code"
group.long 0x04++0x03
line.long 0x00 "SYS_RSTSTS,System Reset Status Register"
bitfld.long 0x00 8. "CPULKRF,CPU Lockup Reset Flag\nNote: Write 1 to clear this bit to 0.\n" "0: No reset from CPU lockup happened,1: The Cortex-M0 lockup happened and chip is reset"
bitfld.long 0x00 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M0 Core and Flash Memory Controller (FMC).\nNote: Write to clear this bit to 0" "0: No reset from CPU,1: The Cortex-M0 Core and FMC are reset by.."
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bitfld.long 0x00 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from Cortex-M0,1: The Cortex- M0 had issued the reset signal to.."
bitfld.long 0x00 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.."
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bitfld.long 0x00 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
bitfld.long 0x00 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\n" "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.."
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bitfld.long 0x00 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to.."
bitfld.long 0x00 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued.."
group.long 0x08++0x03
line.long 0x00 "SYS_IPRST0,Peripheral Reset Control Register 0"
bitfld.long 0x00 7. "CRCRST,CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller" "0: CRC calculation controller normal operation,1: CRC calculation controller reset"
bitfld.long 0x00 4. "HDIV_RST,HDIV Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the hardware divider" "0: Hardware divider controller normal operation,1: Hardware divider controller reset"
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bitfld.long 0x00 3. "EBIRST,EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI" "0: EBI controller normal operation,1: EBI controller reset"
bitfld.long 0x00 2. "PDMARST,PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA" "0: PDMA controller normal operation,1: PDMA controller reset"
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bitfld.long 0x00 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected" "0: Processor core normal operation,1: Processor core one-shot reset"
bitfld.long 0x00 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the chip.." "0: Chip normal operation,1: Chip one-shot reset"
group.long 0x0C++0x03
line.long 0x00 "SYS_IPRST1,Peripheral Reset Control Register 1"
bitfld.long 0x00 28. "ADCRST,ADC Controller Reset" "0: ADC controller normal operation,1: ADC controller reset"
bitfld.long 0x00 27. "USBDRST,USBD Controller Reset" "0: USBD controller normal operation,1: USBD controller reset"
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bitfld.long 0x00 23. "UART7RST,UART7 Controller Reset" "0: UART7 controller normal operation,1: UART7 controller reset"
bitfld.long 0x00 22. "UART6RST,UART6 Controller Reset" "0: UART6 controller normal operation,1: UART6 controller reset"
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bitfld.long 0x00 21. "UART5RST,UART5 Controller Reset" "0: UART5 controller normal operation,1: UART5 controller reset"
bitfld.long 0x00 20. "UART4RST,UART4 Controller Reset" "0: UART4 controller normal operation,1: UART4 controller reset"
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bitfld.long 0x00 19. "UART3RST,UART3 Controller Reset" "0: UART3 controller normal operation,1: UART3 controller reset"
bitfld.long 0x00 18. "UART2RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset"
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bitfld.long 0x00 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
bitfld.long 0x00 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
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bitfld.long 0x00 13. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
bitfld.long 0x00 12. "QSPI0RST,QSPI0 Controller Reset" "0: QSPI0 controller normal operation,1: QSPI0 controller reset"
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bitfld.long 0x00 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset"
bitfld.long 0x00 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x00 7. "ACMP01RST,Analog Comparator 0/1 Controller Reset" "0: Analog Comparator 0/1 controller normal..,1: Analog Comparator 0/1 controller reset"
bitfld.long 0x00 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
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bitfld.long 0x00 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
bitfld.long 0x00 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
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bitfld.long 0x00 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
bitfld.long 0x00 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
group.long 0x10++0x03
line.long 0x00 "SYS_IPRST2,Peripheral Reset Control Register 2"
bitfld.long 0x00 19. "BPWM1RST,BPWM1 Controller Reset" "0: BPWM1 controller normal operation,1: BPWM1 controller reset"
bitfld.long 0x00 18. "BPWM0RST,BPWM0 Controller Reset" "0: BPWM0 controller normal operation,1: BPWM0 controller reset"
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bitfld.long 0x00 17. "PWM1RST,PWM1 Controller Reset" "0: PWM1 controller normal operation,1: PWM1 controller reset"
bitfld.long 0x00 16. "PWM0RST,PWM0 Controller Reset" "0: PWM0 controller normal operation,1: PWM0 controller reset"
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bitfld.long 0x00 9. "USCI1RST,USCI1 Controller Reset" "0: USCI1 controller normal operation,1: USCI1 controller reset"
bitfld.long 0x00 8. "USCI0RST,USCI0 Controller Reset" "0: USCI0 controller normal operation,1: USCI0 controller reset"
group.long 0x18++0x03
line.long 0x00 "SYS_BODCTL,Brown-out Detector Control Register"
bitfld.long 0x00 20. "LVRVL,LVR Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register LVRLVSEL (CONFIG0 [29]).\n" "0: LVR-Out Detector threshold voltage is 1.6V,1: LVR-Out Detector threshold voltage is 1.7V"
bitfld.long 0x00 16. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [21]).\nNote: This bit is write protected" "0: Brown-Out Detector threshold voltage is 2.0V,1: Brown-Out Detector threshold voltage is 2.5V"
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bitfld.long 0x00 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: Without de-glitch function,1: 64 system clock (HCLK),2: 128 system clock (HCLK),3: 256 system clock (HCLK),4: 512 system clock (HCLK),5: 1024 system clock (HCLK),6: 2048 system clock (HCLK),7: 4096 system clock (HCLK)"
bitfld.long 0x00 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: BOD output is sampled by LIRC/4 clock,1: 64 system clock (HCLK),2: 128 system clock (HCLK),3: 256 system clock (HCLK),4: 512 system clock (HCLK),5: 1024 system clock (HCLK),6: 2048 system clock (HCLK),7: 4096 system clock (HCLK)"
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bitfld.long 0x00 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled"
bitfld.long 0x00 6. "BODOUT,Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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bitfld.long 0x00 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\n" "0: BOD operate in normal mode (default),1: BOD Low Power mode Enabled"
bitfld.long 0x00 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.."
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bitfld.long 0x00 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit .\n" "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled"
bitfld.long 0x00 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).\n" "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
group.long 0x24++0x03
line.long 0x00 "SYS_PORCTL,Power-On-reset Controller Register"
hexmask.long.word 0x00 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again"
group.long 0x30++0x03
line.long 0x00 "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PA7MFP,PA.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PA6MFP,PA.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PA5MFP,PA.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PA4MFP,PA.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PA3MFP,PA.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PA2MFP,PA.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PA1MFP,PA.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PA0MFP,PA.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x34++0x03
line.long 0x00 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PA15MFP,PA.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PA14MFP,PA.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PA13MFP,PA.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PA12MFP,PA.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PA11MFP,PA.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PA10MFP,PA.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PA9MFP,PA.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PA8MFP,PA.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x03
line.long 0x00 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PB7MFP,PB.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PB6MFP,PB.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PB5MFP,PB.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PB4MFP,PB.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PB3MFP,PB.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PB2MFP,PB.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PB1MFP,PB.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PB0MFP,PB.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C++0x03
line.long 0x00 "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PB15MFP,PB.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PB14MFP,PB.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PB13MFP,PB.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PB12MFP,PB.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PB11MFP,PB.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PB10MFP,PB.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PB9MFP,PB.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PB8MFP,PB.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PC7MFP,PC.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PC6MFP,PC.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PC5MFP,PC.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PC4MFP,PC.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PC3MFP,PC.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PC2MFP,PC.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PC1MFP,PC.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PC0MFP,PC.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44++0x03
line.long 0x00 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PC15MFP,PC.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PC14MFP,PC.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PC13MFP,PC.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PC12MFP,PC.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PC11MFP,PC.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PC10MFP,PC.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PC9MFP,PC.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PC8MFP,PC.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x48++0x03
line.long 0x00 "SYS_GPD_MFPL,GPIOD Low Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PD7MFP,PD.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PD6MFP,PD.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PD5MFP,PD.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PD4MFP,PD.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PD3MFP,PD.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PD2MFP,PD.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PD1MFP,PD.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PD0MFP,PD.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C++0x03
line.long 0x00 "SYS_GPD_MFPH,GPIOD High Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PD15MFP,PD.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PD14MFP,PD.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PD13MFP,PD.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PD12MFP,PD.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PD11MFP,PD.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PD10MFP,PD.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PD9MFP,PD.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PD8MFP,PD.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50++0x03
line.long 0x00 "SYS_GPE_MFPL,GPIOE Low Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PE7MFP,PE.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PE6MFP,PE.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PE5MFP,PE.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PE4MFP,PE.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PE3MFP,PE.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PE2MFP,PE.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PE1MFP,PE.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PE0MFP,PE.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x03
line.long 0x00 "SYS_GPE_MFPH,GPIOE High Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PE15MFP,PE.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PE14MFP,PE.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PE13MFP,PE.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PE12MFP,PE.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PE11MFP,PE.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PE10MFP,PE.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PE9MFP,PE.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PE8MFP,PE.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x03
line.long 0x00 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PF7MFP,PF.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PF6MFP,PF.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PF5MFP,PF.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PF4MFP,PF.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PF3MFP,PF.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PF2MFP,PF.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PF1MFP,PF.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PF0MFP,PF.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5C++0x03
line.long 0x00 "SYS_GPF_MFPH,GPIOF High Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PF15MFP,PF.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PF14MFP,PF.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PF13MFP,PF.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PF12MFP,PF.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PF11MFP,PF.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PF10MFP,PF.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PF9MFP,PF.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PF8MFP,PF.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60++0x03
line.long 0x00 "SYS_GPG_MFPL,GPIOG Low Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PG7MFP,PG.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PG6MFP,PG.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PG5MFP,PG.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PG4MFP,PG.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PG3MFP,PG.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PG2MFP,PG.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PG1MFP,PG.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PG0MFP,PG.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x64++0x03
line.long 0x00 "SYS_GPG_MFPH,GPIOG High Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PG15MFP,PG.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PG14MFP,PG.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PG13MFP,PG.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PG12MFP,PG.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PG11MFP,PG.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PG10MFP,PG.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PG9MFP,PG.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PG8MFP,PG.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x68++0x03
line.long 0x00 "SYS_GPH_MFPL,GPIOH Low Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PH7MFP,PH.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PH6MFP,PH.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PH5MFP,PH.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PH4MFP,PH.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PH3MFP,PH.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PH2MFP,PH.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PH1MFP,PH.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PH0MFP,PH.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6C++0x03
line.long 0x00 "SYS_GPH_MFPH,GPIOH High Byte Multiple Function Control Register"
bitfld.long 0x00 28.--31. "PH15MFP,PH.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PH14MFP,PH.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PH13MFP,PH.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "PH12MFP,PH.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PH11MFP,PH.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "PH10MFP,PH.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PH9MFP,PH.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "PH8MFP,PH.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xC0++0x03
line.long 0x00 "SYS_MODCTL,Modulation Control Register"
bitfld.long 0x00 4.--7. "MODPWMSEL,PWM0 Channel Select for Modulation\nSelect the PWM0 channel to modulate with the UART0_TXD or USCI0_DAT0.\n0000: PWM0 Channel 0 modulate with UART0_TXD.\n0001: PWM0 Channel 1 modulate with UART0_TXD.\n0010: PWM0 Channel 2 modulate with.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "MODH,Modulation at Data High\nSelect modulation pulse(PWM0) at high or low of UART0_TXD or USCI0_DAT0\n0: Modulation pulse at UART0_TXD low or USCI0_DAT0 low.\n1: Modulation pulse at UART0_TXD high or USCI0_DAT0 high" "0,1"
newline
bitfld.long 0x00 0. "MODEN,Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with PWM0 channel output and USCI0(USCI0_DAT0) or UART0(UART0_TXD) output" "0: Modulation Function Disabled,1: Modulation Function Enabled"
group.long 0xD0++0x03
line.long 0x00 "SYS_SRAM_BISTCTL,System SRAM BIST Test Control Register"
bitfld.long 0x00 18. "SRS2,SRAM Bank0 Section 2 BIST Select (Write Protect)\nThis bit define if the bank0 section2 (0x2001_0000~0x2001_7FFF) of SRAM is selected or not when doing bist test.\nNote: This bit is write protected" "0: SRAM back0 section2 is deselected when doing..,1: SRAM back0 section2 is selected when doing.."
bitfld.long 0x00 17. "SRS1,SRAM Bank0 Section 1 BIST Select (Write Protect)\nThis bit define if the bank0 section1 (0x2000_8000~0x2000_FFFF) of SRAM is selected or not when doing bist test.\nNote: This bit is write protected" "0: SRAM bank0 section1 is deselected when doing..,1: SRAM bank0 section1 is selected when doing.."
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bitfld.long 0x00 16. "SRS0,SRAM Bank0 Section 0 BIST Select (Write Protect)\nThis bit define if the bank0 section0 (0x2000_0000~0x2000_7FFF) of SRAM is selected or not when doing bist test.\nNote: This bit is write protected" "0: SRAM bank0 section0 is deselected when doing..,1: SRAM bank0 section0 is selected when doing.."
bitfld.long 0x00 7. "PDMABIST,PDMA BIST Enable Bit (Write Protect)\nThis bit enables BIST test for PDMA RAM\nNote: This bit is write protected" "0: system PDMA BIST Disabled,1: system PDMA BIST Enabled"
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bitfld.long 0x00 4. "USBBIST,USB BIST Enable Bit (Write Protect) \nThis bit enables BIST test for USB RAM\nNote: This bit is write protected" "0: system USB BIST Disabled,1: system USB BIST Enabled"
bitfld.long 0x00 2. "FMCBIST,FMC CACHE BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE RAM\nNote: This bit is write protected" "0: System CACHE BIST Disabled,1: System CACHE BIST Enabled"
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bitfld.long 0x00 0. "SRBIST,SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM.\nNote: This bit is write protected" "0: system SRAM BIST Disabled,1: system SRAM BIST Enabled"
rgroup.long 0xD4++0x03
line.long 0x00 "SYS_SRAM_BISTSTS,System SRAM BIST Test Status Register"
bitfld.long 0x00 23. "PDMAEND,PDMA SRAM BIST Test Finish" "0: PDMA SRAM BIST is active,1: PDMA SRAM BIST test finish"
bitfld.long 0x00 20. "USBBEND,USB SRAM BIST Test Finish" "0: USB SRAM BIST is active,1: USB SRAM BIST test finish"
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bitfld.long 0x00 17. "CRBEND,CACHE SRAM BIST Test Finish" "0: System CACHE RAM BIST is active,1: System CACHE RAM BIST test finished"
bitfld.long 0x00 16. "SRBEND,System SRAM BIST Test Finish" "0: System SRAM BIST active,1: System SRAM BIST finish"
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bitfld.long 0x00 7. "PDMABISTF,PDMA SRAM BIST Failed Flag" "0: PDMA SRAM BIST pass,1: PDMA SRAM BIST failed"
bitfld.long 0x00 4. "USBBEF,USB SRAM BIST Fail Flag" "0: USB SRAM BIST test pass,1: USB SRAM BIST test fail"
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bitfld.long 0x00 1. "CR0BISTEF,CACHE SRAM BIST Fail Flag" "0: System CACHE RAM BIST test pass,1: System CACHE RAM BIST test failed"
bitfld.long 0x00 0. "SRBISTEF,System SRAM BIST Fail Flag" "0: System SRAM BIST test pass,1: System SRAM BIST test fail"
group.long 0xDC++0x03
line.long 0x00 "SYS_SRAM_INTCTL,System SRAM Interrupt Enable Control Register"
bitfld.long 0x00 0. "PERRIEN,SRAM Parity Check Error Interrupt Enable Bit" "0: SRAM parity check error interrupt Disabled,1: SRAM parity check error interrupt Enabled"
group.long 0xE0++0x03
line.long 0x00 "SYS_SRAM_STATUS,System SRAM Parity Error Status Register"
bitfld.long 0x00 0. "PERRIF,SRAM Parity Check Error Flag\nThis bit indicates the System SRAM parity error occurred" "0: No System SRAM parity error,1: System SRAM parity error occur"
rgroup.long 0xE4++0x03
line.long 0x00 "SYS_SRAM_ERRADDR,System SRAM Parity Check Error Address Register"
hexmask.long 0x00 0.--31. 1. "ERRADDR,System SRAM Parity Error Address\nThis register shows system SRAM parity error byte address"
group.long 0xF0++0x03
line.long 0x00 "SYS_HIRCTRIMCTL,HIRC Trim Control Register"
bitfld.long 0x00 16.--20. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x1F 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 10. "REFCKSEL,Reference Clock Selection\n" "0: HIRC trim reference clock is from LXT (32.768..,1: HIRC trim reference clock is from internal.."
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bitfld.long 0x00 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,2: Trim retry count limitation is 256 loops,3: Trim retry count limitation is 512 loops"
bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
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bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC..,2: Reserved,3: Reserved"
group.long 0xF4++0x03
line.long 0x00 "SYS_HIRCTRIMIEN,HIRC Trim Interrupt Enable Register"
bitfld.long 0x00 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation an interrupt will.." "0: Disable CLKERRIF(SYS_HIRCTRIMSTS[2]) status..,1: Enable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to.."
bitfld.long 0x00 1. "TFALIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]).\nIf this.." "0: Disable TFAILIF(SYS_HIRCTRIMSTS[1]) status to..,1: Enable TFAILIF(SYS_HIRCTRIMSTS[1]) status to.."
group.long 0xF8++0x03
line.long 0x00 "SYS_HIRCTRIMSTS,HIRC Trim Interrupt Status Register"
bitfld.long 0x00 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set if there occurs the over boundary condition this flag will be set.\nNote: Write 1 to clear this flag" "0: Over boundary coundition did not occur,1: Over boundary coundition occurred"
bitfld.long 0x00 2. "CLKERIF,Clock Error Interrupt Status\nWhen the frequency relation between reference clock (LXT or USB sync signals) and 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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bitfld.long 0x00 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked" "0: Trim value update limitation count does not..,1: Trim value update limitation count reached.."
bitfld.long 0x00 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0" "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
group.long 0x100++0x03
line.long 0x00 "SYS_REGLCTL,Register Lock Control Register"
hexmask.long.byte 0x00 0.--7. 1. "REGLCTL,Register Lock Control Code (Write Only)\nSome registers have write-protection function"
group.long 0x1EC++0x03
line.long 0x00 "SYS_PORDISAN,Analog POR Disable Control Register"
hexmask.long.word 0x00 0.--15. 1. "POROFFAN,Power-on Reset Enable Bit (Write Protect)\nAfter powered on User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.\nThe analog POR circuit will be active again when this field is set to another value or.."
tree.end
tree "SYST_SCR (SYST_SCR Register Map)"
base ad:0xE000E000
group.long 0x10++0x03
line.long 0x00 "SYST_CTRL,SysTick Control and Status Register"
bitfld.long 0x00 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1"
bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
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bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
group.long 0x14++0x03
line.long 0x00 "SYST_LOAD,SysTick Reload Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,System Tick Reload Value\nThe value to load into the Current Value register when the counter reaches 0"
group.long 0x18++0x03
line.long 0x00 "SYST_VAL,SysTick Current Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value"
group.long 0xD04++0x03
line.long 0x00 "ICSR,Interrupt Control and State Register"
bitfld.long 0x00 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: No effect.\nNMI exception is not pending,1: Changes NMI exception state to pending.\nNMI.."
bitfld.long 0x00 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
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bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the PendSV.."
bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
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bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the SysTick.."
rbitfld.long 0x00 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state" "0,1"
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rbitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending"
bitfld.long 0x00 12.--17. "VECTPENDING,Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but not any effect of the.." "0: no pending exceptions,?..."
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bitfld.long 0x00 11. "RETTOBASE,Preempted Active Exceptions Indicator\nIndicate whether There are Preempted Active Exceptions" "0: there are preempted active exceptions to..,1: there are no active exceptions or the.."
bitfld.long 0x00 0.--5. "VECTACTIVE,Number of the Current Active Exception" "0: Thread mode,?..."
group.long 0xD08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 1. "TBLOFF,Table Offset Bits\nThe vector table address for the selected Security state"
group.long 0xD0C++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of.."
bitfld.long 0x00 15. "ENDIANNESS,Data Endianness" "0: Little-endian,1: Big-endian"
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bitfld.long 0x00 8.--10. "PRIGROUP,Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence" "0,1"
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bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's.." "0,1"
bitfld.long 0x00 0. "VECTRESET,Reserved" "0,1"
group.long 0xD10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode" "0: Sleep,1: Deep sleep"
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bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enters sleep or deep sleep on return from an.."
group.long 0xD18++0x03
line.long 0x00 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x00 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault"
hexmask.long.byte 0x00 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault"
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hexmask.long.byte 0x00 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage"
group.long 0xD1C++0x03
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. "PRI_11,Priority of System Handler" "0,1,2,3"
group.long 0xD20++0x03
line.long 0x00 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x00 30.--31. "PRI_15,Priority of System Handler" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_14,Priority of System Handler" "0,1,2,3"
tree.end
tree "TIMER (Timer/Counter)"
tree "TMR01"
base ad:0x40050000
group.long 0x00++0x03
line.long 0x00 "TIMER0_CTL,Timer0 Control Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.."
rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.."
bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x00 19. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.."
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bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled"
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bitfld.long 0x00 9. "TRGBPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled"
bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
group.long 0x04++0x03
line.long 0x00 "TIMER0_CMP,Timer0 Comparator Register"
abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
group.long 0x08++0x03
line.long 0x00 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
rgroup.long 0x0C++0x03
line.long 0x00 "TIMER0_CNT,Timer0 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value"
rgroup.long 0x10++0x03
line.long 0x00 "TIMER0_CAP,Timer0 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
group.long 0x14++0x03
line.long 0x00 "TIMER0_EXTCTL,Timer0 External Control Register"
bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Event Counter input source is from USB.."
bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,?,?,?,5: Capture Function source is from LIRC,?..."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin LIRC or ACMP detection..,1: TMx_EXT (x= 0~3) pin LIRC or ACMP detection.."
bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled"
bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on Tx_EXT (x= 0~3) pin LIRC or..,1: A Rising edge on Tx_EXT (x= 0~3) pin LIRC or..,2: Either Rising or Falling edge on Tx_EXT (x=..,3: Reserved"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
group.long 0x18++0x03
line.long 0x00 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
group.long 0x20++0x03
line.long 0x00 "TIMER1_CTL,Timer1 Control Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.."
rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.."
bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x00 19. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.."
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bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled"
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bitfld.long 0x00 9. "TRGBPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled"
bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
group.long 0x24++0x03
line.long 0x00 "TIMER1_CMP,Timer1 Comparator Register"
abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
group.long 0x28++0x03
line.long 0x00 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
group.long 0x2C++0x03
line.long 0x00 "TIMER1_CNT,Timer1 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value"
group.long 0x30++0x03
line.long 0x00 "TIMER1_CAP,Timer1 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
group.long 0x34++0x03
line.long 0x00 "TIMER1_EXTCTL,Timer1 External Control Register"
bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Event Counter input source is from USB.."
bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,?,?,?,5: Capture Function source is from LIRC,?..."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin LIRC or ACMP detection..,1: TMx_EXT (x= 0~3) pin LIRC or ACMP detection.."
bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled"
bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on Tx_EXT (x= 0~3) pin LIRC or..,1: A Rising edge on Tx_EXT (x= 0~3) pin LIRC or..,2: Either Rising or Falling edge on Tx_EXT (x=..,3: Reserved"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
group.long 0x38++0x03
line.long 0x00 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
tree.end
tree "TMR23"
base ad:0x40051000
group.long 0x00++0x03
line.long 0x00 "TIMER2_CTL,Timer2 Control Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.."
rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.."
bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x00 19. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.."
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bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled"
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bitfld.long 0x00 9. "TRGBPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled"
bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
group.long 0x04++0x03
line.long 0x00 "TIMER2_CMP,Timer2 Comparator Register"
abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
group.long 0x08++0x03
line.long 0x00 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
rgroup.long 0x0C++0x03
line.long 0x00 "TIMER2_CNT,Timer2 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value"
rgroup.long 0x10++0x03
line.long 0x00 "TIMER2_CAP,Timer2 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
group.long 0x14++0x03
line.long 0x00 "TIMER2_EXTCTL,Timer2 External Control Register"
bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Event Counter input source is from USB.."
bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,?,?,?,5: Capture Function source is from LIRC,?..."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin LIRC or ACMP detection..,1: TMx_EXT (x= 0~3) pin LIRC or ACMP detection.."
bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled"
bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on Tx_EXT (x= 0~3) pin LIRC or..,1: A Rising edge on Tx_EXT (x= 0~3) pin LIRC or..,2: Either Rising or Falling edge on Tx_EXT (x=..,3: Reserved"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
group.long 0x18++0x03
line.long 0x00 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
group.long 0x20++0x03
line.long 0x00 "TIMER3_CTL,Timer3 Control Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.."
rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.."
bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x00 19. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.."
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bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled"
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bitfld.long 0x00 9. "TRGBPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled"
bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
group.long 0x24++0x03
line.long 0x00 "TIMER3_CMP,Timer3 Comparator Register"
abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
group.long 0x28++0x03
line.long 0x00 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
group.long 0x2C++0x03
line.long 0x00 "TIMER3_CNT,Timer3 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value"
group.long 0x30++0x03
line.long 0x00 "TIMER3_CAP,Timer3 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
group.long 0x34++0x03
line.long 0x00 "TIMER3_EXTCTL,Timer3 External Control Register"
bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Event Counter input source is from USB.."
bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,?,?,?,5: Capture Function source is from LIRC,?..."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin LIRC or ACMP detection..,1: TMx_EXT (x= 0~3) pin LIRC or ACMP detection.."
bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled"
bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on Tx_EXT (x= 0~3) pin LIRC or..,1: A Rising edge on Tx_EXT (x= 0~3) pin LIRC or..,2: Either Rising or Falling edge on Tx_EXT (x=..,3: Reserved"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
group.long 0x38++0x03
line.long 0x00 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
tree.end
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
tree "UART0"
base ad:0x40070000
group.long 0x00++0x03
line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled"
bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
group.long 0x08++0x03
line.long 0x00 "UART_FIFO,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UART_LINE,UART Line Control Register"
bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\n" "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.long 0x10++0x03
line.long 0x00 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
group.long 0x14++0x03
line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
group.long 0x18++0x03
line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
group.long 0x1C++0x03
line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
group.long 0x24++0x03
line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,?,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
group.long 0x3C++0x03
line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
group.long 0x40++0x03
line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode.\n" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
group.long 0x44++0x03
line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
group.long 0x48++0x03
line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
tree.end
tree "UART1"
base ad:0x40071000
group.long 0x00++0x03
line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled"
bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
group.long 0x08++0x03
line.long 0x00 "UART_FIFO,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UART_LINE,UART Line Control Register"
bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\n" "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.long 0x10++0x03
line.long 0x00 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
group.long 0x14++0x03
line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
group.long 0x18++0x03
line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
group.long 0x1C++0x03
line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
group.long 0x24++0x03
line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,?,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
group.long 0x3C++0x03
line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
group.long 0x40++0x03
line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode.\n" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
group.long 0x44++0x03
line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
group.long 0x48++0x03
line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
tree.end
repeat 2. (list 2. 3.) (list ad:0x40072000 ad:0x40073000)
tree "UART$1"
base $2
group.long 0x00++0x03
line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled"
bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
group.long 0x08++0x03
line.long 0x00 "UART_FIFO,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UART_LINE,UART Line Control Register"
bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\n" "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.long 0x10++0x03
line.long 0x00 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
group.long 0x14++0x03
line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
group.long 0x18++0x03
line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
group.long 0x1C++0x03
line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
group.long 0x24++0x03
line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,?,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
group.long 0x40++0x03
line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode.\n" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
group.long 0x44++0x03
line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
group.long 0x48++0x03
line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
tree.end
repeat.end
repeat 2. (list 4. 5.) (list ad:0x40074000 ad:0x40075000)
tree "UART$1"
base $2
group.long 0x00++0x03
line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled"
bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
group.long 0x08++0x03
line.long 0x00 "UART_FIFO,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UART_LINE,UART Line Control Register"
bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\n" "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.long 0x10++0x03
line.long 0x00 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
group.long 0x14++0x03
line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
group.long 0x18++0x03
line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
group.long 0x1C++0x03
line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
group.long 0x24++0x03
line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,?,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
group.long 0x3C++0x03
line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
group.long 0x40++0x03
line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode.\n" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
group.long 0x44++0x03
line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
group.long 0x48++0x03
line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
tree.end
repeat.end
repeat 2. (list 6. 7.) (list ad:0x40076000 ad:0x40077000)
tree "UART$1"
base $2
group.long 0x00++0x03
line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled"
bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
group.long 0x08++0x03
line.long 0x00 "UART_FIFO,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UART_LINE,UART Line Control Register"
bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\n" "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.long 0x10++0x03
line.long 0x00 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
group.long 0x14++0x03
line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
group.long 0x18++0x03
line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
group.long 0x1C++0x03
line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
group.long 0x24++0x03
line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,?,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
group.long 0x40++0x03
line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode.\n" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
group.long 0x44++0x03
line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
group.long 0x48++0x03
line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.."
tree.end
repeat.end
tree.end
tree "UI2CI2C (UI2CI2C Register Map)"
repeat 2. (list 0. 1.) (list ad:0x400D0000 ad:0x400D1000)
tree "UI2C$1"
base $2
group.long 0x00++0x03
line.long 0x00 "UI2C_CTL,USCI Control Register"
bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
group.long 0x08++0x03
line.long 0x00 "UI2C_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
group.long 0x2C++0x03
line.long 0x00 "UI2C_LINECTL,USCI Line Control Register"
bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x03
line.long 0x00 "UI2C_TXDAT,USCI Transmit Data Register"
hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
rgroup.long 0x34++0x03
line.long 0x00 "UI2C_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C"
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0x44)++0x03
line.long 0x00 "UI2C_DEVADDR$1,USCI Device Address Register $1"
abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software set 10'h000 the address.."
repeat.end
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0x4C)++0x03
line.long 0x00 "UI2C_ADDRMSK$1,USCI Device Address Mask Register $1"
hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
repeat.end
group.long 0x54++0x03
line.long 0x00 "UI2C_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according receive..,1: The chip is woken up according address match"
bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
group.long 0x58++0x03
line.long 0x00 "UI2C_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
group.long 0x5C++0x03
line.long 0x00 "UI2C_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x00 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
hexmask.long.word 0x00 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear"
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bitfld.long 0x00 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode" "0: The monitor mode Disabled,1: The monitor mode Enabled"
bitfld.long 0x00 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low" "0: SCL output will be forced high due to open..,1: I2C module may act as a slave peripheral just.."
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bitfld.long 0x00 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested" "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
bitfld.long 0x00 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
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bitfld.long 0x00 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
bitfld.long 0x00 2. "STO,I2C STOP Control" "0,1"
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bitfld.long 0x00 1. "AA,Assert Acknowledge Control" "0,1"
bitfld.long 0x00 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
group.long 0x60++0x03
line.long 0x00 "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0x00 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master" "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
bitfld.long 0x00 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12]))" "0: The error interrupt Disabled,1: The error interrupt Enabled"
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bitfld.long 0x00 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected" "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
bitfld.long 0x00 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master" "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled"
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bitfld.long 0x00 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected" "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
bitfld.long 0x00 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected" "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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bitfld.long 0x00 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event" "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
group.long 0x64++0x03
line.long 0x00 "UI2C_PROTSTS,USCI Protocol Status Register"
bitfld.long 0x00 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor" "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
bitfld.long 0x00 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status" "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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bitfld.long 0x00 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
bitfld.long 0x00 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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bitfld.long 0x00 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
bitfld.long 0x00 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: The device is not selected as slave,1: The device is selected as slave"
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bitfld.long 0x00 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
bitfld.long 0x00 12. "ERRIF,Error Interrupt Flag\n" "0: An I2C error has not been detected,1: An I2C error has been detected"
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bitfld.long 0x00 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost"
bitfld.long 0x00 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
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bitfld.long 0x00 9. "STORIF,Stop Condition Received Interrupt Flag\n" "0: A stop condition has not yet been detected,1: A stop condition has been detected"
bitfld.long 0x00 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode" "0: A start condition has not yet been detected,1: A start condition has been detected"
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bitfld.long 0x00 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
bitfld.long 0x00 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
group.long 0x88++0x03
line.long 0x00 "UI2C_ADMAT,I2C Slave Match Address Register"
bitfld.long 0x00 1. "ADMAT1,USCI Address 1 Match Status Register\nWhen address 1 is matched hardware will inform which address used" "0,1"
bitfld.long 0x00 0. "ADMAT0,USCI Address 0 Match Status Register\nWhen address 0 is matched hardware will inform which address used" "0,1"
group.long 0x8C++0x03
line.long 0x00 "UI2C_TMCTL,I2C Timing Configure Control Register"
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.\nNote: Hold time adjust function can only work in master mode when slave mode this field should set as 0"
hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode"
tree.end
repeat.end
tree.end
tree "USBD (Universal Serial Bus Device)"
base ad:0x400C0000
group.long 0x00++0x03
line.long 0x00 "USBD_INTEN,USB Device Interrupt Enable Register"
bitfld.long 0x00 15. "INNAKEN,Active NAK Function and Its Status in IN Token" "0: When device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS0.."
bitfld.long 0x00 8. "WKEN,Wake-up Function Enable Bit" "0: USB wake-up function Disabled,1: USB wake-up function Enabled"
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bitfld.long 0x00 4. "SOFIEN,Start of Frame Interrupt Enable Bit" "0: SOF Interrupt Disabled,1: SOF Interrupt Enabled"
bitfld.long 0x00 3. "NEVWKIEN,USB No-event-wake-up Interrupt Enable Bit" "0: No-event-wake-up Interrupt Disabled,1: No-event-wake-up Interrupt Enabled"
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bitfld.long 0x00 2. "VBDETIEN,VBUS Detection Interrupt Enable Bit" "0: VBUS detection Interrupt Disabled,1: VBUS detection Interrupt Enabled"
bitfld.long 0x00 1. "USBIEN,USB Event Interrupt Enable Bit" "0: USB event interrupt Disabled,1: USB event interrupt Enabled"
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bitfld.long 0x00 0. "BUSIEN,Bus Event Interrupt Enable Bit" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled"
group.long 0x04++0x03
line.long 0x00 "USBD_INTSTS,USB Device Interrupt Event Status Register"
bitfld.long 0x00 31. "SETUP,Setup Event Status" "0: No Setup event,1: Setup event occurred cleared by write 1 to.."
bitfld.long 0x00 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7 check.."
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bitfld.long 0x00 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6 check.."
bitfld.long 0x00 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5 check.."
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bitfld.long 0x00 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4 check.."
bitfld.long 0x00 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3 check.."
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bitfld.long 0x00 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2 check.."
bitfld.long 0x00 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1 check.."
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bitfld.long 0x00 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0 check.."
bitfld.long 0x00 4. "SOFIF,Start of Frame Interrupt Status" "0: SOF event does not occur,1: SOF event occurred cleared by write 1 to.."
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bitfld.long 0x00 3. "NEVWKIF,No-event-wake-up Interrupt Status" "0: NEVWK event does not occur,1: No-event-wake-up event occurred cleared by.."
bitfld.long 0x00 2. "VBDETIF,VBUS Detection Interrupt Status" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB.."
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bitfld.long 0x00 1. "USBIF,USB Event Interrupt Status\nThe USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus" "0: No USB event occurred,1: USB event occurred check EPSTS0~7[2:0] to.."
bitfld.long 0x00 0. "BUSIF,BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus" "0: No BUS event occurred,1: Bus event occurred check USBD_ATTR[3:0] to.."
group.long 0x08++0x03
line.long 0x00 "USBD_FADDR,USB Device Function Address Register"
hexmask.long.byte 0x00 0.--6. 1. "FADDR,USB Device Function Address"
rgroup.long 0x0C++0x03
line.long 0x00 "USBD_EPSTS,USB Device Endpoint Status Register"
bitfld.long 0x00 7. "OV,Overrun\nIt indicates that the received data is over the maximum payload number or not.\nif received data is over the maximum payload number the extra data will be ignored" "0: No overrun,1: Out Data is more than the Max Payload in.."
group.long 0x10++0x03
line.long 0x00 "USBD_ATTR,USB Device Bus Status and Attribution Register"
rbitfld.long 0x00 13. "L1RESUME,LPM L1 Resume (Read Only)" "0: Bus no LPM L1 state resume,1: LPM L1 state Resume from LPM L1 state suspend"
rbitfld.long 0x00 12. "L1SUSPEND,LPM L1 Suspend (Read Only)" "0: Bus no L1 state suspend,1: This bit is set by the hardware when LPM.."
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bitfld.long 0x00 11. "LPMACK,LPM Token Acknowledge Enable Bit" "0: the valid LPM Token will be NYET,1: the valid LPM Token will be ACK"
bitfld.long 0x00 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode,1: Byte mode"
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bitfld.long 0x00 9. "PWRDN,Power-down PHY Transceiver Low Active" "0: Power-down related circuit of PHY transceiver,1: Turn-on related circuit of PHY transceiver"
bitfld.long 0x00 8. "DPPUEN,Pull-up Resistor on USB_DP Enable Bit" "0: Pull-up resistor in USB_D+ bus Disabled,1: Pull-up resistor in USB_D+ bus Active"
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bitfld.long 0x00 7. "USBEN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled"
bitfld.long 0x00 5. "RWAKEUP,Remote Wake-up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D-: high).."
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bitfld.long 0x00 4. "PHYEN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled"
rbitfld.long 0x00 3. "TOUT,Time-out Status (Read Only)\nWhen USB Device controller after received setup token or out token USB controller stay J state to wait data package" "0: No time-out,1: No Bus response more than 18 bits time"
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rbitfld.long 0x00 2. "RESUME,Resume Status (Read Only)" "0: No bus resume,1: Resume from suspend"
rbitfld.long 0x00 1. "SUSPEND,Suspend Status (Read Only)" "0: Bus no suspend,1: Bus idle more than 3ms either cable is.."
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rbitfld.long 0x00 0. "USBRST,USB Reset Status (Read Only)" "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) more than.."
rgroup.long 0x14++0x03
line.long 0x00 "USBD_VBUSDET,USB Device VBUS Detection Register"
bitfld.long 0x00 0. "VBUSDET,Device VBUS Detection" "0: Controller is not attached to the USB host,1: Controller is attached to the USB host"
group.long 0x18++0x03
line.long 0x00 "USBD_STBUFSEG,SETUP Token Buffer Segmentation Register"
bitfld.long 0x00 3.--8. "STBUFSEG,SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\nUSBD_SRAM address + {STBUFSEG 3'b000} \nNote: It is used for SETUP token.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x20++0x03
line.long 0x00 "USBD_EPSTS0,USB Device Endpoint Status Register 0"
bitfld.long 0x00 28.--31. "EPSTS7,Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
bitfld.long 0x00 24.--27. "EPSTS6,Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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bitfld.long 0x00 20.--23. "EPSTS5,Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
rgroup.long 0x88++0x03
line.long 0x00 "USBD_LPMATTR,USB LPM Attribution Register"
bitfld.long 0x00 8. "LPMRWAKUP,LPM Remote Wakeup\nThis bit contains the bRemoteWake value received with last ACK LPM Token" "0,1"
bitfld.long 0x00 4.--7. "LPMBESL,LPM Best Effort Service Latency\nThese bits contain the BESL value received with last ACK LPM Token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "LPMLINKSTS,LPM Link State\nThese bits contain the bLinkState received with last ACK LPM Token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x8C++0x03
line.long 0x00 "USBD_FN,USB Frame Number Register"
hexmask.long.word 0x00 0.--10. 1. "FN,Frame Number\nThese bits contain the 11-bits frame number in the last received SOF packet"
group.long 0x90++0x03
line.long 0x00 "USBD_SE0,USB Device Drive SE0 Control Register"
bitfld.long 0x00 0. "SE0,Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low" "0: Normal operation,1: Force USB PHY transceiver to drive SE0"
group.long 0x500++0x03
line.long 0x00 "USBD_BUFSEG0,Endpoint 0 Buffer Segmentation Register"
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG 3'b000}\nRefer to the section 6.22.5.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x504++0x03
line.long 0x00 "USBD_MXPLD0,Endpoint 0 Maximal Payload Register"
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
group.long 0x508++0x03
line.long 0x00 "USBD_CFG0,Endpoint 0 Configuration Register"
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nIN Token Transaction:\nThis bit is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50C++0x03
line.long 0x00 "USBD_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
group.long 0x510++0x03
line.long 0x00 "USBD_BUFSEG1,Endpoint 1 Buffer Segmentation Register"
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG 3'b000}\nRefer to the section 6.22.5.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x514++0x03
line.long 0x00 "USBD_MXPLD1,Endpoint 1 Maximal Payload Register"
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
group.long 0x518++0x03
line.long 0x00 "USBD_CFG1,Endpoint 1 Configuration Register"
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nIN Token Transaction:\nThis bit is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x51C++0x03
line.long 0x00 "USBD_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
group.long 0x520++0x03
line.long 0x00 "USBD_BUFSEG2,Endpoint 2 Buffer Segmentation Register"
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG 3'b000}\nRefer to the section 6.22.5.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x524++0x03
line.long 0x00 "USBD_MXPLD2,Endpoint 2 Maximal Payload Register"
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
group.long 0x528++0x03
line.long 0x00 "USBD_CFG2,Endpoint 2 Configuration Register"
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nIN Token Transaction:\nThis bit is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x52C++0x03
line.long 0x00 "USBD_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
group.long 0x530++0x03
line.long 0x00 "USBD_BUFSEG3,Endpoint 3 Buffer Segmentation Register"
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG 3'b000}\nRefer to the section 6.22.5.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x534++0x03
line.long 0x00 "USBD_MXPLD3,Endpoint 3 Maximal Payload Register"
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
group.long 0x538++0x03
line.long 0x00 "USBD_CFG3,Endpoint 3 Configuration Register"
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nIN Token Transaction:\nThis bit is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x53C++0x03
line.long 0x00 "USBD_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
group.long 0x540++0x03
line.long 0x00 "USBD_BUFSEG4,Endpoint 4 Buffer Segmentation Register"
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG 3'b000}\nRefer to the section 6.22.5.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x544++0x03
line.long 0x00 "USBD_MXPLD4,Endpoint 4 Maximal Payload Register"
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
group.long 0x548++0x03
line.long 0x00 "USBD_CFG4,Endpoint 4 Configuration Register"
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nIN Token Transaction:\nThis bit is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54C++0x03
line.long 0x00 "USBD_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
group.long 0x550++0x03
line.long 0x00 "USBD_BUFSEG5,Endpoint 5 Buffer Segmentation Register"
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG 3'b000}\nRefer to the section 6.22.5.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x554++0x03
line.long 0x00 "USBD_MXPLD5,Endpoint 5 Maximal Payload Register"
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
group.long 0x558++0x03
line.long 0x00 "USBD_CFG5,Endpoint 5 Configuration Register"
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nIN Token Transaction:\nThis bit is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x55C++0x03
line.long 0x00 "USBD_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
group.long 0x560++0x03
line.long 0x00 "USBD_BUFSEG6,Endpoint 6 Buffer Segmentation Register"
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG 3'b000}\nRefer to the section 6.22.5.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x564++0x03
line.long 0x00 "USBD_MXPLD6,Endpoint 6 Maximal Payload Register"
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
group.long 0x568++0x03
line.long 0x00 "USBD_CFG6,Endpoint 6 Configuration Register"
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nIN Token Transaction:\nThis bit is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x56C++0x03
line.long 0x00 "USBD_CFGP6,Endpoint 6 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
group.long 0x570++0x03
line.long 0x00 "USBD_BUFSEG7,Endpoint 7 Buffer Segmentation Register"
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + { BUFSEG 3'b000}\nRefer to the section 6.22.5.7.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x574++0x03
line.long 0x00 "USBD_MXPLD7,Endpoint 7 Maximal Payload Register"
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
group.long 0x578++0x03
line.long 0x00 "USBD_CFG7,Endpoint 7 Configuration Register"
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nIN Token Transaction:\nThis bit is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x57C++0x03
line.long 0x00 "USBD_CFGP7,Endpoint 7 Set Stall and Clear In/Out Ready Control Register"
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
tree.end
tree "USCISPI (USCISPI Register Map)"
repeat 2. (list 0. 1.) (list ad:0x400D0000 ad:0x400D1000)
tree "USPI$1"
base $2
group.long 0x00++0x03
line.long 0x00 "USPI_CTL,USCI Control Register"
bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
group.long 0x04++0x03
line.long 0x00 "USPI_INTEN,USCI Interrupt Enable Register"
bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode the receive start event happens when SPI master sends slave select active and spi clock to the external.." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
group.long 0x08++0x03
line.long 0x00 "USPI_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor" "0: fDIV_CLK,1: fPROT_CLK,2: fSCLK,3: fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
group.long 0x10++0x03
line.long 0x00 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
group.long 0x20++0x03
line.long 0x00 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
group.long 0x28++0x03
line.long 0x00 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift unit.\nNote: In SPI.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
group.long 0x2C++0x03
line.long 0x00 "USPI_LINECTL,USCI Line Control Register"
bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pins" "0: Data output values of USCIx_DAT0/1 pins are..,1: Data output values of USCIx_DAT0/1 pins are.."
bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x03
line.long 0x00 "USPI_TXDAT,USCI Transmit Data Register"
bitfld.long 0x00 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
rgroup.long 0x34++0x03
line.long 0x00 "USPI_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer"
group.long 0x38++0x03
line.long 0x00 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
bitfld.long 0x00 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the receive-related counters state.."
bitfld.long 0x00 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared"
bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared"
bitfld.long 0x00 6. "TXUDRIEN,Slave Transmit Under Run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
rgroup.long 0x3C++0x03
line.long 0x00 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
bitfld.long 0x00 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected" "0: A transmit buffer under-run event has not..,1: A transmit buffer under-run event has been.."
bitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for.."
bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected" "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been.."
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bitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
bitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
group.long 0x40++0x03
line.long 0x00 "USPI_PDMACTL,USCI PDMA Control Register"
bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
group.long 0x54++0x03
line.long 0x00 "USPI_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
group.long 0x58++0x03
line.long 0x00 "USPI_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
group.long 0x5C++0x03
line.long 0x00 "USPI_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x00 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
bitfld.long 0x00 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data value of USCIx_DAT1 when no data is available for transferring" "0: The output data value is 0 if TX under run..,1: The output data value is 1 if TX under run.."
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hexmask.long.word 0x00 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only)\nIn Slave mode this bit field is used for Slave time-out period"
bitfld.long 0x00 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "SUSPITV,Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge" "0,1,2,3"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
bitfld.long 0x00 2. "SS,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select back to inactive state.\nNote: In SPI protocol the internal slave.." "0,1"
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bitfld.long 0x00 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
bitfld.long 0x00 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
group.long 0x60++0x03
line.long 0x00 "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0x00 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])" "0: The Slave mode bit count error interrupt..,1: The Slave mode bit count error interrupt.."
bitfld.long 0x00 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event" "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled"
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bitfld.long 0x00 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active" "0: Slave select active interrupt generation..,1: Slave select active interrupt generation.."
bitfld.long 0x00 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation.."
group.long 0x64++0x03
line.long 0x00 "USPI_PROTSTS,USCI Protocol Status Register"
rbitfld.long 0x00 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1" "0: Slave transmit under run event does not occur,1: Slave transmit under run event occurs"
rbitfld.long 0x00 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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rbitfld.long 0x00 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
bitfld.long 0x00 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active" "0: The slave select signal has not changed to..,1: The slave select signal has changed to active"
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bitfld.long 0x00 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive" "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
bitfld.long 0x00 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave time-out event did not occur,1: Slave time-out event occurred"
bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive end event did not occur,1: Receive end event occurred"
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive start event did not occur,1: Receive start event occurred"
bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit end event did not occur,1: Transmit end event occurred"
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit start event did not occur,1: Transmit start event occurred"
tree.end
repeat.end
tree.end
tree "USCIUART (USCIUART Register Map)"
repeat 2. (list 0. 1.) (list ad:0x400D0000 ad:0x400D1000)
tree "UUART$1"
base $2
group.long 0x00++0x03
line.long 0x00 "UUART_CTL,USCI Control Register"
bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
group.long 0x04++0x03
line.long 0x00 "UUART_INTEN,USCI Interrupt Enable Register"
bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
group.long 0x08++0x03
line.long 0x00 "UUART_BRGEN,USCI Baud Rate Generator Register"
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled"
bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
bitfld.long 0x00 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
group.long 0x10++0x03
line.long 0x00 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
bitfld.long 0x00 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 10" "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,2: A falling edge activates the trigger event of..,3: Both edges activate the trigger event of.."
bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
group.long 0x20++0x03
line.long 0x00 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
group.long 0x28++0x03
line.long 0x00 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
group.long 0x2C++0x03
line.long 0x00 "UUART_LINECTL,USCI Line Control Register"
bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin" "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of.."
bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
wgroup.long 0x30++0x03
line.long 0x00 "UUART_TXDAT,USCI Transmit Data Register"
hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
rgroup.long 0x34++0x03
line.long 0x00 "UUART_RXDAT,USCI Receive Data Register"
hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])"
group.long 0x38++0x03
line.long 0x00 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
bitfld.long 0x00 17. "RXRST,Receive Reset\n" "0: No effect,1: Reset the receive-related counters state.."
bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared (filling level.."
bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared (filling level.."
rgroup.long 0x3C++0x03
line.long 0x00 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
bitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
bitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected" "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
bitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
group.long 0x40++0x03
line.long 0x00 "UUART_PDMACTL,USCI PDMA Control Register"
bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
group.long 0x54++0x03
line.long 0x00 "UUART_WKCTL,USCI Wake-up Control Register"
bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
group.long 0x58++0x03
line.long 0x00 "UUART_WKSTS,USCI Wake-up Status Register"
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
group.long 0x5C++0x03
line.long 0x00 "UUART_PROTCTL,USCI Protocol Control Register"
bitfld.long 0x00 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
bitfld.long 0x00 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x00 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information" "0: Stick parity Disabled,1: Stick parity Enabled"
hexmask.long.word 0x00 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits"
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bitfld.long 0x00 11.--14. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x00 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
bitfld.long 0x00 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x00 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART asserted nRTS signal automatically.\n" "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled"
bitfld.long 0x00 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x00 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame" "0: The parity bit Disabled,1: The parity bit Enabled"
bitfld.long 0x00 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame" "0: The number of stop bits is 1,1: The number of stop bits is 2"
group.long 0x60++0x03
line.long 0x00 "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt" "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
bitfld.long 0x00 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
group.long 0x64++0x03
line.long 0x00 "UUART_PROTSTS,USCI Protocol Status Register"
rbitfld.long 0x00 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
rbitfld.long 0x00 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal" "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x00 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun" "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun"
rbitfld.long 0x00 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver" "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x00 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data" "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
bitfld.long 0x00 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x00 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
bitfld.long 0x00 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive finish interrupt status has not..,1: A receive finish interrupt status has occurred"
bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive start interrupt status has not..,1: A receive start interrupt status has occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A transmit end interrupt status has not..,1: A transmit end interrupt status has occurred"
bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\n" "0: A transmit start interrupt status has not..,1: A transmit start interrupt status has occurred"
tree.end
repeat.end
tree.end
tree "WDT (Watchdog Timer Unit)"
base ad:0x40040000
group.long 0x00++0x03
line.long 0x00 "WDT_CTL,WDT Control Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
rbitfld.long 0x00 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 2 * WDT_CLK.." "0: Set WDTEN bit is completed,1: Set WDTEN bit is synchronizing and not become.."
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bitfld.long 0x00 8.--11. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese four bits select the time-out interval period for the WDT.\nNote: This bit is write protected" "0: 24 * WDT_CLK,1: 26 * WDT_CLK,2: 28 * WDT_CLK,3: 210 * WDT_CLK,4: 212 * WDT_CLK,5: 214 * WDT_CLK,6: 216 * WDT_CLK,7: 218 * WDT_CLK,8: 220 * WDT_CLK,?..."
bitfld.long 0x00 7. "WDTEN,WDT Enable Bit (Write Protect)\n" "0: WDT Disabled (This action will reset the..,1: WDT Enabled"
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bitfld.long 0x00 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
bitfld.long 0x00 5. "WKF,WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\n" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.."
bitfld.long 0x00 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
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bitfld.long 0x00 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
bitfld.long 0x00 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
group.long 0x04++0x03
line.long 0x00 "WDT_ALTCTL,WDT Alternative Control Register"
bitfld.long 0x00 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.\nUser can select a.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: WDT Reset Delay Period is 130 * WDT_CLK,2: WDT Reset Delay Period is 18 * WDT_CLK,3: WDT Reset Delay Period is 3 * WDT_CLK"
wgroup.long 0x08++0x03
line.long 0x00 "WDT_RSTCNT,WDT Reset Counter Register"
hexmask.long 0x00 0.--31. 1. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.\n"
tree.end
tree "WWDT (WWDT Register Map)"
base ad:0x40040100
wgroup.long 0x00++0x03
line.long 0x00 "WWDT_RLDCNT,WWDT Reload Counter Register"
hexmask.long 0x00 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.."
group.long 0x04++0x03
line.long 0x00 "WWDT_CTL,WWDT Control Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nNote: WWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 16.--21. "CMPDAT,WWDT Window Compare Register\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--11. "PSCSEL,WWDT Counter Prescale Period Selection" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.."
bitfld.long 0x00 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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bitfld.long 0x00 0. "WWDTEN,WWDT Enable Bit" "0: WWDT counter is stopped,1: WWDT counter starts counting"
group.long 0x08++0x03
line.long 0x00 "WWDT_STATUS,WWDT Status Register"
bitfld.long 0x00 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches CMPDAT"
rgroup.long 0x0C++0x03
line.long 0x00 "WWDT_CNT,WWDT Counter Value Register"
bitfld.long 0x00 0.--5. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
autoindent.off
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