4583 lines
300 KiB
Plaintext
4583 lines
300 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: LPC3180 On-Chip Peripherals
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; @Props: Released
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; @Author: -
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; @Changelog: 2007-05-15
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: user.manual.lpc3180.pdf (Rev. 01 - 2006-06-01)
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; @Core: ARM926EJ-S
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; @Chip: LPC3180
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perlpc3180.per 7592 2017-02-18 13:54:14Z askoncej $
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;Known problems:
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;base address of the "MLC NAND Flash controller" module shown on page 14 is different than base address of his registers
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config 16. 8.
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width 0xB
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tree "ARM Core Registers"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 8.
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tree "ID Registers"
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group c15:0x0000--0x0000
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line.long 0x0 "MIDR,Identity Code"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer"
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hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision"
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hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version"
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hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
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hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision"
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group c15:0x0100--0x0100
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line.long 0x0 "CTR,Cache Type"
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bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
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textline " "
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bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
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textline " "
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bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
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group c15:0x0200--0x0200
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line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register"
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bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes"
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bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes"
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tree.end
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tree "MMU Control and Configuration"
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width 8.
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group c15:0x0001--0x0001
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable"
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bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
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bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable"
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bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable"
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bitfld.long 0x0 7. " B ,Endianism" "Little,Big"
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textline " "
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bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU" "Disable,Enable"
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textline " "
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group c15:0x0002--0x0002
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line.long 0x0 "TTBR,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address"
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textline " "
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group c15:0x3--0x3
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line.long 0x0 "DACR,Domain Access Control Register"
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bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
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textline " "
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group c15:0x0005--0x0005
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line.long 0x0 "DFSR,Data Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0105--0x0105
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line.long 0x0 "IFSR,Instruction Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0006--0x0006
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line.long 0x0 "DFAR,Data Fault Address Register"
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textline " "
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group c15:0x000a--0x000a
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line.long 0x0 "TLBR,TLB Lockdown Register"
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bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. " P ,P bit" "0,1"
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textline " "
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group c15:0x000d--0x000d
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line.long 0x0 "FCSEPID,FCSE Process ID"
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group c15:0x010d--0x010d
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line.long 0x0 "CONTEXT,Context ID"
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tree.end
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tree "Cache Control and Configuration"
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group c15:0x0009--0x0009
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line.long 0x0 "DCACHE,Data Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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group c15:0x0109--0x0109
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line.long 0x0 "ICACHE,Instruction Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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tree.end
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tree "TCM Control and Configuration"
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group c15:0x0019--0x0019
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line.long 0x0 "DTCM,Data TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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group c15:0x0119--0x0119
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line.long 0x0 "ITCM,Instruction TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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tree.end
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tree "Test and Debug"
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group c15:0x000f--0x000f
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line.long 0x0 "DOVRR,Debug Override Register"
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bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable"
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bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort"
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bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort"
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textline " "
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bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable"
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bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable"
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bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable"
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bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT"
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group c15:0x001f--0x001f
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line.long 0x0 "ADDRESS,Debug/Test Address"
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;wgroup c15:0x402f--0x402f
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; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry"
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;wgroup c15:0x403f--0x403f
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; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry"
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;wgroup c15:0x404f--0x404f
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; line.long 0x0 "RMTLBPA,Read PA in main TLB entry"
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;wgroup c15:0x405f--0x405f
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; line.long 0x0 "WMTLBPA,Write PA in main TLB entry"
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;wgroup c15:0x407f--0x407f
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; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM"
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;wgroup c15:0x412f--0x412f
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; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry"
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;wgroup c15:0x413f--0x413f
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; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry"
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;wgroup c15:0x414f--0x414f
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; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry"
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;wgroup c15:0x415f--0x415f
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; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry"
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;wgroup c15:0x417f--0x417f
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; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM"
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group c15:0x101f--0x101f
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line.long 0x0 "TRACE,Trace Control"
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bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall"
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bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall"
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group c15:0x700f--0x700f
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line.long 0x0 "CACHE,Cache Debug Control"
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bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through"
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bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable"
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bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable"
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group c15:0x701f--0x701f
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line.long 0x0 "MMU,MMU Debug Control"
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bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable"
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textline " "
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bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable"
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group c15:0x002f--0x002f
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line.long 0x0 "REMAP,Memory Region Remap"
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bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB"
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textline " "
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bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB"
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tree.end
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tree "ICEbreaker"
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width 8.
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group ice:0x0--0x5 "Debug Control"
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line.long 0x0 "DBGCTRL,Debug Control Register"
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bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled"
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bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled"
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textline " "
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bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled"
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bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled"
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bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x4 "DBGSTAT,Debug Status Register"
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bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
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bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java"
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bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb"
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bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1"
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bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled"
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bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x8 "VECTOR,Vector Catch Register"
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bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena"
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bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena"
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bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena"
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bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena"
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bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena"
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bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena"
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bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena"
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line.long 0x10 "COMCTRL,Debug Communication Control Register"
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bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
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bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend"
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bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend"
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line.long 0x14 "COMDATA,Debug Communication Data Register"
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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tree.end
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AUTOINDENT.POP
|
|
tree.end
|
|
tree "System Control"
|
|
base ad:0x40004014
|
|
width 10.
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "BOOT_MAP,Boot Map Control Register"
|
|
bitfld.long 0x0 0. " ARM_Res_Vec ,Internal ROM/RAM located in the ARM reset vector" "IROM,IRAM"
|
|
width 0xB
|
|
tree.end
|
|
tree "Clocking And Power Control"
|
|
base ad:0x40004000
|
|
width 15.
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "PWR_CTRL,Power Control Register"
|
|
bitfld.long 0x0 10. " HCLK/ARMCLKRun ,Force HCLK and ARMCLK to run with PERIPH_CLK frequency" "Normal mode,PERIPH_CLK"
|
|
bitfld.long 0x0 9. " MPMCSRefReq ,SDRAM self refresh request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 8. " MPMCSRefReqUpd ,MPMCSREFREQ update" "No action,Update"
|
|
bitfld.long 0x0 7. " SDRAMAESRefEn ,SDRAM auto exit self refresh enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " USB_HCLKCtrl ,HCLK to the USB block enable" "Enabled,Disabled"
|
|
bitfld.long 0x0 5. " HIGHCOREPLvl ,HIGHCORE pin level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " SYSCLKENPLvl ,SYSCLKEN pin level" "Low,High"
|
|
bitfld.long 0x0 3. " SYSCLKEN ,SYSCLKEN mode (Not STOP/STOP)" "High/Tri-state,SYSCLKENPLvl"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RUNModCtrl ,RUN mode control" "Direct,Normal"
|
|
bitfld.long 0x0 1. " HIGHCORE ,Core voltage supply level signalling control (STOP/Not STOP)" "High/Low,HIGHCOREPLvl"
|
|
textline " "
|
|
bitfld.long 0x0 0. " STOPModCtrl ,Device STOP mode control" "Not in STOP,In STOP"
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "OSC_CTRL,Main Oscillator Control Register"
|
|
hexmask.long.byte 0x0 2.--8. 1. " CapLoad ,SYSX_IN and SYSX_OUT capatitance load (X 0.1 pF)"
|
|
bitfld.long 0x0 1. " MainOscTest ,Main oscillator test mode" "Normal,Test"
|
|
textline " "
|
|
bitfld.long 0x0 0. " MainOscEn ,Main oscillator enable" "Enabled,Disabled"
|
|
line.long 0x4 "SYSCLK_CTRL,SYSCLK Control Register"
|
|
hexmask.long.word 0x4 2.--11. 1. " TRIGGWAIT ,How long a bad phase must be present before the clock switching is triggered"
|
|
textline " "
|
|
bitfld.long 0x4 1. " CLKSourc ,13 MHz clock source/Main oscillator" "Main oscillator,13 MHz clock source"
|
|
textline " "
|
|
bitfld.long 0x4 0. " SYSCLKMUX ,SYSCLK MUX status (clock source)" "Main oscillator,13 MHz PLL397 output"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PLL397_CTRL,PLL397 Control Register"
|
|
bitfld.long 0x0 10. " PLLMSLock ,PLL main lock" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x0 9. " PLL397Byp ,PLL397 bypass control" "No bypass,Bypass"
|
|
textline " "
|
|
bitfld.long 0x0 6.--8. " PLL397Bias ,PLL397 charge pump bias control" "Normal setting,-12.5% of resistance,-25% of resistance,-37.5% of resistance,+12.5% of resistance,+25% of resistance,+37.5% of resistance,+50% of resistance"
|
|
textline " "
|
|
bitfld.long 0x0 1. " PLL397Oper ,PLL397 operational control" "Running,Stopped"
|
|
textline " "
|
|
bitfld.long 0x0 0. " PLLLockStat ,PLL lock status" "Not locked,Locked"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "HCLKPLL_CTRL,HCLK PLL Control Register"
|
|
bitfld.long 0x0 16. " PLLPwDn ,PLL Power down mode" "Power down,Operating"
|
|
textline " "
|
|
bitfld.long 0x0 15. " BYPASSCtrl ,Bypass control" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x0 14. " DIROUTPCtrl ,PLL direct output control" "Post driver,CCO clock"
|
|
textline " "
|
|
bitfld.long 0x0 13. " FBackDiv ,Feedback divider path control" "CCO clock,PLL_CLKOUT"
|
|
textline " "
|
|
bitfld.long 0x0 11.--12. " PLLPDivide ,PLL post-divider (P) setting" "P=1,P=2,P=4,P=8"
|
|
textline " "
|
|
bitfld.long 0x0 9.--10. " PLLNDivider ,PLL pre-divider (N) setting" "N=1,N=2,N=3,N=4"
|
|
textline " "
|
|
hexmask.long.byte 0x0 1.--8. 1. " PLLMDivider ,PLL feedback divider (M) setting"
|
|
textline " "
|
|
bitfld.long 0x0 0. " PLLLockStat ,PLL lock status" "Not locked,Locked"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "HCLKDIV_CTRL,HCLK Divider Control Register"
|
|
bitfld.long 0x0 7.--8. " DDRAM_CLK ,DDRAM_CLK control" "Stopped,Nominal speed,Half speed,?..."
|
|
textline " "
|
|
bitfld.long 0x0 2.--6. " PERIPHCLKDiv ,PERIPH_CLK divider control" "Not divided,Divided by 2,Divided by 3,Divided by 4,Divided by 5,Divided by 6,Divided by 7,Divided by 8,Divided by 9,Divided by 10,Divided by 11,Divided by 12,Divided by 13,Divided by 14,Divided by 15,Divided by 16,Divided by 17,Divided by 18,Divided by 19,Divided by 20,Divided by 21,Divided by 22,Divided by 23,Divided by 24,Divided by 25,Divided by 26,Divided by 27,Divided by 28,Divided by 29,Divided by 30,Divided by 31,Divided by 32"
|
|
textline " "
|
|
bitfld.long 0x0 0.--1. " HCLKDiv ,HCLK divider control" "Not divided,Divided by 2,Divided by 4,?..."
|
|
group.long 0xA4++0x3
|
|
line.long 0x0 "TEST_CLK,Test Clock Selection Register"
|
|
bitfld.long 0x0 5.--6. " GPO_00/TEST_CLK1Out ,Output on GPO_00/TEST_CLK1 pin" "PERIPH_CLK,RTC clock,Main oscillator,?..."
|
|
textline " "
|
|
bitfld.long 0x0 4. " GPO_00/TST_CLK1Mod ,GPO_00 / TST_CLK1 output mode" "Connected to GPIO,GPO_00/TEST_CLK1Out"
|
|
textline " "
|
|
bitfld.long 0x0 1.--3. " TST_CLK2Out ,Output on TST_CLK2 pin" "HCLK,PERIPH_CLK,USB clock,Reserved,Reserved,Main oscillator,Reserved,PLL397 output"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TST_CLK2Mod ,TST_CLK2O mode" "Turned off,TST_CLK2Out"
|
|
group.long 0xEC++0x3
|
|
line.long 0x0 "AUTOCLK_CTRL,Autoclock Control Register"
|
|
bitfld.long 0x0 6. " ACLKUSB ,Autoclock enable on USB Slave HCLK" "Stop after 128 HCLK,Always clocked"
|
|
textline " "
|
|
bitfld.long 0x0 1. " ACLKIRAM ,Autoclock enable on IRAM" "Stop after 16 HCLK,Always clocked"
|
|
textline " "
|
|
bitfld.long 0x0 0. " ACLKIROM ,Autoclock enable on IROM" "Stop after 8 HCLK,Always clocked"
|
|
tree "Start Enable Registers"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "START_ER_INT,Start Enable Register for Internal Sources"
|
|
bitfld.long 0x0 31. " AD_IRQ , ADC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " USB_AHB_NEED_CLK ,USB_AHB_NEED_CLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " MSTIMER_INT ,MSTIMER interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " RTC_INT ,RTC interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 23. " USB_NEED_CLK ,USB_NEED_CLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " USB_INT ,USB interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 21. " USB_I2C_INT ,USB_I2C interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " USB_OTG_TIMER_INT ,USB_OTG_TIMER interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " USB_OTG_ATX_INT_N ,USB_OTG_ATX interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " KEY_IRQ ,Keyboard scanner interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_05 ,GPIO_05 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " GPIO_04 ,GPIO_04 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_03 ,GPIO_03 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " GPIO_02 ,GPIO_02 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_01 ,GPIO_01 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " GPIO_00 ,GPIO_00 enable" "Disabled,Enabled"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "START_ER_PIN,Start Enable register for Pin Sources"
|
|
bitfld.long 0x0 31. " U7_RX ,U7_RX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " U7_HCTS ,U7_HCTS pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " U6_IRRX ,U6_IRRX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " U5_RX ,U5_RX/USB_DAT_VP pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPI_11 ,GPI_11 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " U3_RX ,U3_RX pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 23. " U2_HCTS ,U2_HCTS pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " U2_RX ,U2_RX pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 21. " U1_RX ,U1_RX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 18. " SDIO_INT_N ,SDIO_INT_N (MS_DIO[1] pin) pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 17. " MSDIO_START ,MSDIO_START (logical OR of MS_DIO[3:0]) pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " GPI_06 ,GPI_06/HSTIM_CAP pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPI_05 ,GPI_05 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " GPI_04 ,GPI_04 pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPI_03 ,GPI_03 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 12. " GPI_02 ,GPI_02 pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPI_01 ,GPI_01/SERVICE_N pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " GPI_00 ,GPI_00 pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " SYSCLKEN ,SYSCLKEN pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " SPI1_DATIN ,SPI1_DATIN pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPI_07 ,GPI_07 pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " SPI2_DATIN ,SPI2_DATIN pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPI_10 ,GPI_10/U4_RX pin enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " GPI_09 ,GPI_09 pin enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPI_08 ,GPI_08 pin enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Start Status Registers"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "START_RSR_INT,Start Raw Status Register for Internal Sources"
|
|
eventfld.long 0x0 31. " AD_IRQ , ADC interrupt active before masking" "Inactive,Active"
|
|
eventfld.long 0x0 26. " USB_AHB_NEED_CLK ,USB_AHB_NEED_CLK active before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 25. " MSTIMER_INT ,MSTIMER interrupt active before masking" "Inactive,Active"
|
|
eventfld.long 0x0 24. " RTC_INT ,RTC interrupt active before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 23. " USB_NEED_CLK ,USB_NEED_CLK active before masking" "Inactive,Active"
|
|
eventfld.long 0x0 22. " USB_INT ,USB interrupt active before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 21. " USB_I2C_INT ,USB_I2C interrupt active before masking" "Inactive,Active"
|
|
eventfld.long 0x0 20. " USB_OTG_TIMER_INT ,USB_OTG_TIMER interrupt active before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 19. " USB_OTG_ATX_INT_N ,USB_OTG_ATX interrupt active before masking" "Inactive,Active"
|
|
eventfld.long 0x0 16. " KEY_IRQ ,Keyboard scanner interrupt active before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 5. " GPIO_05 ,GPIO_05 active before masking" "Inactive,Active"
|
|
eventfld.long 0x0 4. " GPIO_04 ,GPIO_04 active before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 3. " GPIO_03 ,GPIO_03 active before masking" "Inactive,Active"
|
|
eventfld.long 0x0 2. " GPIO_02 ,GPIO_02 active before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 1. " GPIO_01 ,GPIO_01 active before masking" "Inactive,Active"
|
|
eventfld.long 0x0 0. " GPIO_00 ,GPIO_00 active before masking" "Inactive,Active"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "START_RSR_PIN,Start Raw Status Register for Pin Sources"
|
|
eventfld.long 0x0 31. " U7_RX ,U7_RX pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 30. " U7_HCTS ,U7_HCTS pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 28. " U6_IRRX ,U6_IRRX pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 26. " U5_RX ,U5_RX/USB_DAT_VP pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 25. " GPI_11 ,GPI_11 pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 24. " U3_RX ,U3_RX pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 23. " U2_HCTS ,U2_HCTS pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 22. " U2_RX ,U2_RX pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 21. " U1_RX ,U1_RX pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 18. " SDIO_INT_N ,SDIO_INT_N (MS_DIO[1] pin) pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 17. " MSDIO_START ,MSDIO_START (logical OR of MS_DIO[3:0]) pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 16. " GPI_06 ,GPI_06/HSTIM_CAP pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 15. " GPI_05 ,GPI_05 pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 14. " GPI_04 ,GPI_04 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 13. " GPI_03 ,GPI_03 pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 12. " GPI_02 ,GPI_02 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 11. " GPI_01 ,GPI_01/SERVICE_N pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 10. " GPI_00 ,GPI_00 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 9. " SYSCLKEN ,SYSCLKEN pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 8. " SPI1_DATIN ,SPI1_DATIN pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 7. " GPI_07 ,GPI_07 pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 6. " SPI2_DATIN ,SPI2_DATIN pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 5. " GPI_10 ,GPI_10/U4_RX pin state before masking" "Inactive,Active"
|
|
eventfld.long 0x0 4. " GPI_09 ,GPI_09 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 3. " GPI_08 ,GPI_08 pin state before masking" "Inactive,Active"
|
|
group.long 0x28++0x03
|
|
line.long 0x0 "START_SR_INT,Start Status Register for Internal Sources"
|
|
bitfld.long 0x0 31. " AD_IRQ , ADC interrupt active before masking" "Inactive,Active"
|
|
bitfld.long 0x0 26. " USB_AHB_NEED_CLK ,USB_AHB_NEED_CLK active before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 25. " MSTIMER_INT ,MSTIMER interrupt active before masking" "Inactive,Active"
|
|
bitfld.long 0x0 24. " RTC_INT ,RTC interrupt active before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 23. " USB_NEED_CLK ,USB_NEED_CLK active before masking" "Inactive,Active"
|
|
bitfld.long 0x0 22. " USB_INT ,USB interrupt active before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 21. " USB_I2C_INT ,USB_I2C interrupt active before masking" "Inactive,Active"
|
|
bitfld.long 0x0 20. " USB_OTG_TIMER_INT ,USB_OTG_TIMER interrupt active before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 19. " USB_OTG_ATX_INT_N ,USB_OTG_ATX interrupt active before masking" "Inactive,Active"
|
|
bitfld.long 0x0 16. " KEY_IRQ ,Keyboard scanner interrupt active before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_05 ,GPIO_05 active before masking" "Inactive,Active"
|
|
bitfld.long 0x0 4. " GPIO_04 ,GPIO_04 active before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_03 ,GPIO_03 active before masking" "Inactive,Active"
|
|
bitfld.long 0x0 2. " GPIO_02 ,GPIO_02 active before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_01 ,GPIO_01 active before masking" "Inactive,Active"
|
|
bitfld.long 0x0 0. " GPIO_00 ,GPIO_00 active before masking" "Inactive,Active"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "START_SR_PIN,Start Status Register for Pin Sources"
|
|
bitfld.long 0x0 31. " U7_RX ,U7_RX pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 30. " U7_HCTS ,U7_HCTS pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 28. " U6_IRRX ,U6_IRRX pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 26. " U5_RX ,U5_RX/USB_DAT_VP pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPI_11 ,GPI_11 pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 24. " U3_RX ,U3_RX pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 23. " U2_HCTS ,U2_HCTS pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 22. " U2_RX ,U2_RX pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 21. " U1_RX ,U1_RX pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 18. " SDIO_INT_N ,SDIO_INT_N (MS_DIO[1] pin) pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 17. " MSDIO_START ,MSDIO_START (logical OR of MS_DIO[3:0]) pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 16. " GPI_06 ,GPI_06/HSTIM_CAP pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPI_05 ,GPI_05 pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 14. " GPI_04 ,GPI_04 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPI_03 ,GPI_03 pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 12. " GPI_02 ,GPI_02 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPI_01 ,GPI_01/SERVICE_N pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 10. " GPI_00 ,GPI_00 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 9. " SYSCLKEN ,SYSCLKEN pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 8. " SPI1_DATIN ,SPI1_DATIN pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPI_07 ,GPI_07 pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 6. " SPI2_DATIN ,SPI2_DATIN pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPI_10 ,GPI_10/U4_RX pin state before masking" "Inactive,Active"
|
|
bitfld.long 0x0 4. " GPI_09 ,GPI_09 pin state before masking" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPI_08 ,GPI_08 pin state before masking" "Inactive,Active"
|
|
tree.end
|
|
tree "Start Activation Polarity Registers"
|
|
textline ""
|
|
group.long 0x2C++0x03
|
|
line.long 0x0 "START_APR_INT,Start Activation Polarity Register for Internal Sources"
|
|
bitfld.long 0x0 31. " AD_IRQ , ADC interrupt rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 26. " USB_AHB_NEED_CLK ,USB_AHB_NEED_CLK rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 25. " MSTIMER_INT ,MSTIMER interrupt rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 24. " RTC_INT ,RTC interrupt rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 23. " USB_NEED_CLK ,USB_NEED_CLK rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 22. " USB_INT ,USB interrupt rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 21. " USB_I2C_INT ,USB_I2C interrupt rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 20. " USB_OTG_TIMER_INT ,USB_OTG_TIMER interrupt rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 19. " USB_OTG_ATX_INT_N ,USB_OTG_ATX interrupt rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 16. " KEY_IRQ ,Keyboard scanner interrupt rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_05 ,GPIO_05 rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 4. " GPIO_04 ,GPIO_04 rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_03 ,GPIO_03 rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 2. " GPIO_02 ,GPIO_02 rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_01 ,GPIO_01 rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 0. " GPIO_00 ,GPIO_00 rising edge state capture" "Falling,Rising"
|
|
group.long 0x3C++0x03
|
|
line.long 0x0 "START_APR_PIN,Start Activation Polarity Register for Pin Sources"
|
|
bitfld.long 0x0 31. " U7_RX ,U7_RX pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 30. " U7_HCTS ,U7_HCTS pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 28. " U6_IRRX ,U6_IRRX pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 26. " U5_RX ,U5_RX/USB_DAT_VP pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPI_11 ,GPI_11 pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 24. " U3_RX ,U3_RX pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 23. " U2_HCTS ,U2_HCTS pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 22. " U2_RX ,U2_RX pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 21. " U1_RX ,U1_RX pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 18. " SDIO_INT_N ,SDIO_INT_N (MS_DIO[1] pin) pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 17. " MSDIO_START ,MSDIO_START (logical OR of MS_DIO[3:0]) pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 16. " GPI_06 ,GPI_06/HSTIM_CAP pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPI_05 ,GPI_05 pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 14. " GPI_04 ,GPI_04 pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPI_03 ,GPI_03 pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 12. " GPI_02 ,GPI_02 pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPI_01 ,GPI_01/SERVICE_N pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 10. " GPI_00 ,GPI_00 pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 9. " SYSCLKEN ,SYSCLKEN pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 8. " SPI1_DATIN ,SPI1_DATIN pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPI_07 ,GPI_07 pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 6. " SPI2_DATIN ,SPI2_DATIN pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPI_10 ,GPI_10/U4_RX pin Rising edge state capture" "Falling,Rising"
|
|
bitfld.long 0x0 4. " GPI_09 ,GPI_09 pin Rising edge state capture" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPI_08 ,GPI_08 pin Rising edge state capture" "Falling,Rising"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "DMACLK_CTRL,DMA Clock Control Register"
|
|
bitfld.long 0x0 0. " DMACLKEn ,All clocks to DMA enable" "Stopped,Enabled"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "UARTCLK_CTRL,UART Clock Control Register"
|
|
bitfld.long 0x0 3. " Uart6 ,Uart6 HCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " Uart5 ,Uart5 HCLK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " Uart4 ,Uart4 HCLK enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " Uart3 ,Uart3 HCLK enable" "Disabled,Enabled"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "USB_CTRL,USB Control Register"
|
|
bitfld.long 0x0 24. " USBSlaveHCLK ,USB Slave HCLK control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 23. " USB_I2CEn ,Control signal for mux" "ip_3506_otg_tx_en_n,'0'"
|
|
textline " "
|
|
bitfld.long 0x0 22. " USBDevNeedClk ,Usb_dev_need_clk enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 21. " USBHostNeedClk ,Usb_host_need_clk enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19.--20. " PadsCtrl ,Pad control for USB_DAT_VP and USB_SE0_VM pads" "Pull-up added to pad,Bus keeper,No added function,Pull-down added to pad"
|
|
textline " "
|
|
bitfld.long 0x0 18. " USB_Clken2 ,USB_Clken2 clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 17. " USB_Clken1 ,USB_Clken1 clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " PLLPwrDown ,PLL Power down mode" "Power down,Operating"
|
|
textline " "
|
|
bitfld.long 0x0 15. " BypassCtrl ,Bypass control" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x0 14. " DirOutCtrl ,Direct output control" "Post driver,CCO clock"
|
|
textline " "
|
|
bitfld.long 0x0 13. " FBackDrivPath ,Feedback divider path control" "CCO clock,post PLL_CLKOUT"
|
|
textline " "
|
|
bitfld.long 0x0 11.--12. " PLLPostDiv ,PLL post-divider (P) setting" "Divide by 2 (P=1),Divide by 4 (P=2),Divide by 8 (P=4),Divide by 16 (P=8)"
|
|
textline " "
|
|
bitfld.long 0x0 9.--10. " PLLPreDiv ,PLL pre-divider (N) setting" "1,2,3,4"
|
|
textline " "
|
|
hexmask.long.byte 0x0 1.--8. 1. " PLLFBackDiv ,PLL feedback divider (M) setting"
|
|
textline " "
|
|
bitfld.long 0x0 0. " PLLLock ,PLL LOCK status" "Not locked,Locked"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "MS_CTRL,Memory Card Control Register"
|
|
bitfld.long 0x0 9. " PullUpEn ,Pull-ups to MSSDIO pins enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " MSSDIO2/3 ,MSSDIO2 and MSSDIO3 pad control" "Pull-up,No pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 7. " MSSDIO1 ,MSSDIO1 pad control" "Pull-up,No pull-up"
|
|
bitfld.long 0x0 6. " MSSDIO0/MSBS ,MSSDIO1/MSBS pad control" "Pull-up,No pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SDClkCtrl ,SD Card clock control" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--3. " DivRatio ,MSSDCLK equal ARM PLL output clock" "Stopped,Divided by 1,Divided by 2,Divided by 3,Divided by 4,Divided by 5,Divided by 6,Divided by 7,Divided by 8,Divided by 9,Divided by 10,Divided by 11,Divided by 12,Divided by 13,Divided by 14,Divided by 15"
|
|
group.long 0xAC++0x13
|
|
line.long 0x0 "I2CCLK_CTRL,I2C Clock Control Register"
|
|
bitfld.long 0x0 4. " USB_I2CDrvrStr ,Driver strength control for USB_I2C_SCL and USB_I2C_SDA" "Low drive,High drive"
|
|
bitfld.long 0x0 3. " I2C2DrvrStr ,I2C2_SCL and I2C2_SDA driver strength control" "Low drive,High drive"
|
|
textline " "
|
|
bitfld.long 0x0 2. " I2C1DrvrStr ,I2C1_SCL and I2C1_SDA driver strength control" "Low drive,High drive"
|
|
bitfld.long 0x0 1. " I2C2_HCLKEn ,I2C2 block enable" "Stopped,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 0. " I2C1_HCLKEn ,I2C1 block enable" "Stopped,Enable"
|
|
line.long 0x4 "KEYCLK_CTRL,Keyboard Scan Clock Control Register"
|
|
bitfld.long 0x4 0. " KeyClkCtrl ,Clock to keyboard block control" "Disabled,Enabled"
|
|
line.long 0x8 "ADCLK_CTRL,ADC Clock Control Register"
|
|
bitfld.long 0x8 0. " ADCClkCtrl ,32 kHz clock to ADC block control" "Disabled,Enabled"
|
|
line.long 0xC "PWMCLK_CTRL,PWM Clock Control Register"
|
|
bitfld.long 0xC 8.--11. " PWM2_FREQ ,Controls the clock divider for PWM2" "Off,CLKin,CLKin/2,CLKin/3,CLKin/4,CLKin/5,CLKin/6,CLKin/7,CLKin/8,CLKin/9,CLKin/10,CLKin/11,CLKin/12,CLKin/13,CLKin/14,CLKin/15"
|
|
bitfld.long 0xC 4.--7. " PWM1_FREQ ,Controls the clock divider for PWM1" "Off,CLKin,CLKin/2,CLKin/3,CLKin/4,CLKin/5,CLKin/6,CLKin/7,CLKin/8,CLKin/9,CLKin/10,CLKin/11,CLKin/12,CLKin/13,CLKin/14,CLKin/15"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PWM2Src ,PWM2 clock source selection" "32 kHz RTC_CLK,PERIPH_CLK"
|
|
bitfld.long 0xC 2. " PWM2ClkEn ,Clock to PWM2 block enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 1. " PWM1Src ,PWM1 clock source selection" "32 kHz RTC_CLK,PERIPH_CLK"
|
|
bitfld.long 0xC 0. " PWM1ClkEn ,Clock to PWM1 block enable" "Disabled,Enabled"
|
|
line.long 0x10 "TIMCLK_CTRL,Timer Clock Control Register"
|
|
bitfld.long 0x10 1. " HSTimerClkEn ,HSTimer clock enable control" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " WDGClkEn ,Watchdog clock enable control" "Disabled,Enabled"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "SPI_CTRL,SPI Block Control Register"
|
|
bitfld.long 0x0 7. " SPI2_DATIOLvl ,SPI2_DATIO output level" "Low,High"
|
|
bitfld.long 0x0 6. " SPI2_CLKLvl ,SPI2_CLK output level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " OutPin2Ctrl ,SPI2_DATIO and SPI2_CLK outputs control" "By bits [7:6],By SPI2"
|
|
bitfld.long 0x0 4. " SPI2ClkEn ,SPI2 clock enable control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " SPI1_DATIOLvl ,SPI1_DATIO output level" "Low,High"
|
|
bitfld.long 0x0 2. " SPI1_CLKLvl ,SPI1_CLK output level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " OutPin1Ctrl ,SPI1_DATIO and SPI1_CLK outputs control" "By bits [3:2],By SPI2"
|
|
bitfld.long 0x0 0. " SPI1ClkEn ,SPI1 clock enable control" "Disabled,Enabled"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "FLASHCLK_CTRL,NAND Flash Clock Control Register"
|
|
bitfld.long 0x0 5. " NANDFlshCI ,NAND Flash controller interrupt connected to the interrupt controller" "SLC,MLC"
|
|
bitfld.long 0x0 4. " DMA_REQ_RNb ,NAND_DMA_REQ on NAND_RnB enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " DMA_REQ_INT ,NAND_DMA_REQ on NAND_INT enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SLC/MLCSel ,SLC/MLC NAND Flash controller select" "MLC,SLC"
|
|
textline " "
|
|
bitfld.long 0x0 1. " MLC_NANDClkEn ,MLC NAND Flash clock enable control" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " SLC_NANDClkEn ,SLC NAND Flash clock enable control" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SDRAM Memory Controller"
|
|
base ad:0x40004000
|
|
width 23.
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "SDRAMCLK_CTRL,SDRAM Clock Control Register"
|
|
bitfld.long 0x0 22. " SDRAM_PIN_SPEED3 ,Slew rate of the pin SDRAM pin RAM_CLK" "Fast,Slower"
|
|
textline " "
|
|
bitfld.long 0x0 21. " SDRAM_PIN_SPEED2 ,Slew rate of the pin SDRAM pads RAM_A[14:0].RAM_CKE.RAM_CS_N.RAM_RAS_N.RAM_CAS_N.RAM_WR_N." "Fast,Slower"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SDRAM_PIN_SPEED1 ,Slew rate of the pin SDRAM pads RAM_D[31:0] and RAM_DQM[3:0]" "Fast,Slower"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SW_DDR_RESET ,SDRAM controller reset" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x0 14.--18. " HCLKDELAY_DELAY ,Delay of the HCLKDELAY input from the HCLK" "0 ns,0.25 ns,0.5 ns,0.75 ns,1 ns,1.25 ns,1.5 ns,1.75 ns,2 ns,2.25 ns,2.5 ns,2.75 ns,3 ns,3.25 ns,3.5 ns,3.75 ns,4 ns,4.25 ns,4.5 ns,4.75 ns,5 ns,5.25 ns,5.5 ns,5.75 ns,6 ns,6.25 ns,6.5 ns,6.75 ns,7 ns,7.25 ns,7.5 ns,7.75 ns"
|
|
textline " "
|
|
bitfld.long 0x0 13. " DCircStat ,Delay circuitry Adder status" "No under/over-flow,Under/over-flow"
|
|
textline " "
|
|
bitfld.long 0x0 10.--12. " SensFactor ,Sensitivity Factor for DDR SDRAM calibration" "No shift right,Shift right with 1,Shift right with 2,Shift right with 3,Shift right with 4,Shift right with 5,Shift right with 6,Shift right with 7"
|
|
textline " "
|
|
bitfld.long 0x0 9. " CAL_DELAY ,Calibrated delay settings for DDR SDRAM" "Un-calibrated,Calibrated"
|
|
textline " "
|
|
bitfld.long 0x0 8. " SW_DDR_CAL ,Manual DDR delay calibration" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x0 7. " RTC_TICK_EN ,Automatic DDR delay calibration enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2.--6. " DDR_DQSIN_DELAY ,Delay of the DQS input from the DDR SDRAM device" "No delay,0.25 ns,0.50 ns,0.75 ns,1 ns,1.25 ns,1.5 ns,1.75 ns,2 ns,2.25 ns,2.5 ns,2.75 ns,3 ns,3.25 ns,3.5 ns,3.75 ns,4 ns,4.25 ns,4.5 ns,4.75 ns,5 ns,5.25 ns,5.5 ns,5.75 ns,6 ns,6.25 ns,6.5 ns,6.75 ns,7 ns,7.25 ns,7.5 ns,7.75 ns"
|
|
textline " "
|
|
bitfld.long 0x0 1. " DDR_SEL ,SRD or DDR selection" "SDR,DDR"
|
|
textline " "
|
|
bitfld.long 0x0 0. " SDRAMClksEn ,Clocks to SDRAM" "Disabled,Enabled"
|
|
base ad:0x31080000
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "MPMCControl,SDRAM Controller Control Register"
|
|
bitfld.long 0x0 2. " L ,Low-power mode" "Normal,Low-power"
|
|
bitfld.long 0x0 0. " E ,SDRAM Controller Enable " "Disabled,Enabled"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "MPMCStatus,SDRAM Controller Status Register"
|
|
bitfld.long 0x0 2. " SA ,Self-refresh acknowledge" "Normal,Self-refresh"
|
|
bitfld.long 0x0 0. " B ,SDRAM Controller state" "Idle,Busy"
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "MPMCConfig,SDRAM Controller Configuration Register"
|
|
bitfld.long 0x0 0. " N ,Endian mode" "Little-endian,Big-endian"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "MPMCDynamicControl,Dynamic Memory Control Register"
|
|
bitfld.long 0x0 13. " DP ,Low-power SDRAM deep-sleep mode" "Normal,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x0 7.--8. " I ,SDRAM initialization" "NORMAL,MODE,PALL,NOP"
|
|
textline " "
|
|
bitfld.long 0x0 5. " MMC ,Memory clock control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " IMCC ,Memory clock control" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " SRMCC ,Self-Refresh Clock Control" "Running,Stopped"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SR ,Self-refresh request; MPMCSREFREQ" "Normal,Self-refresh"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CS ,Dynamic memory clock control" "Stopped,Running"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CE ,Dynamic memory clock enable" "Disabled,Enabled"
|
|
line.long 0x4 "MPMCDynamicRefresh,Dynamic Memory Refresh Timer Register"
|
|
hexmask.long.word 0x4 0.--10. 1. " REFRESH ,Refresh timer"
|
|
line.long 0x8 "MPMCDynamicReadConfig,Dynamic Memory Read Configuration Register"
|
|
bitfld.long 0x8 12. " DRP , DDR SDRAM read data capture polarity" "Negative,Positive"
|
|
bitfld.long 0x8 8.--9. " DRD ,DDR SDRAM read data strategy" "Clock out delayed,Command delayed,Command delayed+1Clk,Command delayed+2Clk"
|
|
textline " "
|
|
bitfld.long 0x8 4. " SRP ,SDR-SDRAM read data capture polarity" "Negative,Positive"
|
|
bitfld.long 0x8 0.--1. " SRD ,SDR SDRAM read data strategy" "Clock out delayed,Command delayed,Command delayed+1Clk,Command delayed+2Clk"
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "MPMCDynamictRP,Dynamic Memory Precharge Command Period Register"
|
|
bitfld.long 0x0 0.--3. " tRP ,Precharge command period" "1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycle,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles,16 clock cycles"
|
|
line.long 0x4 "MPMCDynamictRAS,Dynamic Memory Active to Precharge Command Period Register"
|
|
bitfld.long 0x4 0.--3. " tRAS ,Active to precharge command period" "1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycles,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles,16 clock cycles"
|
|
line.long 0x8 "MPMCDynamictSREX,Dynamic Memory Self-refresh Exit Time Register"
|
|
hexmask.long.byte 0x8 0.--6. 1. " tSREX ,Self-refresh exit time"
|
|
group.long 0x44++0x1B
|
|
line.long 0x0 "MPMCDynamictWR,Dynamic Memory Write Recovery Time Register"
|
|
bitfld.long 0x0 0.--3. " tWR ,Write recovery time" "1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycles,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles,16 clock cycles"
|
|
line.long 0x4 "MPMCDynamictRC,Dynamic Memory Active To Active Command Period Register"
|
|
bitfld.long 0x4 0.--4. " tRC ,Active to active command period" "1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycles,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles,16 clock cycles,16 clock cycles,17 clock cycles,18 clock cycles,19 clock cycles,20 clock cycles,21 clock cycles,22 clock cycles,23 clock cycles,24 clock cycles,25 clock cycles,26 clock cycles,27 clock cycles,28 clock cycles,29 clock cycles,31 clock cycles,32 clock cycles"
|
|
line.long 0x8 "MPMCDynamictRFC,Dynamic Memory Auto-refresh Period Register"
|
|
bitfld.long 0x8 0.--4. " tRFC ,Auto-refresh and Auto-refresh to active command period" "1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycles,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles,16 clock cycles,16 clock cycles,17 clock cycles,18 clock cycles,19 clock cycles,20 clock cycles,21 clock cycles,22 clock cycles,23 clock cycles,24 clock cycles,25 clock cycles,26 clock cycles,27 clock cycles,28 clock cycles,29 clock cycles,31 clock cycles,32 clock cycles"
|
|
line.long 0xC "MPMCDynamictXSR,Dynamic Memory Exit Self-refresh Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. " tXSR ,Exit self-refresh to active command time"
|
|
line.long 0x10 "MPMCDynamictRRD,Dynamic Memory Active Bank A to Active Bank B Time Register"
|
|
bitfld.long 0x10 0.--3. " tRRD ,Active bank A to active bank B latency" "1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycles,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles,16 clock cycles"
|
|
line.long 0x14 "MPMCDynamictMRD,Dynamic Memory Load Mode Register To Active Command Time"
|
|
bitfld.long 0x14 0.--3. " tMRD ,Load mode register to active command time" "1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycles,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles,16 clock cycles"
|
|
line.long 0x18 "MPMCDynamicCDLR,Dynamic Memory Last Data In to Read Command Time"
|
|
bitfld.long 0x18 0.--3. " tCDLR ,Last data in to read command time" "1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycles,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles,16 clock cycles"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "MPMCDynamicConfig0,Dynamic Memory Configuration Register"
|
|
bitfld.long 0x0 20. " P ,Write protect" "Not protected,Protected"
|
|
hexmask.long.byte 0x0 7.--14. 1. " AM ,Address mapping"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MD ,Memory device" "SDR SDRAM,Reserved,Low power SDR SDRAM,Reserved,DDR SDRAM,Reserved,Low power DDR SDRAM,?..."
|
|
line.long 0x4 "MPMCDynamicRasCas0,Dynamic Memory RAS and CAS Delay Register"
|
|
bitfld.long 0x4 7.--10. " CAS ,CAS latency" "Reserved,0.5 clock cycle,1 clock cycle,1.5 clock cycles,2 clock cycles,2.5 clock cycles,3 clock cycles,3.5 clock cycles,4 clock cycles,4.5 clock cycles,5 clock cycles,5.5 clock cycles,6 clock cycles,6.5 clock cycles,7 clock cycles,7.5 clock cycles"
|
|
bitfld.long 0x4 0.--3. " RAS ,RAS latency" "Reserved,1 clock cycle,2 clock cycles,3 clock cycles,4 clock cycles,5 clock cycles,6 clock cycles,7 clock cycles,8 clock cycles,9 clock cycles,10 clock cycles,11 clock cycles,12 clock cycles,13 clock cycles,14 clock cycles,15 clock cycles"
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "MPMCAHBControl0,SDRAM Controller 0 AHB Control Register"
|
|
bitfld.long 0x0 0. " E ,AHB Port Buffer Enable" "Disabled,Enabled"
|
|
rgroup.long (0x400+0x4)++0x3
|
|
line.long 0x0 "MPMCAHBStatus0,SDRAM Controller 0 AHB Status Register"
|
|
bitfld.long 0x0 1. " S ,AHB Port Buffer Status" "Empty,Not empty"
|
|
group.long (0x400+0x8)++0x3
|
|
line.long 0x0 "MPMCAHBTime0,SDRAM Controller 0 AHB Timeout Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " AHBTIMEOUT ,AHB Timeout"
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "MPMCAHBControl2,SDRAM Controller 2 AHB Control Register"
|
|
bitfld.long 0x0 0. " E ,AHB Port Buffer Enable" "Disabled,Enabled"
|
|
rgroup.long (0x440+0x4)++0x3
|
|
line.long 0x0 "MPMCAHBStatus2,SDRAM Controller 2 AHB Status Register"
|
|
bitfld.long 0x0 1. " S ,AHB Port Buffer Status" "Empty,Not empty"
|
|
group.long (0x440+0x8)++0x3
|
|
line.long 0x0 "MPMCAHBTime2,SDRAM Controller 2 AHB Timeout Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " AHBTIMEOUT ,AHB Timeout"
|
|
group.long 0x460++0x3
|
|
line.long 0x0 "MPMCAHBControl4,SDRAM Controller 4 AHB Control Register"
|
|
bitfld.long 0x0 0. " E ,AHB Port Buffer Enable" "Disabled,Enabled"
|
|
rgroup.long (0x460+0x4)++0x3
|
|
line.long 0x0 "MPMCAHBStatus4,SDRAM Controller 4 AHB Status Register"
|
|
bitfld.long 0x0 1. " S ,AHB Port Buffer Status" "Empty,Not empty"
|
|
group.long (0x460+0x8)++0x3
|
|
line.long 0x0 "MPMCAHBTime4,SDRAM Controller 4 AHB Timeout Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " AHBTIMEOUT ,AHB Timeout"
|
|
group.long 0x480++0x3
|
|
line.long 0x0 "MPMCAHBControl6,SDRAM Controller 6 AHB Control Register"
|
|
bitfld.long 0x0 0. " E ,AHB Port Buffer Enable" "Disabled,Enabled"
|
|
rgroup.long (0x480+0x4)++0x3
|
|
line.long 0x0 "MPMCAHBStatus6,SDRAM Controller 6 AHB Status Register"
|
|
bitfld.long 0x0 1. " S ,AHB Port Buffer Status" "Empty,Not empty"
|
|
group.long (0x480+0x8)++0x3
|
|
line.long 0x0 "MPMCAHBTime6,SDRAM Controller 6 AHB Timeout Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " AHBTIMEOUT ,AHB Timeout"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "DDR_LAP_NOM,DDR Calibration Nominal Value"
|
|
rgroup.long 0x70++0x7
|
|
line.long 0x0 "DDR_LAP_COUNT,DDR Calibration Measured Value"
|
|
line.long 0x4 "DDR_CAL_DELAY,DDR Calibration Delay Value"
|
|
hexmask.long.byte 0x4 0.--4. 1. " CurrentCalDel ,Current calibrated delay setting"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "RINGOSC_CTRL,Ring Oscillator Control Register"
|
|
bitfld.long 0x0 10. " RingOscMeas ,Ring oscillator start measure control" "Powered down,Capture sequence"
|
|
hexmask.long.word 0x0 0.--9. 1. " CounterVal ,Ring oscillator clock counter value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Interrupt Controllers"
|
|
base ad:0x40008000
|
|
width 10.
|
|
tree "Main Interrupt Controller"
|
|
group.long 0x00++0x7
|
|
line.long 0x0 "MIC_ER,Interrupt Enable Register for the Main Interrupt Controller"
|
|
bitfld.long 0x0 31. " Sub2FIQn ,High priority (FIQ) interrupts from SIC2" "Enabled,Disabled"
|
|
bitfld.long 0x0 30. " Sub1FIQn ,High priority (FIQ) interrupts from SIC1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DMAINT ,General Purpose DMA Controller interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " IIR1 ,UART1 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " IIR2 ,UART2 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " IIR7 ,UART7 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " IIR6 ,UART6 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " IIR5 ,UART5 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " IIR4 ,UART4 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " IIR3 ,UART3 interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " WATCH_INT ,Watchdog Timer interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " Sub2IRQn ,Low priority (FIQ) interrupts from SIC2" "Enabled,Disabled"
|
|
bitfld.long 0x0 0. " Sub1IRQn ,Low priority (FIQ) interrupts from SIC1" "Enabled,Disabled"
|
|
line.long 0x4 "MIC_RSR,Main Interrupt Controller Raw Status Register"
|
|
eventfld.long 0x4 31. " Sub2FIQn ,High priority (FIQ) interrupts from SIC2" "Not active,Active"
|
|
eventfld.long 0x4 30. " Sub1FIQn ,High priority (FIQ) interrupts from SIC1" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 28. " DMAINT ,General Purpose DMA Controller interrupt" "Not active,Active"
|
|
eventfld.long 0x4 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 26. " IIR1 ,UART1 interrupt" "Not active,Active"
|
|
eventfld.long 0x4 25. " IIR2 ,UART2 interrupt" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 24. " IIR7 ,UART7 interrupt" "Not active,Active"
|
|
eventfld.long 0x4 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "Not active,Active"
|
|
eventfld.long 0x4 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 10. " IIR6 ,UART6 interrupt" "Not active,Active"
|
|
eventfld.long 0x4 9. " IIR5 ,UART5 interrupt" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 8. " IIR4 ,UART4 interrupt" "Not active,Active"
|
|
eventfld.long 0x4 7. " IIR3 ,UART3 interrupt" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 6. " WATCH_INT ,Watchdog Timer interrupt" "Not active,Active"
|
|
eventfld.long 0x4 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 1. " Sub2IRQn ,Low priority (FIQ) interrupts from SIC2" "Not active,Active"
|
|
eventfld.long 0x4 0. " Sub1IRQn ,Low priority (FIQ) interrupts from SIC1" "Not active,Active"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x0 "MIC_SR,Main Interrupt Controller Status Register"
|
|
bitfld.long 0x0 31. " Sub2FIQn ,High priority (FIQ) interrupts from SIC2" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 30. " Sub1FIQn ,High priority (FIQ) interrupts from SIC1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DMAINT ,General Purpose DMA Controller interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 26. " IIR1 ,UART1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 25. " IIR2 ,UART2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 24. " IIR7 ,UART7 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 10. " IIR6 ,UART6 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 9. " IIR5 ,UART5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 8. " IIR4 ,UART4 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 7. " IIR3 ,UART3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 6. " WATCH_INT ,Watchdog Timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " Sub2IRQn ,Low priority (FIQ) interrupts from SIC2" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " Sub1IRQn ,Low priority (FIQ) interrupts from SIC1" "No interrupt,Interrupt"
|
|
group.long 0x0C++0xB
|
|
line.long 0x0 "MIC_APR,Main Interrupt Controller Activation Polarity Register"
|
|
bitfld.long 0x0 31. " Sub2FIQn ,High priority (FIQ) interrupts from SIC2" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 30. " Sub1FIQn ,High priority (FIQ) interrupts from SIC1" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DMAINT ,General Purpose DMA Controller interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 26. " IIR1 ,UART1 interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 25. " IIR2 ,UART2 interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 24. " IIR7 ,UART7 interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 10. " IIR6 ,UART6 interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 9. " IIR5 ,UART5 interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 8. " IIR4 ,UART4 interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IIR3 ,UART3 interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 6. " WATCH_INT ,Watchdog Timer interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 1. " Sub2IRQn ,Low priority (FIQ) interrupts from SIC2" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 0. " Sub1IRQn ,Low priority (FIQ) interrupts from SIC1" "Low level/falling edge,High level/rising edge"
|
|
line.long 0x4 "MIC_ATR,Main Interrupt Controller Activation Type Register"
|
|
bitfld.long 0x4 31. " Sub2FIQn ,High priority (FIQ) interrupts from SIC2" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 30. " Sub1FIQn ,High priority (FIQ) interrupts from SIC1" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 28. " DMAINT ,General Purpose DMA Controller interrupt" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 26. " IIR1 ,UART1 interrupt" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 25. " IIR2 ,UART2 interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 24. " IIR7 ,UART7 interrupt" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 10. " IIR6 ,UART6 interrupt" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 9. " IIR5 ,UART5 interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 8. " IIR4 ,UART4 interrupt" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 7. " IIR3 ,UART3 interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 6. " WATCH_INT ,Watchdog Timer interrupt" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 1. " Sub2IRQn ,Low priority (FIQ) interrupts from SIC2" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 0. " Sub1IRQn ,Low priority (FIQ) interrupts from SIC1" "Level sensitive,Edge sensitive"
|
|
line.long 0x8 "MIC_ITR,Main Interrupt Controller Interrupt Type Register"
|
|
bitfld.long 0x8 31. " Sub2FIQn ,High priority (FIQ) interrupts from SIC2" "IRQ,FIQ"
|
|
bitfld.long 0x8 30. " Sub1FIQn ,High priority (FIQ) interrupts from SIC1" "IRQ,FIQ"
|
|
bitfld.long 0x8 28. " DMAINT ,General Purpose DMA Controller interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 27. " MSTIMER_INT ,Match interrupt 0 or 1 from the Millisecond Timer" "IRQ,FIQ"
|
|
bitfld.long 0x8 26. " IIR1 ,UART1 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 25. " IIR2 ,UART2 interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 24. " IIR7 ,UART7 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 15. " SD0_INT ,Interrupt 0 from the SD Card interface" "IRQ,FIQ"
|
|
bitfld.long 0x8 13. " SD1_INT ,Interrupt 1 from the SD Card interface" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 11. " FLASH_INT ,Interrupt from the NAND Flash controller" "IRQ,FIQ"
|
|
bitfld.long 0x8 10. " IIR6 ,UART6 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 9. " IIR5 ,UART5 interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 8. " IIR4 ,UART4 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 7. " IIR3 ,UART3 interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 6. " WATCH_INT ,Watchdog Timer interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 5. " HSTIMER_INT ,Match interrupt from the High Speed Timer" "IRQ,FIQ"
|
|
bitfld.long 0x8 1. " Sub2IRQn ,Low priority (FIQ) interrupts from SIC2" "IRQ,FIQ"
|
|
bitfld.long 0x8 0. " Sub1IRQn ,Low priority (FIQ) interrupts from SIC1" "IRQ,FIQ"
|
|
tree.end
|
|
tree "Sub Interrupt Controller 1"
|
|
group.long 0x4000++0x7
|
|
line.long 0x0 "SIC1_ER,Interrupt Enable Register for Sub Interrupt Controller 1"
|
|
bitfld.long 0x0 31. " USB_i2c_int ,Interrupt from the USB I2C interface" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " USB_dev_hp_int ,USB high priority interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " USB_dev_lp_int ,USB low priority interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " USB_dev_dma_int ,USB DMA interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " USB_host_int ,USB host interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " USB_otg_atx_int_n ,External USB transceiver interrupt" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " USB_otg_timer_int ,USB timer interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " SW_INT ,Software interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 23. " SPI1_INT ,Interrupt from the SPI1 interface" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " KEY_IRQ ,Keyboard scanner interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "Disabled,Enabled"
|
|
bitfld.long 0x0 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "Disabled,Enabled"
|
|
bitfld.long 0x0 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " SPI2_INT ,Interrupt from the SPI2 interface" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " ADC_INT ,A/D Converter interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " GPI_11 ,Interrupt from the GPI_11 pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " JTAG_COMM_RX ,Receiver full interrupt from the JTAG" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " JTAG_COMM_TX ,Transmitter empty interrupt from the JTAG" "Disabled,Enabled"
|
|
line.long 0x4 "SIC1_RSR,Sub1 Raw Status Register"
|
|
eventfld.long 0x4 31. " USB_i2c_int ,Interrupt from the USB I2C interface" "Not active,Active"
|
|
eventfld.long 0x4 30. " USB_dev_hp_int ,USB high priority interrupt" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 29. " USB_dev_lp_int ,USB low priority interrupt" "Not active,Active"
|
|
eventfld.long 0x4 28. " USB_dev_dma_int ,USB DMA interrupt" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 27. " USB_host_int ,USB host interrupt" "Not active,Active"
|
|
eventfld.long 0x4 26. " USB_otg_atx_int_n ,External USB transceiver interrupt" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 25. " USB_otg_timer_int ,USB timer interrupt" "Not active,Active"
|
|
eventfld.long 0x4 24. " SW_INT ,Software interrupt" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 23. " SPI1_INT ,Interrupt from the SPI1 interface" "Not active,Active"
|
|
eventfld.long 0x4 22. " KEY_IRQ ,Keyboard scanner interrupt" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "Not active,Active"
|
|
eventfld.long 0x4 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "Not active,Active"
|
|
eventfld.long 0x4 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "Not active,Active"
|
|
eventfld.long 0x4 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 12. " SPI2_INT ,Interrupt from the SPI2 interface" "Not active,Active"
|
|
eventfld.long 0x4 7. " ADC_INT ,A/D Converter interrupt" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 4. " GPI_11 ,Interrupt from the GPI_11 pin" "Not active,Active"
|
|
eventfld.long 0x4 2. " JTAG_COMM_RX ,Receiver full interrupt from the JTAG" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 1. " JTAG_COMM_TX ,Transmitter empty interrupt from the JTAG" "Not active,Active"
|
|
rgroup.long 0x4008++0xB
|
|
line.long 0x0 "SIC1_SR,Sub1 Status Register"
|
|
bitfld.long 0x0 31. " USB_i2c_int ,Interrupt from the USB I2C interface" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 30. " USB_dev_hp_int ,USB high priority interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 29. " USB_dev_lp_int ,USB low priority interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 28. " USB_dev_dma_int ,USB DMA interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 27. " USB_host_int ,USB host interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 26. " USB_otg_atx_int_n ,External USB transceiver interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 25. " USB_otg_timer_int ,USB timer interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 24. " SW_INT ,Software interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 23. " SPI1_INT ,Interrupt from the SPI1 interface" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 22. " KEY_IRQ ,Keyboard scanner interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 12. " SPI2_INT ,Interrupt from the SPI2 interface" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 7. " ADC_INT ,A/D Converter interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 4. " GPI_11 ,Interrupt from the GPI_11 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " JTAG_COMM_RX ,Receiver full interrupt from the JTAG" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " JTAG_COMM_TX ,Transmitter empty interrupt from the JTAG" "No interrupt,Interrupt"
|
|
group.long 0x400C++0xB
|
|
line.long 0x0 "SIC1_APR,Sub1 Activation Polarity Register"
|
|
bitfld.long 0x0 31. " USB_i2c_int ,Interrupt from the USB I2C interface" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 30. " USB_dev_hp_int ,USB high priority interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 29. " USB_dev_lp_int ,USB low priority interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 28. " USB_dev_dma_int ,USB DMA interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 27. " USB_host_int ,USB host interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 26. " USB_otg_atx_int_n ,External USB transceiver interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 25. " USB_otg_timer_int ,USB timer interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 24. " SW_INT ,Software interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 23. " SPI1_INT ,Interrupt from the SPI1 interface" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 22. " KEY_IRQ ,Keyboard scanner interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 12. " SPI2_INT ,Interrupt from the SPI2 interface" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ADC_INT ,A/D Converter interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 4. " GPI_11 ,Interrupt from the GPI_11 pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 2. " JTAG_COMM_RX ,Receiver full interrupt from the JTAG" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 1. " JTAG_COMM_TX ,Transmitter empty interrupt from the JTAG" "Low level/falling edge,High level/rising edge"
|
|
line.long 0x4 "SIC1_ATR,Sub1 Activation Type Register"
|
|
bitfld.long 0x4 31. " USB_i2c_int ,Interrupt from the USB I2C interface" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 30. " USB_dev_hp_int ,USB high priority interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 29. " USB_dev_lp_int ,USB low priority interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 28. " USB_dev_dma_int ,USB DMA interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 27. " USB_host_int ,USB host interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 26. " USB_otg_atx_int_n ,External USB transceiver interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 25. " USB_otg_timer_int ,USB timer interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 24. " SW_INT ,Software interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 23. " SPI1_INT ,Interrupt from the SPI1 interface" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 22. " KEY_IRQ ,Keyboard scanner interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 12. " SPI2_INT ,Interrupt from the SPI2 interface" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 7. " ADC_INT ,A/D Converter interrupt" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 4. " GPI_11 ,Interrupt from the GPI_11 pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 2. " JTAG_COMM_RX ,Receiver full interrupt from the JTAG" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 1. " JTAG_COMM_TX ,Transmitter empty interrupt from the JTAG" "Level sensitive,Edge sensitive"
|
|
line.long 0x8 "SIC1_ITR,Sub1 Interrupt Type Register"
|
|
bitfld.long 0x8 31. " USB_i2c_int ,Interrupt from the USB I2C interface" "IRQ,FIQ"
|
|
bitfld.long 0x8 30. " USB_dev_hp_int ,USB high priority interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 29. " USB_dev_lp_int ,USB low priority interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 28. " USB_dev_dma_int ,USB DMA interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 27. " USB_host_int ,USB host interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 26. " USB_otg_atx_int_n ,External USB transceiver interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 25. " USB_otg_timer_int ,USB timer interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 24. " SW_INT ,Software interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 23. " SPI1_INT ,Interrupt from the SPI1 interface" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 22. " KEY_IRQ ,Keyboard scanner interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 20. " RTC_INT ,Match interrupt 0 or 1 from the RTC" "IRQ,FIQ"
|
|
bitfld.long 0x8 19. " I2C_1_INT ,Interrupt from the I2C1 interface" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 18. " I2C_2_INT ,Interrupt from the I2C2 interface" "IRQ,FIQ"
|
|
bitfld.long 0x8 17. " PLL397_INT ,Lock interrupt from the 397x PLL" "IRQ,FIQ"
|
|
bitfld.long 0x8 14. " PLLHCLK_INT ,Lock interrupt from the HCLK PLL" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 13. " PLLUSB_INT ,Lock interrupt from the USB PLL" "IRQ,FIQ"
|
|
bitfld.long 0x8 12. " SPI2_INT ,Interrupt from the SPI2 interface" "IRQ,FIQ"
|
|
bitfld.long 0x8 7. " ADC_INT ,A/D Converter interrupt" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 4. " GPI_11 ,Interrupt from the GPI_11 pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 2. " JTAG_COMM_RX ,Receiver full interrupt from the JTAG" "IRQ,FIQ"
|
|
bitfld.long 0x8 1. " JTAG_COMM_TX ,Transmitter empty interrupt from the JTAG" "IRQ,FIQ"
|
|
tree.end
|
|
tree "Sub Interrupt Controller 2"
|
|
group.long 0x8000++0x7
|
|
line.long 0x0 "SIC2_ER,Interrupt Enable Register for Sub Interrupt Controller 2"
|
|
bitfld.long 0x0 31. " SYSCLKmux ,SYSCLK Mux interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " GPI_05 ,Interrupt from the GPI_05 pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPI_03 ,Interrupt from the GPI_03 pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 24. " GPI_02 ,Interrupt from the GPI_02 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 22. " GPI_00 ,Interrupt from the GPI_00 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 19. " U5_RX ,Interrupt from the UART5 RX pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " GPI_07 ,Interrupt from the GPI_07 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " GPI_10 ,Interrupt from the GPI_10 (U4_RX) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "Disabled,Enabled"
|
|
line.long 0x4 "SIC2_RSR,Sub2 Raw Status Register"
|
|
eventfld.long 0x4 31. " SYSCLKmux ,SYSCLK Mux interrupt" "Not active,Active"
|
|
eventfld.long 0x4 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 27. " GPI_05 ,Interrupt from the GPI_05 pin" "Not active,Active"
|
|
eventfld.long 0x4 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 25. " GPI_03 ,Interrupt from the GPI_03 pin" "Not active,Active"
|
|
eventfld.long 0x4 24. " GPI_02 ,Interrupt from the GPI_02 pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "Not active,Active"
|
|
eventfld.long 0x4 22. " GPI_00 ,Interrupt from the GPI_00 pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "Not active,Active"
|
|
eventfld.long 0x4 19. " U5_RX ,Interrupt from the UART5 RX pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "Not active,Active"
|
|
eventfld.long 0x4 15. " GPI_07 ,Interrupt from the GPI_07 pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "Not active,Active"
|
|
eventfld.long 0x4 11. " GPI_10 ,Interrupt from the GPI_10 (U4_RX) pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "Not active,Active"
|
|
eventfld.long 0x4 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "Not active,Active"
|
|
eventfld.long 0x4 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "Not active,Active"
|
|
eventfld.long 0x4 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "Not active,Active"
|
|
eventfld.long 0x4 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "Not active,Active"
|
|
textline " "
|
|
eventfld.long 0x4 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "Not active,Active"
|
|
eventfld.long 0x4 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "Not active,Active"
|
|
rgroup.long 0x8008++0x3
|
|
line.long 0x0 "SIC2_SR,Sub2 Status Register"
|
|
bitfld.long 0x0 31. " SYSCLKmux ,SYSCLK Mux interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 27. " GPI_05 ,Interrupt from the GPI_05 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPI_03 ,Interrupt from the GPI_03 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 24. " GPI_02 ,Interrupt from the GPI_02 pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 22. " GPI_00 ,Interrupt from the GPI_00 pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 19. " U5_RX ,Interrupt from the UART5 RX pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 15. " GPI_07 ,Interrupt from the GPI_07 pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 11. " GPI_10 ,Interrupt from the GPI_10 (U4_RX) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "No interrupt,Interrupt"
|
|
group.long 0x800C++0xB
|
|
line.long 0x0 "SIC2_APR,Sub2 Activation Polarity Register"
|
|
bitfld.long 0x0 31. " SYSCLKmux ,SYSCLK Mux interrupt" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 27. " GPI_05 ,Interrupt from the GPI_05 pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 25. " GPI_03 ,Interrupt from the GPI_03 pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 24. " GPI_02 ,Interrupt from the GPI_02 pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 22. " GPI_00 ,Interrupt from the GPI_00 pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 19. " U5_RX ,Interrupt from the UART5 RX pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 15. " GPI_07 ,Interrupt from the GPI_07 pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 11. " GPI_10 ,Interrupt from the GPI_10 (U4_RX) pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "Low level/falling edge,High level/rising edge"
|
|
textline " "
|
|
bitfld.long 0x0 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "Low level/falling edge,High level/rising edge"
|
|
line.long 0x4 "SIC2_ATR,Sub2 Activation Type Register"
|
|
bitfld.long 0x4 31. " SYSCLKmux ,SYSCLK Mux interrupt" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 27. " GPI_05 ,Interrupt from the GPI_05 pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 25. " GPI_03 ,Interrupt from the GPI_03 pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 24. " GPI_02 ,Interrupt from the GPI_02 pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 22. " GPI_00 ,Interrupt from the GPI_00 pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 19. " U5_RX ,Interrupt from the UART5 RX pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 15. " GPI_07 ,Interrupt from the GPI_07 pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 11. " GPI_10 ,Interrupt from the GPI_10 (U4_RX) pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "Level sensitive,Edge sensitive"
|
|
textline " "
|
|
bitfld.long 0x4 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "Level sensitive,Edge sensitive"
|
|
bitfld.long 0x4 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "Level sensitive,Edge sensitive"
|
|
line.long 0x8 "SIC2_ITR,Sub2 Interrupt Type Register"
|
|
bitfld.long 0x8 31. " SYSCLKmux ,SYSCLK Mux interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x8 28. " GPI_06 ,Interrupt from the GPI_06 (HSTIM_CAP) pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 27. " GPI_05 ,Interrupt from the GPI_05 pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 26. " GPI_04 ,Interrupt from the GPI_04 (SPI1_BUSY) pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 25. " GPI_03 ,Interrupt from the GPI_03 pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 24. " GPI_02 ,Interrupt from the GPI_02 pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 23. " GPI_01 ,Interrupt from the GPI_01 (SERVICE_N) pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 22. " GPI_00 ,Interrupt from the GPI_00 pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 20. " SPI1_DATIN ,Interrupt from the SPI1_DATIN pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 19. " U5_RX ,Interrupt from the UART5 RX pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 18. " SDIO_INT_N ,Interrupt from the MS_DIO1 pin" "FIQ,IRQ"
|
|
bitfld.long 0x8 15. " GPI_07 ,Interrupt from the GPI_07 pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 12. " U7_HCTS ,Interrupt from the UART7 HCTS pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 11. " GPI_10 ,Interrupt from the GPI_10 (U4_RX) pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 10. " GPI_09 ,Interrupt from the GPI_09 (KEY_COL7) pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 9. " GPI_08 ,Interrupt from the GPI_08 (KEY_COL6, SPI2_BUSY) pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 7. " U2_HCTS ,Interrupt from the UART2 HCTS pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 6. " SPI2_DATIN ,Interrupt from the SPI1_DATIN) pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 5. " GPIO_05 ,Interrupt from the GPI_05 pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 4. " GPIO_04 ,Interrupt from the GPI_04 pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 3. " GPIO_03 ,Interrupt from the GPI_03 (KEY_ROW7) pin" "IRQ,FIQ"
|
|
textline " "
|
|
bitfld.long 0x8 2. " GPIO_02 ,Interrupt from the GPI_02 (KEY_ROW6) pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 1. " GPIO_01 ,Interrupt from the GPI_01 pin" "IRQ,FIQ"
|
|
bitfld.long 0x8 0. " GPIO_00 ,Interrupt from the GPI_00 pin" "IRQ,FIQ"
|
|
tree.end
|
|
base ad:0x400040A8
|
|
textline " "
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SW_INT,Software Interrupt Register"
|
|
hexmask.long.byte 0x0 1.--7. 1. " PassParam ,Parameter to the interrupt service routine"
|
|
bitfld.long 0x0 0. " SW_INT ,Software interrupt source" "Inactive,Active"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Multi-level NAND Flash Controller"
|
|
base ad:0x200B8000
|
|
width 22.
|
|
wgroup.long 0x00++0x3B
|
|
line.long 0x0 "MLC_CMD,MLC NAND flash Command register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CmdCode ,Command Code"
|
|
line.long 0x4 "MLC_ADDR,MLC NAND flash Address register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " Address ,Flash address"
|
|
line.long 0x8 "MLC_ECC_ENC_REG,MLC NAND ECC Encode Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " Start ,Write to start data encode cycle"
|
|
line.long 0xC "MLC_ECC_DEC_REG,MLC NAND ECC Decode Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. " Start ,Write to start data encode cycle"
|
|
line.long 0x10 "MLC_ECC_AUTO_ENC_REG,MLC NAND ECC Auto Encode Register"
|
|
bitfld.long 0x10 8. " APrCmdEn ,Auto-program command enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x10 0.--7. 1. " AProgCmd ,Auto-program command"
|
|
line.long 0x14 "MLC_ECC_AUTO_DEC_REG,MLC NAND ECC Auto Decode Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " Start ,Write to start automatic decode cycle"
|
|
line.long 0x18 "MLC_RPR,MLC NAND Read Parity Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " Force ,Write to force the controller to read 10 byte parity data"
|
|
line.long 0x1C "MLC_WPR,MLC NAND Write Parity Register"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " Force ,Write to force the controller to write 10 byte parity data"
|
|
line.long 0x20 "MLC_RUBP,MLC NAND Reset User Buffer Pointer Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " Force ,Write to force the serial Data Buffer pointer to the start of the user data region"
|
|
line.long 0x24 "MLC_ROBP,MLC NAND Reset Overhead Buffer Pointer Register"
|
|
bitfld.long 0x24 0. " Force ,Force the serial Data Buffer pointer to start of the overhead data region" "Not forced,Forced"
|
|
line.long 0x28 "MLC_SW_WP_ADD_LOW,MLC NAND Software Write Protection Address Low Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " LoBound ,The lower bound for the write protected area"
|
|
line.long 0x2C "MLC_SW_WP_ADD_HIG,MLC NAND Software Write Protection Address High Register"
|
|
hexmask.long.tbyte 0x2C 0.--23. 1. " HiBound ,The upper bound for the write protected area"
|
|
line.long 0x30 "MLC_ICR,MLC NAND Controller Configuration Register"
|
|
bitfld.long 0x30 3. " SWWrProt ,Software Write protection enable" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " BlockSiz ,Size of block flash device" "Small,Large"
|
|
textline " "
|
|
bitfld.long 0x30 1. " AddrCnt ,NAND flash address word count" "3,4"
|
|
bitfld.long 0x30 0. " BusWidth ,NAND flash I/O bus with" "8-bit,16-bit"
|
|
line.long 0x34 "MLC_TIME_REG,MLC NAND Timing Register"
|
|
bitfld.long 0x34 24.--25. " TCEA_DELAY ,nCE low to dout valid (tCEA)" "0,1,2,3"
|
|
bitfld.long 0x34 19.--23. " BUSY_DELA ,Read/Write high to busy (tWB/tRB)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x34 16.--18. " NAND_TA ,Read high to high impedance (tRHZ)" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x34 12.--15. " RD_HIGH ,Read high hold time (tREH)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 8.--11. " RD_LOW ,Read pulse width (tRP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x34 4.--7. " WR_HIGH ,Write high hold time (tWH)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x34 0.--3. " WR_LOW ,Write pulse width (tWP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x38 "MLC_IRQ_MR,MLC NAND Interrupt Mask Register"
|
|
bitfld.long 0x38 5. " NANDRdy ,NAND Ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x38 4. " ContRdy ,Controller Ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x38 3. " DecFail ,Decode failure interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 2. " DecErDet ,Decode error detected interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x38 1. " ECCRdy ,ECC Encode/Decode ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x38 0. " WProtFau ,Software write protection fault interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x0 "MLC_IRQ_SR,MLC NAND Interrupt Status Register"
|
|
bitfld.long 0x0 5. " NANDRdy ,NAND Ready interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 4. " ContRdy ,Controller Ready interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 3. " DecFail ,Decode failureinterrupt" "Inactive,Active"
|
|
bitfld.long 0x0 2. " DecErDet ,Decode error detected interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " ECCRdy ,ECC Encode/Decode ready interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 0. " WProtFau ,Software write protection fault interrupt" "Inactive,Active"
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x0 "MLC_LOCK_PR,MLC NAND Lock Protection Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " Unlock ,Write a value of 0xA25E to this register unlock the access"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "MLC_ISR,MLC NAND Status Register"
|
|
bitfld.long 0x0 6. " DecFail ,Decoder Failure" "Not failed,Failed"
|
|
bitfld.long 0x0 4.--5. " R/SSymEr ,Number of R/S symbols errors" "One symbol,Two symbol,Three symbol,Four symbol"
|
|
textline " "
|
|
bitfld.long 0x0 3. " ErDetect ,Errors detected" "Not detected,Detected"
|
|
bitfld.long 0x0 2. " ECCRdy ,ECC ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x0 1. " ContrRdy ,Controller ready" "Not ready,Ready"
|
|
bitfld.long 0x0 0. " NANDRdy ,NAND ready" "Not ready,Ready"
|
|
wgroup.long 0x4C++0x3
|
|
line.long 0x0 "MLC_CEH,MLC NAND Chip-Enable Host Control Register"
|
|
bitfld.long 0x0 0. " nCEassert ,Force nCE assert" "Forced,Normal"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Single-level NAND Flash Controller"
|
|
base ad:0x20020000
|
|
width 14.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "SLC_DATA,SLC NAND flash Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " Data ,NAND flash read or write data"
|
|
wgroup.long 0x04++0xB
|
|
line.long 0x0 "SLC_ADDR,SLC NAND flash Address Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " Address ,NAND flash read or write address"
|
|
line.long 0x4 "SLC_CMD,SLC NAND flash Command Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " Command ,NAND flash command"
|
|
line.long 0x8 "SLC_STOP,SLC NAND flash STOP Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " Stop ,Write to stop all command/address sequences"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "SLC_CTRL,SLC NAND flash Control Register"
|
|
bitfld.long 0x0 2. " SW_RESET ,Reset of the SLC NAND flash controller" "No reset,Reset"
|
|
bitfld.long 0x0 1. " ECC_CLEAR ,Clear of ECC parity bits and counter reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 0. " DMA_START ,DMA data channel start" "Not started,Started"
|
|
line.long 0x4 "SLC_CFG,SLC NAND flash Configuration Register"
|
|
bitfld.long 0x4 5. " CE_LOW ,CEn always low" "Not always,Always"
|
|
bitfld.long 0x4 4. " DMA_ECC ,DMA ECC channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " ECC_EN ,ECC enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " DMA_BURST ,Burst enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " DMA_DIR ,DMA read from or write to SLC" "Write,Read"
|
|
bitfld.long 0x4 0. " WIDTH ,External device width select" "8-bit,Not used"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SLC_STAT,SLC NAND flash Status Register"
|
|
bitfld.long 0x0 2. " DMA_ACTIVE ,DMA_FIFO status" "No data,Contain data"
|
|
bitfld.long 0x0 1. " SLC_ACTIVE ,SLC_FIFO status" "No data,Contain data"
|
|
bitfld.long 0x0 0. " READY ,NAND flash device ready signal" "Busy,Ready"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "SLC_INT_STAT,SLC NAND flash Interrupt Status Register"
|
|
setclrfld.long 0x0 1. 0x8 1. 0xC 1. " INT_TC_set/clr ,Terminal Count interrupt status" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0x8 0. 0xC 0. " INT_RDY_set/clr ,Device ready interrupt status" "No interrupt,Interrupt"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SLC_IEN,SLC NAND flash Interrupt Enable Register"
|
|
bitfld.long 0x0 1. " INT_TC_EN ,Enable interrupt when TC has reached 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " INT_RDY_EN ,enable interrupt when RDY asserted" "Disabled,Enabled"
|
|
group.long 0x2C++0x7
|
|
line.long 0x0 "SLC_TAC,SLC NAND flash Timing Arcs configuration Register"
|
|
bitfld.long 0x0 28.--31. " W_RDY ,The time before the signal RDY is tested in clock cycles" "0 clock,2 clocks,4 clocks,6 clocks,8 clocks,10 clocks,12 clocks,14 clocks,16 clocks,18 clocks,20 clocks,22 clocks,24 clocks,26 clocks,28 clocks,30 clocks"
|
|
bitfld.long 0x0 24.--27. " W_WIDTH ,Write pulse width in clock cycles" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
bitfld.long 0x0 20.--23. " W_HOLD ,Write hold time of ALE, CLE, CEn, and Data in clock cycles" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " W_SETUP ,Write setup time of ALE, CLE, CEn, and Data in clock cycles" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
bitfld.long 0x0 12.--15. " R_RDY ,Time before the signal RDY is tested in clock cycles" "0 clock,2 clocks,4 clocks,6 clocks,8 clocks,10 clocks,12 clocks,14 clocks,?..."
|
|
bitfld.long 0x0 8.--11. " R_WIDTH ,Read pulse in clock cycles" "0 clock,2 clocks,4 clocks,6 clocks,8 clocks,10 clocks,12 clocks,14 clocks,16 clocks,18 clocks,20 clocks,22 clocks,24 clocks,26 clocks,28 clocks,30 clocks"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " R_HOLD ,Read hold time of ALE, CLE, and CEn in clock cycles" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
bitfld.long 0x0 0.--3. " R_SETUP ,Read setup time of ALE, CLE, and CEn in clock cycles" "1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks"
|
|
line.long 0x4 "SLC_TC,SLC NAND flash Transfer Count Register"
|
|
hexmask.long 0x4 0.--15. 1. " T_C ,Number of remaining bytes to be transferred to or from NAND flash memory"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "SLC_ECC,SLC NAND flash Error Correction Code Register"
|
|
hexmask.long.word 0x0 6.--21. 1. " LP[15:0] ,Line parity"
|
|
hexmask.long.byte 0x0 0.--5. 1. " CP[5:0] ,Column parity"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "SLC_DMA_DATA,SLC NAND flash DMA Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " 1DBT ,First data byte transferred"
|
|
hexmask.long.byte 0x0 16.--23. 1. " 2DBT ,Second data byte transferred"
|
|
hexmask.long.byte 0x0 8.--15. 1. " 3DBT ,Third data byte transferred"
|
|
hexmask.long.byte 0x0 0.--7. 1. " 4DBT ,Fourth data byte transferred"
|
|
width 0x0B
|
|
tree.end
|
|
tree "General Purpose Input/Output"
|
|
base ad:0x40028000
|
|
width 17.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x0 "PIO_INP_STATE,Input Pin State Register"
|
|
bitfld.long 0x0 28. " GPI_11 ,General purpose input pin GPI_11" "Low,High"
|
|
bitfld.long 0x0 27. " SPI2_DATIN ,State of the input pin SPI2_DATIN" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPI1_DATIN ,State of the input pin SPI1_DATIN." "Low,High"
|
|
bitfld.long 0x0 24. " GPIO_05 ,General purpose I/O pin GPIO_05" "Low,High"
|
|
bitfld.long 0x0 23. " U7_RX ,State of the input pin U7_RX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " U7_HCTS ,state of the input pin U7_HCTS" "Low,High"
|
|
bitfld.long 0x0 21. " U6_IRRX ,State of the input pin U6_IRRX" "Low,High"
|
|
bitfld.long 0x0 20. " U5_RX ,State of the input pin U5_RX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " GPI_10 ,General purpose input pin GPI_10 / U4_RX" "Low,High"
|
|
bitfld.long 0x0 18. " U3_RX ,State of the input pin U3_RX" "Low,High"
|
|
bitfld.long 0x0 17. " U2_RX ,State of the input pin U2_RX" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " U2_HCTS ,State of the input pin U2_HCTS" "Low,High"
|
|
bitfld.long 0x0 15. " U1_RX ,State of the input pin U1_RX" "Low,High"
|
|
bitfld.long 0x0 14. " GPIO_04 ,General purpose I/O pin GPIO_04" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " GPIO_03 ,General purpose I/O pin GPIO_03 / KEY_ROW7" "Low,High"
|
|
bitfld.long 0x0 12. " GPIO_02 ,General purpose I/O pin GPIO_02 / KEY_ROW6" "Low,High"
|
|
bitfld.long 0x0 11. " GPIO_01 ,General purpose I/O pin " "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " GPIO_00 ,General purpose I/O pin GPIO_00" "Low,High"
|
|
bitfld.long 0x0 9. " GPI_09 ,General purpose I/O pin GPI_09 / KEY_COL7" "Low,High"
|
|
bitfld.long 0x0 8. " GPI_08 ,General purpose I/O pin GPI_08 / KEY_COL6 / SPI2_BUSY" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " GPI_07 ,General purpose I/O pin GPI_07" "Low,High"
|
|
bitfld.long 0x0 6. " GPI_06 ,General purpose I/O pin GPI_06 / HSTIM_CAP" "Low,High"
|
|
bitfld.long 0x0 5. " GPI_05 ,General purpose I/O pin GPI_05" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " GPI_04 ,General purpose I/O pin GPI_04 / SPI1_BUSY" "Low,High"
|
|
bitfld.long 0x0 3. " GPI_03 ,General purpose I/O pin GPI_03" "Low,High"
|
|
bitfld.long 0x0 2. " GPI_02 ,General purpose I/O pin GPI_02" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPI_01 ,General purpose I/O pin GPI_01 / SERVICE_N" "Low,High"
|
|
bitfld.long 0x0 0. " GPI_00 ,General purpose I/O pin GPI_00" "Low,High"
|
|
group.long 0x0C++0x3
|
|
line.long 0x0 "PIO_OUTP_STATE,Output Pin State Register"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " GPIO_05_set/clr ,General purpose I/O pin GPIO_05" "Low,High"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " GPIO_04_set/clr ,General purpose I/O pin GPIO_04" "Low,High"
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " GPIO_03_set/clr ,General purpose I/O pin GPIO_03" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " GPIO_02_set/clr ,General purpose I/O pin GPIO_02" "Low,High"
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " GPIO_01_set/clr ,General purpose I/O pin GPIO_01" "Low,High"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " GPIO_00_set/clr ,General purpose I/O pin GPIO_00" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 23. -0x8 23. -0x4 23. " GPO_23_set/clr ,General purpose output pin GPO_23/U2_HRTS" "Low,High"
|
|
setclrfld.long 0x0 22. -0x8 22. -0x4 22. " GPO_22_set/clr ,General purpose output pin GPO_22/U7_HRTS" "Low,High"
|
|
setclrfld.long 0x0 21. -0x8 21. -0x4 21. " GPO_21_set/clr ,General purpose output pin GPO_21/U4_TX" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 20. -0x8 20. -0x4 20. " GPO_20_set/clr ,General purpose output pin GPO_20" "Low,High"
|
|
setclrfld.long 0x0 19. -0x8 19. -0x4 19. " GPO_19_set/clr ,General purpose output pin GPO_19" "Low,High"
|
|
setclrfld.long 0x0 18. -0x8 18. -0x4 18. " GPO_18_set/clr ,General purpose output pin GPO_18" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 17. -0x8 17. -0x4 17. " GPO_17_set/clr ,General purpose output pin GPO_17" "Low,High"
|
|
setclrfld.long 0x0 16. -0x8 16. -0x4 16. " GPO_16_set/clr ,General purpose output pin GPO_16" "Low,High"
|
|
setclrfld.long 0x0 15. -0x8 15. -0x4 15. " GPO_15_set/clr ,General purpose output pin GPO_15" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 14. -0x8 14. -0x4 14. " GPO_14_set/clr ,General purpose output pin GPO_14" "Low,High"
|
|
setclrfld.long 0x0 13. -0x8 13. -0x4 13. " GPO_13_set/clr ,General purpose output pin GPO_13" "Low,High"
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " GPO_12_set/clr ,General purpose output pin GPO_12" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " GPO_11_set/clr ,General purpose output pin GPO_11" "Low,High"
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " GPO_10_set/clr ,General purpose output pin GPO_10" "Low,High"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " GPO_09_set/clr ,General purpose output pin GPO_09" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " GPO_08_set/clr ,General purpose output pin GPO_08" "Low,High"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " GPO_07_set/clr ,General purpose output pin GPO_07" "Low,High"
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " GPO_06_set/clr ,General purpose output pin GPO_06" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " GPO_05_set/clr ,General purpose output pin GPO_05" "Low,High"
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " GPO_04_set/clr ,General purpose output pin GPO_04" "Low,High"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " GPO_03_set/clr ,General purpose output pin GPO_03" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " GPO_02_set/clr ,General purpose output pin GPO_02" "Low,High"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " GPO_01_set/clr ,General purpose output pin GPO_01" "Low,High"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " GPO_00_set/clr ,General purpose output pin GPO_00/TST_CLK1" "Low,High"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PIO_DIR_STATE,GPIO Direction State Register"
|
|
setclrfld.long 0x0 30. -0x8 30. -0x4 30. " GPIO_05_set/clr ,General purpose I/O pin GPIO_05" "Input,Output"
|
|
setclrfld.long 0x0 29. -0x8 29. -0x4 29. " GPIO_04_set/clr ,General purpose I/O pin GPIO_04" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 28. -0x8 28. -0x4 28. " GPIO_03_set/clr ,General purpose I/O pin GPIO_03" "Input,Output"
|
|
setclrfld.long 0x0 27. -0x8 27. -0x4 27. " GPIO_02_set/clr ,General purpose I/O pin GPIO_02" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 26. -0x8 26. -0x4 26. " GPIO_01_set/clr ,General purpose I/O pin GPIO_01" "Input,Output"
|
|
setclrfld.long 0x0 25. -0x8 25. -0x4 25. " GPIO_00_set/clr ,General purpose I/O pin GPIO_00" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 12. -0x8 12. -0x4 12. " RAM_D[31]_set/clr ,RAM_D[31] pin" "Input,Output"
|
|
setclrfld.long 0x0 11. -0x8 11. -0x4 11. " RAM_D[30]_set/clr ,RAM_D[30] pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 10. -0x8 10. -0x4 10. " RAM_D[29]_set/clr ,RAM_D[29] pin" "Input,Output"
|
|
setclrfld.long 0x0 9. -0x8 9. -0x4 9. " RAM_D[28]_set/clr ,RAM_D[28] pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 8. -0x8 8. -0x4 8. " RAM_D[27]_set/clr ,RAM_D[27] pin" "Input,Output"
|
|
setclrfld.long 0x0 7. -0x8 7. -0x4 7. " RAM_D[26]_set/clr ,RAM_D[26] pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 6. -0x8 6. -0x4 6. " RAM_D[25]_set/clr ,RAM_D[25] pin" "Input,Output"
|
|
setclrfld.long 0x0 5. -0x8 5. -0x4 5. " RAM_D[24]_set/clr ,RAM_D[24] pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 4. -0x8 4. -0x4 4. " RAM_D[23]_set/clr ,RAM_D[23] pin" "Input,Output"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " RAM_D[22]_set/clr ,RAM_D[22] pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " RAM_D[21]_set/clr ,RAM_D[21] pin" "Input,Output"
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " RAM_D[20]_set/clr ,RAM_D[20] pin" "Input,Output"
|
|
textline " "
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " RAM_D[19]_set/clr ,RAM_D[19] pin" "Input,Output"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PIO_SDINP_STATE,Input Pin State Register For SDRAM Pins"
|
|
bitfld.long 0x0 12. " RAM_D[31] ,RAM_D[31] pin" "Low,High"
|
|
bitfld.long 0x0 11. " RAM_D[30] ,RAM_D[30] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " RAM_D[29] ,RAM_D[29] pin" "Low,High"
|
|
bitfld.long 0x0 9. " RAM_D[28] ,RAM_D[28] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 8. " RAM_D[27] ,RAM_D[27] pin" "Low,High"
|
|
bitfld.long 0x0 7. " RAM_D[26] ,RAM_D[26] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RAM_D[25] ,RAM_D[25] pin" "Low,High"
|
|
bitfld.long 0x0 5. " RAM_D[24] ,RAM_D[24] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " RAM_D[23] ,RAM_D[23] pin" "Low,High"
|
|
bitfld.long 0x0 3. " RAM_D[22] ,RAM_D[22] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RAM_D[21] ,RAM_D[21] pin" "Low,High"
|
|
bitfld.long 0x0 1. " RAM_D[20] ,RAM_D[20] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RAM_D[19] ,RAM_D[19] pin" "Low,High"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "PIO_SDOUTP_SET,Output Pin Set Register For SDRAM Pins"
|
|
bitfld.long 0x0 12. " RAM_D[31] ,RAM_D[31] pin" "Low,High"
|
|
bitfld.long 0x0 11. " RAM_D[30] ,RAM_D[30] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " RAM_D[29] ,RAM_D[29] pin" "Low,High"
|
|
bitfld.long 0x0 9. " RAM_D[28] ,RAM_D[28] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 8. " RAM_D[27] ,RAM_D[27] pin" "Low,High"
|
|
bitfld.long 0x0 7. " RAM_D[26] ,RAM_D[26] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 6. " RAM_D[25] ,RAM_D[25] pin" "Low,High"
|
|
bitfld.long 0x0 5. " RAM_D[24] ,RAM_D[24] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " RAM_D[23] ,RAM_D[23] pin" "Low,High"
|
|
bitfld.long 0x0 3. " RAM_D[22] ,RAM_D[22] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 2. " RAM_D[21] ,RAM_D[21] pin" "Low,High"
|
|
bitfld.long 0x0 1. " RAM_D[20] ,RAM_D[20] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RAM_D[19] ,RAM_D[19] pin" "Low,High"
|
|
line.long 0x4 "PIO_SDOUTP_CLR,Output Pin Clear Register For SDRAM Pins"
|
|
bitfld.long 0x4 12. " RAM_D[31] ,RAM_D[31] pin" "Low,High"
|
|
bitfld.long 0x4 11. " RAM_D[30] ,RAM_D[30] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " RAM_D[29] ,RAM_D[29] pin" "Low,High"
|
|
bitfld.long 0x4 9. " RAM_D[28] ,RAM_D[28] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 8. " RAM_D[27] ,RAM_D[27] pin" "Low,High"
|
|
bitfld.long 0x4 7. " RAM_D[26] ,RAM_D[26] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 6. " RAM_D[25] ,RAM_D[25] pin" "Low,High"
|
|
bitfld.long 0x4 5. " RAM_D[24] ,RAM_D[24] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 4. " RAM_D[23] ,RAM_D[23] pin" "Low,High"
|
|
bitfld.long 0x4 3. " RAM_D[22] ,RAM_D[22] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 2. " RAM_D[21] ,RAM_D[21] pin" "Low,High"
|
|
bitfld.long 0x4 1. " RAM_D[20] ,RAM_D[20] pin" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 0. " RAM_D[19] ,RAM_D[19] pin" "Low,High"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PIO_MUX_STATE,PIO Multiplexer State Register"
|
|
setclrfld.long 0x0 3. -0x8 3. -0x4 3. " GPIO_SDRAM_SEL_set/clr ,SDRAM_D[31:19] connection" "SDRAM controller,GPIO block"
|
|
setclrfld.long 0x0 2. -0x8 2. -0x4 2. " GPIO_21MuxCtrl_set/clr ,GPO_21 mux control" "GPO_21,U4_TX"
|
|
textline " "
|
|
setclrfld.long 0x0 1. -0x8 1. -0x4 1. " GPIO_03MuxCtrl_set/clr ,GPO_03 mux control" "GPO_03,KeyScan Row[7]"
|
|
setclrfld.long 0x0 0. -0x8 0. -0x4 0. " GPIO_02MuxCtrl_set/clr ,GPO_02 mux control" "GPO_02,KeyScan Row[6]"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "USB Device Controller"
|
|
base ad:0x31020200
|
|
width 16.
|
|
tree "Interrupt Registers"
|
|
group.long 0x00++0x7
|
|
line.long 0x0 "USBDevIntSt,USB Device Interrupt Status Register"
|
|
setclrfld.long 0x0 9. 0xC 9. 0x8 9. " ERR_INT_set/clr ,Error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 8. 0xC 8. 0x8 8. " EP_RLZED_set/clr ,Endpoints realized interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0xC 7. 0x8 7. " TxENDPKT_set/clr ,TxPacket length interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 6. 0xC 6. 0x8 6. " RxENDPKT_set/clr ,RxPacket length interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0xC 5. 0x8 5. " CDFULL_set/clr ,Command data register is full interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 4. 0xC 4. 0x8 4. " CCEMPTY_set/clr ,The command code register is empty interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0xC 3. 0x8 3. " DEV_STAT_set/clr ,Device state interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 2. 0xC 2. 0x8 2. " EP_SLOW_set/clr ,Slow interrupt transfer for the endpoint" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0xC 1. 0x8 1. " EP_FAST_set/clr ,Fast interrupt transfer for the endpoint" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0xC 0. 0x8 0. " FRAME_set/clr ,Frame interrupt" "No interrupt,Interrupt"
|
|
line.long 0x4 "USBDevIntEn,USB Device Interrupt Enable Register"
|
|
bitfld.long 0x4 9. " ERR_INT ,Error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 8. " EP_RLZED ,Endpoints realized interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 7. " TxENDPKT ,TxPacket length interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 6. " RxENDPKT ,RxPacket length interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " CDFULL ,Command data register is full interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 4. " CCEMPTY ,The command code register is empty interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " DEV_STAT ,Device state interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " EP_SLOW ,Slow interrupt transfer for the endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " EP_FAST ,Fast interrupt transfer for the endpoint" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0. " FRAME ,Frame interrupt" "Disabled,Enabled"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "USBDevIntPri,USB Device Interrupt Priority Register"
|
|
bitfld.long 0x0 1. " EP_FAST ,Endpoint fast interrupt transfer priority" "Low,High"
|
|
bitfld.long 0x0 0. " FRAME ,Frame interruptpriority" "Low,High"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "USBEpIntSt,USB Endpoint Interrupt Status Register"
|
|
setclrfld.long 0x0 31. 0xC 31. 0x8 31. " EP15TX_set/clr ,Endpoint 15. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 30. 0xC 30. 0x8 30. " EP15RX_set/clr ,Endpoint 15. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0xC 29. 0x8 29. " EP14TX_set/clr ,Endpoint 14. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 28. 0xC 28. 0x8 28. " EP14RX_set/clr ,Endpoint 14. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0xC 27. 0x8 27. " EP13TX_set/clr ,Endpoint 13. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 26. 0xC 26. 0x8 26. " EP13RX_set/clr ,Endpoint 13. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0xC 25. 0x8 25. " EP12TX_set/clr ,Endpoint 12. Isochronous endpoint" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 24. 0xC 24. 0x8 24. " EP12RX_set/clr ,Endpoint 12. Isochronous endpoint" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0xC 23. 0x8 23. " EP11TX_set/clr ,Endpoint 11. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 22. 0xC 22. 0x8 22. " EP11RX_set/clr ,Endpoint 11, Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0xC 21. 0x8 21. " EP10TX_set/clr ,Endpoint 10. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 20. 0xC 20. 0x8 20. " EP10RX_set/clr ,Endpoint 10. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0xC 19. 0x8 19. " EP9TX_set/clr ,Endpoint 9. Isochronous endpoint" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 18. 0xC 18. 0x8 18. " EP9RX_set/clr ,Endpoint 9. Isochronous endpoint" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0xC 17. 0x8 17. " EP8TX_set/clr ,Endpoint 8. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 16. 0xC 16. 0x8 16. " EP8RX_set/clr ,Endpoint 8. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0xC 15. 0x8 15. " EP7TX_set/clr ,Endpoint 7. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 14. 0xC 14. 0x8 14. " EP7RX_set/clr ,Endpoint 7. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0xC 13. 0x8 13. " EP6TX_set/clr ,Endpoint 6. Isochronous endpoint" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 12. 0xC 12. 0x8 12. " EP6RX_set/clr ,Endpoint 6. Isochronous endpoint" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0xC 11. 0x8 11. " EP5TX_set/clr ,Endpoint 5. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 10. 0xC 10. 0x8 10. " EP5RX_set/clr ,Endpoint 5. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0xC 9. 0x8 9. " EP4TX_set/clr ,Endpoint 4. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 8. 0xC 8. 0x8 8. " EP4RX_set/clr ,Endpoint 4. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0xC 7. 0x8 7. " EP3TX_set/clr ,Endpoint 3. Isochronous endpoint" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 6. 0xC 6. 0x8 6. " EP3RX_set/clr ,Endpoint 3. Isochronous endpoint" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0xC 5. 0x8 5. " EP2TX_set/clr ,Endpoint 2. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 4. 0xC 4. 0x8 4. " EP2RX_set/clr ,Endpoint 2. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0xC 3. 0x8 3. " EP1TX_set/clr ,Endpoint 1. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 2. 0xC 2. 0x8 2. " EP1RX_set/clr ,Endpoint 1. Data Received Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0xC 1. 0x8 1. " EP0TX_set/clr ,Endpoint 0. Data Transmitted Interrupt or sent a NAK" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0xC 0. 0x8 0. " EP0RX_set/clr ,Endpoint 0. Data Received Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x4 "USBEpIntEn,USB Endpoint Interrupt Enable Register"
|
|
bitfld.long 0x4 31. " EP15TX ,Endpoint 15. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 30. " EP15RX ,Endpoint 15. Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 29. " EP14TX ,Endpoint 14. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 28. " EP14RX ,Endpoint 14. Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 27. " EP13TX ,Endpoint 13. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 26. " EP13RX ,Endpoint 13. Data Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " EP12TX ,Endpoint 12. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 24. " EP12RX ,Endpoint 12. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 23. " EP11TX ,Endpoint 11. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 22. " EP11RX ,Endpoint 11, Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " EP10TX ,Endpoint 10. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " EP10RX ,Endpoint 10. Data Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 19. " EP9TX ,Endpoint 9. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 18. " EP9RX ,Endpoint 9. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 17. " EP8TX ,Endpoint 8. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16. " EP8RX ,Endpoint 8. Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 15. " EP7TX ,Endpoint 7. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " EP7RX ,Endpoint 7. Data Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " EP6TX ,Endpoint 6. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 12. " EP6RX ,Endpoint 6. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 11. " EP5TX ,Endpoint 5. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 10. " EP5RX ,Endpoint 5. Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 9. " EP4TX ,Endpoint 4. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 8. " EP4RX ,Endpoint 4. Data Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " EP3TX ,Endpoint 3. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " EP3RX ,Endpoint 3. Isochronous endpoint" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " EP2TX ,Endpoint 2. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " EP2RX ,Endpoint 2. Data Received Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 3. " EP1TX ,Endpoint 1. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " EP1RX ,Endpoint 1. Data Received Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " EP0TX ,Endpoint 0. Data Transmitted Interrupt or sent a NAK" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " EP0RX ,Endpoint 0. Data Received Interrupt" "Disabled,Enabled"
|
|
wgroup.long 0x40++0x3
|
|
line.long 0x0 "USBEpIntPri,USB Endpoint Interrupt Priority Register"
|
|
bitfld.long 0x0 31. " EP15TX ,Endpoint 15. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 30. " EP15RX ,Endpoint 15. Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 29. " EP14TX ,Endpoint 14. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 28. " EP14RX ,Endpoint 14. Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 27. " EP13TX ,Endpoint 13. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 26. " EP13RX ,Endpoint 13. Data Received Interrupt" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EP12TX ,Endpoint 12. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 24. " EP12RX ,Endpoint 12. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 23. " EP11TX ,Endpoint 11. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 22. " EP11RX ,Endpoint 11, Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 21. " EP10TX ,Endpoint 10. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 20. " EP10RX ,Endpoint 10. Data Received Interrupt" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 19. " EP9TX ,Endpoint 9. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 18. " EP9RX ,Endpoint 9. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 17. " EP8TX ,Endpoint 8. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EP8RX ,Endpoint 8. Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 15. " EP7TX ,Endpoint 7. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 14. " EP7RX ,Endpoint 7. Data Received Interrupt" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EP6TX ,Endpoint 6. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 12. " EP6RX ,Endpoint 6. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 11. " EP5TX ,Endpoint 5. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EP5RX ,Endpoint 5. Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 9. " EP4TX ,Endpoint 4. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 8. " EP4RX ,Endpoint 4. Data Received Interrupt" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EP3TX ,Endpoint 3. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 6. " EP3RX ,Endpoint 3. Isochronous endpoint" "Slow,Fast"
|
|
bitfld.long 0x0 5. " EP2TX ,Endpoint 2. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EP2RX ,Endpoint 2. Data Received Interrupt" "Slow,Fast"
|
|
bitfld.long 0x0 3. " EP1TX ,Endpoint 1. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 2. " EP1RX ,Endpoint 1. Data Received Interrupt" "Slow,Fast"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EP0TX ,Endpoint 0. Data Transmitted Interrupt or sent a NAK" "Slow,Fast"
|
|
bitfld.long 0x0 0. " EP0RX ,Endpoint 0. Data Received Interrupt" "Slow,Fast"
|
|
tree.end
|
|
tree "Realization, Transfer and Command Registers"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "USBReEp,USB Realize Endpoint Register"
|
|
bitfld.long 0x0 31. " EP31 ,Endpoint 31 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 30. " EP30 ,Endpoint 30 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 29. " EP29 ,Endpoint 29 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 28. " EP28 ,Endpoint 28 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 27. " EP27 ,Endpoint 27 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 26. " EP26 ,Endpoint 26 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EP25 ,Endpoint 25 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 24. " EP24 ,Endpoint 24 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 23. " EP23 ,Endpoint 23 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 22. " EP22 ,Endpoint 22 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 21. " EP21 ,Endpoint 21 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 20. " EP20 ,Endpoint 20 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 19. " EP19 ,Endpoint 19 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 18. " EP18 ,Endpoint 18 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 17. " EP17 ,Endpoint 17 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EP16 ,Endpoint 16 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 15. " EP15 ,Endpoint 15 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 14. " EP14 ,Endpoint 14 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EP13 ,Endpoint 13 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 12. " EP12 ,Endpoint 12 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 11. " EP11 ,Endpoint 11 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EP10 ,Endpoint 10 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 9. " EP9 ,Endpoint 9 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 8. " EP8 ,Endpoint 8 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EP7 ,Endpoint 7 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 6. " EP6 ,Endpoint 6 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 5. " EP5 ,Endpoint 5 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EP4 ,Endpoint 4 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 3. " EP3 ,Endpoint 3 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 2. " EP2 ,Endpoint 2 realized" "Unrealized,Realized"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EP1 ,Endpoint 1 realized" "Unrealized,Realized"
|
|
bitfld.long 0x0 0. " EP0 ,Endpoint 0 realized" "Unrealized,Realized"
|
|
wgroup.long 0x48++0x3
|
|
line.long 0x0 "USBEpInd,USB Endpoint Index Register"
|
|
bitfld.long 0x0 0.--4. " PhyEndp ,Physical endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "USBMaxPSize,USB MaxPacketSize Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " MaxPacketSize ,Maximum packet size value"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "USBRxData,USB Receive Data Register"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "USBRxPLen,USB Receive Packet Length Register"
|
|
bitfld.long 0x0 11. " PKT_RDY ,Packet length field ready" "Not ready,Ready"
|
|
bitfld.long 0x0 10. " DV ,Data valid" "Invalid,Valid"
|
|
hexmask.long.word 0x0 0.--9. 1. " PKT_LNGTH ,Remaining amount of data in bytes still to be read from the RAM"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "USBTxData,USB Transmit Data Register"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "USBTxPLen,USB Transmit Packet Length Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " PKT_LNGTH ,Remaining amount of data in bytes to be written to the EP_RAM"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "USBCtrl,USB Control Register"
|
|
bitfld.long 0x0 2.--5. " LOG_ENDPOINT ,Logical Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 1. " WR_EN ,Write mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RD_EN ,Read mode enable" "Disabled,Enabled"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "USBCmdCode,USB Command Code Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. " CMD_CODE ,Code for the command"
|
|
hexmask.long.byte 0x0 8.--15. 1. " CMD_PHASE ,Command phase"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "USBCmdData,USB Command Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " CMD_DATA ,Command Data"
|
|
tree.end
|
|
tree "DMA Registers"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "USBDMARSt,USB DMA Request Status Register"
|
|
setclrfld.long 0x0 31. 0x8 31. 0x4 31. " EP31_set/clr ,Endpoint 31 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 30. 0x8 30. 0x4 30. " EP30_set/clr ,Endpoint 30 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x8 29. 0x4 29. " EP29_set/clr ,Endpoint 29 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 28. 0x8 28. 0x4 28. " EP28_set/clr ,Endpoint 28 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x8 27. 0x4 27. " EP27_set/clr ,Endpoint 27 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 26. 0x8 26. 0x4 26. " EP26_set/clr ,Endpoint 26 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x8 25. 0x4 25. " EP25_set/clr ,Endpoint 25 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 24. 0x8 24. 0x4 24. " EP24_set/clr ,Endpoint 24 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x8 23. 0x4 23. " EP23_set/clr ,Endpoint 23 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 22. 0x8 22. 0x4 22. " EP22_set/clr ,Endpoint 22 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x8 21. 0x4 21. " EP21_set/clr ,Endpoint 21 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 20. 0x8 20. 0x4 20. " EP20_set/clr ,Endpoint 20 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x8 19. 0x4 19. " EP19_set/clr ,Endpoint 19 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 18. 0x8 18. 0x4 18. " EP18_set/clr ,Endpoint 18 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x8 17. 0x4 17. " EP17_set/clr ,Endpoint 17 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 16. 0x8 16. 0x4 16. " EP16_set/clr ,Endpoint 16 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x8 15. 0x4 15. " EP15_set/clr ,Endpoint 15 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 14. 0x8 14. 0x4 14. " EP14_set/clr ,Endpoint 14 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x8 13. 0x4 13. " EP13_set/clr ,Endpoint 13 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 12. 0x8 12. 0x4 12. " EP12_set/clr ,Endpoint 12 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x8 11. 0x4 11. " EP11_set/clr ,Endpoint 11 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 10. 0x8 10. 0x4 10. " EP10_set/clr ,Endpoint 10 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x8 9. 0x4 9. " EP9_set/clr ,Endpoint 9 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 8. 0x8 8. 0x4 8. " EP8_set/clr ,Endpoint 8 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x8 7. 0x4 7. " EP7_set/clr ,Endpoint 7 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 6. 0x8 6. 0x4 6. " EP6_set/clr ,Endpoint 6 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x8 5. 0x4 5. " EP5_set/clr ,Endpoint 5 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 4. 0x8 4. 0x4 4. " EP4_set/clr ,Endpoint 4 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x8 3. 0x4 3. " EP3_set/clr ,Endpoint 3 DMA request" "Not requested,Requested"
|
|
setclrfld.long 0x0 2. 0x8 2. 0x4 2. " EP2_set/clr ,Endpoint 2 DMA request" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x8 1. 0x4 1. " EP1_set/clr ,Control endpoint IN" "Not requested,Requested"
|
|
setclrfld.long 0x0 0. 0x8 0. 0x4 0. " EP0_set/clr ,Control endpoint OUT" "Not requested,Requested"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "USBUDCAH,USB UDCA Head Register"
|
|
hexmask.long 0x0 7.--31. 0x80 " UDCAHeader ,Start address of the UDCA Header"
|
|
line.long 0x4 "USBEpDMASt,USB EP DMA Status Register"
|
|
setclrfld.long 0x4 31. 0x8 31. 0xC 31. " EP31_set/clr ,DMA for Endpoint 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 30. 0x8 30. 0xC 30. " EP30_set/clr ,DMA for Endpoint 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 29. 0x8 29. 0xC 29. " EP29_set/clr ,DMA for Endpoint 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 28. 0x8 28. 0xC 28. " EP28_set/clr ,DMA for Endpoint 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 27. 0x8 27. 0xC 27. " EP27_set/clr ,DMA for Endpoint 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 26. 0x8 26. 0xC 26. " EP26_set/clr ,DMA for Endpoint 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 25. 0x8 25. 0xC 25. " EP25_set/clr ,DMA for Endpoint 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 24. 0x8 24. 0xC 24. " EP24_set/clr ,DMA for Endpoint 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 23. 0x8 23. 0xC 23. " EP23_set/clr ,DMA for Endpoint 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 22. 0x8 22. 0xC 22. " EP22_set/clr ,DMA for Endpoint 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 21. 0x8 21. 0xC 21. " EP21_set/clr ,DMA for Endpoint 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 20. 0x8 20. 0xC 20. " EP20_set/clr ,DMA for Endpoint 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 19. 0x8 19. 0xC 19. " EP19_set/clr ,DMA for Endpoint 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 18. 0x8 18. 0xC 18. " EP18_set/clr ,DMA for Endpoint 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 17. 0x8 17. 0xC 17. " EP17_set/clr ,DMA for Endpoint 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 16. 0x8 16. 0xC 16. " EP16_set/clr ,DMA for Endpoint 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 15. 0x8 15. 0xC 15. " EP15_set/clr ,DMA for Endpoint 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 14. 0x8 14. 0xC 14. " EP14_set/clr ,DMA for Endpoint 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 13. 0x8 13. 0xC 13. " EP13_set/clr ,DMA for Endpoint 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 12. 0x8 12. 0xC 12. " EP12_set/clr ,DMA for Endpoint 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 11. 0x8 11. 0xC 11. " EP11_set/clr ,DMA for Endpoint 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 10. 0x8 10. 0xC 10. " EP10_set/clr ,DMA for Endpoint 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 9. 0x8 9. 0xC 9. " EP9_set/clr ,DMA for Endpoint 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 8. 0x8 8. 0xC 8. " EP8_set/clr ,DMA for Endpoint 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 7. 0x8 7. 0xC 7. " EP7_set/clr ,DMA for Endpoint 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 6. 0x8 6. 0xC 6. " EP6_set/clr ,DMA for Endpoint 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 5. 0x8 5. 0xC 5. " EP5_set/clr ,DMA for Endpoint 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 4. 0x8 4. 0xC 4. " EP4_set/clr ,DMA for Endpoint 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 3. 0x8 3. 0xC 3. " EP3_set/clr ,DMA for Endpoint 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x4 2. 0x8 2. 0xC 2. " EP2_set/clr ,DMA for Endpoint 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x4 1. 0x8 1. 0xC 1. " EP1_set/clr ,Control endpoint IN" "0,1"
|
|
setclrfld.long 0x4 0. 0x8 0. 0xC 0. " EP0_set/clr ,Control endpoint OUT" "0,1"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "USBDMAIntSt,USB DMA Interrupt Status Register"
|
|
bitfld.long 0x0 2. " SysErrInt ,System error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 1. " NewDDReqInt ,New DD Request Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 0. " EndOfTrInt ,End of Transfer Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "USBDMAIntEn,USB DMA Interrupt Enable Register"
|
|
bitfld.long 0x0 2. " SysErrInt ,System error interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " NewDDReqInt ,New DD Request Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " EndOfTrInt ,End of Transfer Interrupt" "Disabled,Enabled"
|
|
group.long 0xAC++0x3
|
|
line.long 0x0 "USBNDDRIntSt,USB New DD Request Interrupt Status Register"
|
|
setclrfld.long 0x0 31. 0x8 31. 0x4 31. " EP31_set/clr ,New DD Request for Endpoint 31" "Not requested,Requested"
|
|
setclrfld.long 0x0 30. 0x8 30. 0x4 30. " EP30_set/clr ,New DD Request for Endpoint 30" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x8 29. 0x4 29. " EP29_set/clr ,New DD Request for Endpoint 29" "Not requested,Requested"
|
|
setclrfld.long 0x0 28. 0x8 28. 0x4 28. " EP28_set/clr ,New DD Request for Endpoint 28" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x8 27. 0x4 27. " EP27_set/clr ,New DD Request for Endpoint 27" "Not requested,Requested"
|
|
setclrfld.long 0x0 26. 0x8 26. 0x4 26. " EP26_set/clr ,New DD Request for Endpoint 26" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x8 25. 0x4 25. " EP25_set/clr ,New DD Request for Endpoint 25" "Not requested,Requested"
|
|
setclrfld.long 0x0 24. 0x8 24. 0x4 24. " EP24_set/clr ,New DD Request for Endpoint 24" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x8 23. 0x4 23. " EP23_set/clr ,New DD Request for Endpoint 23" "Not requested,Requested"
|
|
setclrfld.long 0x0 22. 0x8 22. 0x4 22. " EP22_set/clr ,New DD Request for Endpoint 22" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x8 21. 0x4 21. " EP21_set/clr ,New DD Request for Endpoint 21" "Not requested,Requested"
|
|
setclrfld.long 0x0 20. 0x8 20. 0x4 20. " EP20_set/clr ,New DD Request for Endpoint 20" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x8 19. 0x4 19. " EP19_set/clr ,New DD Request for Endpoint 19" "Not requested,Requested"
|
|
setclrfld.long 0x0 18. 0x8 18. 0x4 18. " EP18_set/clr ,New DD Request for Endpoint 18" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x8 17. 0x4 17. " EP17_set/clr ,New DD Request for Endpoint 17" "Not requested,Requested"
|
|
setclrfld.long 0x0 16. 0x8 16. 0x4 16. " EP16_set/clr ,New DD Request for Endpoint 16" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x8 15. 0x4 15. " EP15_set/clr ,New DD Request for Endpoint 15" "Not requested,Requested"
|
|
setclrfld.long 0x0 14. 0x8 14. 0x4 14. " EP14_set/clr ,New DD Request for Endpoint 14" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x8 13. 0x4 13. " EP13_set/clr ,New DD Request for Endpoint 13" "Not requested,Requested"
|
|
setclrfld.long 0x0 12. 0x8 12. 0x4 12. " EP12_set/clr ,New DD Request for Endpoint 12" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x8 11. 0x4 11. " EP11_set/clr ,New DD Request for Endpoint 11" "Not requested,Requested"
|
|
setclrfld.long 0x0 10. 0x8 10. 0x4 10. " EP10_set/clr ,New DD Request for Endpoint 10" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x8 9. 0x4 9. " EP9_set/clr ,New DD Request for Endpoint 9" "Not requested,Requested"
|
|
setclrfld.long 0x0 8. 0x8 8. 0x4 8. " EP8_set/clr ,New DD Request for Endpoint 8" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x8 7. 0x4 7. " EP7_set/clr ,New DD Request for Endpoint 7" "Not requested,Requested"
|
|
setclrfld.long 0x0 6. 0x8 6. 0x4 6. " EP6_set/clr ,New DD Request for Endpoint 6" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x8 5. 0x4 5. " EP5_set/clr ,New DD Request for Endpoint 5" "Not requested,Requested"
|
|
setclrfld.long 0x0 4. 0x8 4. 0x4 4. " EP4_set/clr ,New DD Request for Endpoint 4" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x8 3. 0x4 3. " EP3_set/clr ,New DD Request for Endpoint 3" "Not requested,Requested"
|
|
setclrfld.long 0x0 2. 0x8 2. 0x4 2. " EP2_set/clr ,New DD Request for Endpoint 2" "Not requested,Requested"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x8 1. 0x4 1. " EP1_set/clr ,New DD Request for Endpoint 1" "Not requested,Requested"
|
|
setclrfld.long 0x0 0. 0x8 0. 0x4 0. " EP0_set/clr ,New DD Request for Endpoint 0" "Not requested,Requested"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "USBEoTIntSt,USB End Of Transfer Interrupt Status Register"
|
|
setclrfld.long 0x0 31. 0x8 31. 0x4 31. " EP31_set/clr ,End of Transfer Interrupt request for Endpoint 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 30. 0x8 30. 0x4 30. " EP30_set/clr ,End of Transfer Interrupt request for Endpoint 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x8 29. 0x4 29. " EP29_set/clr ,End of Transfer Interrupt request for Endpoint 29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 28. 0x8 28. 0x4 28. " EP28_set/clr ,End of Transfer Interrupt request for Endpoint 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x8 27. 0x4 27. " EP27_set/clr ,End of Transfer Interrupt request for Endpoint 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 26. 0x8 26. 0x4 26. " EP26_set/clr ,End of Transfer Interrupt request for Endpoint 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x8 25. 0x4 25. " EP25_set/clr ,End of Transfer Interrupt request for Endpoint 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 24. 0x8 24. 0x4 24. " EP24_set/clr ,End of Transfer Interrupt request for Endpoint 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x8 23. 0x4 23. " EP23_set/clr ,End of Transfer Interrupt request for Endpoint 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 22. 0x8 22. 0x4 22. " EP22_set/clr ,End of Transfer Interrupt request for Endpoint 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x8 21. 0x4 21. " EP21_set/clr ,End of Transfer Interrupt request for Endpoint 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 20. 0x8 20. 0x4 20. " EP20_set/clr ,End of Transfer Interrupt request for Endpoint 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x8 19. 0x4 19. " EP19_set/clr ,End of Transfer Interrupt request for Endpoint 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 18. 0x8 18. 0x4 18. " EP18_set/clr ,End of Transfer Interrupt request for Endpoint 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x8 17. 0x4 17. " EP17_set/clr ,End of Transfer Interrupt request for Endpoint 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 16. 0x8 16. 0x4 16. " EP16_set/clr ,End of Transfer Interrupt request for Endpoint 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x8 15. 0x4 15. " EP15_set/clr ,End of Transfer Interrupt request for Endpoint 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 14. 0x8 14. 0x4 14. " EP14_set/clr ,End of Transfer Interrupt request for Endpoint 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x8 13. 0x4 13. " EP13_set/clr ,End of Transfer Interrupt request for Endpoint 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 12. 0x8 12. 0x4 12. " EP12_set/clr ,End of Transfer Interrupt request for Endpoint 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x8 11. 0x4 11. " EP11_set/clr ,End of Transfer Interrupt request for Endpoint 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 10. 0x8 10. 0x4 10. " EP10_set/clr ,End of Transfer Interrupt request for Endpoint 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x8 9. 0x4 9. " EP9_set/clr ,End of Transfer Interrupt request for Endpoint 9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 8. 0x8 8. 0x4 8. " EP8_set/clr ,End of Transfer Interrupt request for Endpoint 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x8 7. 0x4 7. " EP7_set/clr ,End of Transfer Interrupt request for Endpoint 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 6. 0x8 6. 0x4 6. " EP6_set/clr ,End of Transfer Interrupt request for Endpoint 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x8 5. 0x4 5. " EP5_set/clr ,End of Transfer Interrupt request for Endpoint 5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 4. 0x8 4. 0x4 4. " EP4_set/clr ,End of Transfer Interrupt request for Endpoint 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x8 3. 0x4 3. " EP3_set/clr ,End of Transfer Interrupt request for Endpoint 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 2. 0x8 2. 0x4 2. " EP2_set/clr ,End of Transfer Interrupt request for Endpoint 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x8 1. 0x4 1. " EP1_set/clr ,End of Transfer Interrupt request for Endpoint 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0x8 0. 0x4 0. " EP0_set/clr ,End of Transfer Interrupt request for Endpoint 0" "No interrupt,Interrupt"
|
|
group.long 0xB8++0x3
|
|
line.long 0x0 "USBSysErrIntSt,USB System Error Interrupt Status Register"
|
|
setclrfld.long 0x0 31. 0x8 31. 0x4 31. " EP31_set/clr ,System Error Interrupt request for Endpoint 31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 30. 0x8 30. 0x4 30. " EP30_set/clr ,System Error Interrupt request for Endpoint 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 29. 0x8 29. 0x4 29. " EP29_set/clr ,System Error Interrupt request for Endpoint 29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 28. 0x8 28. 0x4 28. " EP28_set/clr ,System Error Interrupt request for Endpoint 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 27. 0x8 27. 0x4 27. " EP27_set/clr ,System Error Interrupt request for Endpoint 27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 26. 0x8 26. 0x4 26. " EP26_set/clr ,System Error Interrupt request for Endpoint 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 25. 0x8 25. 0x4 25. " EP25_set/clr ,System Error Interrupt request for Endpoint 25" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 24. 0x8 24. 0x4 24. " EP24_set/clr ,System Error Interrupt request for Endpoint 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 23. 0x8 23. 0x4 23. " EP23_set/clr ,System Error Interrupt request for Endpoint 23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 22. 0x8 22. 0x4 22. " EP22_set/clr ,System Error Interrupt request for Endpoint 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 21. 0x8 21. 0x4 21. " EP21_set/clr ,System Error Interrupt request for Endpoint 21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 20. 0x8 20. 0x4 20. " EP20_set/clr ,System Error Interrupt request for Endpoint 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 19. 0x8 19. 0x4 19. " EP19_set/clr ,System Error Interrupt request for Endpoint 19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 18. 0x8 18. 0x4 18. " EP18_set/clr ,System Error Interrupt request for Endpoint 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 17. 0x8 17. 0x4 17. " EP17_set/clr ,System Error Interrupt request for Endpoint 17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 16. 0x8 16. 0x4 16. " EP16_set/clr ,System Error Interrupt request for Endpoint 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 15. 0x8 15. 0x4 15. " EP15_set/clr ,System Error Interrupt request for Endpoint 15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 14. 0x8 14. 0x4 14. " EP14_set/clr ,System Error Interrupt request for Endpoint 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 13. 0x8 13. 0x4 13. " EP13_set/clr ,System Error Interrupt request for Endpoint 13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 12. 0x8 12. 0x4 12. " EP12_set/clr ,System Error Interrupt request for Endpoint 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 11. 0x8 11. 0x4 11. " EP11_set/clr ,System Error Interrupt request for Endpoint 11" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 10. 0x8 10. 0x4 10. " EP10_set/clr ,System Error Interrupt request for Endpoint 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 9. 0x8 9. 0x4 9. " EP9_set/clr ,System Error Interrupt request for Endpoint 9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 8. 0x8 8. 0x4 8. " EP8_set/clr ,System Error Interrupt request for Endpoint 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 7. 0x8 7. 0x4 7. " EP7_set/clr ,System Error Interrupt request for Endpoint 7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 6. 0x8 6. 0x4 6. " EP6_set/clr ,System Error Interrupt request for Endpoint 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 5. 0x8 5. 0x4 5. " EP5_set/clr ,System Error Interrupt request for Endpoint 5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 4. 0x8 4. 0x4 4. " EP4_set/clr ,System Error Interrupt request for Endpoint 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 3. 0x8 3. 0x4 3. " EP3_set/clr ,System Error Interrupt request for Endpoint 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 2. 0x8 2. 0x4 2. " EP2_set/clr ,System Error Interrupt request for Endpoint 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x8 1. 0x4 1. " EP1_set/clr ,System Error Interrupt request for Endpoint 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x0 0. 0x8 0. 0x4 0. " EP0_set/clr ,System Error Interrupt request for Endpoint 0" "No interrupt,Interrupt"
|
|
sif (cpu()=="LPC3180")
|
|
group.long 0xFC++0x3
|
|
line.long 0x0 "USBModId,USB Module ID Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " IP_Number ,USB Device Core IP number"
|
|
hexmask.long.byte 0x0 8.--15. 1. " VER ,Version Number"
|
|
hexmask.long.byte 0x0 0.--7. 1. " REV ,Reversion Number"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "UBS Host (OHCI) Controller"
|
|
base ad:0x31020000
|
|
width 22.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x0 "HcRevision,BCD Representation Of The Version Of The HCI Specification Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " REV ,BCD Representation Of The Version Of The HCI Specification"
|
|
group.long 0x04++0x3
|
|
line.long 0x0 "HcControl,HC Operating Modes Register"
|
|
bitfld.long 0x0 10. " RWE ,Remote Wakeup Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 9. " RWC ,Remote Wakeup Connected" "Not connected,Connected"
|
|
bitfld.long 0x0 8. " IR ,Interrupt Routing" "Normal host bus,System Management"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " HCFS ,Host Controller Functional State for USB" "Reset,Resume,Operational,Suspend"
|
|
bitfld.long 0x0 5. " BLE ,Bulk List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " CLE ,Control List Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IE ,Isochronous Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " PLE ,Periodic List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0.--1. " CBSR ,Control Bulk Service Ratio" "1:1,2:1,3:1,4:1"
|
|
group.long 0x08++0x3
|
|
line.long 0x0 "HcCommandStatus,HC Status Register"
|
|
bitfld.long 0x0 16.--17. " SOC ,Scheduling Overrun Count" "0,1,2,3"
|
|
bitfld.long 0x0 3. " OCR ,Ownership Change Request" "Not requested,Requested"
|
|
bitfld.long 0x0 2. " BLF ,Bulk List Filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CLF ,Control List Filled" "Not filled,Filled"
|
|
bitfld.long 0x0 0. " HCR ,Host Controller Reset" "No effect,Reset"
|
|
group.long 0x0c++0x3
|
|
line.long 0x0 "HcInterruptStatus,HC Interrupt Status Register"
|
|
bitfld.long 0x0 30. " OC ,Ownership Change" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 6. " RHSC ,Root Hub Status Change" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 5. " FNO ,Frame Number Overflow" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 4. " UE ,Unrecoverable Error" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 3. " RD ,Resume Detected" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " SF ,Start of Frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " WDH ,Writeback Done Head" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " SO ,Scheduling Overrun" "No interrupt,Interrupt"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "HcInterruptEn/Dis,HC Interrupt Enable/Disable Register"
|
|
setclrfld.long 0x0 31. 0x0 31. 0x4 31. " MIE_set/clr ,Master Interrupt Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x0 30. 0x0 30. 0x4 30. " OCMIE_set/clr ,Ownership Change" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 6. 0x0 6. 0x4 6. " RHSCMIE_set/clr ,Root Hub Status Change" "Disabled,Enabled"
|
|
setclrfld.long 0x0 5. 0x0 5. 0x4 5. " FNOMIE_set/clr ,Frame Number Overflow" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 4. 0x0 4. 0x4 4. " UEMIE_set/clr ,Unrecoverable Error" "Disabled,Enabled"
|
|
setclrfld.long 0x0 3. 0x0 3. 0x4 3. " RDMIE_set/clr ,Resume Detected" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 2. 0x0 2. 0x4 2. " SFMIE_set/clr ,Start of Frame" "Disabled,Enabled"
|
|
setclrfld.long 0x0 1. 0x0 1. 0x4 1. " WDHMIE_set/clr ,Writeback Done Head" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0 0. 0x0 0. 0x4 0. " SOMIE_set/clr ,Scheduling Overrun" "Disabled,Enabled"
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "HcHCCA,Host Controller Communication Area Physical Address Register"
|
|
hexmask.long 0x00 8.--31. 0x100 " HCCA ,Host Controller Communication Area Base Address"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "HcPeriodCurrentED,Current Isochronous Or Interrupt Endpoint Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " PCED ,Period Current ED"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "HcControlHeadED,First Endpoint Of The Control List Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " CHED ,Control Head ED"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "HcControlCurrentED,Current Endpoint Of The Control List Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " CCED ,Control Current ED"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "HcBulkHeadED,First Endpoint Of The Bulk List Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " BHED ,Bulk Head ED"
|
|
group.long 0x2c++0x3
|
|
line.long 0x0 "HcBulkCurrentED,Current Endpoint Of The Bulk List Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " BCED ,Bulk Current ED"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "HcDoneHead,Last Transfer Descriptor Added Physical Address Register"
|
|
hexmask.long 0x0 4.--31. 0x10 " DH ,Done Head"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "HcFmInterval,HC Frame Interval Register"
|
|
bitfld.long 0x0 31. " FIT ,Frame Interval Toggle" "Not toggled,Toggled"
|
|
hexmask.long.word 0x0 16.--30. 1. " FSMPS ,FS Largest Data Packet"
|
|
hexmask.long.word 0x0 0.--13. 1. " FI ,Frame Interval"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "HcFmRemaining,HC Frame Remaining Register"
|
|
bitfld.long 0x0 31. " FRT ,Frame Remaining Toggle" "Not toggled,Toggled"
|
|
hexmask.long.word 0x0 0.--13. 1. " FR ,Frame Remaining"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x0 "HcFmNumber,HC Frame Number Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " FN ,Frame Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "HcPeriodicStart,HC Periodic Start Register"
|
|
hexmask.long.word 0x0 0.--13. 1. " PS ,Periodic Start"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "HcLSThreshold,HC LS Threshold Register"
|
|
hexmask.long.word 0x0 0.--11. 1. " LST ,LS Threshold"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "HcRhDescriptorA,HC Root Hub Descriptor A Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x0 12. " NOCP ,No Over Current Protection" "Protection,No protection"
|
|
bitfld.long 0x0 11. " OCPM ,Over Current Protection Mode" "Collectively,Per-port basis"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DT ,Device Type" "Not compound,Compound"
|
|
bitfld.long 0x0 9. " PSM ,Power Switching Mode" "Global,Individual"
|
|
bitfld.long 0x0 8. " NPS ,No Power Switching" "Switched,Not switched"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " NDP ,Number Downstream Ports"
|
|
group.long 0x4c++0x3
|
|
line.long 0x0 "HcRhDescriptorB,HC Root Hub Descriptor B Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " PPCM ,Port Power Control Mask"
|
|
hexmask.long.word 0x0 0.--15. 1. " DR ,Device Removable"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "HcRhStatus,HC Root Hub Status Register"
|
|
bitfld.long 0x0 31. " CRWE ,Clear Remote Wakeup Enable" "No effect,Cleared"
|
|
eventfld.long 0x0 17. " OCIC ,Over Current Indicator Change" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0 16. " LPSC ,Local Power Status Change/Set Global Power (read/write)" "Not supported/No effect,Not supported/Turn power on"
|
|
bitfld.long 0x0 15. " DRWE ,Device Remote Wakeup Enable/Set Remote Wakeup Enable (read/write)" "No wakeup/No effect,Wakeup/Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " OCI ,OverCurrent Indicator" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x0 0. " LPS ,Local Power Status/Clear Global Power (read/write)" "Not supported/No effect,Not supported/Turn power off"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "HcRhPortStatus[1],HC Root Hub Port Status 1 Register"
|
|
eventfld.long 0x0 20. " PRSC ,Port Reset Status Change" "Not changed,Changed"
|
|
eventfld.long 0x0 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x0 18. " PSSC ,Port Suspend Status Change" "Not changed,Changed"
|
|
eventfld.long 0x0 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x0 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x0 9. " LSDA ,Low Speed Device Attached/Clear Port Power (read/write)" "Full speed/No effect,Low speed/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 8. " PPS ,Port Power Status/Set Port Power (read/write)" "Off/No effect,On/Set"
|
|
bitfld.long 0x0 4. " PRS ,Port Reset Status/Set Port Reset (read/write)" "Inactive/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " POCI ,Port Over Current Indicator/Clear Suspend Status (read/write)" "No overcurrent/No effect,Overcurrent/Clear"
|
|
bitfld.long 0x0 2. " PSS ,Port Suspend Status/Set Port Suspend (read/write)" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " PES ,Port Enable Status/Set Port Enable (read/write)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x0 0. " CCS ,Current Connect Status/Clear Port Enable (read/write)" "Not connected/No effect,Connected/Clear"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "HcRhPortStatus[2],HC Root Hub Port Status 2 Register"
|
|
eventfld.long 0x0 20. " PRSC ,Port Reset Status Change" "Not changed,Changed"
|
|
eventfld.long 0x0 19. " OCIC ,Port Over Current Indicator Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x0 18. " PSSC ,Port Suspend Status Change" "Not changed,Changed"
|
|
eventfld.long 0x0 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x0 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x0 9. " LSDA ,Low Speed Device Attached/Clear Port Power (read/write)" "Full speed/No effect,Low speed/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 8. " PPS ,Port Power Status/Set Port Power (read/write)" "Off/No effect,On/Set"
|
|
bitfld.long 0x0 4. " PRS ,Port Reset Status/Set Port Reset (read/write)" "Inactive/No effect,Active/Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " POCI ,Port Over Current Indicator/Clear Suspend Status (read/write)" "No overcurrent/No effect,Overcurrent/Clear"
|
|
bitfld.long 0x0 2. " PSS ,Port Suspend Status/Set Port Suspend (read/write)" "Not suspended/No effect,Suspended/Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " PES ,Port Enable Status/Set Port Enable (read/write)" "Disabled/No effect,Enabled/Set"
|
|
bitfld.long 0x0 0. " CCS ,Current Connect Status/Clear Port Enable (read/write)" "Not connected/No effect,Connected/Clear"
|
|
sif (cpu()=="LPC3180"||cpuis("LPC293*"))
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "Module_ID/Ver_Rev_ID,Module Version And Reversion ID Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "UBS OTG Controller"
|
|
base ad:0x31020100
|
|
width 16.
|
|
group.long 0x00++0x7
|
|
line.long 0x0 "OTG_int_status,OTG Interrupt Status Register"
|
|
setclrfld.long 0x0 3. 0x8 3. 0xC 3. " hnp_success_set/clr ,hnp_success interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 2. 0x8 2. 0xC 2. " hnp_failure_set/clr ,hnp_failure interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 1. 0x8 1. 0xC 1. " remove_pullup_set/clr ,remove_pullup interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
setclrfld.long 0x0 0. 0x8 3. 0xC 3. " timer_interrupt_set/clr ,timer_interrupt interrupt" "No interrupt,Interrupt"
|
|
line.long 0x4 "OTG_int_enable,OTG Interrupt Enable Register"
|
|
bitfld.long 0x4 3. " hnp_success ,hnp_success interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " hnp_failure ,hnp_failure interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 1. " remove_pullup ,remove_pullup interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x4 0. " timer_interrupt ,timer_interrupt interrupt" "Disabled,Enabled"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "OTG_status,OTG Status And Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " TimCountSt ,Timer count status"
|
|
bitfld.long 0x0 10. " Pullup_removed ,Pullup Removed" "Not removed,Removed"
|
|
textline " "
|
|
bitfld.long 0x0 9. " a_to_b_hnp_track ,A to B hnp track" "Not switched,Switched"
|
|
bitfld.long 0x0 8. " b_to_a_hnp_track ,B to A hnp track" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x0 7. " Transp_I2C_en ,Transparent I2C enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " Timer_reset ,Timer reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0 5. " Timer_enable ,Timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " Timer_mode ,Timer mode" "Monoshot,Free running"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " Timer_scale ,Timer granularity selection" "10 us,100 us,1000 us,?..."
|
|
bitfld.long 0x0 0. " Host_En ,USB Host or Device selection" "Device,Host"
|
|
line.long 0x4 "OTG_timer,OTG Timer Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " TimerValue ,16-bit timer value to be counted"
|
|
base ad:0x31020F00
|
|
group.long 0xF4++0x7
|
|
line.long 0x0 "OTG_clock_ctrl,OTG Clock Control Register"
|
|
bitfld.long 0x0 4. " AHB_CLK_ON ,AHB clock control" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " OTG_CLK_ON ,OTG clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " I2C_CLK_ON ,I2C clock control" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " DEV_CLK_ON ,Device clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HOST_CLK_ON ,Host clock control" "Disabled,Enabled"
|
|
line.long 0x4 "OTG_clock_stat,OTG Clock Status Register"
|
|
bitfld.long 0x4 4. " AHB_CLK_ON ,AHB clock status" "Not available,Available"
|
|
bitfld.long 0x4 3. " OTG_CLK_ON ,OTG clock status" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x4 2. " I2C_CLK_ON ,I2C clock status" "Not available,Available"
|
|
bitfld.long 0x4 1. " DEV_CLK_ON ,Device clock status" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x4 0. " HOST_CLK_ON ,Host clock status" "Not available,Available"
|
|
sif (cpu()=="LPC3180")
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "OTG_module_id,OTG Module ID Register"
|
|
hexmask.long.word 0x0 16.--31. 1. " IP_Number ,USB OTG IP number"
|
|
hexmask.long.byte 0x0 8.--15. 1. " VER ,Version Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " REV ,Reversion Number"
|
|
endif
|
|
base ad:0x31020300
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "I2C_RX/TX,I2C RX/TX Register"
|
|
in
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "I2C_STS,I2C STS Register"
|
|
bitfld.long 0x0 11. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x0 10. " TFF ,Transmit FIFO Full" "Not full,Full"
|
|
bitfld.long 0x0 9. " RFE ,Receive FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x0 8. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x0 7. " SDA ,Value of the SDA signal" "Low,High"
|
|
bitfld.long 0x0 6. " SCL ,Value of the SCL signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " Active ,Bus Active" "Not active,Active"
|
|
bitfld.long 0x0 4. " DRSI ,Slave Data Request" "No request,Request"
|
|
bitfld.long 0x0 3. " DRMI ,Master Data Request" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x0 2. " NAI ,No Acknowledge" "Acknowledge,No acknowledge"
|
|
bitfld.long 0x0 1. " AFI ,Arbitration Failure" "Not occurred,Occurred"
|
|
bitfld.long 0x0 0. " TDI ,Transaction Done" "Undone,Done"
|
|
group.long 0x08++0xB
|
|
line.long 0x0 "I2C_CTL,I2C CTL Register"
|
|
bitfld.long 0x0 8. " SRST ,Soft reset" "No reset,Reset"
|
|
bitfld.long 0x0 7. " TFFIE ,Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RFDAIE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RFFIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DRSIE ,Slave Transmitter Data Request Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " DRMIE ,Master Transmitter Data Request Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " NAIE ,Transmitter No Acknowledge Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " AFIE ,Transmitter Arbitration Failure Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " TDIE ,Transmit Done Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x4 "I2C_CLKHI,I2C CLock High Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " CDHI ,Clock divisor high"
|
|
line.long 0x8 "I2C_CLKLO,I2C Clock Low Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " CDLO ,Clock divisor low"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "UARTs"
|
|
tree "Standard UART 3"
|
|
base ad:0x40080000
|
|
width 11.
|
|
if (((d.b(ad:0x40080000+0xC))&0x80)==0x0)
|
|
hgroup.byte 0x00++0x0
|
|
hide.byte 0x0 "U3RBR/THR,UART 3 Receiver Buffer/Transmitter Holding Register"
|
|
in
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U3IER,UART 3 Interrupt Enable Register"
|
|
bitfld.byte 0x0 2. " RxLinSt_IE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 1. " THRE_IE ,Transmit Holding Register Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " RDA_IE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x0
|
|
line.byte 0x0 "U3DLL,UART 3 Divisor Latch LSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLL ,Divisor Latch LSB"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U3DLM,UART 3 Divisor Latch MSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLM ,Divisor Latch MSB"
|
|
endif
|
|
rgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U3IIR,UART 3 Interrupt Identification Register"
|
|
bitfld.byte 0x0 7. " FIFO_En ,UART 3 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " FIFO_En ,UART 3 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0.--3. " Int_ID ,Interrupt Identification" "Reserved,Reserved,THRE,Reserved,RDA,Reserved,RLS,Reserved,Reserved,Reserved,Reserved,Reserved,CTI,?..."
|
|
bitfld.byte 0x0 0. " IntPend ,Interrupt Pending" "Pending,No pending"
|
|
wgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U3FCR,UART3 FIFO Control Register"
|
|
bitfld.byte 0x0 6.--7. " RxTrigLvl ,Receiver Trigger Level Select" "16,32,48,60"
|
|
bitfld.byte 0x0 4.--5. " TxTrigLvl ,Transmitter Trigger Level Select" "0,4,8,16"
|
|
bitfld.byte 0x0 3. " FIFOCtrl ,Internal UART 3 FIFO control" "Reserved,1"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " TxFIFORes ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 1. " RxFIFORes ,Receiver FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 0. " FIFOEn ,UART 3 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
if (((d.b(ad:0x40080000+0xC))&0x3)==0x0)
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U3LCR,UART 3 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,1.5 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U3LCR,UART 3 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,2 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
endif
|
|
hgroup.byte 0x14++0x0
|
|
hide.byte 0x0 "U3LSR,UART 3 Line Status Register"
|
|
in
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "U3RXLEV,UART 3 Rx FIFO Level Register"
|
|
hexmask.byte 0x0 0.--6. 1. " RXLEV ,Current receiver FIFO level"
|
|
base ad:0x400040D0
|
|
group.long 0x00++0x03
|
|
line.long 0x0 "U3_CLK,UART 3 Clock Select Registers"
|
|
bitfld.long 0x0 16. " ClkSource ,Clock source select" "PERIPH_CLK,HCLK"
|
|
hexmask.long 0x0 8.--15. 1. " XDivVal ,X divider value"
|
|
hexmask.long 0x0 0.--7. 1. " YDivVal ,Y divider value"
|
|
width 0xB
|
|
tree.end
|
|
tree "Standard UART 4"
|
|
base ad:0x40088000
|
|
width 11.
|
|
if (((d.b(ad:0x40088000+0xC))&0x80)==0x0)
|
|
hgroup.byte 0x00++0x0
|
|
hide.byte 0x0 "U4RBR/THR,UART 4 Receiver Buffer/Transmitter Holding Register"
|
|
in
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U4IER,UART 4 Interrupt Enable Register"
|
|
bitfld.byte 0x0 2. " RxLinSt_IE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 1. " THRE_IE ,Transmit Holding Register Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " RDA_IE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x0
|
|
line.byte 0x0 "U4DLL,UART 4 Divisor Latch LSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLL ,Divisor Latch LSB"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U4DLM,UART 4 Divisor Latch MSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLM ,Divisor Latch MSB"
|
|
endif
|
|
rgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U4IIR,UART 4 Interrupt Identification Register"
|
|
bitfld.byte 0x0 7. " FIFO_En ,UART 4 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " FIFO_En ,UART 4 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0.--3. " Int_ID ,Interrupt Identification" "Reserved,Reserved,THRE,Reserved,RDA,Reserved,RLS,Reserved,Reserved,Reserved,Reserved,Reserved,CTI,?..."
|
|
bitfld.byte 0x0 0. " IntPend ,Interrupt Pending" "Pending,No pending"
|
|
wgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U4FCR,UART4 FIFO Control Register"
|
|
bitfld.byte 0x0 6.--7. " RxTrigLvl ,Receiver Trigger Level Select" "16,32,48,60"
|
|
bitfld.byte 0x0 4.--5. " TxTrigLvl ,Transmitter Trigger Level Select" "0,4,8,16"
|
|
bitfld.byte 0x0 3. " FIFOCtrl ,Internal UART 4 FIFO control" "Reserved,1"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " TxFIFORes ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 1. " RxFIFORes ,Receiver FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 0. " FIFOEn ,UART 4 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
if (((d.b(ad:0x40088000+0xC))&0x3)==0x0)
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U4LCR,UART 4 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,1.5 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U4LCR,UART 4 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,2 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
endif
|
|
hgroup.byte 0x14++0x0
|
|
hide.byte 0x0 "U4LSR,UART 4 Line Status Register"
|
|
in
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "U4RXLEV,UART 4 Rx FIFO Level Register"
|
|
hexmask.byte 0x0 0.--6. 1. " RXLEV ,Current receiver FIFO level"
|
|
base ad:0x400040D4
|
|
group.long 0x00++0x03
|
|
line.long 0x0 "U4_CLK,UART 4 Clock Select Registers"
|
|
bitfld.long 0x0 16. " ClkSource ,Clock source select" "PERIPH_CLK,HCLK"
|
|
hexmask.long 0x0 8.--15. 1. " XDivVal ,X divider value"
|
|
hexmask.long 0x0 0.--7. 1. " YDivVal ,Y divider value"
|
|
width 0xB
|
|
tree.end
|
|
tree "Standard UART 5"
|
|
base ad:0x40090000
|
|
width 11.
|
|
if (((d.b(ad:0x40090000+0xC))&0x80)==0x0)
|
|
hgroup.byte 0x00++0x0
|
|
hide.byte 0x0 "U5RBR/THR,UART 5 Receiver Buffer/Transmitter Holding Register"
|
|
in
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U5IER,UART 5 Interrupt Enable Register"
|
|
bitfld.byte 0x0 2. " RxLinSt_IE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 1. " THRE_IE ,Transmit Holding Register Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " RDA_IE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x0
|
|
line.byte 0x0 "U5DLL,UART 5 Divisor Latch LSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLL ,Divisor Latch LSB"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U5DLM,UART 5 Divisor Latch MSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLM ,Divisor Latch MSB"
|
|
endif
|
|
rgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U5IIR,UART 5 Interrupt Identification Register"
|
|
bitfld.byte 0x0 7. " FIFO_En ,UART 5 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " FIFO_En ,UART 5 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0.--3. " Int_ID ,Interrupt Identification" "Reserved,Reserved,THRE,Reserved,RDA,Reserved,RLS,Reserved,Reserved,Reserved,Reserved,Reserved,CTI,?..."
|
|
bitfld.byte 0x0 0. " IntPend ,Interrupt Pending" "Pending,No pending"
|
|
wgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U5FCR,UART5 FIFO Control Register"
|
|
bitfld.byte 0x0 6.--7. " RxTrigLvl ,Receiver Trigger Level Select" "16,32,48,60"
|
|
bitfld.byte 0x0 4.--5. " TxTrigLvl ,Transmitter Trigger Level Select" "0,4,8,16"
|
|
bitfld.byte 0x0 3. " FIFOCtrl ,Internal UART 5 FIFO control" "Reserved,1"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " TxFIFORes ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 1. " RxFIFORes ,Receiver FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 0. " FIFOEn ,UART 5 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
if (((d.b(ad:0x40090000+0xC))&0x3)==0x0)
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U5LCR,UART 5 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,1.5 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U5LCR,UART 5 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,2 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
endif
|
|
hgroup.byte 0x14++0x0
|
|
hide.byte 0x0 "U5LSR,UART 5 Line Status Register"
|
|
in
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "U5RXLEV,UART 5 Rx FIFO Level Register"
|
|
hexmask.byte 0x0 0.--6. 1. " RXLEV ,Current receiver FIFO level"
|
|
base ad:0x400040D8
|
|
group.long 0x00++0x03
|
|
line.long 0x0 "U5_CLK,UART 5 Clock Select Registers"
|
|
bitfld.long 0x0 16. " ClkSource ,Clock source select" "PERIPH_CLK,HCLK"
|
|
hexmask.long 0x0 8.--15. 1. " XDivVal ,X divider value"
|
|
hexmask.long 0x0 0.--7. 1. " YDivVal ,Y divider value"
|
|
width 0xB
|
|
tree.end
|
|
tree "Standard UART 6"
|
|
base ad:0x40098000
|
|
width 11.
|
|
if (((d.b(ad:0x40098000+0xC))&0x80)==0x0)
|
|
hgroup.byte 0x00++0x0
|
|
hide.byte 0x0 "U6RBR/THR,UART 6 Receiver Buffer/Transmitter Holding Register"
|
|
in
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U6IER,UART 6 Interrupt Enable Register"
|
|
bitfld.byte 0x0 2. " RxLinSt_IE ,Rx Line Status Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 1. " THRE_IE ,Transmit Holding Register Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " RDA_IE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x0
|
|
line.byte 0x0 "U6DLL,UART 6 Divisor Latch LSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLL ,Divisor Latch LSB"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x0 "U6DLM,UART 6 Divisor Latch MSB Register"
|
|
hexmask.byte 0x0 0.--7. 1. " DLM ,Divisor Latch MSB"
|
|
endif
|
|
rgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U6IIR,UART 6 Interrupt Identification Register"
|
|
bitfld.byte 0x0 7. " FIFO_En ,UART 6 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " FIFO_En ,UART 6 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 0.--3. " Int_ID ,Interrupt Identification" "Reserved,Reserved,THRE,Reserved,RDA,Reserved,RLS,Reserved,Reserved,Reserved,Reserved,Reserved,CTI,?..."
|
|
bitfld.byte 0x0 0. " IntPend ,Interrupt Pending" "Pending,No pending"
|
|
wgroup.byte 0x08++0x0
|
|
line.byte 0x0 "U6FCR,UART6 FIFO Control Register"
|
|
bitfld.byte 0x0 6.--7. " RxTrigLvl ,Receiver Trigger Level Select" "16,32,48,60"
|
|
bitfld.byte 0x0 4.--5. " TxTrigLvl ,Transmitter Trigger Level Select" "0,4,8,16"
|
|
bitfld.byte 0x0 3. " FIFOCtrl ,Internal UART 6 FIFO control" "Reserved,1"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " TxFIFORes ,Transmitter FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 1. " RxFIFORes ,Receiver FIFO Reset" "No reset,Reset"
|
|
bitfld.byte 0x0 0. " FIFOEn ,UART 6 transmit and receive FIFO enable" "Disabled,Enabled"
|
|
if (((d.b(ad:0x40098000+0xC))&0x3)==0x0)
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U6LCR,UART 6 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,1.5 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "U6LCR,UART 6 Line Control Register"
|
|
bitfld.byte 0x0 7. " DLAB ,Divisor Latch Access Bit" "Disabled,Enabled"
|
|
bitfld.byte 0x0 6. " BreakCtrl ,Break Transmission Control" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4.--5. " PairSel ,Parity Select" "Odd,Even,Forced 1,Forced 0"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " PairEn ,Parity Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 2. " StopBitSel ,Stop Bit Select" "1 stop bit,2 stop bits"
|
|
bitfld.byte 0x0 0.--1. " WordLength ,Word Length Select" "5 bit,6 bit,7 bit,8bit"
|
|
endif
|
|
hgroup.byte 0x14++0x0
|
|
hide.byte 0x0 "U6LSR,UART 6 Line Status Register"
|
|
in
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "U6RXLEV,UART 6 Rx FIFO Level Register"
|
|
hexmask.byte 0x0 0.--6. 1. " RXLEV ,Current receiver FIFO level"
|
|
base ad:0x400040DC
|
|
group.long 0x00++0x03
|
|
line.long 0x0 "U6_CLK,UART 6 Clock Select Registers"
|
|
bitfld.long 0x0 16. " ClkSource ,Clock source select" "PERIPH_CLK,HCLK"
|
|
hexmask.long 0x0 8.--15. 1. " XDivVal ,X divider value"
|
|
hexmask.long 0x0 0.--7. 1. " YDivVal ,Y divider value"
|
|
width 0xB
|
|
tree.end
|
|
tree "Fast UART 1"
|
|
base ad:0x40014000
|
|
width 12.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "HSU1_RX/TX,High Speed UART 1 Receiver/Transmitter FIFO Register"
|
|
in
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "HSU1_LEVEL,High Speed UART 1 Level Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " HSU_TX_LEV ,Current transmitter FIFO level"
|
|
hexmask.long.byte 0x0 0.--7. 1. " HSU_RX_LEV ,Current receiver FIFO level"
|
|
group.long 0x08++0xB
|
|
line.long 0x0 "HSU1_IIR,High Speed UART 1 Interrupt Identification Register"
|
|
bitfld.long 0x0 6. " HSU_TX_INT_SET ,Transmit interrupt flag set" "No effect,Set"
|
|
textline " "
|
|
eventfld.long 0x0 5. " HSU_RX_OE ,Overrun error flag" "No overflow,Overrun"
|
|
textline " "
|
|
eventfld.long 0x0 4. " HSU_BRK ,Break flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x0 3. " HSU_FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " HSU_RX_TIMEOUT ,Receiver timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0 1. " HSU_RX_TRIG ,Receiver trigger level" "Below,Above"
|
|
textline " "
|
|
eventfld.long 0x0 0. " HSU_TX ,Transmitter interrupt" "Inactive,Active"
|
|
line.long 0x4 "HSU1_CTRL,High Speed UART 1 Control Register"
|
|
bitfld.long 0x4 21. " HRTS_INV ,U1_HRTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 19.--20. " HRTS_TRIG ,Hardware RTS flow control trigger level control" "8 bytes,16 bytes,32 bytes,48 bytes"
|
|
textline " "
|
|
bitfld.long 0x4 18. " HRTS_EN ,Hardware RTS flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 16.--17. " TMO_CONFIG ,Receiver timeout interrupt configuration" "Disabled,4 characters,8 characters,16 characters"
|
|
textline " "
|
|
bitfld.long 0x4 15. " HCTS_INV ,Un_HCTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 14. " HCTS_EN ,Hardware CTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9.--13. " HSU_OFFSET ,First bit sampling point" "0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks"
|
|
bitfld.long 0x4 8. " HSU_BREAK ,Break on the transmit data line generation control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " HSU_ERR_INT_EN ,UART 1 error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " HSU_RX_INT_EN ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " HSU_TX_INT_EN ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--4. " HSU_RX_TRIG ,Receiver FIFO trigger level" "1 byte,4 bytes,8 bytes,16 bytes,32 bytes,48 bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " HSU_TX_TRIG ,Transmitter FIFO trigger level" "Empty,4 bytes,8 bytes,16 bytes"
|
|
line.long 0x8 "HSU1_RATE,High Speed UART 1 Rate Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " HSU_RATE ,High speed UART clock divider"
|
|
width 0xB
|
|
tree.end
|
|
tree "Fast UART 2"
|
|
base ad:0x40018000
|
|
width 12.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "HSU2_RX/TX,High Speed UART 2 Receiver/Transmitter FIFO Register"
|
|
in
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "HSU2_LEVEL,High Speed UART 2 Level Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " HSU_TX_LEV ,Current transmitter FIFO level"
|
|
hexmask.long.byte 0x0 0.--7. 1. " HSU_RX_LEV ,Current receiver FIFO level"
|
|
group.long 0x08++0xB
|
|
line.long 0x0 "HSU2_IIR,High Speed UART 2 Interrupt Identification Register"
|
|
bitfld.long 0x0 6. " HSU_TX_INT_SET ,Transmit interrupt flag set" "No effect,Set"
|
|
textline " "
|
|
eventfld.long 0x0 5. " HSU_RX_OE ,Overrun error flag" "No overflow,Overrun"
|
|
textline " "
|
|
eventfld.long 0x0 4. " HSU_BRK ,Break flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x0 3. " HSU_FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " HSU_RX_TIMEOUT ,Receiver timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0 1. " HSU_RX_TRIG ,Receiver trigger level" "Below,Above"
|
|
textline " "
|
|
eventfld.long 0x0 0. " HSU_TX ,Transmitter interrupt" "Inactive,Active"
|
|
line.long 0x4 "HSU2_CTRL,High Speed UART 2 Control Register"
|
|
bitfld.long 0x4 21. " HRTS_INV ,U2_HRTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 19.--20. " HRTS_TRIG ,Hardware RTS flow control trigger level control" "8 bytes,16 bytes,32 bytes,48 bytes"
|
|
textline " "
|
|
bitfld.long 0x4 18. " HRTS_EN ,Hardware RTS flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 16.--17. " TMO_CONFIG ,Receiver timeout interrupt configuration" "Disabled,4 characters,8 characters,16 characters"
|
|
textline " "
|
|
bitfld.long 0x4 15. " HCTS_INV ,Un_HCTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 14. " HCTS_EN ,Hardware CTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9.--13. " HSU_OFFSET ,First bit sampling point" "0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks"
|
|
bitfld.long 0x4 8. " HSU_BREAK ,Break on the transmit data line generation control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " HSU_ERR_INT_EN ,UART 2 error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " HSU_RX_INT_EN ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " HSU_TX_INT_EN ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--4. " HSU_RX_TRIG ,Receiver FIFO trigger level" "1 byte,4 bytes,8 bytes,16 bytes,32 bytes,48 bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " HSU_TX_TRIG ,Transmitter FIFO trigger level" "Empty,4 bytes,8 bytes,16 bytes"
|
|
line.long 0x8 "HSU2_RATE,High Speed UART 2 Rate Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " HSU_RATE ,High speed UART clock divider"
|
|
width 0xB
|
|
tree.end
|
|
tree "Fast UART 7"
|
|
base ad:0x4001C000
|
|
width 12.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "HSU7_RX/TX,High Speed UART 7 Receiver/Transmitter FIFO Register"
|
|
in
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "HSU7_LEVEL,High Speed UART 7 Level Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " HSU_TX_LEV ,Current transmitter FIFO level"
|
|
hexmask.long.byte 0x0 0.--7. 1. " HSU_RX_LEV ,Current receiver FIFO level"
|
|
group.long 0x08++0xB
|
|
line.long 0x0 "HSU7_IIR,High Speed UART 7 Interrupt Identification Register"
|
|
bitfld.long 0x0 6. " HSU_TX_INT_SET ,Transmit interrupt flag set" "No effect,Set"
|
|
textline " "
|
|
eventfld.long 0x0 5. " HSU_RX_OE ,Overrun error flag" "No overflow,Overrun"
|
|
textline " "
|
|
eventfld.long 0x0 4. " HSU_BRK ,Break flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x0 3. " HSU_FE ,Framing error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 2. " HSU_RX_TIMEOUT ,Receiver timeout" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x0 1. " HSU_RX_TRIG ,Receiver trigger level" "Below,Above"
|
|
textline " "
|
|
eventfld.long 0x0 0. " HSU_TX ,Transmitter interrupt" "Inactive,Active"
|
|
line.long 0x4 "HSU7_CTRL,High Speed UART 7 Control Register"
|
|
bitfld.long 0x4 21. " HRTS_INV ,U7_HRTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 19.--20. " HRTS_TRIG ,Hardware RTS flow control trigger level control" "8 bytes,16 bytes,32 bytes,48 bytes"
|
|
textline " "
|
|
bitfld.long 0x4 18. " HRTS_EN ,Hardware RTS flow control enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 16.--17. " TMO_CONFIG ,Receiver timeout interrupt configuration" "Disabled,4 characters,8 characters,16 characters"
|
|
textline " "
|
|
bitfld.long 0x4 15. " HCTS_INV ,Un_HCTS signal polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x4 14. " HCTS_EN ,Hardware CTS flow control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9.--13. " HSU_OFFSET ,First bit sampling point" "0 clocks,1 clock,2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks,10 clocks,11 clocks,12 clocks,13 clocks,14 clocks,15 clocks,16 clocks,17 clocks,18 clocks,19 clocks,20 clocks,21 clocks,22 clocks,23 clocks,24 clocks,25 clocks,26 clocks,27 clocks,28 clocks,29 clocks,30 clocks,31 clocks"
|
|
bitfld.long 0x4 8. " HSU_BREAK ,Break on the transmit data line generation control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 7. " HSU_ERR_INT_EN ,UART 7 error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 6. " HSU_RX_INT_EN ,Receive interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 5. " HSU_TX_INT_EN ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2.--4. " HSU_RX_TRIG ,Receiver FIFO trigger level" "1 byte,4 bytes,8 bytes,16 bytes,32 bytes,48 bytes,?..."
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " HSU_TX_TRIG ,Transmitter FIFO trigger level" "Empty,4 bytes,8 bytes,16 bytes"
|
|
line.long 0x8 "HSU7_RATE,High Speed UART 7 Rate Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " HSU_RATE ,High speed UART clock divider"
|
|
width 0xB
|
|
tree.end
|
|
tree "UARTs"
|
|
base ad:0x400040E0
|
|
width 14.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "IRDACLK,IrDA Clock Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. " XDivVal ,X divider value"
|
|
hexmask.long.byte 0x0 0.--7. 1. " YDivVal ,Y divider value"
|
|
base ad:0x40054000
|
|
group.long 0x00++0xB
|
|
line.long 0x0 "UART_CTRL,UART Control Register"
|
|
sif (cpu()!="LPC3180")
|
|
bitfld.long 0x0 10. " UART3_MD_CTRL ,Modem control pins usage by UART3" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0 10. " HDPX_INV ,HDPX inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x0 9. " HDPX_EN ,HDPX enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " UART6_IRDA ,UART6 of IRDA usage" "Used,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x0 4. " IRTX6_INV ,IRTX6 pin inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IRRX6_INV ,IRRX6 pin inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x0 2. " IR_RxLength ,IRDA Rx pulses period expectation" "3/16 of selected bit,3/16 of 115.2 kbps"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IR_TxLength ,IRDA Tx pulses period usage" "3/16 of selected bit,3/16 of 115.2 kbps"
|
|
textline " "
|
|
bitfld.long 0x0 0. " UART5_MODE ,UART5 TX/RX function routing" "UART5,UART5+USB"
|
|
line.long 0x4 "UART_CLKMODE,UART Clock Mode Register"
|
|
bitfld.long 0x4 22. " CLK_STAT7 ,UART 7 clock status" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " CLK_STAT6 ,UART 6 clock status" "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " CLK_STAT5 ,UART 5 clock status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 19. " CLK_STAT4 ,UART 4 clock status" "Disabled,Enabled"
|
|
bitfld.long 0x4 18. " CLK_STAT3 ,UART 3 clock status" "Disabled,Enabled"
|
|
bitfld.long 0x4 17. " CLK_STAT2 ,UART 2 clock status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16. " CLK_STAT1 ,UART 1 clock status" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " CLK_STAT ,Some of UART clocks are running" "Stopped,Running"
|
|
bitfld.long 0x4 10.--11. " UART6_CLK ,Selects the clock mode for UART6" "Clock off,Clock on,Auto clock,Not used"
|
|
textline " "
|
|
bitfld.long 0x4 8.--9. " UART5_CLK ,Selects the clock mode for UART5" "Clock off,Clock on,Auto clock,Not used"
|
|
bitfld.long 0x4 6.--7. " UART4_CLK ,Selects the clock mode for UART4" "Clock off,Clock on,Auto clock,Not used"
|
|
bitfld.long 0x4 4.--5. " UART3_CLK ,Selects the clock mode for UART3" "Clock off,Clock on,Auto clock,Not used"
|
|
line.long 0x8 "UART_LOOP,UART Loopback Control Register"
|
|
bitfld.long 0x8 6. " LOOPBACK7 ,UART 7 loopback mode" "Turned off,Loopback"
|
|
bitfld.long 0x8 5. " LOOPBACK6 ,UART 6 loopback mode" "Turned off,Loopback"
|
|
bitfld.long 0x8 4. " LOOPBACK5 ,UART 5 loopback mode" "Turned off,Loopback"
|
|
textline " "
|
|
bitfld.long 0x8 3. " LOOPBACK4 ,UART 4 loopback mode" "Turned off,Loopback"
|
|
bitfld.long 0x8 2. " LOOPBACK3 ,UART 3 loopback mode" "Turned off,Loopback"
|
|
bitfld.long 0x8 1. " LOOPBACK2 ,UART 2 loopback mode" "Turned off,Loopback"
|
|
textline " "
|
|
bitfld.long 0x8 0. " LOOPBACK1 ,UART 1 loopback mode" "Turned off,Loopback"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree.open "SPI Controllers"
|
|
tree "SPI 1"
|
|
base ad:0x20088000
|
|
width 16.
|
|
group.long 0x00++0xF
|
|
line.long 0x0 "SPI1_GLOBAL,SPI 1 Global Control Register"
|
|
bitfld.long 0x0 1. " RST ,SPI interface reset" "No effect,Reset"
|
|
bitfld.long 0x0 0. " ENABLE ,SPI interface enable" "Disabled,Enabled"
|
|
line.long 0x4 "SPI1_CON,SPI 1 Control Register"
|
|
bitfld.long 0x4 23. " UNIDIR ,Bidirectional or unidirectional usage of the SPIn_DATIO pin" "Bidirectional,Unidirectional"
|
|
bitfld.long 0x4 22. " BHALT ,Busy halt" "Not halted,Halted"
|
|
bitfld.long 0x4 21. " BPOL ,Busy polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x4 19. " MSB ,Order in which data bits are transferred" "MSB first,LSB first"
|
|
bitfld.long 0x4 16.--17. " MODE ,SPI mode selection" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
bitfld.long 0x4 15. " RXTX ,Direction of data transfer" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.long 0x4 14. " THR ,FIFO threshold control" "Disabled,Enabled"
|
|
bitfld.long 0x4 13. " SHIFT_OFF ,Generation of clock pulses on SPIn_CLK control" "Enabled,Disabled"
|
|
bitfld.long 0x4 9.--12. " BITNUM ,Number of bits to be transmitted or received in one block transfer" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
textline " "
|
|
bitfld.long 0x4 7. " MS ,SPI master mode enable" "Not supported,Master mode"
|
|
hexmask.long.byte 0x4 0.--6. 1. " RATE ,SPI transfer rate"
|
|
line.long 0x8 "SPI1_FRM,SPI 1 Frame Count Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " SPIF ,SPI frame count"
|
|
line.long 0xC "SPI1_IER,SPI 1 Interrupt Enable Register"
|
|
bitfld.long 0xC 1. " INTEOT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " INTTHR ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
if (((d.l(ad:0x20088000+0x4))&0x8000)==0x0)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SPI1_STAT,SPI 1 Status Register"
|
|
bitfld.long 0x0 8. " INTCLR ,SPI interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x0 7. " EOT ,End of transfer interrupt flag" "Not reached,Reached"
|
|
textline " "
|
|
bitfld.long 0x0 6. " BUSYLEV ,SPIn_BUSY input level" "Low,High"
|
|
bitfld.long 0x0 3. " SHIFTACT ,Shift active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x0 2. " BF ,FIFO full interrupt flag" "Not full,Full"
|
|
bitfld.long 0x0 1. " THR ,Number of entries in the FIFO" "Below threshold,At or above threshold"
|
|
textline " "
|
|
bitfld.long 0x0 0. " BE ,FIFO empty interrupt flag" "Not empty,Empty"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SPI1_STAT,SPI 1 Status Register"
|
|
bitfld.long 0x0 8. " INTCLR ,SPI interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x0 7. " EOT ,End of transfer interrupt flag" "Not reached,Reached"
|
|
textline " "
|
|
bitfld.long 0x0 6. " BUSYLEV ,SPIn_BUSY input level" "Low,High"
|
|
bitfld.long 0x0 3. " SHIFTACT ,Shift active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x0 2. " BF ,FIFO full interrupt flag" "Not full,Full"
|
|
bitfld.long 0x0 1. " THR ,Number of entries in the FIFO" "Above threshold,At or below threshold"
|
|
textline " "
|
|
bitfld.long 0x0 0. " BE ,FIFO empty interrupt flag" "Not empty,Empty"
|
|
endif
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "SPI1_DAT,SPI 1 Data Buffer Register"
|
|
in
|
|
group.long 0x400++0xB
|
|
line.long 0x0 "SPI1_TIM_CTRL,SPI1 Timer Control Register"
|
|
bitfld.long 0x0 2. " TIRQE ,Timed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " PIRQE ,Peripheral interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " MODE ,Mode" "Timed interrupt,DMA time out"
|
|
line.long 0x4 "SPI1_TIM_COUNT,SPI 1 Timer Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " Count ,Timed interrupt period"
|
|
line.long 0x8 "SPI1_TIM_STAT,SPI 1 Timer Status Register"
|
|
eventfld.long 0x8 15. " TIRQSTAT ,Timed interrupt status flag" "Not pending,Pending"
|
|
width 0xB
|
|
tree.end
|
|
tree "SPI 2"
|
|
base ad:0x20090000
|
|
width 16.
|
|
group.long 0x00++0xF
|
|
line.long 0x0 "SPI2_GLOBAL,SPI 2 Global Control Register"
|
|
bitfld.long 0x0 1. " RST ,SPI interface reset" "No effect,Reset"
|
|
bitfld.long 0x0 0. " ENABLE ,SPI interface enable" "Disabled,Enabled"
|
|
line.long 0x4 "SPI2_CON,SPI 2 Control Register"
|
|
bitfld.long 0x4 23. " UNIDIR ,Bidirectional or unidirectional usage of the SPIn_DATIO pin" "Bidirectional,Unidirectional"
|
|
bitfld.long 0x4 22. " BHALT ,Busy halt" "Not halted,Halted"
|
|
bitfld.long 0x4 21. " BPOL ,Busy polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x4 19. " MSB ,Order in which data bits are transferred" "MSB first,LSB first"
|
|
bitfld.long 0x4 16.--17. " MODE ,SPI mode selection" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
bitfld.long 0x4 15. " RXTX ,Direction of data transfer" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.long 0x4 14. " THR ,FIFO threshold control" "Disabled,Enabled"
|
|
bitfld.long 0x4 13. " SHIFT_OFF ,Generation of clock pulses on SPIn_CLK control" "Enabled,Disabled"
|
|
bitfld.long 0x4 9.--12. " BITNUM ,Number of bits to be transmitted or received in one block transfer" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
textline " "
|
|
bitfld.long 0x4 7. " MS ,SPI master mode enable" "Not supported,Master mode"
|
|
hexmask.long.byte 0x4 0.--6. 1. " RATE ,SPI transfer rate"
|
|
line.long 0x8 "SPI2_FRM,SPI 2 Frame Count Register"
|
|
hexmask.long.word 0x8 0.--15. 1. " SPIF ,SPI frame count"
|
|
line.long 0xC "SPI2_IER,SPI 2 Interrupt Enable Register"
|
|
bitfld.long 0xC 1. " INTEOT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 0. " INTTHR ,FIFO threshold interrupt enable" "Disabled,Enabled"
|
|
if (((d.l(ad:0x20090000+0x4))&0x8000)==0x0)
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SPI2_STAT,SPI 2 Status Register"
|
|
bitfld.long 0x0 8. " INTCLR ,SPI interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x0 7. " EOT ,End of transfer interrupt flag" "Not reached,Reached"
|
|
textline " "
|
|
bitfld.long 0x0 6. " BUSYLEV ,SPIn_BUSY input level" "Low,High"
|
|
bitfld.long 0x0 3. " SHIFTACT ,Shift active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x0 2. " BF ,FIFO full interrupt flag" "Not full,Full"
|
|
bitfld.long 0x0 1. " THR ,Number of entries in the FIFO" "Below threshold,At or above threshold"
|
|
textline " "
|
|
bitfld.long 0x0 0. " BE ,FIFO empty interrupt flag" "Not empty,Empty"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SPI2_STAT,SPI 2 Status Register"
|
|
bitfld.long 0x0 8. " INTCLR ,SPI interrupt clear" "No effect,Clear"
|
|
bitfld.long 0x0 7. " EOT ,End of transfer interrupt flag" "Not reached,Reached"
|
|
textline " "
|
|
bitfld.long 0x0 6. " BUSYLEV ,SPIn_BUSY input level" "Low,High"
|
|
bitfld.long 0x0 3. " SHIFTACT ,Shift active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x0 2. " BF ,FIFO full interrupt flag" "Not full,Full"
|
|
bitfld.long 0x0 1. " THR ,Number of entries in the FIFO" "Above threshold,At or below threshold"
|
|
textline " "
|
|
bitfld.long 0x0 0. " BE ,FIFO empty interrupt flag" "Not empty,Empty"
|
|
endif
|
|
hgroup.long 0x14++0x3
|
|
hide.long 0x0 "SPI2_DAT,SPI 2 Data Buffer Register"
|
|
in
|
|
group.long 0x400++0xB
|
|
line.long 0x0 "SPI2_TIM_CTRL,SPI2 Timer Control Register"
|
|
bitfld.long 0x0 2. " TIRQE ,Timed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " PIRQE ,Peripheral interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " MODE ,Mode" "Timed interrupt,DMA time out"
|
|
line.long 0x4 "SPI2_TIM_COUNT,SPI 2 Timer Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " Count ,Timed interrupt period"
|
|
line.long 0x8 "SPI2_TIM_STAT,SPI 2 Timer Status Register"
|
|
eventfld.long 0x8 15. " TIRQSTAT ,Timed interrupt status flag" "Not pending,Pending"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "SD Card Interface"
|
|
base ad:0x20098000
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x0 "SD_Power,Power Control Register"
|
|
bitfld.long 0x0 6. " OpenDrain ,SDCMD output control" "Push-pull,Open drain"
|
|
bitfld.long 0x0 0.--1. " Ctrl ,Power mode control" "Power off,Reserved,Power up,Power on"
|
|
line.long 0x4 "SD_Clock,Clock Control Register"
|
|
bitfld.long 0x4 11. " WideBus ,Wide bus mode" "Standard,Wide"
|
|
bitfld.long 0x4 10. " Bypass ,Bypassing the clock divide logic (SDCLK)" "Not bypassed,Bypassed"
|
|
bitfld.long 0x4 9. " PwrSave ,Power save" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " Enable ,SD card clock enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x4 0.--7. 1. " ClkDiv ,SD card clock period"
|
|
line.long 0x8 "SD_Argument,Argument Register"
|
|
line.long 0xC "SD_Command,Command Register"
|
|
bitfld.long 0xC 10. " Enable ,Command Path State Machine Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 9. " Pending ,Wait for CmdPend before sending the command" "Don't wait,Wait"
|
|
textline " "
|
|
bitfld.long 0xC 8. " Interrupt ,Disable the command timer and wait for a card interrupt" "No interrupt,Wait for interrupt"
|
|
bitfld.long 0xC 7. " LongRsp ,Long response" "Short (48-bit),Long (136-bit)"
|
|
textline " "
|
|
bitfld.long 0xC 6. " Response ,Response to a command require" "Not required,Required"
|
|
hexmask.long.byte 0xC 0.--5. 1. " CmdIndex ,Command Index"
|
|
rgroup.long 0x10++0x13
|
|
line.long 0x0 "SD_Respcmd,Command Response Register"
|
|
hexmask.long.byte 0x0 0.--5. 1. " RespCmd ,Response Command Index"
|
|
if ((d.l(ad:0x20098000+0xC)&0x80)==0x80)
|
|
rgroup.long 0x14++0xF
|
|
line.long 0x00 "SD_Response0,Response register 0"
|
|
line.long 0x04 "SD_Response1,Response register 1"
|
|
line.long 0x08 "SD_Response2,Response register 2"
|
|
line.long 0x0C "SD_Response3,Response register 3"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SD_Response0,Response register 0"
|
|
endif
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "SD_DataTimer,Data Timer Register"
|
|
line.long 0x4 "SD_DataLength,Data Length Register"
|
|
hexmask.long.word 0x4 0.--15. 1. " DataLength ,Data length value"
|
|
line.long 0x8 "SD_DataCtrl,Data Control Register"
|
|
bitfld.long 0x8 4.--7. " BlockSize ,Block Size" "1 byte,2 bytes,4 bytes,8 bytes,16 bytes,31 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes,2048 bytes,?..."
|
|
bitfld.long 0x8 3. " DMAEnable ,DMA Enbable" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " Mode ,Data transfer mode" "Block,Stream"
|
|
textline " "
|
|
bitfld.long 0x8 1. " Direction ,Direction" "Transmit,Receive"
|
|
bitfld.long 0x8 0. " Enable ,Data transfer enable" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "SD_DataCnt,Data Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. " DataCount ,Indicates the number of bytes remaining to transfer"
|
|
line.long 0x4 "SD_Status,Status Register"
|
|
bitfld.long 0x4 21. " RxDataAvlbl ,Data available in receive FIFO" "Unavailable,Available"
|
|
textline " "
|
|
bitfld.long 0x4 20. " TxDataAvlbl ,Data available in transmit FIFO" "Unavailable,Available"
|
|
textline " "
|
|
bitfld.long 0x4 19. " RxFifoEmpty ,Receive FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x4 18. " TxFifoEmpty ,Transmit FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x4 17. " RxFifoFull ,Receive FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x4 16. " TxFifoFull ,Transmit FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x4 15. " RxFifoHalfFull ,Receive FIFO half full" "Not half-full,Half-full"
|
|
textline " "
|
|
bitfld.long 0x4 14. " TxFifoHalfEmpty ,Transmit FIFO half empty" "Not half-empty,Half-empty"
|
|
textline " "
|
|
bitfld.long 0x4 13. " RxActive ,Data receive active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x4 12. " TxActive ,Data transmit active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x4 11. " CmdActive ,Command transfer active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x4 10. " DataBlockEnd ,Data block sent/received (CRC check passed)" "Not sent/received,Sent/received"
|
|
textline " "
|
|
bitfld.long 0x4 9. " StartBitErr ,Start Bit Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x4 8. " DataEnd ,Data end" "No end,End"
|
|
textline " "
|
|
bitfld.long 0x4 7. " CmdSent ,Command sent (No response required)" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x4 6. " CmdRespEnd ,Command Response received (CRC check passed)" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RxOverrun ,Receive FIFO overrun" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x4 4. " TxUnderrun ,Transmit FIFO underrun" "No underrun,Underrun"
|
|
textline " "
|
|
bitfld.long 0x4 3. " DataTimeOut ,Data Timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x4 2. " CmdTimeOut ,Command Response Timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x4 1. " DataCrcFail ,Data block sent/received (CRC check failed)" "Not sent/received,Sent/received"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CmdCrcFail ,Command response received (CRC check failed)" "Not received,Received"
|
|
wgroup.long 0x38++0x3
|
|
line.long 0x0 "SD_Clear,Clear Register"
|
|
bitfld.long 0x0 10. " DataBlockEndClr ,DataBlockEnd flag clear" "No effect,Clear"
|
|
bitfld.long 0x0 9. " StartBitErrClr ,StartBitErr flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 8. " DataEndClr ,DataEnd flag clear" "No effect,Clear"
|
|
bitfld.long 0x0 7. " CmdSentClr ,CmdSent flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 6. " CmdRespEndClr ,CmdRespEnd flag clear" "No effect,Clear"
|
|
bitfld.long 0x0 5. " RxOverrunClr ,RxOverrun flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 4. " TxUnderrunClr ,TxUnderrun flag clear" "No effect,Clear"
|
|
bitfld.long 0x0 3. " DataTimeOutClr ,DataTimeOut flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 2. " CmdTimeOutClr ,CmdTimeOut flag clear" "No effect,Clear"
|
|
bitfld.long 0x0 1. " DataCrcFailClr ,DataCrcFail flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CmdCrcFailClr ,CmdCrcFail flag clear" "No effect,Clear"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "SD_Mask0,Interrupt Mask 0 Register"
|
|
bitfld.long 0x0 21. " Mask21 ,RxDataAvlbl flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 20. " Mask20 ,TxDataAvlbl flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 19. " Mask19 ,RxFifoEmpty flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 18. " Mask18 ,TxFifoEmpty flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 17. " Mask17 ,RxFifoFull flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 16. " Mask16 ,TxFifoFull flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " Mask15 ,RxFifoHalfFull flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " Mask14 ,TxFifoHalfEmpty flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " Mask13 ,RxActive flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " Mask12 ,TxActive flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Mask11 ,CmdActive flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 10. " Mask10 ,DataBlockEnd flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " Mask9 ,StartBitErr flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 8. " Mask8 ,DataEnd flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " Mask7 ,CmdSent flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " Mask6 ,CmdRespEnd flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 5. " Mask5 ,RxOverrun flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " Mask4 ,TxUnderrun flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " Mask3 ,DataTimeOut flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " Mask2 ,CmdTimeOut flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " Mask1 ,DataCrcFail flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " Mask0 ,CmdCrcFail flag interrupt enable" "Disabled,Enabled"
|
|
line.long 0x4 "SD_Mask1,Interrupt Mask 1 Register"
|
|
bitfld.long 0x4 21. " Mask21 ,RxDataAvlbl flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 20. " Mask20 ,TxDataAvlbl flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 19. " Mask19 ,RxFifoEmpty flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 18. " Mask18 ,TxFifoEmpty flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 17. " Mask17 ,RxFifoFull flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 16. " Mask16 ,TxFifoFull flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 15. " Mask15 ,RxFifoHalfFull flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 14. " Mask14 ,TxFifoHalfEmpty flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 13. " Mask13 ,RxActive flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 12. " Mask12 ,TxActive flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 11. " Mask11 ,CmdActive flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 10. " Mask10 ,DataBlockEnd flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " Mask9 ,StartBitErr flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 8. " Mask8 ,DataEnd flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 7. " Mask7 ,CmdSent flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 6. " Mask6 ,CmdRespEnd flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 5. " Mask5 ,RxOverrun flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 4. " Mask4 ,TxUnderrun flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 3. " Mask3 ,DataTimeOut flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 2. " Mask2 ,CmdTimeOut flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " Mask1 ,DataCrcFail flag interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0. " Mask0 ,CmdCrcFail flag interrupt enable" "Disabled,Enabled"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "SD_FIFO0,Data FIFO Register 0"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "SD_FIFO1,Data FIFO Register 1"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "SD_FIFO2,Data FIFO Register 2"
|
|
in
|
|
hgroup.long 0x8C++0x3
|
|
hide.long 0x00 "SD_FIFO3,Data FIFO Register 3"
|
|
in
|
|
hgroup.long 0x90++0x3
|
|
hide.long 0x00 "SD_FIFO4,Data FIFO Register 4"
|
|
in
|
|
hgroup.long 0x94++0x3
|
|
hide.long 0x00 "SD_FIFO5,Data FIFO Register 5"
|
|
in
|
|
hgroup.long 0x98++0x3
|
|
hide.long 0x00 "SD_FIFO6,Data FIFO Register 6"
|
|
in
|
|
hgroup.long 0x9C++0x3
|
|
hide.long 0x00 "SD_FIFO7,Data FIFO Register 7"
|
|
in
|
|
hgroup.long 0xA0++0x3
|
|
hide.long 0x00 "SD_FIFO8,Data FIFO Register 8"
|
|
in
|
|
hgroup.long 0xA4++0x3
|
|
hide.long 0x00 "SD_FIFO9,Data FIFO Register 9"
|
|
in
|
|
hgroup.long 0xA8++0x3
|
|
hide.long 0x00 "SD_FIFO10,Data FIFO Register 10"
|
|
in
|
|
hgroup.long 0xAC++0x3
|
|
hide.long 0x00 "SD_FIFO11,Data FIFO Register 11"
|
|
in
|
|
hgroup.long 0xB0++0x3
|
|
hide.long 0x00 "SD_FIFO12,Data FIFO Register 12"
|
|
in
|
|
hgroup.long 0xB4++0x3
|
|
hide.long 0x00 "SD_FIFO13,Data FIFO Register 13"
|
|
in
|
|
hgroup.long 0xB8++0x3
|
|
hide.long 0x00 "SD_FIFO14,Data FIFO Register 14"
|
|
in
|
|
hgroup.long 0xBC++0x3
|
|
hide.long 0x00 "SD_FIFO15,Data FIFO Register 15"
|
|
in
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "SD_FIFOCnt,FIFO Counter Register"
|
|
hexmask.long.word 0x0 0.--14. 1. " DataCount ,Remaining data words to transfer"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "I2C Interfaces"
|
|
tree "I2C Block 1"
|
|
base ad:0x400A0000
|
|
width 13.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "I2C1_RX/TX,I2C 1 RX/TX Data FIFO"
|
|
in
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "I2C1_STS,I2C 1 Status Register"
|
|
bitfld.long 0x0 11. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x0 10. " TFF ,Transmit FIFO Full" "Not full,Full"
|
|
bitfld.long 0x0 9. " RFE ,Receive FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x0 8. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x0 7. " SDA ,Current value of the SDA signal" "Low,High"
|
|
bitfld.long 0x0 6. " SCL ,Current value of the SCL signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " ACTIVE ,Bus activity" "Stopped,Started"
|
|
bitfld.long 0x0 3. " DRMI ,Master Data Request Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " NAI ,No Acknowledge Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TDI ,Transaction Done Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x08++0xB
|
|
line.long 0x0 "I2C1_CTRL,I2C 1 Control Register"
|
|
bitfld.long 0x0 8. " RESET ,Soft Reset" "No effect,Reset"
|
|
bitfld.long 0x0 7. " TFFIE ,Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RFDAIE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " DAIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " DRMIE ,Master Transmitter Data Request Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " NAIE ,Transmitter No Acknowledge Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TDIE ,Transmit Done Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x4 "I2C1_CLK_HI,I2C 1 Clock Divider High Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " CLK_DIV_HI ,Clock Divisor High"
|
|
line.long 0x8 "I2C1_CLK_LO,I2C 1 Clock Divider Low Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " CLK_DIV_LO ,Clock Divisor Low"
|
|
width 0xB
|
|
tree.end
|
|
tree "I2C Block 2"
|
|
base ad:0x400A8000
|
|
width 13.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x0 "I2C2_RX/TX,I2C 2 RX/TX Data FIFO"
|
|
in
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "I2C2_STS,I2C 2 Status Register"
|
|
bitfld.long 0x0 11. " TFE ,Transmit FIFO Empty" "Not empty,Empty"
|
|
bitfld.long 0x0 10. " TFF ,Transmit FIFO Full" "Not full,Full"
|
|
bitfld.long 0x0 9. " RFE ,Receive FIFO Empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x0 8. " RFF ,Receive FIFO Full" "Not full,Full"
|
|
bitfld.long 0x0 7. " SDA ,Current value of the SDA signal" "Low,High"
|
|
bitfld.long 0x0 6. " SCL ,Current value of the SCL signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 5. " ACTIVE ,Bus activity" "Stopped,Started"
|
|
bitfld.long 0x0 3. " DRMI ,Master Data Request Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " NAI ,No Acknowledge Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TDI ,Transaction Done Interrupt" "No interrupt,Interrupt"
|
|
group.long 0x08++0xB
|
|
line.long 0x0 "I2C2_CTRL,I2C 2 Control Register"
|
|
bitfld.long 0x0 8. " RESET ,Soft Reset" "No effect,Reset"
|
|
bitfld.long 0x0 7. " TFFIE ,Transmit FIFO Not Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " RFDAIE ,Receive Data Available Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " DAIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " DRMIE ,Master Transmitter Data Request Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " NAIE ,Transmitter No Acknowledge Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " TDIE ,Transmit Done Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x4 "I2C2_CLK_HI,I2C 2 Clock Divider High Register"
|
|
hexmask.long.word 0x4 0.--9. 1. " CLK_DIV_HI ,Clock Divisor High"
|
|
line.long 0x8 "I2C2_CLK_LO,I2C 2 Clock Divider Low Register"
|
|
hexmask.long.word 0x8 0.--9. 1. " CLK_DIV_LO ,Clock Divisor Low"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "Keyboard Scan"
|
|
base ad:0x40050000
|
|
width 15.
|
|
group.long 0x00++0x3
|
|
line.long 0x0 "KS_DEB,Keypad De-bouncing Duration Register"
|
|
hexmask.long.word 0x0 0.--7. 1. " Duration ,Keypad de-bouncing duration"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x0 "KS_STATE_COND,Keypad State Machine Current State Register"
|
|
bitfld.long 0x0 0.--1. " STATE ,State" "Idle,Scan Once,IRQ generation,Scan Matrix"
|
|
group.long 0x08++0xF
|
|
line.long 0x0 "KS_IRQ,Keypad Interrupt Register"
|
|
bitfld.long 0x0 0. " KIRQN ,Active interrupt" "Interrupt,No interrupt"
|
|
line.long 0x4 "KS_SCAN_CTL,Keypad Scan Delay Control Register"
|
|
hexmask.long 0x4 0.--7. 1. " SCN_CTL ,Time between each keypad scan in STATE: Scan Matrix"
|
|
line.long 0x8 "KS_FAST_TST,Keypad Scan Clock Control Register"
|
|
bitfld.long 0x8 0. " Jump ,Jump to" "No jump,STATE: Scan Once"
|
|
bitfld.long 0x8 1. " ClkSrc ,Clock Source" "PERIPH_CLK,32 KHz RTC"
|
|
line.long 0xC "KS_MATRIX_DIM,Keypad Matrix Dimension Select Register"
|
|
bitfld.long 0xC 0.--3. " MX_DIM ,Matrix dimension" "Reserved,1 x 1,Reserved,Reserved,Reserved,Reserved,6 x 6,Reserved,8 x 8,?..."
|
|
rgroup.long 0x40++0x1F
|
|
line.long 0x0 "KS_DATA0,Keypad Data Register 0"
|
|
bitfld.long 0x0 7. " KEY_R0_C7 ,Key state of Column 7 on Row 0" "Low,High"
|
|
bitfld.long 0x0 6. " KEY_R0_C6 ,Key state of Column 6 on Row 0" "Low,High"
|
|
bitfld.long 0x0 5. " KEY_R0_C5 ,Key state of Column 5 on Row 0" "Low,High"
|
|
bitfld.long 0x0 4. " KEY_R0_C4 ,Key state of Column 4 on Row 0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 3. " KEY_R0_C3 ,Key state of Column 3 on Row 0" "Low,High"
|
|
bitfld.long 0x0 2. " KEY_R0_C2 ,Key state of Column 2 on Row 0" "Low,High"
|
|
bitfld.long 0x0 1. " KEY_R0_C1 ,Key state of Column 1 on Row 0" "Low,High"
|
|
bitfld.long 0x0 0. " KEY_R0_C0 ,Key state of Column 0 on Row 0" "Low,High"
|
|
line.long 0x4 "KS_DATA1,Keypad Data Register 1"
|
|
bitfld.long 0x4 7. " KEY_R1_C7 ,Key state of Column 7 on Row 1" "Low,High"
|
|
bitfld.long 0x4 6. " KEY_R1_C6 ,Key state of Column 6 on Row 1" "Low,High"
|
|
bitfld.long 0x4 5. " KEY_R1_C5 ,Key state of Column 5 on Row 1" "Low,High"
|
|
bitfld.long 0x4 4. " KEY_R1_C4 ,Key state of Column 4 on Row 1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 3. " KEY_R1_C3 ,Key state of Column 3 on Row 1" "Low,High"
|
|
bitfld.long 0x4 2. " KEY_R1_C2 ,Key state of Column 2 on Row 1" "Low,High"
|
|
bitfld.long 0x4 1. " KEY_R1_C1 ,Key state of Column 1 on Row 1" "Low,High"
|
|
bitfld.long 0x4 0. " KEY_R1_C0 ,Key state of Column 0 on Row 1" "Low,High"
|
|
line.long 0x8 "KS_DATA2,Keypad Data Register 2"
|
|
bitfld.long 0x8 7. " KEY_R2_C7 ,Key state of Column 7 on Row 2" "Low,High"
|
|
bitfld.long 0x8 6. " KEY_R2_C6 ,Key state of Column 6 on Row 2" "Low,High"
|
|
bitfld.long 0x8 5. " KEY_R2_C5 ,Key state of Column 5 on Row 2" "Low,High"
|
|
bitfld.long 0x8 4. " KEY_R2_C4 ,Key state of Column 4 on Row 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 3. " KEY_R2_C3 ,Key state of Column 3 on Row 2" "Low,High"
|
|
bitfld.long 0x8 2. " KEY_R2_C2 ,Key state of Column 2 on Row 2" "Low,High"
|
|
bitfld.long 0x8 1. " KEY_R2_C1 ,Key state of Column 1 on Row 2" "Low,High"
|
|
bitfld.long 0x8 0. " KEY_R2_C0 ,Key state of Column 0 on Row 2" "Low,High"
|
|
line.long 0xC "KS_DATA3,Keypad Data Register 3"
|
|
bitfld.long 0xC 7. " KEY_R3_C7 ,Key state of Column 7 on Row 3" "Low,High"
|
|
bitfld.long 0xC 6. " KEY_R3_C6 ,Key state of Column 6 on Row 3" "Low,High"
|
|
bitfld.long 0xC 5. " KEY_R3_C5 ,Key state of Column 5 on Row 3" "Low,High"
|
|
bitfld.long 0xC 4. " KEY_R3_C4 ,Key state of Column 4 on Row 3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 3. " KEY_R3_C3 ,Key state of Column 3 on Row 3" "Low,High"
|
|
bitfld.long 0xC 2. " KEY_R3_C2 ,Key state of Column 2 on Row 3" "Low,High"
|
|
bitfld.long 0xC 1. " KEY_R3_C1 ,Key state of Column 1 on Row 3" "Low,High"
|
|
bitfld.long 0xC 0. " KEY_R3_C0 ,Key state of Column 0 on Row 3" "Low,High"
|
|
line.long 0x10 "KS_DATA4,Keypad Data Register 4"
|
|
bitfld.long 0x10 7. " KEY_R4_C7 ,Key state of Column 7 on Row 4" "Low,High"
|
|
bitfld.long 0x10 6. " KEY_R4_C6 ,Key state of Column 6 on Row 4" "Low,High"
|
|
bitfld.long 0x10 5. " KEY_R4_C5 ,Key state of Column 5 on Row 4" "Low,High"
|
|
bitfld.long 0x10 4. " KEY_R4_C4 ,Key state of Column 4 on Row 4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 3. " KEY_R4_C3 ,Key state of Column 3 on Row 4" "Low,High"
|
|
bitfld.long 0x10 2. " KEY_R4_C2 ,Key state of Column 2 on Row 4" "Low,High"
|
|
bitfld.long 0x10 1. " KEY_R4_C1 ,Key state of Column 1 on Row 4" "Low,High"
|
|
bitfld.long 0x10 0. " KEY_R4_C0 ,Key state of Column 0 on Row 4" "Low,High"
|
|
line.long 0x14 "KS_DATA5,Keypad Data Register 5"
|
|
bitfld.long 0x14 7. " KEY_R5_C7 ,Key state of Column 7 on Row 5" "Low,High"
|
|
bitfld.long 0x14 6. " KEY_R5_C6 ,Key state of Column 6 on Row 5" "Low,High"
|
|
bitfld.long 0x14 5. " KEY_R5_C5 ,Key state of Column 5 on Row 5" "Low,High"
|
|
bitfld.long 0x14 4. " KEY_R5_C4 ,Key state of Column 4 on Row 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 3. " KEY_R5_C3 ,Key state of Column 3 on Row 5" "Low,High"
|
|
bitfld.long 0x14 2. " KEY_R5_C2 ,Key state of Column 2 on Row 5" "Low,High"
|
|
bitfld.long 0x14 1. " KEY_R5_C1 ,Key state of Column 1 on Row 5" "Low,High"
|
|
bitfld.long 0x14 0. " KEY_R5_C0 ,Key state of Column 0 on Row 5" "Low,High"
|
|
line.long 0x18 "KS_DATA6,Keypad Data Register 6"
|
|
bitfld.long 0x18 7. " KEY_R6_C7 ,Key state of Column 7 on Row 6" "Low,High"
|
|
bitfld.long 0x18 6. " KEY_R6_C6 ,Key state of Column 6 on Row 6" "Low,High"
|
|
bitfld.long 0x18 5. " KEY_R6_C5 ,Key state of Column 5 on Row 6" "Low,High"
|
|
bitfld.long 0x18 4. " KEY_R6_C4 ,Key state of Column 4 on Row 6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 3. " KEY_R6_C3 ,Key state of Column 3 on Row 6" "Low,High"
|
|
bitfld.long 0x18 2. " KEY_R6_C2 ,Key state of Column 2 on Row 6" "Low,High"
|
|
bitfld.long 0x18 1. " KEY_R6_C1 ,Key state of Column 1 on Row 6" "Low,High"
|
|
bitfld.long 0x18 0. " KEY_R6_C0 ,Key state of Column 0 on Row 6" "Low,High"
|
|
line.long 0x1C "KS_DATA7,Keypad Data Register 7"
|
|
bitfld.long 0x1C 7. " KEY_R7_C7 ,Key state of Column 7 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 6. " KEY_R7_C6 ,Key state of Column 6 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 5. " KEY_R7_C5 ,Key state of Column 5 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 4. " KEY_R7_C4 ,Key state of Column 4 on Row 7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " KEY_R7_C3 ,Key state of Column 3 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 2. " KEY_R7_C2 ,Key state of Column 2 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 1. " KEY_R7_C1 ,Key state of Column 1 on Row 7" "Low,High"
|
|
bitfld.long 0x1C 0. " KEY_R7_C0 ,Key state of Column 0 on Row 7" "Low,High"
|
|
width 0xB
|
|
tree.end
|
|
tree "High Speed Timer"
|
|
base ad:0x40038000
|
|
width 15.
|
|
group.long 0x00++0x23
|
|
line.long 0x0 "HSTIM_INT,High Speed Timer Interrupt Status Register"
|
|
eventfld.long 0x0 5. " RTC_TICK ,RTC tick capture status" "Inactive,Active"
|
|
eventfld.long 0x0 4. " GPI_06 ,GPI_06 tick capture status" "Inactive,Active"
|
|
eventfld.long 0x0 2. " MATCH2_INT ,MATCH2 interrupt status" "Inactive,Active"
|
|
textline " "
|
|
eventfld.long 0x0 1. " MATCH1_INT ,MATCH1 interrupt status" "Inactive,Active"
|
|
eventfld.long 0x0 0. " MATCH0_INT ,MATCH0 interrupt status" "Inactive,Active"
|
|
line.long 0x4 "HSTIM_CTRL,High Speed Timer Control Register"
|
|
bitfld.long 0x4 2. " PAUSE_EN ,Pause enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " RESET_COUNT ,Timer counter reset" "No reset,Reset"
|
|
bitfld.long 0x4 0. " COUNT_ENAB ,Timer counter enable" "Stopped,Enabled"
|
|
line.long 0x8 "HSTIM_COUNTER,High Speed Timer Counter Value Register"
|
|
line.long 0xC "HSTIM_PMATCH,High Speed Timer Prescale Counter Match Register"
|
|
hexmask.long.word 0xC 0.--15. 1. " PMATCH ,Prescale counter match value"
|
|
line.long 0x10 "HSTIM_PCOUNT,High Speed Timer Prescale Counter Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " HSTIM_PCOUNT ,Current value of the Prescale Counter"
|
|
line.long 0x14 "HSTIM_MCTRL,High Speed Timer Match Control Register"
|
|
bitfld.long 0x14 8. " STOP_COUNT2 ,Stop functionality on Match 2" "Disabled,Enabled"
|
|
bitfld.long 0x14 7. " RESET_COUNT2 ,Reset of Timer Counter on Match 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " MR2_INT ,Interrupt on the Match 2 register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " STOP_COUNT1 ,Stop functionality on Match 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " RESET_COUNT1 ,Reset of Timer Counter on Match 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " MR1_INT ,Interrupt on the Match 1 register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " STOP_COUNT0 ,Stop functionality on Match 0" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " RESET_COUNT0 ,Reset of Timer Counter on Match 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " MR0_INT ,Interrupt on the Match 0 register enable" "Disabled,Enabled"
|
|
line.long 0x18 "HSTIM_MATCH0,High Speed Timer Match 0 Register"
|
|
line.long 0x1C "HSTIM_MATCH1,High Speed Timer Match 1 Register"
|
|
line.long 0x20 "HSTIM_MATCH2,High Speed Timer Match 2 Register"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "HSTIM_CCR,High Speed Timer Capture Control Register"
|
|
bitfld.long 0x0 5. " RTC_TICK_EVENT ,RTC tick evet capture" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RTC_TICK_FALL ,RTC tick falling edge detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RTC_TICK_RISE ,RTC tick rising edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " GPI_06_EVENT ,GPI_06 capture" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " GPI_06_FALL ,GPI_06 falling edge detection" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " GPI_06_RISE ,GPI_06 rising edge detection" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "HSTIM_CR0,High Speed Timer Capture 0 Register"
|
|
line.long 0x4 "HSTIM_CR1,High Speed Timer Capture 1 Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "Milisecond Timer"
|
|
base ad:0x40034000
|
|
width 15.
|
|
group.long 0x00++0xB
|
|
line.long 0x0 "MSTIM_INT,Millisecond Timer Interrupt Status Register"
|
|
eventfld.long 0x0 1. " MATCH1_INT ,MATCH 1 interrupt active" "Inactive,Active"
|
|
eventfld.long 0x0 0. " MATCH0_INT ,MATCH 0 interrupt active" "Inactive,Active"
|
|
line.long 0x4 "MSTIM_CTRL,Millisecond Timer Control Register"
|
|
bitfld.long 0x4 2. " PAUSE_EN ,Pause enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " RESET_COUNT ,Timer counter reset" "No reset,Reset"
|
|
bitfld.long 0x4 0. " COUNT_ENAB ,Timer counter enable" "Stopped,Enabled"
|
|
line.long 0x8 "MSTIM_COUNTER,Millisecond Timer Counter Value Register"
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "MSTIM_MCTRL,Millisecond Timer Match Control Register"
|
|
bitfld.long 0x0 5. " STOP_COUNT1 ,Stop functionality on Match 1" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " RESET_COUNT1 ,Reset of Timer Counter on Match 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " MR1_INT ,Interrupt on the Match 1 register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " STOP_COUNT0 ,Stop functionality on Match 0" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " RESET_COUNT0 ,Reset of Timer Counter on Match 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " MR0_INT ,Interrupt on the Match 0 register enable" "Disabled,Enabled"
|
|
line.long 0x4 "MSTIM_MATCH0,Millisecond Timer Match 0 Register"
|
|
line.long 0x8 "MSTIM_MATCH1,Millisecond Timer Match 1 Register"
|
|
width 0xB
|
|
tree.end
|
|
tree "Pulse Width Modulators"
|
|
base ad:0x4005C000
|
|
width 11.
|
|
group.long 0x00++0x3 "PWM1"
|
|
line.long 0x0 "PWM1_CTRL,PWM1 Control Register"
|
|
bitfld.long 0x0 31. " PWM1_EN ,PWM1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " PWM1_PIN_LEVEL ,PWM_OUT1 pin state" "Low,High"
|
|
textline " "
|
|
hexmask.long.byte 0x0 8.--15. 1. " PWM1_RELOADV ,Reload value for the PWM output frequency"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PWM1_DUTY ,Output duty cycle"
|
|
group.long 0x04++0x3 "PWM2"
|
|
line.long 0x0 "PWM2_CTRL,PWM2 Control Register"
|
|
bitfld.long 0x0 31. " PWM2_EN ,PWM2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " PWM2_PIN_LEVEL ,PWM_OUT2 pin state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 29. " PWM2_INT ,PWM_OUT2 functionality" "Normal,Interrupt Status"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PWM1_RELOADV ,Reload value for the PWM output frequency"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--7. 1. " PWM1_DUTY ,Output duty cycle"
|
|
width 0xB
|
|
tree.end
|
|
tree "Real Time Clock And Battery Ram"
|
|
base ad:0x40024000
|
|
width 12.
|
|
group.long 0x00++0x1B
|
|
line.long 0x0 "RTC_UCOUNT,RTC Up Counter Value Register"
|
|
line.long 0x4 "RTC_DCOUNT,RTC Down Counter Value Register"
|
|
line.long 0x8 "RTC_MATCH0,RTC Match 0 Register"
|
|
line.long 0xC "RTC_MATCH1,RTC Match 1 Register"
|
|
line.long 0x10 "RTC_CTRL,RTC Control Register"
|
|
bitfld.long 0x10 10. " 32kHzOut ,Output from the 32 kHz oscillator" "Low,High"
|
|
bitfld.long 0x10 7. " ForceONSW ,RTC force ONSW high signal" "Not forced,Forced"
|
|
bitfld.long 0x10 6. " CountClkDis ,RTC counter clock disable" "Running,Stopped"
|
|
textline " "
|
|
bitfld.long 0x10 4. " SWRTCRes ,Software controlled RTC reset" "No reset,Reset"
|
|
bitfld.long 0x10 3. " M1ONSWCtrl ,Match 1 ONSW control" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " M0ONSWCtrl ,Match 0 ONSW control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " M1IntEn ,Match 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " M0IntEn ,Match 0 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x14 "RTC_INTSTAT,RTC Interrupt Status Register"
|
|
eventfld.long 0x14 2. " ONSW_MSt ,ONSW Match status" "No interrupt,Interrupt"
|
|
eventfld.long 0x14 1. " M1IntStat ,Match 1 interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x14 0. " M0IntStat ,Match 0 interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x18 "RTC_KEY,RTC Key Register"
|
|
tree "Battery Ram"
|
|
group.long 0x80++0x7F
|
|
line.long 0x0 "RTC_SRAM0,Battery RAM 0"
|
|
line.long 0x4 "RTC_SRAM1,Battery RAM 1"
|
|
line.long 0x8 "RTC_SRAM2,Battery RAM 2"
|
|
line.long 0xC "RTC_SRAM3,Battery RAM 3"
|
|
line.long 0x10 "RTC_SRAM4,Battery RAM 4"
|
|
line.long 0x14 "RTC_SRAM5,Battery RAM 5"
|
|
line.long 0x18 "RTC_SRAM6,Battery RAM 6"
|
|
line.long 0x1C "RTC_SRAM7,Battery RAM 7"
|
|
line.long 0x20 "RTC_SRAM8,Battery RAM 8"
|
|
line.long 0x24 "RTC_SRAM9,Battery RAM 9"
|
|
line.long 0x28 "RTC_SRAM10,Battery RAM 10"
|
|
line.long 0x2C "RTC_SRAM11,Battery RAM 11"
|
|
line.long 0x30 "RTC_SRAM12,Battery RAM 12"
|
|
line.long 0x34 "RTC_SRAM13,Battery RAM 13"
|
|
line.long 0x38 "RTC_SRAM14,Battery RAM 14"
|
|
line.long 0x3C "RTC_SRAM15,Battery RAM 15"
|
|
line.long 0x40 "RTC_SRAM16,Battery RAM 16"
|
|
line.long 0x44 "RTC_SRAM17,Battery RAM 17"
|
|
line.long 0x48 "RTC_SRAM18,Battery RAM 18"
|
|
line.long 0x4C "RTC_SRAM19,Battery RAM 19"
|
|
line.long 0x50 "RTC_SRAM20,Battery RAM 20"
|
|
line.long 0x54 "RTC_SRAM21,Battery RAM 21"
|
|
line.long 0x58 "RTC_SRAM22,Battery RAM 22"
|
|
line.long 0x5C "RTC_SRAM23,Battery RAM 23"
|
|
line.long 0x60 "RTC_SRAM24,Battery RAM 24"
|
|
line.long 0x64 "RTC_SRAM25,Battery RAM 25"
|
|
line.long 0x68 "RTC_SRAM26,Battery RAM 26"
|
|
line.long 0x6C "RTC_SRAM27,Battery RAM 27"
|
|
line.long 0x70 "RTC_SRAM28,Battery RAM 28"
|
|
line.long 0x74 "RTC_SRAM29,Battery RAM 29"
|
|
line.long 0x78 "RTC_SRAM30,Battery RAM 30"
|
|
line.long 0x7C "RTC_SRAM31,Battery RAM 31"
|
|
tree.end
|
|
width 0xB
|
|
tree.end
|
|
tree "Watchdog Timer"
|
|
base ad:0x4003C000
|
|
width 15.
|
|
group.long 0x00++0x1F
|
|
line.long 0x0 "WDTIM_INT,Watchdog Timer Interrupt Status Register"
|
|
eventfld.long 0x0 0. " MATCH_INT ,Match 0 interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x4 "WDTIM_CTRL,Watchdog Timer Control Register"
|
|
bitfld.long 0x4 2. " PAUSE_EN ,Pause enable (debug mode on)" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " RESET_COUNT ,Timer counter reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x4 0. " COUNT_ENAB ,Timer counter enable" "Stopped,Enabled"
|
|
line.long 0x8 "WDTIM_COUNTER,Watchdog Timer Counter Value Register"
|
|
line.long 0xC "WDTIM_MCTRL,Watchdog Timer Match Control Register"
|
|
bitfld.long 0xC 6. " RESFRC2 ,WDOG_RESET2 signal active force" "Not forced,Forced"
|
|
bitfld.long 0xC 5. " RESFRC1 ,RESOUT_N signal active force" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0xC 4. " M_RES2 ,Match output to generate active WDOG_RESET2 signal" "No effect,Reset"
|
|
bitfld.long 0xC 3. " M_RES1 ,Match output to generate internal device reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0xC 2. " STOP_COUNT0 ,Stop functionality on Match 0" "Disabled,Enabled"
|
|
bitfld.long 0xC 1. " RESET_COUNT0 ,Reset of Timer Counter on Match 0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0. " MR0_INT ,Interrupt on the Match 0 enable" "Disabled,Enabled"
|
|
line.long 0x10 "WDTIM_MATCH0,Watchdog Timer Match 0 Register"
|
|
line.long 0x14 "WDTIM_EMR,Watchdog Timer External Match Control Register"
|
|
bitfld.long 0x14 4.--5. " MATCH_CTRL ,External Match Control" "No operation,Reserved,Output high on match,?..."
|
|
bitfld.long 0x14 0. " EXT_MATCH0 ,Value of the match output signal" "Low,High"
|
|
line.long 0x18 "WDTIM_PULSE,Watchdog Timer Reset Pulse Length Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " PULSE ,This register gives the RESET pulse length"
|
|
line.long 0x1C "WDTIM_RES,Watchdog Timer Reset Source Register"
|
|
bitfld.long 0x1C 0. " LastRes ,Last reset source" "RESET_N,Watchdog"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "DMA Controller"
|
|
tree "General DMA Registers"
|
|
base ad:0x31000000
|
|
width 19.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x0 "DMACIntStat,DMA Interrupt Status Register"
|
|
bitfld.long 0x0 7. " IntStat7 ,DMA channel 7 interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 6. " IntStat6 ,DMA channel 6 interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 5. " IntStat5 ,DMA channel 5 interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 4. " IntStat4 ,DMA channel 4 interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IntStat3 ,DMA channel 3 interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 2. " IntStat2 ,DMA channel 2 interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IntStat1 ,DMA channel 1 interrupt" "Inactive,Active"
|
|
bitfld.long 0x0 0. " IntStat0 ,DMA channel 0 interrupt" "Inactive,Active"
|
|
line.long 0x4 "DMACIntTCStat,DMA Interrupt Terminal Count Request Status Register"
|
|
bitfld.long 0x4 7. " IntTCStat7 ,DMA channel 7 terminal count interrupt request" "Inactive,Active"
|
|
bitfld.long 0x4 6. " IntTCStat6 ,DMA channel 6 terminal count interrupt request" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x4 5. " IntTCStat5 ,DMA channel 5 terminal count interrupt request" "Inactive,Active"
|
|
bitfld.long 0x4 4. " IntTCStat4 ,DMA channel 4 terminal count interrupt request" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x4 3. " IntTCStat3 ,DMA channel 3 terminal count interrupt request" "Inactive,Active"
|
|
bitfld.long 0x4 2. " IntTCStat2 ,DMA channel 2 terminal count interrupt request" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x4 1. " IntTCStat1 ,DMA channel 1 terminal count interrupt request" "Inactive,Active"
|
|
bitfld.long 0x4 0. " IntTCStat0 ,DMA channel 0 terminal count interrupt request" "Inactive,Active"
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x0 "DMACIntTCClear,DMA Interrupt Terminal Count Request Clear Register"
|
|
bitfld.long 0x0 7. " IntTCClear7 ,DMA channel 7 terminal count interrupt request clear" "No effect,Clear"
|
|
bitfld.long 0x0 6. " IntTCClear6 ,DMA channel 6 terminal count interrupt request clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 5. " IntTCClear5 ,DMA channel 5 terminal count interrupt request clear" "No effect,Clear"
|
|
bitfld.long 0x0 4. " IntTCClear4 ,DMA channel 4 terminal count interrupt request clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IntTCClear3 ,DMA channel 3 terminal count interrupt request clear" "No effect,Clear"
|
|
bitfld.long 0x0 2. " IntTCClear2 ,DMA channel 2 terminal count interrupt request clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IntTCClear1 ,DMA channel 1 terminal count interrupt request clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " IntTCClear0 ,DMA channel 0 terminal count interrupt request clear" "No effect,Clear"
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x0 "DMACIntErrStat,DMA Interrupt Error Status Register"
|
|
bitfld.long 0x0 7. " IntErrStat7 ,DMA channel 7 interrupt error status" "No error,Error"
|
|
bitfld.long 0x0 6. " IntErrStat6 ,DMA channel 6 interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 5. " IntErrStat5 ,DMA channel 5 interrupt error status" "No error,Error"
|
|
bitfld.long 0x0 4. " IntErrStat4 ,DMA channel 4 interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IntErrStat3 ,DMA channel 3 interrupt error status" "No error,Error"
|
|
bitfld.long 0x0 2. " IntErrStat2 ,DMA channel 2 interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IntErrStat1 ,DMA channel 1 interrupt error status" "No error,Error"
|
|
bitfld.long 0x0 0. " IntErrStat0 ,DMA channel 0 interrupt error status" "No error,Error"
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "DMACIntErrClr,DMA Interrupt Error Clear Register"
|
|
bitfld.long 0x0 7. " IntErrClr7 ,DMA channel 7 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x0 6. " IntErrClr6 ,DMA channel 6 interrupt error clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 5. " IntErrClr5 ,DMA channel 5 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x0 4. " IntErrClr4 ,DMA channel 4 interrupt error clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 3. " IntErrClr3 ,DMA channel 3 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x0 2. " IntErrClr2 ,DMA channel 2 interrupt error clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0 1. " IntErrClr1 ,DMA channel 1 interrupt error clear" "No effect,Clear"
|
|
bitfld.long 0x0 0. " IntErrClr0 ,DMA channel 0 interrupt error clear" "No effect,Clear"
|
|
rgroup.long 0x14++0xB
|
|
line.long 0x0 "DMACRawIntTCStat,DMA Raw Interrupt Terminal Count Status Register"
|
|
bitfld.long 0x0 7. " RawIntTCStat7 ,DMA channel 7 terminal count interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 6. " RawIntTCStat6 ,DMA channel 6 terminal count interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RawIntTCStat5 ,DMA channel 5 terminal count interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 4. " RawIntTCStat4 ,DMA channel 4 terminal count interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 3. " RawIntTCStat3 ,DMA channel 3 terminal count interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 2. " RawIntTCStat2 ,DMA channel 2 terminal count interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 1. " RawIntTCStat1 ,DMA channel 1 terminal count interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 0. " RawIntTCStat0 ,DMA channel 0 terminal count interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x4 "DMACRawIntErrStat,DMA Raw Error Interrupt Status Register"
|
|
bitfld.long 0x4 7. " RawIntErrStat7 ,DMA channel 7 raw interrupt error status" "No error,Error"
|
|
bitfld.long 0x4 6. " RawIntErrStat6 ,DMA channel 6 raw interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x4 5. " RawIntErrStat5 ,DMA channel 5 raw interrupt error status" "No error,Error"
|
|
bitfld.long 0x4 4. " RawIntErrStat4 ,DMA channel 4 raw interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x4 3. " RawIntErrStat3 ,DMA channel 3 raw interrupt error status" "No error,Error"
|
|
bitfld.long 0x4 2. " RawIntErrStat2 ,DMA channel 2 raw interrupt error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x4 1. " RawIntErrStat1 ,DMA channel 1 raw interrupt error status" "No error,Error"
|
|
bitfld.long 0x4 0. " RawIntErrStat0 ,DMA channel 0 raw interrupt error status" "No error,Error"
|
|
line.long 0x8 "DMACEnbldChns,DMA Enabled Channel Register"
|
|
bitfld.long 0x8 7. " Channel7En ,DMA channel 7 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x8 6. " Channel6En ,DMA channel 6 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 5. " Channel5En ,DMA channel 5 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x8 4. " Channel4En ,DMA channel 4 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 3. " Channel3En ,DMA channel 3 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x8 2. " Channel2En ,DMA channel 2 enable status" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 1. " Channel1En ,DMA channel 1 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x8 0. " Channel0En ,DMA channel 0 enable status" "Disabled,Enabled"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "DMACSoftBReq,DMA Software Burst Request Register"
|
|
bitfld.long 0x0 15. " SoftBReq15 ,DMA burst request for line 15" "No effect,Requested"
|
|
bitfld.long 0x0 14. " SoftBReq14 ,DMA burst request for line 14" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 13. " SoftBReq13 ,DMA burst request for line 13" "No effect,Requested"
|
|
bitfld.long 0x0 12. " SoftBReq12 ,DMA burst request for line 12" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 11. " SoftBReq11 ,DMA burst request for line 11" "No effect,Requested"
|
|
bitfld.long 0x0 10. " SoftBReq10 ,DMA burst request for line 10" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 9. " SoftBReq9 ,DMA burst request for line 9" "No effect,Requested"
|
|
bitfld.long 0x0 8. " SoftBReq8 ,DMA burst request for line 8" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 7. " SoftBReq7 ,DMA burst request for line 7" "No effect,Requested"
|
|
bitfld.long 0x0 6. " SoftBReq6 ,DMA burst request for line 6" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SoftBReq5 ,DMA burst request for line 5" "No effect,Requested"
|
|
bitfld.long 0x0 4. " SoftBReq4 ,DMA burst request for line 4" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 3. " SoftBReq3 ,DMA burst request for line 3" "No effect,Requested"
|
|
bitfld.long 0x0 2. " SoftBReq2 ,DMA burst request for line 2" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x0 1. " SoftBReq1 ,DMA burst request for line 1" "No effect,Requested"
|
|
bitfld.long 0x0 0. " SoftBReq0 ,DMA burst request for line 0" "No effect,Requested"
|
|
line.long 0x4 "DMACSoftSReq,DMA Software Single Request Register"
|
|
bitfld.long 0x4 15. " SoftSReq15 ,DMA single transfer request for line 15" "No effect,Requested"
|
|
bitfld.long 0x4 14. " SoftSReq14 ,DMA single transfer request for line 14" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 13. " SoftSReq13 ,DMA single transfer request for line 13" "No effect,Requested"
|
|
bitfld.long 0x4 12. " SoftSReq12 ,DMA single transfer request for line 12" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 11. " SoftSReq11 ,DMA single transfer request for line 11" "No effect,Requested"
|
|
bitfld.long 0x4 10. " SoftSReq10 ,DMA single transfer request for line 10" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 9. " SoftSReq9 ,DMA single transfer request for line 9" "No effect,Requested"
|
|
bitfld.long 0x4 8. " SoftSReq8 ,DMA single transfer request for line 8" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 7. " SoftSReq7 ,DMA single transfer request for line 7" "No effect,Requested"
|
|
bitfld.long 0x4 6. " SoftSReq6 ,DMA single transfer request for line 6" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 5. " SoftSReq5 ,DMA single transfer request for line 5" "No effect,Requested"
|
|
bitfld.long 0x4 4. " SoftSReq4 ,DMA single transfer request for line 4" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 3. " SoftSReq3 ,DMA single transfer request for line 3" "No effect,Requested"
|
|
bitfld.long 0x4 2. " SoftSReq2 ,DMA single transfer request for line 2" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x4 1. " SoftSReq1 ,DMA single transfer request for line 1" "No effect,Requested"
|
|
bitfld.long 0x4 0. " SoftSReq0 ,DMA single transfer request for line 0" "No effect,Requested"
|
|
line.long 0x8 "DMACSoftLBReq,DMA Software Last Burst Requested Register"
|
|
bitfld.long 0x8 15. " SoftLBReq15 ,DMA last burst request for line 15" "No effect,Requested"
|
|
bitfld.long 0x8 14. " SoftLBReq14 ,DMA last burst request for line 14" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 13. " SoftLBReq13 ,DMA last burst request for line 13" "No effect,Requested"
|
|
bitfld.long 0x8 12. " SoftLBReq12 ,DMA last burst request for line 12" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 11. " SoftLBReq11 ,DMA last burst request for line 11" "No effect,Requested"
|
|
bitfld.long 0x8 10. " SoftLBReq10 ,DMA last burst request for line 10" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 9. " SoftLBReq9 ,DMA last burst request for line 9" "No effect,Requested"
|
|
bitfld.long 0x8 8. " SoftLBReq8 ,DMA last burst request for line 8" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 7. " SoftLBReq7 ,DMA last burst request for line 7" "No effect,Requested"
|
|
bitfld.long 0x8 6. " SoftLBReq6 ,DMA last burst request for line 6" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 5. " SoftLBReq5 ,DMA last burst request for line 5" "No effect,Requested"
|
|
bitfld.long 0x8 4. " SoftLBReq4 ,DMA last burst request for line 4" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 3. " SoftLBReq3 ,DMA last burst request for line 3" "No effect,Requested"
|
|
bitfld.long 0x8 2. " SoftLBReq2 ,DMA last burst request for line 2" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0x8 1. " SoftLBReq1 ,DMA last burst request for line 1" "No effect,Requested"
|
|
bitfld.long 0x8 0. " SoftLBReq0 ,DMA last burst request for line 0" "No effect,Requested"
|
|
line.long 0xC "DMACSoftLSReq,DMA Software Last Single Requested Register"
|
|
bitfld.long 0xC 15. " SoftLSReq15 ,DMA last single transfer request for line 15" "No effect,Requested"
|
|
bitfld.long 0xC 14. " SoftLSReq14 ,DMA last single transfer request for line 14" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 13. " SoftLSReq13 ,DMA last single transfer request for line 13" "No effect,Requested"
|
|
bitfld.long 0xC 12. " SoftLSReq12 ,DMA last single transfer request for line 12" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 11. " SoftLSReq11 ,DMA last single transfer request for line 11" "No effect,Requested"
|
|
bitfld.long 0xC 10. " SoftLSReq10 ,DMA last single transfer request for line 10" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 9. " SoftLSReq9 ,DMA last single transfer request for line 9" "No effect,Requested"
|
|
bitfld.long 0xC 8. " SoftLSReq8 ,DMA last single transfer request for line 8" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 7. " SoftLSReq7 ,DMA last single transfer request for line 7" "No effect,Requested"
|
|
bitfld.long 0xC 6. " SoftLSReq6 ,DMA last single transfer request for line 6" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 5. " SoftLSReq5 ,DMA last single transfer request for line 5" "No effect,Requested"
|
|
bitfld.long 0xC 4. " SoftLSReq4 ,DMA last single transfer request for line 4" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 3. " SoftLSReq3 ,DMA last single transfer request for line 3" "No effect,Requested"
|
|
bitfld.long 0xC 2. " SoftLSReq2 ,DMA last single transfer request for line 2" "No effect,Requested"
|
|
textline " "
|
|
bitfld.long 0xC 1. " SoftLSReq1 ,DMA last single transfer request for line 1" "No effect,Requested"
|
|
bitfld.long 0xC 0. " SoftLSReq0 ,DMA last single transfer request for line 0" "No effect,Requested"
|
|
line.long 0x10 "DMACConfig,DMA Configuration Register"
|
|
bitfld.long 0x10 2. " M1 ,AHB Master 1 endianness configuration" "Little-endian,Big-endian"
|
|
bitfld.long 0x10 1. " M0 ,AHB Master 0 endianness configuration" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,DMA controller enable" "Disabled,Enabled"
|
|
line.long 0x14 "DMACSync,DMA Synchronization Register"
|
|
bitfld.long 0x14 15. " DMACSync15 ,Synchronization logic for request line 15 signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DMACSync14 ,Synchronization logic for request line 14 signal enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DMACSync13 ,Synchronization logic for request line 13 signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DMACSync12 ,Synchronization logic for request line 12 signal enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DMACSync11 ,Synchronization logic for request line 11 signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DMACSync10 ,Synchronization logic for request line 10 signal enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DMACSync9 ,Synchronization logic for request line 9 signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DMACSync8 ,Synchronization logic for request line 8 signal enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DMACSync7 ,Synchronization logic for request line 7 signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DMACSync6 ,Synchronization logic for request line 6 signal enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DMACSync5 ,Synchronization logic for request line 5 signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DMACSync4 ,Synchronization logic for request line 4 signal enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DMACSync3 ,Synchronization logic for request line 3 signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DMACSync2 ,Synchronization logic for request line 2 signal enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DMACSync1 ,Synchronization logic for request line 1 signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DMACSync0 ,Synchronization logic for request line 0 signal enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 0 Registers"
|
|
base ad:0x31000100
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC0SrcAddr,DMA Channel 0 Source Address Register"
|
|
line.long 0x4 "DMACC0DestAddr,DMA Channel 0 Destination Address Register"
|
|
line.long 0x8 "DMACC0LLI,DMA Channel 0 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC0Control,DMA channel 0 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " Prot3 ,Access cacheable" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0xC 29. " Prot2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0xC 28. " Prot1 ,Access mode" "User,Pivileged"
|
|
textline " "
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC0Config,Channel 0 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripherial/Memory to peripheral,Peripherial/Peripherial to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripherial ,Destination Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripherial ,Source Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 1 Registers"
|
|
base ad:0x31000120
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC1SrcAddr,DMA Channel 1 Source Address Register"
|
|
line.long 0x4 "DMACC1DestAddr,DMA Channel 1 Destination Address Register"
|
|
line.long 0x8 "DMACC1LLI,DMA Channel 1 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC1Control,DMA channel 1 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " Prot3 ,Access cacheable" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0xC 29. " Prot2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0xC 28. " Prot1 ,Access mode" "User,Pivileged"
|
|
textline " "
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC1Config,Channel 1 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripherial/Memory to peripheral,Peripherial/Peripherial to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripherial ,Destination Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripherial ,Source Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 2 Registers"
|
|
base ad:0x31000140
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC2SrcAddr,DMA Channel 2 Source Address Register"
|
|
line.long 0x4 "DMACC2DestAddr,DMA Channel 2 Destination Address Register"
|
|
line.long 0x8 "DMACC2LLI,DMA Channel 2 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC2Control,DMA channel 2 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " Prot3 ,Access cacheable" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0xC 29. " Prot2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0xC 28. " Prot1 ,Access mode" "User,Pivileged"
|
|
textline " "
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC2Config,Channel 2 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripherial/Memory to peripheral,Peripherial/Peripherial to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripherial ,Destination Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripherial ,Source Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 3 Registers"
|
|
base ad:0x31000160
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC3SrcAddr,DMA Channel 3 Source Address Register"
|
|
line.long 0x4 "DMACC3DestAddr,DMA Channel 3 Destination Address Register"
|
|
line.long 0x8 "DMACC3LLI,DMA Channel 3 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC3Control,DMA channel 3 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " Prot3 ,Access cacheable" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0xC 29. " Prot2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0xC 28. " Prot1 ,Access mode" "User,Pivileged"
|
|
textline " "
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC3Config,Channel 3 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripherial/Memory to peripheral,Peripherial/Peripherial to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripherial ,Destination Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripherial ,Source Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 4 Registers"
|
|
base ad:0x31000180
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC4SrcAddr,DMA Channel 4 Source Address Register"
|
|
line.long 0x4 "DMACC4DestAddr,DMA Channel 4 Destination Address Register"
|
|
line.long 0x8 "DMACC4LLI,DMA Channel 4 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC4Control,DMA channel 4 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " Prot3 ,Access cacheable" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0xC 29. " Prot2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0xC 28. " Prot1 ,Access mode" "User,Pivileged"
|
|
textline " "
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC4Config,Channel 4 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripherial/Memory to peripheral,Peripherial/Peripherial to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripherial ,Destination Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripherial ,Source Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 5 Registers"
|
|
base ad:0x310001A0
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC5SrcAddr,DMA Channel 5 Source Address Register"
|
|
line.long 0x4 "DMACC5DestAddr,DMA Channel 5 Destination Address Register"
|
|
line.long 0x8 "DMACC5LLI,DMA Channel 5 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC5Control,DMA channel 5 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " Prot3 ,Access cacheable" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0xC 29. " Prot2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0xC 28. " Prot1 ,Access mode" "User,Pivileged"
|
|
textline " "
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC5Config,Channel 5 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripherial/Memory to peripheral,Peripherial/Peripherial to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripherial ,Destination Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripherial ,Source Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 6 Registers"
|
|
base ad:0x310001C0
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC6SrcAddr,DMA Channel 6 Source Address Register"
|
|
line.long 0x4 "DMACC6DestAddr,DMA Channel 6 Destination Address Register"
|
|
line.long 0x8 "DMACC6LLI,DMA Channel 6 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC6Control,DMA channel 6 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " Prot3 ,Access cacheable" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0xC 29. " Prot2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0xC 28. " Prot1 ,Access mode" "User,Pivileged"
|
|
textline " "
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC6Config,Channel 6 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripherial/Memory to peripheral,Peripherial/Peripherial to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripherial ,Destination Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripherial ,Source Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 7 Registers"
|
|
base ad:0x310001E0
|
|
width 16.
|
|
group.long 0x00++0x13
|
|
line.long 0x0 "DMACC7SrcAddr,DMA Channel 7 Source Address Register"
|
|
line.long 0x4 "DMACC7DestAddr,DMA Channel 7 Destination Address Register"
|
|
line.long 0x8 "DMACC7LLI,DMA Channel 7 Linked List Item Register"
|
|
hexmask.long 0x8 2.--31. 0x4 " LLI ,Address for next linked list item"
|
|
bitfld.long 0x8 0. " LM ,AHB master select for loading next LLI" "Master 0,Master 1"
|
|
line.long 0xC "DMACC7Control,DMA channel 7 control Register"
|
|
bitfld.long 0xC 31. " I ,Terminal count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 30. " Prot3 ,Access cacheable" "Not cacheable,Cacheable"
|
|
textline " "
|
|
bitfld.long 0xC 29. " Prot2 ,Access bufferable" "Not bufferable,Bufferable"
|
|
bitfld.long 0xC 28. " Prot1 ,Access mode" "User,Pivileged"
|
|
textline " "
|
|
bitfld.long 0xC 27. " DI ,Destination increment after each transfer" "Not incremented,Incremented"
|
|
bitfld.long 0xC 26. " SI ,Source increment after each transfer" "Not incremented,Incremented"
|
|
textline " "
|
|
bitfld.long 0xC 25. " D ,Destination AHB master select" "Master 0,Master 1"
|
|
bitfld.long 0xC 24. " S ,Source AHB master select" "Master 0,Master 1"
|
|
textline " "
|
|
bitfld.long 0xC 21.--23. " DWidth ,Destination transfer width" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.long 0xC 18.--20. " SWidth ,Source transfer width" "8-bit,16-bit,32-bit,?..."
|
|
textline " "
|
|
bitfld.long 0xC 15.--17. " DBSize ,Destination burst size" "1,4,8,16,32,64,128,256"
|
|
bitfld.long 0xC 12.--14. " SBSize ,Source burst size" "1,4,8,16,32,64,128,256"
|
|
textline " "
|
|
hexmask.long.word 0xC 0.--11. 1. " TransferSize ,Transfer size"
|
|
line.long 0x10 "DMACC7Config,Channel 7 Configuration Register"
|
|
bitfld.long 0x10 18. " H ,Halt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " A ,Active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L ,Locked transfers enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " ITC ,Terminal count interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 14. " IE ,Interrupt error mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 11.--13. " FlowCntrl ,Flow control and transfer type" "DMA/Memory to memory,DMA/Memory to peripheral,DMA/Peripheral to memory,DMA/Source peripheral to destination peripheral,Destination periph./Source per. to destination per.,Peripherial/Memory to peripheral,Peripherial/Peripherial to memory,Source Periph./Source per. to destination per."
|
|
textline " "
|
|
bitfld.long 0x10 6.--10. " DestPeripherial ,Destination Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1.--5. " SrcPeripherial ,Source Peripheral" "Reserved,NAND Flash,Reserved,SPI2 Rx/Tx,SD Card interface Rx/Tx,HS-Uart1 Tx,HS-Uart1 Rx,HS-Uart2 Tx,HS-Uart2 Rx,HS-Uart7 Tx,HS-Uart7 Rx,SPI1 Rx/Tx,NAND Flash,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0. " E ,Channel enable" "Disabled,Enabled"
|
|
width 0xB
|
|
tree.end
|
|
tree "Peripherial And PrimeCell Identification Registers"
|
|
base ad:0xFFE04FE0
|
|
width 15.
|
|
rgroup.byte 0x00++0x0 "Peripherial Identification"
|
|
line.byte 0x0 "DMACPeriphID0,Peripheral ID Register 0"
|
|
hexmask.byte 0x0 0.--7. 1. " PartNumber0 ,Part Number 0"
|
|
rgroup.byte 0x04++0x0
|
|
line.byte 0x0 "DMACPeriphID1,Peripheral ID Register 1"
|
|
hexmask.byte 0x0 4.--7. 1. " Designer0 ,Designer 0"
|
|
hexmask.byte 0x0 0.--3. 1. " PartNumber1 ,Part Number 1"
|
|
rgroup.byte 0x8++0x0
|
|
line.byte 0x0 "DMACPeriphID2,Peripheral ID Register 2"
|
|
hexmask.byte 0x0 4.--7. 1. " Revision ,Revision Number"
|
|
hexmask.byte 0x0 0.--3. 1. " Designer1 ,Designer 1"
|
|
rgroup.byte 0xC++0x0
|
|
line.byte 0x0 "DMACPeriphID3,Peripheral ID Register 3"
|
|
bitfld.byte 0x0 7. " DMASrcReqCfg ,Number of DMA source requestors for GPDMA configuration" "16 requestors,32 requestors"
|
|
bitfld.byte 0x0 4.--6. " AHBMasBWidthCfg ,AHB master bus width" "32-bit,64-bit,128-bit,256-bit,512-bit,1024-bit,?..."
|
|
textline " "
|
|
bitfld.byte 0x0 3. " AHBMasNumCfg ,Number of AHB masters" "1 master,2 masters"
|
|
bitfld.byte 0x0 0.--2. " ChanNumCfg ,Number of channels" "2 channels,4 channels,8 channels,16 channels,32 channels,?..."
|
|
group.byte 0x10++0x0 "PrimeCell Identification"
|
|
line.byte 0x0 "DMACPCellID0,PrimeCell ID Register 0"
|
|
hexmask.byte 0x0 0.--7. 1. " DMACPCellID0 ,DMAC Prime Cell Identification 0"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "DMACPCellID1,PrimeCell ID Register 1"
|
|
hexmask.byte 0x0 0.--7. 1. " DMACPCellID1 ,DMAC Prime Cell Identification 1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "DMACPCellID2,PrimeCell ID Register 2"
|
|
hexmask.byte 0x0 0.--7. 1. " DMACPCellID2 ,DMAC Prime Cell Identification 2"
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "DMACPCellID3,PrimeCell ID Register 3"
|
|
hexmask.byte 0x0 0.--7. 1. " DMACPCellID3 ,DMAC Prime Cell Identification 3"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "Analog/Digital Converter"
|
|
base ad:0x40048000
|
|
width 8.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x0 "ADSTAT,A/D Status Register"
|
|
bitfld.long 0x0 4.--6. " ADCSt ,ADC status" "Stopped,Input rise time delay,Sample and hold,Conversion in progress,Delay for ADC ready,?..."
|
|
group.long 0x04++0x7
|
|
line.long 0x0 "ADSEL,A/D Select Register"
|
|
bitfld.long 0x0 8.--9. " AD_Ref- ,A/D negative reference voltage" "Reserved,Reserved,VSS_AD,?..."
|
|
bitfld.long 0x0 6.--7. " AD_Ref+ ,A/D positive reference voltage" "Reserved,Reserved,VDD_AD,?..."
|
|
bitfld.long 0x0 4.--5. " AD_IN ,A/D input select" "ADIN0,ADIN1,ADIN2,?..."
|
|
line.long 0x4 "ADCON,A/D Control Register"
|
|
bitfld.long 0x4 7.--9. " AD_ACC ,Number of bits delivered by the ADC" "10 bits,9 bits,8 bits,7 bits,6 bits,5 bits,4 bits,3 bits"
|
|
bitfld.long 0x4 2. " AD_PDN_CTRL ,ADC power" "Powered down,Powered up"
|
|
bitfld.long 0x4 1. " AD_STROBE ,A/D conversion start" "Not started,Started"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "ADDAT,A/D Data Register"
|
|
hexmask.long.word 0x0 0.--9. 1. " ADC_VALUE ,ADC value of the last conversion"
|
|
width 0xB
|
|
tree.end
|
|
tree "ETM9 And Embedded Trace Buffer"
|
|
base ad:0x40040000
|
|
width 13.
|
|
group.long 0x00++0x7 "ETM9"
|
|
line.long 0x0 "DEBUG_CTRL,Debug Control Register"
|
|
bitfld.long 0x0 4. " VFP9_CLKEN ,VFP9 GCLK control" "Stopped,Enabled"
|
|
bitfld.long 0x0 3. " VFP_BIGEND ,Endianess of VFP control" "Same as ARM926,Big endian"
|
|
textline " "
|
|
bitfld.long 0x0 2. " ARMDBG_DIS ,ARM debug logic control" "Enabled,Disabled"
|
|
line.long 0x4 "DEBUG_GRANT,Master Grant Debug Mode Register"
|
|
bitfld.long 0x4 7. " USBMas ,USB Master force GRANT inactive in ARM debug mode" "Not forced,Forced"
|
|
bitfld.long 0x4 1. " DMAMas1 ,DMA M1 Master force GRANT inactive in ARM debug mode" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x4 0. " DMAMas0 ,DMA M0 Master force GRANT inactive in ARM debug mode" "Not forced,Forced"
|
|
base ad:0x311E0000
|
|
rgroup.long 0x00++0xF "ETB"
|
|
line.long 0x0 "Register_0,Identification Register"
|
|
line.long 0x4 "Register_1,RAM Depth Register"
|
|
line.long 0x8 "Register_2,RAM Width Register"
|
|
bitfld.long 0x8 0.--5. " RamWidth ,RAM data width" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,24-bit,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,32-bit,?..."
|
|
line.long 0xC "Register_3,Status Register"
|
|
bitfld.long 0xC 3. " DFEmpty ,Data Formatter pipeline empty" "Not empty,Empty"
|
|
bitfld.long 0xC 2. " AcqComp ,Acquisition complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0xC 1. " Triggered ,Triggered" "Not triggered,Triggered"
|
|
bitfld.long 0xC 0. " Full ,RAM full" "Not full,Full"
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x0 "Register_4,RAM Data Register"
|
|
in
|
|
if (((d.l(ad:0x311E0000+0x20))&0x1)==0x0)
|
|
group.long 0x14++0xB
|
|
line.long 0x0 "Register_5,RAM Read Pointer Register"
|
|
line.long 0x4 "Register_6,RAM Write Pointer Register"
|
|
line.long 0x8 "Register_7,Trigger Counter Register"
|
|
else
|
|
rgroup.long 0x14++0xB
|
|
line.long 0x0 "Register_5,RAM Read Pointer Register"
|
|
line.long 0x4 "Register_6,RAM Write Pointer Register"
|
|
line.long 0x8 "Register_7,Trigger Counter Register"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "Register_8,Control Register"
|
|
bitfld.long 0x0 2. " SoftwareCntl ,Software of hardware register access" "Software,JTAG"
|
|
bitfld.long 0x0 1. " Demux ,Demultiplexed memory support" "Enabled,Disabled"
|
|
bitfld.long 0x0 0. " TraceCaptEn ,Trace capture enable" "Enabled,Disabled"
|
|
width 0xB
|
|
tree.end
|
|
textline ""
|